[llvm] e7bf451 - [M68k][NFC] Fix indentation in M68kInstrArithmetic.td
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 17 18:46:56 PDT 2021
Author: Jim Lin
Date: 2021-06-18T09:49:04+08:00
New Revision: e7bf4510564a7f4eb924d2e79db0ab7926968583
URL: https://github.com/llvm/llvm-project/commit/e7bf4510564a7f4eb924d2e79db0ab7926968583
DIFF: https://github.com/llvm/llvm-project/commit/e7bf4510564a7f4eb924d2e79db0ab7926968583.diff
LOG: [M68k][NFC] Fix indentation in M68kInstrArithmetic.td
Merely fix indentation
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D104434
Added:
Modified:
llvm/lib/Target/M68k/M68kInstrArithmetic.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/M68k/M68kInstrArithmetic.td b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
index 81286c8f162c2..47deb59c7742f 100644
--- a/llvm/lib/Target/M68k/M68kInstrArithmetic.td
+++ b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
@@ -90,13 +90,13 @@ let Constraints = "$src = $dst" in {
// $reg, $ccr <- $reg op $reg
class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD, MxBead REG>
: MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
- MN#"."#TYPE.Prefix#"\t$opd, $dst",
- [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
- MxArithEncoding<MxBead4Bits<CMD>,
- !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
- REG,
- !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_2"),
- MxExtEmpty>>;
+ MN#"."#TYPE.Prefix#"\t$opd, $dst",
+ [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
+ MxArithEncoding<MxBead4Bits<CMD>,
+ !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
+ REG,
+ !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_2"),
+ MxExtEmpty>>;
/// This Op is similar to the one above except it uses reversed opmode, some
/// commands(e.g. eor) do not support dEA or rEA modes and require EAd for
@@ -106,42 +106,42 @@ class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD, MxBead
/// mess.
class MxBiArOp_RFRR_EAd<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
: MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
- MN#"."#TYPE.Prefix#"\t$opd, $dst",
- [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
- MxArithEncoding<MxBead4Bits<CMD>,
- !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EAd"),
- MxBeadDReg<2>, MxEncEAd_0, MxExtEmpty>>;
+ MN#"."#TYPE.Prefix#"\t$opd, $dst",
+ [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
+ MxArithEncoding<MxBead4Bits<CMD>,
+ !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EAd"),
+ MxBeadDReg<2>, MxEncEAd_0, MxExtEmpty>>;
// $reg <- $reg op $imm
class MxBiArOp_RFRI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
: MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
- MN#"."#TYPE.Prefix#"\t$opd, $dst",
- [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
- MxArithEncoding<MxBead4Bits<CMD>,
- !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
- MxBeadDReg<0>, MxEncEAi,
- !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
+ MN#"."#TYPE.Prefix#"\t$opd, $dst",
+ [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
+ MxArithEncoding<MxBead4Bits<CMD>,
+ !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
+ MxBeadDReg<0>, MxEncEAi,
+ !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
// Again, there are two ways to write an immediate to Dn register either dEA
// opmode or using *I encoding, and again some instrucitons also support address
// registers some do not.
class MxBiArOp_RFRI<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
: MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
- MN#"i."#TYPE.Prefix#"\t$opd, $dst",
- [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
- MxArithImmEncoding<MxBead4Bits<CMD>, !cast<MxEncSize>("MxEncSize"#TYPE.Size),
- !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_0"), MxExtEmpty,
- !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
+ MN#"i."#TYPE.Prefix#"\t$opd, $dst",
+ [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
+ MxArithImmEncoding<MxBead4Bits<CMD>, !cast<MxEncSize>("MxEncSize"#TYPE.Size),
+ !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_0"), MxExtEmpty,
+ !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
let mayLoad = 1 in
class MxBiArOp_RFRM<string MN, SDNode NODE, MxType TYPE, MxOperand OPD, ComplexPattern PAT,
bits<4> CMD, MxEncEA EA, MxEncExt EXT>
: MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, OPD:$opd),
- MN#"."#TYPE.Prefix#"\t$opd, $dst",
- [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))],
- MxArithEncoding<MxBead4Bits<CMD>,
- !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
- MxBeadDReg<0>, EA, EXT>>;
+ MN#"."#TYPE.Prefix#"\t$opd, $dst",
+ [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))],
+ MxArithEncoding<MxBead4Bits<CMD>,
+ !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
+ MxBeadDReg<0>, EA, EXT>>;
} // Constraints
@@ -153,22 +153,22 @@ class MxBiArOp_FMR<string MN, SDNode NODE, MxType TYPE,
MxOperand MEMOpd, ComplexPattern MEMPat,
bits<4> CMD, MxEncEA EA, MxEncExt EXT>
: MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$opd),
- MN#"."#TYPE.Prefix#"\t$opd, $dst",
- [],
- MxArithEncoding<MxBead4Bits<CMD>,
- !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EA"#TYPE.RLet),
- MxBeadDReg<1>, EA, EXT>>;
+ MN#"."#TYPE.Prefix#"\t$opd, $dst",
+ [],
+ MxArithEncoding<MxBead4Bits<CMD>,
+ !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EA"#TYPE.RLet),
+ MxBeadDReg<1>, EA, EXT>>;
class MxBiArOp_FMI<string MN, SDNode NODE, MxType TYPE,
MxOperand MEMOpd, ComplexPattern MEMPat,
bits<4> CMD, MxEncEA MEMEA, MxEncExt MEMExt>
: MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$opd),
- MN#"."#TYPE.Prefix#"\t$opd, $dst",
- [],
- MxArithImmEncoding<MxBead4Bits<CMD>,
- !cast<MxEncSize>("MxEncSize"#TYPE.Size),
- MEMEA, MEMExt,
- !cast<MxEncExt>("MxExtI"#TYPE.Size#"_1")>>;
+ MN#"."#TYPE.Prefix#"\t$opd, $dst",
+ [],
+ MxArithImmEncoding<MxBead4Bits<CMD>,
+ !cast<MxEncSize>("MxEncSize"#TYPE.Size),
+ MEMEA, MEMExt,
+ !cast<MxEncExt>("MxExtI"#TYPE.Size#"_1")>>;
} // mayLoad, mayStore
} // Defs = [CCR]
@@ -481,8 +481,8 @@ let Defs = [CCR] in
let Constraints = "$src = $dst" in
class MxExt<MxType TO, MxType FROM>
: MxInst<(outs TO.ROp:$dst), (ins TO.ROp:$src),
- "ext."#TO.Prefix#"\t$src", [],
- MxExtEncoding<!cast<MxBead3Bits>("MxExtOpmode_"#TO.Prefix#FROM.Prefix)>>;
+ "ext."#TO.Prefix#"\t$src", [],
+ MxExtEncoding<!cast<MxBead3Bits>("MxExtOpmode_"#TO.Prefix#FROM.Prefix)>>;
def EXT16 : MxExt<MxType16d, MxType8d>;
def EXT32 : MxExt<MxType32d, MxType16d>;
@@ -781,13 +781,13 @@ foreach N = ["add", "addc"] in {
// add imm, (An)
def : Pat<(store (!cast<SDNode>(N) (load MxType8.JPat:$dst), MxType8.IPat:$opd),
- MxType8.JPat:$dst),
+ MxType8.JPat:$dst),
(ADD8ji MxType8.JOp:$dst, imm:$opd)>;
def : Pat<(store (!cast<SDNode>(N) (load MxType16.JPat:$dst), MxType16.IPat:$opd),
- MxType16.JPat:$dst),
+ MxType16.JPat:$dst),
(ADD16ji MxType16.JOp:$dst, imm:$opd)>;
def : Pat<(store (!cast<SDNode>(N) (load MxType32.JPat:$dst), MxType32.IPat:$opd),
- MxType32.JPat:$dst),
+ MxType32.JPat:$dst),
(ADD32ji MxType32.JOp:$dst, imm:$opd)>;
} // foreach add, addc
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