[llvm] dc11d4e - [MCA] [RegisterFile] Allow for skipping Defs with RegID of 0 (rather than assert(RegID) like we do before this patch).

Patrick Holland via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 17 11:53:07 PDT 2021


Author: Patrick Holland
Date: 2021-06-17T11:52:43-07:00
New Revision: dc11d4e6be2455e666319e01bc1c79a3ba750fbf

URL: https://github.com/llvm/llvm-project/commit/dc11d4e6be2455e666319e01bc1c79a3ba750fbf
DIFF: https://github.com/llvm/llvm-project/commit/dc11d4e6be2455e666319e01bc1c79a3ba750fbf.diff

LOG: [MCA] [RegisterFile] Allow for skipping Defs with RegID of 0 (rather than assert(RegID) like we do before this patch).

This patch will allow developers to remove unwanted instruction Defs (most likely from within a target specific InstrPostProcess) by setting that Def's RegisterID to 0.
Differential Revision: https://reviews.llvm.org/D104433

Added: 
    

Modified: 
    llvm/lib/MCA/HardwareUnits/RegisterFile.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
index 5e38569f8bfb5..81c4f682f63d2 100644
--- a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
+++ b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
@@ -109,7 +109,12 @@ void RegisterFile::onInstructionExecuted(Instruction *IS) {
       return;
 
     MCPhysReg RegID = WS.getRegisterID();
-    assert(RegID != 0 && "A write of an invalid register?");
+
+    // This allows InstrPostProcess to remove register Defs
+    // by setting their RegisterID to 0.
+    if (!RegID)
+      continue;
+
     assert(WS.getCyclesLeft() != UNKNOWN_CYCLES &&
            "The number of cycles should be known at this point!");
     assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!");
@@ -224,7 +229,11 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
                                     MutableArrayRef<unsigned> UsedPhysRegs) {
   WriteState &WS = *Write.getWriteState();
   MCPhysReg RegID = WS.getRegisterID();
-  assert(RegID && "Adding an invalid register definition?");
+
+  // This allows InstrPostProcess to remove register Defs
+  // by setting their RegisterID to 0.
+  if (!RegID)
+    return;
 
   LLVM_DEBUG({
     dbgs() << "[PRF] addRegisterWrite [ " << Write.getSourceIndex() << ", "
@@ -316,7 +325,11 @@ void RegisterFile::removeRegisterWrite(
 
   MCPhysReg RegID = WS.getRegisterID();
 
-  assert(RegID != 0 && "Invalidating an already invalid register?");
+  // This allows InstrPostProcess to remove register Defs
+  // by setting their RegisterID to 0.
+  if (!RegID)
+    return;
+
   assert(WS.getCyclesLeft() != UNKNOWN_CYCLES &&
          "Invalidating a write of unknown cycles!");
   assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!");


        


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