[llvm] e70d499 - test: clean up some of the RISCV tests (NFC)
Saleem Abdulrasool via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 17 09:51:46 PDT 2021
Author: Saleem Abdulrasool
Date: 2021-06-17T09:51:09-07:00
New Revision: e70d4994ea9eb44ba5a86c5073ac83cf500aabdd
URL: https://github.com/llvm/llvm-project/commit/e70d4994ea9eb44ba5a86c5073ac83cf500aabdd
DIFF: https://github.com/llvm/llvm-project/commit/e70d4994ea9eb44ba5a86c5073ac83cf500aabdd.diff
LOG: test: clean up some of the RISCV tests (NFC)
This addresses some post-commit comments from jrtc27 to make the tests
easier to process.
Added:
Modified:
llvm/test/CodeGen/RISCV/fixups-diff.ll
llvm/test/CodeGen/RISCV/fixups-relax-diff.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/fixups-
diff .ll b/llvm/test/CodeGen/RISCV/fixups-
diff .ll
index 22b2dca2bee7..70e15f356ebc 100644
--- a/llvm/test/CodeGen/RISCV/fixups-
diff .ll
+++ b/llvm/test/CodeGen/RISCV/fixups-
diff .ll
@@ -22,18 +22,18 @@ entry:
ret i32 0
}
-; CHECK: Section {{.*}} .rela.debug_info {
-; CHECK: 0x22 R_RISCV_ADD32 - 0x0
-; CHECK-NEXT: 0x22 R_RISCV_SUB32 - 0x0
-; CHECK: 0x2B R_RISCV_ADD32 - 0x0
-; CHECK-NEXT: 0x2B R_RISCV_SUB32 - 0x0
-; CHECK: }
+; CHECK: Section {{.*}} .rela.debug_info {
+; CHECK: 0x22 R_RISCV_ADD32 - 0x0
+; CHECK-NEXT: 0x22 R_RISCV_SUB32 - 0x0
+; CHECK: 0x2B R_RISCV_ADD32 - 0x0
+; CHECK-NEXT: 0x2B R_RISCV_SUB32 - 0x0
+; CHECK: }
-; CHECK: Section {{.*}} .rela.eh_frame {
-; CHECK: 0x1C R_RISCV_32_PCREL - 0x0
-; CHECK: 0x20 R_RISCV_ADD32 - 0x0
-; CHECK-NEXT: 0x20 R_RISCV_SUB32 - 0x0
-; CHECK: }
+; CHECK: Section {{.*}} .rela.eh_frame {
+; CHECK: 0x1C R_RISCV_32_PCREL - 0x0
+; CHECK: 0x20 R_RISCV_ADD32 - 0x0
+; CHECK-NEXT: 0x20 R_RISCV_SUB32 - 0x0
+; CHECK: }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5}
diff --git a/llvm/test/CodeGen/RISCV/fixups-relax-
diff .ll b/llvm/test/CodeGen/RISCV/fixups-relax-
diff .ll
index cf431d95ae45..4316453ae9bb 100644
--- a/llvm/test/CodeGen/RISCV/fixups-relax-
diff .ll
+++ b/llvm/test/CodeGen/RISCV/fixups-relax-
diff .ll
@@ -1,7 +1,5 @@
-; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o - \
-; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELAX %s
-; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=-relax %s -o - \
-; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELAX %s
+; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o - | llvm-readobj -r - | FileCheck %s
+; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=-relax %s -o - | llvm-readobj -r - | FileCheck %s
; This test checks that a
diff inserted via inline assembly always causes
; relocations. This isn't an assembly test as the assembler takes a
diff erent
@@ -11,8 +9,8 @@ define i32 @main() nounwind {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval, align 4
- ; RELAX: R_RISCV_ADD64 b
- ; RELAX: R_RISCV_SUB64 a
+ ; CHECK: R_RISCV_ADD64 b
+ ; CHECK-NEXT: R_RISCV_SUB64 a
call void asm sideeffect "a:\0Ab:\0A.dword b-a", ""()
ret i32 0
}
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