[PATCH] D103539: RISCV: adjust handling of relocation emission for RISCV

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

_sigh_ forgot to submit these review comments



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Comment at: llvm/test/CodeGen/RISCV/fixups-diff.ll:25-27
+; CHECK: Section {{.*}} .rela.debug_info {
+; CHECK: 0x22 R_RISCV_ADD32 - 0x0
+; CHECK-NEXT: 0x22 R_RISCV_SUB32 - 0x0
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Please line things up, and ideally also indent within `{` (matching the relative indentation of the output) to make it clearer


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Comment at: llvm/test/CodeGen/RISCV/fixups-relax-diff.ll:1-4
 ; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o - \
 ; RUN:     | llvm-readobj -r - | FileCheck -check-prefix=RELAX %s
 ; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=-relax %s -o - \
+; RUN:     | llvm-readobj -r - | FileCheck -check-prefix=RELAX %s
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No need for a custom prefix


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Comment at: llvm/test/CodeGen/RISCV/fixups-relax-diff.ll:15
   ; RELAX: R_RISCV_ADD64 b
   ; RELAX: R_RISCV_SUB64 a
   call void asm sideeffect "a:\0Ab:\0A.dword b-a", ""()
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-NEXT?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D103539/new/

https://reviews.llvm.org/D103539