[PATCH] D102766: [SelectionDAG] Implement PromoteIntRes_INSERT_SUBVECTOR

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll:8
+
+define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_zero_i8(<vscale x 8 x i8>* %a, <vscale x 4 x i8>* %b) #0 {
+; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i8:
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Can you pass <vscale x ...> by value rather than by pointer? I realise the loads are required in the fixed case, but that might shrink the code a little.


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Comment at: llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll:24
+; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
+  %vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
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There is a bit of extraneous stuff going on in these tests, if you choose a couple of optimization passes are you able to shrink them a bit? I'm looking at the store of x29 and extra addpl.


Repository:
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  https://reviews.llvm.org/D102766/new/

https://reviews.llvm.org/D102766