[compiler-rt] 6f0e74c - Avoid unnecessary AArch64 DSB in __clear_cache in some situations.

[Kristof Beyls via llvm-commits]

Author: Kristof Beyls
Date: 2021-06-17T07:45:06+01:00
New Revision: 6f0e74cd583ba6fbb897d3ab16a9b75e91484275

URL: https://github.com/llvm/llvm-project/commit/6f0e74cd583ba6fbb897d3ab16a9b75e91484275
DIFF: https://github.com/llvm/llvm-project/commit/6f0e74cd583ba6fbb897d3ab16a9b75e91484275.diff

LOG: Avoid unnecessary AArch64 DSB in __clear_cache in some situations.

The dsb after instruction cache invalidation only needs to be executed
if any instruction cache invalidation did happen.
Without this change, if the CTR_EL0.DIC bit indicates that instruction
cache invalidation is not needed, __clear_cache would execute two dsb
instructions in a row; with the second one being unnecessary.

Differential Revision: https://reviews.llvm.org/D104371

Added: 
    

Modified: 
    compiler-rt/lib/builtins/clear_cache.c

Removed: 
    


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diff  --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c
index f0a84c4c59546..3c12b74e8fa62 100644
--- a/compiler-rt/lib/builtins/clear_cache.c
+++ b/compiler-rt/lib/builtins/clear_cache.c
@@ -127,8 +127,8 @@ void __clear_cache(void *start, void *end) {
     for (addr = xstart & ~(icache_line_size - 1); addr < xend;
          addr += icache_line_size)
       __asm __volatile("ic ivau, %0" ::"r"(addr));
+    __asm __volatile("dsb ish");
   }
-  __asm __volatile("dsb ish");
   __asm __volatile("isb sy");
 #elif defined(__powerpc64__)
   const size_t line_size = 32;