[PATCH] D104408: AMDGPU/GlobalISel: Treat undef as KnownNeverNaN

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
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Vectors of odd sizes are often padded with undef to reach available
operation size. Treat undef as KnownNeverNaN. Later patches will add
support to recognize constant splat that was padded with undefs.


https://reviews.llvm.org/D104408

Files:
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir


Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
@@ -1028,8 +1028,7 @@
     ; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
     ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[DEF]](s32)
     ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
-    ; GFX9: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[BUILD_VECTOR_TRUNC]]
-    ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+    ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR_TRUNC]]
     ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x s16>)
     %0:_(<2 x s16>) = COPY $vgpr0
     %1:_(s16) = G_FCONSTANT half 0xH0000
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
@@ -1028,8 +1028,7 @@
     ; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
     ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[DEF]](s32)
     ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
-    ; GFX9: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[BUILD_VECTOR_TRUNC]]
-    ; GFX9: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+    ; GFX9: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR_TRUNC]]
     ; GFX9: $vgpr0 = COPY [[FMAXNUM_IEEE]](<2 x s16>)
     %0:_(<2 x s16>) = COPY $vgpr0
     %1:_(s16) = G_FCONSTANT half 0xH0000
Index: llvm/lib/CodeGen/GlobalISel/Utils.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -559,6 +559,10 @@
            (SNaN && !FPVal->getValueAPF().isSignaling());
   }
 
+  if (DefMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
+    return true;
+  }
+
   if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
     for (const auto &Op : DefMI->uses())
       if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))


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