[PATCH] D104236: [AArch64] Add a TableGen pattern to generate uaddlv from uaddlp and addv

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks. I would expect 2 more types I think. v2i32 and v2i64?  It may be better to create a new multiclass like SIMDAcrossLanesIntrinsic.

It's a shame the types needed are a little different, else the same multiclass could be used for both the new and the old opcodes. That would add a both the base pattern and the insert/extract pattern, although I'm not entirely sure that both are needed.


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  https://reviews.llvm.org/D104236/new/

https://reviews.llvm.org/D104236