[llvm] 66234ce - [AMDGPU] Set VOP3P flag on Real instructions

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-06-16T15:00:45+01:00
New Revision: 66234ce49f254fc1d83de41daae8c8a16423bec2

URL: https://github.com/llvm/llvm-project/commit/66234ce49f254fc1d83de41daae8c8a16423bec2
DIFF: https://github.com/llvm/llvm-project/commit/66234ce49f254fc1d83de41daae8c8a16423bec2.diff

LOG: [AMDGPU] Set VOP3P flag on Real instructions

This does not affect codegen but might benefit llvm-mca.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index b8c3ab9659a6..48f5eb1dc272 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -504,6 +504,7 @@ multiclass VOP3P_Real_vi<bits<7> op> {
             VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
     let AssemblerPredicate = HasVOP3PInsts;
     let DecoderNamespace = "GFX8";
+    let VOP3P = 1;
   }
 }
 
@@ -646,12 +647,12 @@ let SubtargetPredicate = HasPackedFP32Ops in {
 // GFX10.
 //===----------------------------------------------------------------------===//
 
-let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
+let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10", VOP3P = 1 in {
   multiclass VOP3P_Real_gfx10<bits<7> op> {
     def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>,
                  VOP3Pe_gfx10 <op, !cast<VOP3P_Pseudo>(NAME).Pfl>;
   }
-} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
+} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10", VOP3P = 1
 
 defm V_PK_MAD_I16     : VOP3P_Real_gfx10<0x00>;
 defm V_PK_MUL_LO_U16  : VOP3P_Real_gfx10<0x01>;