[PATCH] D101469: [RISCV] Enable interleaved vectorization for RVV

[Luke via Phabricator via llvm-commits]

luke957 added inline comments.


================
Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll:4
+; CHECK-LABEL: foo
+; CHECK: LV: IC is 2
+
----------------
luke957 wrote:
> jrtc27 wrote:
> > luke957 wrote:
> > > craig.topper wrote:
> > > > Why are we not checking the generated IR?
> > > Checking the generated IR is better.
> > Why is this not using update_test_checks.py?
> Yeah, using update_test_checks.py is better. But as said update_test_checks.py itself, update_test_checks.py is not designed to be authoritative about what constitutes a good test :)
Thanks for the comment. I'll try to update the test case using update_test_checks.py.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101469/new/

https://reviews.llvm.org/D101469