[PATCH] D104232: [WIP][DAGCombiner] createBuildVecShuffle(): more vector concatenation

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

@RKSimon there are two changes here:

1. `InVT2Size * 2 == VTSize && InVT1Size == VTSize` -> `(VTSize % InVT2Size == 0) && InVT1Size == VTSize`
2. merging two blocks together.

Could you please specify if you'd like to have them separately, or bundled is fine?
Theoretically, both are testable separately, but coming up with test[s] will be comutational-expensive,
so i'd like to know how to proceed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104232/new/

https://reviews.llvm.org/D104232