[PATCH] D104264: Fix atomic loads and stores of 64-bit values in non-default address spaces on ARM

[Koutheir Attouchi via Phabricator via llvm-commits]

koutheir added a comment.

> Not quite. Address spaces in LLVM are a somewhat opaque concept, and can mean anything. I'm just not sure they are exchangeable like you propose on all cases.

Would this qualify atomic operations in non-default address spaces as undefined behavior?

> How are you generating that IR? Is that something that comes from Clang or another official front-end?

The IR is coming from our custom port of the LLVM back-end of GraalVM to ARMv7-A.

> I agree this isn't correct.
> ...
> The crash only happens with 64-bit types because there's an i8* conversion to map i64 into {i32, i32}, so it's accidental. Changing the code to accept any addrspace in that cast is fixing the wrong thing.

How should we correct this?

> I'm not sure the back-end is ready to consume that kind of pattern.

Does this mean we should keep the current state as is, and simply never feed the ARM back-end this kind of instructions?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D104264/new/

https://reviews.llvm.org/D104264