[PATCH] D103689: [RISCV] Add support for BSWAP and BITREVERSE for RVP

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5033
     // value.
-    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, GREVI));
+    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NewOp));
     break;
----------------
catch i8/i16 on RV32/RV64 and i32 on RV64 


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6330
+    break;
+  }
   case RISCVISD::READ_VLENB:
----------------
I have the concern about correctness here.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:1266
+// bswap
+let Predicates = [HasStdExtZpn] in
+def : Pat<(bswap i32:$rs1), (SWAP16 (SWAP8 GPR:$rs1))>;
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craig.topper wrote:
> What if Zbb is enabled. Who gets priority?
Zbb would be first. Zbb only emit one grev instructions. That is better I think.


Repository:
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  https://reviews.llvm.org/D103689/new/

https://reviews.llvm.org/D103689