[PATCH] D104094: Add missing AArch64 data synchronization barrier (dsb) to __clear_cache

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls added a comment.

In D104094#2817317 <https://reviews.llvm.org/D104094#2817317>, @pcc wrote:

> Do we still need the DSB on line 119?

I believe so.
Quoting from the ArmARM (ARM DDI 0487G.a), "B2 <https://reviews.llvm.org/B2>.3.8 Ordering of instruction fetches":

> Ordering of instruction fetches
> For two memory locations A and B, if A has been written to and been made coherent with the instruction fetches of
> the shareability domain, before an update to B by an observer in the same shareability domain, then the instruction
> stream of each observer in the shareability domain will not see the updated value of B without also seeing the
> updated value of A.
> A write has been made coherent with an instruction fetch of a shareability domain when:
>
> CTR_EL0.{DIC, IDC} == {0, 0}
>
> The location written to has been cleaned to the Point of unification (PoU) from the data cache, and
> that clean is complete for the shareability domain. Subsequently the location has been invalidated
> to the Point of unification (PoU) from the instruction cache, and that invalidation is complete for
> the shareability domain.

The last paragraph ("..., and that clean is complete for the shareability domain. Subsequently...") implies that dsb on line 119 is needed.


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