[PATCH] D103597: [AArch64LoadStoreOptimizer] Generate more STPs by renaming registers earlier

[Meera Nakrani via Phabricator via llvm-commits]

MeeraN updated this revision to Diff 352084.
MeeraN edited the summary of this revision.
MeeraN added a comment.

Added checks to ensure that STPs are only generated when the base register is not in use or has not been modified. Also added test cases when the base register has been modified and when there are no registers available for renaming.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103597/new/

https://reviews.llvm.org/D103597

Files:
  llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
  llvm/test/CodeGen/AArch64/consthoist-gep.ll
  llvm/test/CodeGen/AArch64/ldst-opt.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

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