[PATCH] D94467: [PowerPC] Use rldimi/rlwimi instructions to optimize build_vector

[ChenZheng via Phabricator via llvm-commits]

shchenz added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9038
+  // There're already patterns for v4i32 and v2i64 construction.
+  if (VT == MVT::v16i8 || VT == MVT::v8i16) {
+    int NumElt = VT.getVectorNumElements();
----------------
out of curiosity, if we already have patterns for v4i32 and v2i64, should we also handle v16i8 and v8i16 there?


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9065
+    return DAG.getBitcast(VT, DAG.getBuildVector(MVT::v4i32, dl, NewVecElts));
+  } else {
+    return SDValue();
----------------
No need for the `else`, return directly


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Comment at: llvm/test/CodeGen/PowerPC/pre-inc-disable.ll:343
 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r5
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Why do we eliminate so many instructions in the entry block? Are they moved to the `for.body` block? 
If so, if `for.body` is a real loop body(for now it is not, maybe we can change the IR to make the `for.body` be a loop body), will this increase the loop size?


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  https://reviews.llvm.org/D94467/new/

https://reviews.llvm.org/D94467