[PATCH] D104156: [DAGCombine][X86][ARM] EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(?,?,Mask)) -> VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(?, ?), EXTRACT_SUBVECTOR(?, ?), Mask')

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Many remaining cases are rotates, with the pattern like:

  Combining: t0: ch = EntryToken
  Optimized vector-legalized selection DAG: %bb.0 'splatvar_funnnel_v8i32:'
  SelectionDAG has 26 nodes:
    t0: ch = EntryToken
    t2: v8i32,ch = CopyFromReg t0, Register:v8i32 %0
            t25: v2i64 = zero_extend_vector_inreg t45
          t26: v4i32 = bitcast t25
        t27: v8i32 = X86ISD::VSHL t2, t26
                t40: v4i32 = BUILD_VECTOR Constant:i32<32>, Constant:i32<32>, Constant:i32<32>, Constant:i32<32>
              t38: v4i32 = sub t40, t45
            t30: v2i64 = zero_extend_vector_inreg t38
          t31: v4i32 = bitcast t30
        t32: v8i32 = X86ISD::VSRL t2, t31
      t21: v8i32 = or t27, t32
    t10: ch,glue = CopyToReg t0, Register:v8i32 $ymm0, t21
          t4: v8i32,ch = CopyFromReg t0, Register:v8i32 %1
        t6: v8i32 = vector_shuffle<0,0,0,0,0,0,0,0> t4, undef:v8i32
      t43: v4i32 = extract_subvector t6, Constant:i64<0>
      t47: v4i32 = BUILD_VECTOR Constant:i32<31>, Constant:i32<31>, Constant:i32<31>, Constant:i32<31>
    t45: v4i32 = and t43, t47
    t11: ch = X86ISD::RET_FLAG t10, TargetConstant:i32<0>, Register:v8i32 $ymm0, t10:1

Let's suppose we start at `t27: v8i32 = X86ISD::VSHL t2, t26`, and demand the 0'th element of shift amount `t26`.
I think the problem is that `t45` has another use - `t38`,
for another shift. Likewise, if we start from the other shift.
I'm not sure if this can be solved within the existing demandedelts infra?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D104156/new/

https://reviews.llvm.org/D104156