[PATCH] D104149: [MCA] Adding the CustomBehaviour class to llvm-mca

[Patrick Holland via Phabricator via llvm-commits]

holland11 added a comment.

I just spoke with Quentin, and we both agree with you. If it's alright with @foad, we'd like to push the current patch with the AMDGPU example (after I finish making the modifications Andrea suggested in his first comment). Afterwards, I will submit a bug report regarding the relevant flags not being transferred from pseudo -> real instructions. This will allow me to clean up the `cnt` detection logic and make it a lot more similar to the logic found in the `si-insert-waitcnts` pass (which will make the `s_waitcnt` modelling more accurate).

> I'm surprised by this. I don't see anything in the tablegen files to say that DS instructions write to M0.

This is interesting. The `MCInst` for `DS_READ_U8_gfx10` definitely has a `Def` for `M0`.

  		Opcode Name= DS_READ_U8_gfx10
  		SchedClassID=4
  		Resource Mask=0x00000000000004, Reserved=0, #Units=1, cy=1
  		Resource Mask=0x00000000000008, Reserved=0, #Units=1, cy=1
  		Buffer Mask=0x00000000000004
  		Buffer Mask=0x00000000000008
  		 Used Units=0x0000000000000c
  		Used Groups=0x00000000000000
  		[Def]    OpIdx=0, Latency=20, WriteResourceID=0
  		[Def][V] OpIdx=4, Latency=20, WriteResourceID=0
  		[Use]    OpIdx=1, UseIndex=0
  		[Use][V] OpIdx=4, UseIndex=3
  		MaxLatency=20

The `M0` def corresponds to `[Def][V] OpIdx=4, Latency=20, WriteResourceID=0` where the `[V]` signifies that it's a 'variadic' operand (I'm not entirely sure what this means).

I can submit a separate bug report for this if you'd like. It's not really related to the `CustomBehaviour` class or the `s_waitcnt` instruction.


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