[PATCH] D104032: [RISCV] Transform unaligned RVV vector loads/stores to aligned ones

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1906
+                                                    SelectionDAG &DAG) const {
+  auto *Load = dyn_cast<LoadSDNode>(Op);
+  assert(Load && Load->getMemoryVT().isVector() && "Expected vector load");
----------------
cast instead of dyn_cast?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1935
+                                                     SelectionDAG &DAG) const {
+  auto *Store = dyn_cast<StoreSDNode>(Op);
+  assert(Store && Store->getValue().getValueType().isVector() &&
----------------
cast


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104032/new/

https://reviews.llvm.org/D104032