[PATCH] D104149: [MCA] Adding the CustomBehaviour class to llvm-mca

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

> Another issue that I had to face was that mca (properly) enforces in-order writes on all instructions (even ones that don’t write anything such as s_waitcnt). This means that if there is a 300 cycle memory instruction currently executing, and then an s_waitcnt comes along (that isn’t meant for the 300 cycle instruction), we’ll still end up stalling for those ~300 cycles (because otherwise, the s_waitcnt instruction would finish before the memory instruction). However, mca uses a RetireOOO flag that can be set on scheduling classes within tablegen. For this reason, I modified the AMDGPU tablegen slightly to set that flag for the s_waitcnt variants. The flag is only used within mca, so (in theory) this shouldn’t have any side-effects. As mentioned earlier, if the AMDGPU folks do not want these changes, I’m happy to remove this example from the patch.

The rules are quite complicated for which types of instruction are guaranteed to complete in order with respect to which other types of instruction. The whole point of s_waitcnt is to enforce that ordering in cases where it would otherwise be unspecified. I'm not sure that a single RetireOOO flag is enough to model that complexity. It is certainly true that in most cases a simple ALU instruction can complete while there are still outstanding memory instructions.


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  https://reviews.llvm.org/D104149/new/

https://reviews.llvm.org/D104149