[PATCH] D104205: [X86] Schedule-model second (mask) output of GATHER instruction

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

What about the avx512 gather ops - are they OK?



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Comment at: llvm/lib/Target/X86/X86Schedule.td:128
 def WriteMove    : SchedWrite;
+def WriteGatherMaskWriteback : SchedWrite;
 def WriteCopy    : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
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Maybe call this WriteVecMaskedGather to more closely match the other vector load/store classes? Maybe move it to be with the WriteVecMaskedLoad defs as well for clarity.

I'm assuming we don't need separate float/integer classes for this?


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  https://reviews.llvm.org/D104205/new/

https://reviews.llvm.org/D104205