[PATCH] D104042: [AArch64] Improve SAD pattern

Mon Jun 14 00:04:34 PDT 2021

jaykang10 added a comment.

In D104042#2813609 <https://reviews.llvm.org/D104042#2813609>, @dmgreen wrote:

>> It is good point! I have tried below pattern following your suggestion. It seems to work. If you are ok, let me add below pattern in this patch.
>>
>>   let AddedComplexity = 10 in { 
>>   def : Pat<(i32 (extractelt
>>                    (v4i32 (AArch64uaddv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))),
>>                    (i64 0))),
>>             (UADDLVv8i16v V128:$op)>;
>>   }
>
> Do you mind doing this as a new patch? As it does feel logically separable. If we can test them, it would be good to add the various other sizes too. And, I'm not sure about this, but maybe it doesn't need to start from the extract, and can produce a INSERT_SUBREG like some of the other patterns do (like the ones from SIMDAcrossLanesIntrinsic). That might remove the need for the added complexity, and the INSERT_SUBREG / EXRACT_SUBREG should all get cleared up later in the pipeline.

Yep, let me create a new patch for it.

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https://reviews.llvm.org/D104042