[PATCH] D104178: [X86] Add ISD::FREEZE and ISD::AssertAlign to the list of opcodes that don't guarantee upper 32 bits are zero.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/lib/Target/X86/X86InstrCompiler.td:1357
 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
 // 32 bits, they're probably just qualifying a CopyFromReg.
 def def32 : PatLeaf<(i32 GR32:$src), [{
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Nit: Should add comments for `AssertAlign` and `FREEZE`?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104178/new/

https://reviews.llvm.org/D104178