[llvm] 0aef747 - [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 11 13:57:38 PDT 2021
Author: Roman Lebedev
Date: 2021-06-11T23:57:02+03:00
New Revision: 0aef747b846586c29ed3285bbed20a3d607576fa
URL: https://github.com/llvm/llvm-project/commit/0aef747b846586c29ed3285bbed20a3d607576fa
DIFF: https://github.com/llvm/llvm-project/commit/0aef747b846586c29ed3285bbed20a3d607576fa.diff
LOG: [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
The motivation is that the update script has at least two deviations
(`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from
what pretty much all the checklines were generated with,
and most of the tests are still not updated, so each time one of the
non-up-to-date tests is updated to see the effect of the code change,
there is a lot of noise. Instead of having to deal with that each
time, let's just deal with everything at once.
This has been done via:
```
cd llvm-project/llvm/test/CodeGen/X86
grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc
```
Not all tests were regenerated, however.
Added:
Modified:
llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll
llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll
llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll
llvm/test/CodeGen/X86/2009-01-31-BigShift.ll
llvm/test/CodeGen/X86/2009-04-12-picrel.ll
llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
llvm/test/CodeGen/X86/20090313-signext.ll
llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
llvm/test/CodeGen/X86/GlobalISel/fconstant.ll
llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll
llvm/test/CodeGen/X86/PR40322.ll
llvm/test/CodeGen/X86/SwitchLowering.ll
llvm/test/CodeGen/X86/TruncAssertZext.ll
llvm/test/CodeGen/X86/addr-mode-matcher-2.ll
llvm/test/CodeGen/X86/alias-static-alloca.ll
llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll
llvm/test/CodeGen/X86/alloca-overaligned.ll
llvm/test/CodeGen/X86/atomic-fp.ll
llvm/test/CodeGen/X86/atomic-idempotent.ll
llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
llvm/test/CodeGen/X86/atomic-non-integer.ll
llvm/test/CodeGen/X86/atomic-unordered.ll
llvm/test/CodeGen/X86/atomic128.ll
llvm/test/CodeGen/X86/atomic32.ll
llvm/test/CodeGen/X86/atomic64.ll
llvm/test/CodeGen/X86/atomicf128.ll
llvm/test/CodeGen/X86/avg.ll
llvm/test/CodeGen/X86/avoid-sfb.ll
llvm/test/CodeGen/X86/avx-arith.ll
llvm/test/CodeGen/X86/avx-basic.ll
llvm/test/CodeGen/X86/avx-brcond.ll
llvm/test/CodeGen/X86/avx-cmp.ll
llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
llvm/test/CodeGen/X86/avx-load-store.ll
llvm/test/CodeGen/X86/avx-logic.ll
llvm/test/CodeGen/X86/avx-shift.ll
llvm/test/CodeGen/X86/avx-trunc.ll
llvm/test/CodeGen/X86/avx-vperm2x128.ll
llvm/test/CodeGen/X86/avx1-logical-load-folding.ll
llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
llvm/test/CodeGen/X86/avx2-nontemporal.ll
llvm/test/CodeGen/X86/avx2-shift.ll
llvm/test/CodeGen/X86/avx2-vbroadcast.ll
llvm/test/CodeGen/X86/avx2-vbroadcasti128.ll
llvm/test/CodeGen/X86/avx512-any_extend_load.ll
llvm/test/CodeGen/X86/avx512-arith.ll
llvm/test/CodeGen/X86/avx512-bugfix-23634.ll
llvm/test/CodeGen/X86/avx512-calling-conv.ll
llvm/test/CodeGen/X86/avx512-cmp.ll
llvm/test/CodeGen/X86/avx512-cvt.ll
llvm/test/CodeGen/X86/avx512-ext.ll
llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll
llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
llvm/test/CodeGen/X86/avx512-insert-extract.ll
llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
llvm/test/CodeGen/X86/avx512-intrinsics.ll
llvm/test/CodeGen/X86/avx512-logic.ll
llvm/test/CodeGen/X86/avx512-mask-op.ll
llvm/test/CodeGen/X86/avx512-rotate.ll
llvm/test/CodeGen/X86/avx512-trunc.ll
llvm/test/CodeGen/X86/avx512-vbroadcast.ll
llvm/test/CodeGen/X86/avx512-vbroadcasti128.ll
llvm/test/CodeGen/X86/avx512-vbroadcasti256.ll
llvm/test/CodeGen/X86/avx512-vec-cmp.ll
llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
llvm/test/CodeGen/X86/avx512vbmi2-funnel-shifts.ll
llvm/test/CodeGen/X86/avx512vbmi2vl-funnel-shifts.ll
llvm/test/CodeGen/X86/avx512vl-arith.ll
llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
llvm/test/CodeGen/X86/avx512vl-logic.ll
llvm/test/CodeGen/X86/avx512vl-vbroadcast.ll
llvm/test/CodeGen/X86/backpropmask.ll
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
llvm/test/CodeGen/X86/bitcast-setcc-128.ll
llvm/test/CodeGen/X86/bitreverse.ll
llvm/test/CodeGen/X86/bittest-intrin.ll
llvm/test/CodeGen/X86/bool-zext.ll
llvm/test/CodeGen/X86/brcond.ll
llvm/test/CodeGen/X86/break-anti-dependencies.ll
llvm/test/CodeGen/X86/break-false-dep.ll
llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
llvm/test/CodeGen/X86/bswap.ll
llvm/test/CodeGen/X86/bt.ll
llvm/test/CodeGen/X86/bug37521.ll
llvm/test/CodeGen/X86/byval.ll
llvm/test/CodeGen/X86/byval2.ll
llvm/test/CodeGen/X86/byval3.ll
llvm/test/CodeGen/X86/byval4.ll
llvm/test/CodeGen/X86/byval5.ll
llvm/test/CodeGen/X86/byval6.ll
llvm/test/CodeGen/X86/byval7.ll
llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll
llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll
llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll
llvm/test/CodeGen/X86/cgp-usubo.ll
llvm/test/CodeGen/X86/clear-highbits.ll
llvm/test/CodeGen/X86/clear-lowbits.ll
llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll
llvm/test/CodeGen/X86/cmov-double.ll
llvm/test/CodeGen/X86/cmov-fp.ll
llvm/test/CodeGen/X86/cmov.ll
llvm/test/CodeGen/X86/cmovcmov.ll
llvm/test/CodeGen/X86/cmp.ll
llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll
llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
llvm/test/CodeGen/X86/cmpxchg8b.ll
llvm/test/CodeGen/X86/coalescer-remat.ll
llvm/test/CodeGen/X86/code-model-elf-memset.ll
llvm/test/CodeGen/X86/code-model-elf.ll
llvm/test/CodeGen/X86/combine-abs.ll
llvm/test/CodeGen/X86/combine-add-ssat.ll
llvm/test/CodeGen/X86/combine-add-usat.ll
llvm/test/CodeGen/X86/combine-add.ll
llvm/test/CodeGen/X86/combine-and.ll
llvm/test/CodeGen/X86/combine-bextr.ll
llvm/test/CodeGen/X86/combine-bitreverse.ll
llvm/test/CodeGen/X86/combine-bitselect.ll
llvm/test/CodeGen/X86/combine-concatvectors.ll
llvm/test/CodeGen/X86/combine-fabs.ll
llvm/test/CodeGen/X86/combine-fcopysign.ll
llvm/test/CodeGen/X86/combine-multiplies.ll
llvm/test/CodeGen/X86/combine-or.ll
llvm/test/CodeGen/X86/combine-pmuldq.ll
llvm/test/CodeGen/X86/combine-srem.ll
llvm/test/CodeGen/X86/combine-sub.ll
llvm/test/CodeGen/X86/combine-udiv.ll
llvm/test/CodeGen/X86/combine-umax.ll
llvm/test/CodeGen/X86/combine-umin.ll
llvm/test/CodeGen/X86/combine-urem.ll
llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
llvm/test/CodeGen/X86/concat-cast.ll
llvm/test/CodeGen/X86/consecutive-load-shuffle.ll
llvm/test/CodeGen/X86/copy-eflags.ll
llvm/test/CodeGen/X86/copysign-constant-magnitude.ll
llvm/test/CodeGen/X86/critical-anti-dep-breaker.ll
llvm/test/CodeGen/X86/csr-split.ll
llvm/test/CodeGen/X86/cvt16.ll
llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
llvm/test/CodeGen/X86/divmod128.ll
llvm/test/CodeGen/X86/divrem8_ext.ll
llvm/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll
llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
llvm/test/CodeGen/X86/exedepsfix-broadcast.ll
llvm/test/CodeGen/X86/extract-fp.ll
llvm/test/CodeGen/X86/extractelement-fp.ll
llvm/test/CodeGen/X86/fabs.ll
llvm/test/CodeGen/X86/fadd-combines.ll
llvm/test/CodeGen/X86/fast-isel-bc.ll
llvm/test/CodeGen/X86/fast-isel-constpool.ll
llvm/test/CodeGen/X86/fast-isel-fneg.ll
llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll
llvm/test/CodeGen/X86/fdiv-combine.ll
llvm/test/CodeGen/X86/fdiv.ll
llvm/test/CodeGen/X86/fildll.ll
llvm/test/CodeGen/X86/finite-libcalls.ll
llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
llvm/test/CodeGen/X86/fma-fneg-combine.ll
llvm/test/CodeGen/X86/fma-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/fma-scalar-combine.ll
llvm/test/CodeGen/X86/fma-signed-zero.ll
llvm/test/CodeGen/X86/fma4-fneg-combine.ll
llvm/test/CodeGen/X86/fma_patterns.ll
llvm/test/CodeGen/X86/fma_patterns_wide.ll
llvm/test/CodeGen/X86/fmaxnum.ll
llvm/test/CodeGen/X86/fmf-flags.ll
llvm/test/CodeGen/X86/fminnum.ll
llvm/test/CodeGen/X86/fmsubadd-combine.ll
llvm/test/CodeGen/X86/fmul-combines.ll
llvm/test/CodeGen/X86/fold-call-3.ll
llvm/test/CodeGen/X86/fold-load-vec.ll
llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
llvm/test/CodeGen/X86/fold-rmw-ops.ll
llvm/test/CodeGen/X86/fp-cvt.ll
llvm/test/CodeGen/X86/fp-intrinsics-fma.ll
llvm/test/CodeGen/X86/fp-intrinsics.ll
llvm/test/CodeGen/X86/fp-logic.ll
llvm/test/CodeGen/X86/fp-round.ll
llvm/test/CodeGen/X86/fp-stack-2results.ll
llvm/test/CodeGen/X86/fp-stack-set-st1.ll
llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
llvm/test/CodeGen/X86/fp-strict-scalar-round.ll
llvm/test/CodeGen/X86/fp-strict-scalar.ll
llvm/test/CodeGen/X86/fp-une-cmp.ll
llvm/test/CodeGen/X86/fp128-cast-strict.ll
llvm/test/CodeGen/X86/fp128-cast.ll
llvm/test/CodeGen/X86/fp128-compare.ll
llvm/test/CodeGen/X86/fp128-extract.ll
llvm/test/CodeGen/X86/fp128-i128.ll
llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
llvm/test/CodeGen/X86/fp128-libcalls.ll
llvm/test/CodeGen/X86/fp128-load.ll
llvm/test/CodeGen/X86/fp128-select.ll
llvm/test/CodeGen/X86/fp80-strict-libcalls.ll
llvm/test/CodeGen/X86/fp80-strict-scalar.ll
llvm/test/CodeGen/X86/fptosi-constant.ll
llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
llvm/test/CodeGen/X86/freeze.ll
llvm/test/CodeGen/X86/ftrunc.ll
llvm/test/CodeGen/X86/funnel-shift-rot.ll
llvm/test/CodeGen/X86/h-registers-3.ll
llvm/test/CodeGen/X86/haddsub-3.ll
llvm/test/CodeGen/X86/haddsub-broadcast.ll
llvm/test/CodeGen/X86/half-constrained.ll
llvm/test/CodeGen/X86/hidden-vis-2.ll
llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
llvm/test/CodeGen/X86/hoist-invariant-load.ll
llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
llvm/test/CodeGen/X86/i128-sdiv.ll
llvm/test/CodeGen/X86/i128-udiv.ll
llvm/test/CodeGen/X86/i64-to-float.ll
llvm/test/CodeGen/X86/immediate_merging.ll
llvm/test/CodeGen/X86/imul-lea.ll
llvm/test/CodeGen/X86/inline-0bh.ll
llvm/test/CodeGen/X86/inline-asm-flag-output.ll
llvm/test/CodeGen/X86/inline-asm-fpstack.ll
llvm/test/CodeGen/X86/innermost-loop-alignment.ll
llvm/test/CodeGen/X86/insert-into-constant-vector.ll
llvm/test/CodeGen/X86/insertelement-ones.ll
llvm/test/CodeGen/X86/insertelement-var-index.ll
llvm/test/CodeGen/X86/insertps-combine.ll
llvm/test/CodeGen/X86/isint.ll
llvm/test/CodeGen/X86/keylocker-intrinsics.ll
llvm/test/CodeGen/X86/known-bits-vector.ll
llvm/test/CodeGen/X86/known-signbits-vector.ll
llvm/test/CodeGen/X86/large-pic-string.ll
llvm/test/CodeGen/X86/lea-recursion.ll
llvm/test/CodeGen/X86/lifetime-alias.ll
llvm/test/CodeGen/X86/limited-prec.ll
llvm/test/CodeGen/X86/live-out-reg-info.ll
llvm/test/CodeGen/X86/load-chain.ll
llvm/test/CodeGen/X86/load-local-v3i1.ll
llvm/test/CodeGen/X86/load-local-v4i5.ll
llvm/test/CodeGen/X86/load-partial.ll
llvm/test/CodeGen/X86/load-scalar-as-vector.ll
llvm/test/CodeGen/X86/lower-bitcast.ll
llvm/test/CodeGen/X86/lower-vec-shift.ll
llvm/test/CodeGen/X86/lrshrink.ll
llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
llvm/test/CodeGen/X86/lsr-sort.ll
llvm/test/CodeGen/X86/machine-combiner.ll
llvm/test/CodeGen/X86/machine-cp.ll
llvm/test/CodeGen/X86/machine-cse.ll
llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
llvm/test/CodeGen/X86/madd.ll
llvm/test/CodeGen/X86/mask-negated-bool.ll
llvm/test/CodeGen/X86/masked_expandload.ll
llvm/test/CodeGen/X86/masked_gather.ll
llvm/test/CodeGen/X86/masked_gather_scatter.ll
llvm/test/CodeGen/X86/masked_load.ll
llvm/test/CodeGen/X86/masked_store.ll
llvm/test/CodeGen/X86/masked_store_trunc.ll
llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
llvm/test/CodeGen/X86/mcu-abi.ll
llvm/test/CodeGen/X86/memcmp-minsize.ll
llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
llvm/test/CodeGen/X86/memcmp-optsize.ll
llvm/test/CodeGen/X86/memcmp-pgso.ll
llvm/test/CodeGen/X86/memcmp.ll
llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll
llvm/test/CodeGen/X86/memcpy-struct-by-value.ll
llvm/test/CodeGen/X86/memcpy.ll
llvm/test/CodeGen/X86/memset-nonzero.ll
llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll
llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll
llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
llvm/test/CodeGen/X86/min-legal-vector-width.ll
llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
llvm/test/CodeGen/X86/mmx-arg-passing.ll
llvm/test/CodeGen/X86/mmx-arith.ll
llvm/test/CodeGen/X86/mmx-bitcast.ll
llvm/test/CodeGen/X86/mmx-fold-zero.ll
llvm/test/CodeGen/X86/movmsk-cmp.ll
llvm/test/CodeGen/X86/ms-inline-asm-redundant-clobber.ll
llvm/test/CodeGen/X86/mul-constant-result.ll
llvm/test/CodeGen/X86/mul128.ll
llvm/test/CodeGen/X86/musttail-varargs.ll
llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll
llvm/test/CodeGen/X86/narrow_op-1.ll
llvm/test/CodeGen/X86/neg_fp.ll
llvm/test/CodeGen/X86/negate.ll
llvm/test/CodeGen/X86/negative-sin.ll
llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll
llvm/test/CodeGen/X86/no-sse-x86.ll
llvm/test/CodeGen/X86/nobt.ll
llvm/test/CodeGen/X86/nontemporal-loads.ll
llvm/test/CodeGen/X86/nontemporal.ll
llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
llvm/test/CodeGen/X86/packss.ll
llvm/test/CodeGen/X86/paddus.ll
llvm/test/CodeGen/X86/peep-test-1.ll
llvm/test/CodeGen/X86/peephole-fold-movsd.ll
llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
llvm/test/CodeGen/X86/pic-load-remat.ll
llvm/test/CodeGen/X86/pmul.ll
llvm/test/CodeGen/X86/pointer-vector.ll
llvm/test/CodeGen/X86/popcnt.ll
llvm/test/CodeGen/X86/pow.75.ll
llvm/test/CodeGen/X86/pow.ll
llvm/test/CodeGen/X86/pr13577.ll
llvm/test/CodeGen/X86/pr14161.ll
llvm/test/CodeGen/X86/pr15309.ll
llvm/test/CodeGen/X86/pr15981.ll
llvm/test/CodeGen/X86/pr21792.ll
llvm/test/CodeGen/X86/pr22774.ll
llvm/test/CodeGen/X86/pr23103.ll
llvm/test/CodeGen/X86/pr2326.ll
llvm/test/CodeGen/X86/pr23603.ll
llvm/test/CodeGen/X86/pr2585.ll
llvm/test/CodeGen/X86/pr2656.ll
llvm/test/CodeGen/X86/pr27591.ll
llvm/test/CodeGen/X86/pr29112.ll
llvm/test/CodeGen/X86/pr30290.ll
llvm/test/CodeGen/X86/pr30511.ll
llvm/test/CodeGen/X86/pr31045.ll
llvm/test/CodeGen/X86/pr31956.ll
llvm/test/CodeGen/X86/pr32282.ll
llvm/test/CodeGen/X86/pr32284.ll
llvm/test/CodeGen/X86/pr32329.ll
llvm/test/CodeGen/X86/pr32345.ll
llvm/test/CodeGen/X86/pr32368.ll
llvm/test/CodeGen/X86/pr32420.ll
llvm/test/CodeGen/X86/pr32451.ll
llvm/test/CodeGen/X86/pr32588.ll
llvm/test/CodeGen/X86/pr32659.ll
llvm/test/CodeGen/X86/pr33010.ll
llvm/test/CodeGen/X86/pr33290.ll
llvm/test/CodeGen/X86/pr33828.ll
llvm/test/CodeGen/X86/pr33960.ll
llvm/test/CodeGen/X86/pr34080-2.ll
llvm/test/CodeGen/X86/pr34080.ll
llvm/test/CodeGen/X86/pr34088.ll
llvm/test/CodeGen/X86/pr34137.ll
llvm/test/CodeGen/X86/pr34177.ll
llvm/test/CodeGen/X86/pr34271-1.ll
llvm/test/CodeGen/X86/pr34271.ll
llvm/test/CodeGen/X86/pr34292.ll
llvm/test/CodeGen/X86/pr34381.ll
llvm/test/CodeGen/X86/pr34421.ll
llvm/test/CodeGen/X86/pr34605.ll
llvm/test/CodeGen/X86/pr34629.ll
llvm/test/CodeGen/X86/pr34634.ll
llvm/test/CodeGen/X86/pr34653.ll
llvm/test/CodeGen/X86/pr35316.ll
llvm/test/CodeGen/X86/pr35443.ll
llvm/test/CodeGen/X86/pr35761.ll
llvm/test/CodeGen/X86/pr35763.ll
llvm/test/CodeGen/X86/pr35765.ll
llvm/test/CodeGen/X86/pr36312.ll
llvm/test/CodeGen/X86/pr36553.ll
llvm/test/CodeGen/X86/pr36865.ll
llvm/test/CodeGen/X86/pr37820.ll
llvm/test/CodeGen/X86/pr37826.ll
llvm/test/CodeGen/X86/pr37916.ll
llvm/test/CodeGen/X86/pr38743.ll
llvm/test/CodeGen/X86/pr38803.ll
llvm/test/CodeGen/X86/pr38865-2.ll
llvm/test/CodeGen/X86/pr40529.ll
llvm/test/CodeGen/X86/pr40539.ll
llvm/test/CodeGen/X86/pr40891.ll
llvm/test/CodeGen/X86/pr42064.ll
llvm/test/CodeGen/X86/pr43157.ll
llvm/test/CodeGen/X86/pr43509.ll
llvm/test/CodeGen/X86/pr43529.ll
llvm/test/CodeGen/X86/pr43952.ll
llvm/test/CodeGen/X86/pr44140.ll
llvm/test/CodeGen/X86/pr44396.ll
llvm/test/CodeGen/X86/pr44412.ll
llvm/test/CodeGen/X86/pr44749.ll
llvm/test/CodeGen/X86/pr45067.ll
llvm/test/CodeGen/X86/pr45995.ll
llvm/test/CodeGen/X86/pr46527.ll
llvm/test/CodeGen/X86/pr46585.ll
llvm/test/CodeGen/X86/pr47000.ll
llvm/test/CodeGen/X86/pr47299.ll
llvm/test/CodeGen/X86/pr47482.ll
llvm/test/CodeGen/X86/pr47517.ll
llvm/test/CodeGen/X86/pr48215.ll
llvm/test/CodeGen/X86/pr49451.ll
llvm/test/CodeGen/X86/pr50254.ll
llvm/test/CodeGen/X86/pr5145.ll
llvm/test/CodeGen/X86/pr9517.ll
llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll
llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll
llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
llvm/test/CodeGen/X86/prefer-avx256-mulo.ll
llvm/test/CodeGen/X86/prefer-avx256-trunc.ll
llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
llvm/test/CodeGen/X86/promote-cmp.ll
llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
llvm/test/CodeGen/X86/recip-fastmath2.ll
llvm/test/CodeGen/X86/remat-constant.ll
llvm/test/CodeGen/X86/ret-mmx.ll
llvm/test/CodeGen/X86/reverse_branches.ll
llvm/test/CodeGen/X86/rotate_vec.ll
llvm/test/CodeGen/X86/rtm.ll
llvm/test/CodeGen/X86/sad.ll
llvm/test/CodeGen/X86/sadd_sat.ll
llvm/test/CodeGen/X86/sadd_sat_vec.ll
llvm/test/CodeGen/X86/sandybridge-loads.ll
llvm/test/CodeGen/X86/sar_fold64.ll
llvm/test/CodeGen/X86/sat-add.ll
llvm/test/CodeGen/X86/scalar-fp-to-i32.ll
llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
llvm/test/CodeGen/X86/scalar-int-to-fp.ll
llvm/test/CodeGen/X86/scalarize-fp.ll
llvm/test/CodeGen/X86/sdiv-exact.ll
llvm/test/CodeGen/X86/select-of-fp-constants.ll
llvm/test/CodeGen/X86/select-sra.ll
llvm/test/CodeGen/X86/select.ll
llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
llvm/test/CodeGen/X86/semantic-interposition-asm.ll
llvm/test/CodeGen/X86/setcc-lowering.ll
llvm/test/CodeGen/X86/setcc-narrowing.ll
llvm/test/CodeGen/X86/setcc.ll
llvm/test/CodeGen/X86/shadow-stack.ll
llvm/test/CodeGen/X86/shift-and.ll
llvm/test/CodeGen/X86/shift-combine.ll
llvm/test/CodeGen/X86/shift-logic.ll
llvm/test/CodeGen/X86/shift-parts.ll
llvm/test/CodeGen/X86/shift-pcmp.ll
llvm/test/CodeGen/X86/shift_minsize.ll
llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
llvm/test/CodeGen/X86/shrink-compare-pgso.ll
llvm/test/CodeGen/X86/shrink-compare.ll
llvm/test/CodeGen/X86/shrink-const.ll
llvm/test/CodeGen/X86/shrink-fp-const1.ll
llvm/test/CodeGen/X86/shrink-fp-const2.ll
llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll
llvm/test/CodeGen/X86/shrink_vmul.ll
llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
llvm/test/CodeGen/X86/sibcall.ll
llvm/test/CodeGen/X86/signbit-shift.ll
llvm/test/CodeGen/X86/sink-addsub-of-const.ll
llvm/test/CodeGen/X86/small-byval-memcpy.ll
llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll
llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/speculative-load-hardening.ll
llvm/test/CodeGen/X86/splat-for-size.ll
llvm/test/CodeGen/X86/split-eh-lpad-edges.ll
llvm/test/CodeGen/X86/split-vector-rem.ll
llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
llvm/test/CodeGen/X86/sqrt-fastmath.ll
llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll
llvm/test/CodeGen/X86/srem-vector-lkk.ll
llvm/test/CodeGen/X86/sse-fcopysign.ll
llvm/test/CodeGen/X86/sse-load-ret.ll
llvm/test/CodeGen/X86/sse-minmax.ll
llvm/test/CodeGen/X86/sse-varargs.ll
llvm/test/CodeGen/X86/sse1-fcopysign.ll
llvm/test/CodeGen/X86/sse1.ll
llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
llvm/test/CodeGen/X86/sse2.ll
llvm/test/CodeGen/X86/sse3.ll
llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
llvm/test/CodeGen/X86/sse41.ll
llvm/test/CodeGen/X86/ssub_sat.ll
llvm/test/CodeGen/X86/ssub_sat_vec.ll
llvm/test/CodeGen/X86/stack-folding-int-avx2.ll
llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
llvm/test/CodeGen/X86/statepoint-allocas.ll
llvm/test/CodeGen/X86/statepoint-call-lowering.ll
llvm/test/CodeGen/X86/statepoint-duplicates-export.ll
llvm/test/CodeGen/X86/statepoint-gc-live.ll
llvm/test/CodeGen/X86/statepoint-invoke.ll
llvm/test/CodeGen/X86/statepoint-live-in-remat.ll
llvm/test/CodeGen/X86/statepoint-live-in.ll
llvm/test/CodeGen/X86/statepoint-no-realign-stack.ll
llvm/test/CodeGen/X86/statepoint-regs.ll
llvm/test/CodeGen/X86/statepoint-spill-slot-size-promotion.ll
llvm/test/CodeGen/X86/statepoint-uniqueing.ll
llvm/test/CodeGen/X86/statepoint-vector.ll
llvm/test/CodeGen/X86/statepoint-vreg.ll
llvm/test/CodeGen/X86/store-narrow.ll
llvm/test/CodeGen/X86/sub-with-overflow.ll
llvm/test/CodeGen/X86/subvector-broadcast.ll
llvm/test/CodeGen/X86/swift-return.ll
llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
llvm/test/CodeGen/X86/tail-opts.ll
llvm/test/CodeGen/X86/tail-threshold.ll
llvm/test/CodeGen/X86/tailcall-64.ll
llvm/test/CodeGen/X86/tailcc-fastcc.ll
llvm/test/CodeGen/X86/test-shrink-bug.ll
llvm/test/CodeGen/X86/test-shrink.ll
llvm/test/CodeGen/X86/test-vs-bittest.ll
llvm/test/CodeGen/X86/tls-pie.ll
llvm/test/CodeGen/X86/trunc-and.ll
llvm/test/CodeGen/X86/trunc-ext-ld-st.ll
llvm/test/CodeGen/X86/twoaddr-coalesce.ll
llvm/test/CodeGen/X86/udiv_fix.ll
llvm/test/CodeGen/X86/uint64-to-float.ll
llvm/test/CodeGen/X86/uint_to_fp-2.ll
llvm/test/CodeGen/X86/uint_to_fp-3.ll
llvm/test/CodeGen/X86/uintr-intrinsics.ll
llvm/test/CodeGen/X86/umul-with-carry.ll
llvm/test/CodeGen/X86/umul-with-overflow.ll
llvm/test/CodeGen/X86/unaligned-load.ll
llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll
llvm/test/CodeGen/X86/urem-power-of-two.ll
llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
llvm/test/CodeGen/X86/urem-vector-lkk.ll
llvm/test/CodeGen/X86/use-add-flags.ll
llvm/test/CodeGen/X86/usub_sat_vec.ll
llvm/test/CodeGen/X86/v8i1-masks.ll
llvm/test/CodeGen/X86/var-permute-128.ll
llvm/test/CodeGen/X86/var-permute-256.ll
llvm/test/CodeGen/X86/var-permute-512.ll
llvm/test/CodeGen/X86/vec-copysign-avx512.ll
llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll
llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
llvm/test/CodeGen/X86/vec_cast3.ll
llvm/test/CodeGen/X86/vec_ctbits.ll
llvm/test/CodeGen/X86/vec_ext_inreg.ll
llvm/test/CodeGen/X86/vec_extract.ll
llvm/test/CodeGen/X86/vec_fabs.ll
llvm/test/CodeGen/X86/vec_fneg.ll
llvm/test/CodeGen/X86/vec_fp_to_int.ll
llvm/test/CodeGen/X86/vec_fpext.ll
llvm/test/CodeGen/X86/vec_fptrunc.ll
llvm/test/CodeGen/X86/vec_insert-7.ll
llvm/test/CodeGen/X86/vec_insert-mmx.ll
llvm/test/CodeGen/X86/vec_int_to_fp.ll
llvm/test/CodeGen/X86/vec_logical.ll
llvm/test/CodeGen/X86/vec_minmax_match.ll
llvm/test/CodeGen/X86/vec_partial.ll
llvm/test/CodeGen/X86/vec_reassociate.ll
llvm/test/CodeGen/X86/vec_setcc-2.ll
llvm/test/CodeGen/X86/vec_shift4.ll
llvm/test/CodeGen/X86/vec_smulo.ll
llvm/test/CodeGen/X86/vec_ss_load_fold.ll
llvm/test/CodeGen/X86/vec_umulo.ll
llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll
llvm/test/CodeGen/X86/vec_zero_cse.ll
llvm/test/CodeGen/X86/vector-bitreverse.ll
llvm/test/CodeGen/X86/vector-compare-simplify.ll
llvm/test/CodeGen/X86/vector-ext-logic.ll
llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
llvm/test/CodeGen/X86/vector-intrinsics.ll
llvm/test/CodeGen/X86/vector-lzcnt-128.ll
llvm/test/CodeGen/X86/vector-lzcnt-256.ll
llvm/test/CodeGen/X86/vector-lzcnt-512.ll
llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
llvm/test/CodeGen/X86/vector-mul.ll
llvm/test/CodeGen/X86/vector-narrow-binop.ll
llvm/test/CodeGen/X86/vector-pack-128.ll
llvm/test/CodeGen/X86/vector-pack-256.ll
llvm/test/CodeGen/X86/vector-pack-512.ll
llvm/test/CodeGen/X86/vector-partial-undef.ll
llvm/test/CodeGen/X86/vector-pcmp.ll
llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
llvm/test/CodeGen/X86/vector-popcnt-128.ll
llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
llvm/test/CodeGen/X86/vector-popcnt-256.ll
llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
llvm/test/CodeGen/X86/vector-popcnt-512.ll
llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
llvm/test/CodeGen/X86/vector-reduce-fadd.ll
llvm/test/CodeGen/X86/vector-reduce-fmul.ll
llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
llvm/test/CodeGen/X86/vector-reduce-smax.ll
llvm/test/CodeGen/X86/vector-reduce-smin.ll
llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
llvm/test/CodeGen/X86/vector-rem.ll
llvm/test/CodeGen/X86/vector-rotate-256.ll
llvm/test/CodeGen/X86/vector-rotate-512.ll
llvm/test/CodeGen/X86/vector-sext.ll
llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
llvm/test/CodeGen/X86/vector-shuffle-mmx.ll
llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
llvm/test/CodeGen/X86/vector-tzcnt-128.ll
llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
llvm/test/CodeGen/X86/vector-zext.ll
llvm/test/CodeGen/X86/vmovq.ll
llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
llvm/test/CodeGen/X86/vselect-avx.ll
llvm/test/CodeGen/X86/vselect-constants.ll
llvm/test/CodeGen/X86/vselect-pcmp.ll
llvm/test/CodeGen/X86/vselect-zero.ll
llvm/test/CodeGen/X86/vselect.ll
llvm/test/CodeGen/X86/vshift-6.ll
llvm/test/CodeGen/X86/vshli-simplify-demanded-bits.ll
llvm/test/CodeGen/X86/widen_cast-5.ll
llvm/test/CodeGen/X86/widen_load-2.ll
llvm/test/CodeGen/X86/widen_mul.ll
llvm/test/CodeGen/X86/x86-64-baseptr.ll
llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll
llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
llvm/test/CodeGen/X86/x86-64-mem.ll
llvm/test/CodeGen/X86/x86-64-pic-4.ll
llvm/test/CodeGen/X86/x86-64-pic-5.ll
llvm/test/CodeGen/X86/x86-64-pic-6.ll
llvm/test/CodeGen/X86/x86-64-pic-7.ll
llvm/test/CodeGen/X86/x86-64-pic-8.ll
llvm/test/CodeGen/X86/x86-64-pic-9.ll
llvm/test/CodeGen/X86/x86-64-psub.ll
llvm/test/CodeGen/X86/x86-64-ret0.ll
llvm/test/CodeGen/X86/x86-64-varargs.ll
llvm/test/CodeGen/X86/x86-interleaved-access.ll
llvm/test/CodeGen/X86/x86-interrupt_cc.ll
llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
llvm/test/CodeGen/X86/x86-store-gv-addr.ll
llvm/test/CodeGen/X86/xchg-nofold.ll
llvm/test/CodeGen/X86/xop-mask-comments.ll
llvm/test/CodeGen/X86/zext-fold.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll b/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
index fc57d506147e9..771a5124a1fa9 100644
--- a/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
+++ b/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
@@ -10,7 +10,7 @@ target triple = "i686-unknown-unknown"
define i32 @test5(i32 %B, i8 %C) {
; CHECK-LABEL: test5:
-; CHECK: # %bb.0:
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl A, %eax
diff --git a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
index b231a258e9d1e..5ad7d50ca1fc6 100644
--- a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
+++ b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -139,7 +139,7 @@ define dso_local void @foo(i32* %a0, i32* %a1, i32* %a2, i32* %a3, i32* %a4, i32
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: addss %xmm0, %xmm2
; CHECK-NEXT: addss %xmm1, %xmm2
-; CHECK-NEXT: movss %xmm2, {{.*}}(%rip)
+; CHECK-NEXT: movss %xmm2, i6000(%rip)
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: jne .LBB0_36
; CHECK-NEXT: jmp .LBB0_9
diff --git a/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll b/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
index edd2f67fd10ed..b134db36858cc 100644
--- a/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
+++ b/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
@@ -9,7 +9,7 @@ define i32 @main() {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: ## InlineAsm Start
-; CHECK-NEXT: bsrl LCPI0_0, %eax
+; CHECK-NEXT: bsrl {{\.?LCPI[0-9]+_[0-9]+}}, %eax
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll b/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
index cb09d8f22cc59..73cb72ca19df0 100644
--- a/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
+++ b/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
@@ -9,7 +9,7 @@ define void @foo(<1 x i64> %A, <1 x i64> %B) nounwind {
; CHECK-NEXT: movq %rsi, %mm0
; CHECK-NEXT: movq %rdi, %mm1
; CHECK-NEXT: paddusw %mm0, %mm1
-; CHECK-NEXT: movq _R@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _R at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq %mm1, (%rax)
; CHECK-NEXT: emms
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll b/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
index 645c6478e6781..dba27937634a2 100644
--- a/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
+++ b/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
@@ -55,7 +55,7 @@ define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %
; CHECK-NEXT: cmpl $-1, %ecx
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: LBB0_3: ## %bb4
-; CHECK-NEXT: movq _PyArray_API@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _PyArray_API at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: movq 16(%rax), %rax
; CHECK-NEXT: jmp LBB0_10
@@ -66,7 +66,7 @@ define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %
; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: LBB0_6: ## %bb35
-; CHECK-NEXT: movq _PyUFunc_API@{{.*}}(%rip), %rbp
+; CHECK-NEXT: movq _PyUFunc_API at GOTPCREL(%rip), %rbp
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: callq *216(%rax)
; CHECK-NEXT: movb {{[0-9]+}}(%rsp), %dl
@@ -86,7 +86,7 @@ define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: ## %bb.9: ## %cond_next
-; CHECK-NEXT: movq _PyArray_API@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _PyArray_API at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: movq 80(%rax), %rax
; CHECK-NEXT: LBB0_10: ## %bb4
@@ -128,7 +128,7 @@ define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %
; CHECK-NEXT: ## %bb.19: ## %cond_true61
; CHECK-NEXT: movl %eax, %ebx
; CHECK-NEXT: movq (%rbp), %rax
-; CHECK-NEXT: movq _.str5@{{.*}}(%rip), %rdi
+; CHECK-NEXT: movq _.str5 at GOTPCREL(%rip), %rdi
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
@@ -152,7 +152,7 @@ define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.22: ## %cond_next97
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: movq _PyArray_API@{{.*}}(%rip), %rbp
+; CHECK-NEXT: movq _PyArray_API at GOTPCREL(%rip), %rbp
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: movq 200(%rax), %rdi
; CHECK-NEXT: xorl %esi, %esi
diff --git a/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll b/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
index b2d8016915087..9e6a17a3900b0 100644
--- a/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
+++ b/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
@@ -13,7 +13,7 @@ define fastcc void @sample_3d_linear(%struct.gl_texture_object* %tObj, %struct.g
; CHECK-NEXT: movl 0, %esi
; CHECK-NEXT: pushl $0
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
-; CHECK-NEXT: calll floorf
+; CHECK-NEXT: calll floorf at PLT
; CHECK-NEXT: fstp %st(0)
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
diff --git a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
index b8729a200a329..c6623a3bd529e 100644
--- a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
; Make sure xorl operands are 32-bit registers.
diff --git a/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll b/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
index a931220cb19ad..3b52c57dca20f 100644
--- a/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
@@ -21,7 +21,7 @@ define void @testit63_entry_2E_ce() nounwind {
; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl g1s63+60, %eax
; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)
-; CHECK-NEXT: calll test63
+; CHECK-NEXT: calll test63 at PLT
; CHECK-NEXT: addl $64, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll b/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
index 43dc21972edb5..8411a409a522d 100644
--- a/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
+++ b/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
@@ -17,7 +17,7 @@ define i32 @test(double %p) nounwind {
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %bb
-; CHECK-NEXT: calll test2
+; CHECK-NEXT: calll test2 at PLT
; CHECK-NEXT: movl $17, %eax
; CHECK-NEXT: retl
%tmp5 = fcmp uno double %p, 0.000000e+00
diff --git a/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll b/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll
index 799ba0582aac2..d5ceafbcde7f9 100644
--- a/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll
+++ b/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll
@@ -16,7 +16,7 @@ define i32 @main() nounwind {
; CHECK-NEXT: movl $.str, %edi
; CHECK-NEXT: movl %ebx, %esi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq printf
+; CHECK-NEXT: callq printf at PLT
; CHECK-NEXT: addl $-10, %ebx
; CHECK-NEXT: cmpl $1, %ebx
; CHECK-NEXT: jne .LBB0_1
diff --git a/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll b/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
index 67155f3936fa2..c21b6c294b58b 100644
--- a/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
+++ b/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
@@ -32,7 +32,7 @@ define i32 @func_44(i16 signext %p_46) nounwind {
; SOURCE-SCHED-NEXT: pushl $0
; SOURCE-SCHED-NEXT: pushl %ecx
; SOURCE-SCHED-NEXT: pushl %edx
-; SOURCE-SCHED-NEXT: calll func_48
+; SOURCE-SCHED-NEXT: calll func_48 at PLT
; SOURCE-SCHED-NEXT: addl $28, %esp
; SOURCE-SCHED-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll b/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll
index 4c81df7de61ac..f24bf6eafe89f 100644
--- a/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll
+++ b/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll
@@ -11,7 +11,7 @@ define i32 @main() nounwind {
; CHECK-NEXT: movl g_407, %eax
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: calll func_45
+; CHECK-NEXT: calll func_45 at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll b/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
index 7ec3b23017bb0..59afc7bd9c9d7 100644
--- a/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
+++ b/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
@@ -13,7 +13,7 @@ define i32 @main() {
; CHECK: ## %bb.0: ## %entry_nan.main
; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: fldl LCPI0_0
+; CHECK-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
diff --git a/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll b/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
index 108d8800a3c66..ef4a8cda097fe 100644
--- a/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
+++ b/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
@@ -18,11 +18,11 @@ define i32 @main() {
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
-; CHECK-NEXT: fldt LCPI0_0
+; CHECK-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
-; CHECK-NEXT: fldt LCPI0_1
+; CHECK-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
diff --git a/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll b/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
index 44ea429bb6333..ef04effc0fb8e 100644
--- a/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
+++ b/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
@@ -6,7 +6,7 @@ define void @f(float %wt) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl $44
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
-; CHECK-NEXT: calll g
+; CHECK-NEXT: calll g at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: xorps %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll b/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
index 6944f9b0993bf..1a4bb99663c54 100644
--- a/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
+++ b/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
@@ -10,7 +10,7 @@ define i32 @a(i32 %x) nounwind {
; CHECK-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: jns .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: calll b
+; CHECK-NEXT: calll b at PLT
; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll b/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll
index b7e733ec4fe67..58daa550322ea 100644
--- a/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll
+++ b/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll
@@ -9,11 +9,11 @@ define void @foo() nounwind {
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: calll frob
+; CHECK-NEXT: calll frob at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: leal X(%esp), %eax
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: calll borf
+; CHECK-NEXT: calll borf at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl
@@ -35,11 +35,11 @@ define void @bar(i32 %i) nounwind {
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: calll frob
+; CHECK-NEXT: calll frob at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: leal X(%esp,%esi,4), %eax
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: calll borf
+; CHECK-NEXT: calll borf at PLT
; CHECK-NEXT: addl $44, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll b/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll
index a45751f1ed93d..3a151e898048a 100644
--- a/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll
+++ b/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll
@@ -14,7 +14,7 @@ define void @x(i288 %i) nounwind {
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
-; CHECK-NEXT: calll add
+; CHECK-NEXT: calll add at PLT
; CHECK-NEXT: addl $36, %esp
; CHECK-NEXT: retl
call void @add(i288 %i)
diff --git a/llvm/test/CodeGen/X86/2009-04-12-picrel.ll b/llvm/test/CodeGen/X86/2009-04-12-picrel.ll
index ce875e5cee7c4..050538d6eeff3 100644
--- a/llvm/test/CodeGen/X86/2009-04-12-picrel.ll
+++ b/llvm/test/CodeGen/X86/2009-04-12-picrel.ll
@@ -8,7 +8,7 @@ define void @off01(i64 %i) nounwind {
; CHECK-LABEL: off01:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: leaq dst+64(,%rdi,4), %rax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
+; CHECK-NEXT: movq %rax, ptr(%rip)
; CHECK-NEXT: retq
entry:
%.sum = add i64 %i, 16
diff --git a/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll b/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
index f4b651365c742..68465a072fb04 100644
--- a/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
+++ b/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
@@ -9,13 +9,13 @@ define fastcc i8* @_D3gcx2GC12callocNoSyncMFmkZPv() nounwind {
; CHECK-LABEL: _D3gcx2GC12callocNoSyncMFmkZPv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
-; CHECK-NEXT: calll _D3gcx2GC12mallocNoSyncMFmkZPv
+; CHECK-NEXT: calll _D3gcx2GC12mallocNoSyncMFmkZPv at PLT
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl $2
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: calll memset
+; CHECK-NEXT: calll memset at PLT
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll b/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
index a74b814304ff9..214da14322d51 100644
--- a/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
+++ b/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
@@ -38,7 +38,7 @@ define internal fastcc i32 @foo(i64 %bar) nounwind ssp {
; CHECK-NEXT: cmpq $25, %rdi
; CHECK-NEXT: ja LBB0_2
; CHECK-NEXT: ## %bb.1: ## %bb49
-; CHECK-NEXT: leaq {{.*}}(%rip), %rax
+; CHECK-NEXT: leaq LJTI0_0(%rip), %rax
; CHECK-NEXT: movslq (%rax,%rdi,4), %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: jmpq *%rcx
diff --git a/llvm/test/CodeGen/X86/20090313-signext.ll b/llvm/test/CodeGen/X86/20090313-signext.ll
index 688cb07ac8e4f..b6130426b3595 100644
--- a/llvm/test/CodeGen/X86/20090313-signext.ll
+++ b/llvm/test/CodeGen/X86/20090313-signext.ll
@@ -10,7 +10,7 @@ define signext i16 @f() nounwind {
; CHECK-NEXT: callq h at PLT
; CHECK-NEXT: movswl %ax, %edi
; CHECK-NEXT: callq g at PLT
-; CHECK-NEXT: movq x@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq x at GOTPCREL(%rip), %rax
; CHECK-NEXT: movzwl (%rax), %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll b/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
index 63b575487b40d..dde6a6d3f493e 100644
--- a/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
+++ b/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
@@ -11,20 +11,20 @@ define dso_local i32 @main() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpq {{.*}}(%rip), %rax
+; CHECK-NEXT: cmpq g_16(%rip), %rax
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: testb $-106, %al
; CHECK-NEXT: jle .LBB0_1
; CHECK-NEXT: # %bb.2: # %if.then
-; CHECK-NEXT: movl $1, {{.*}}(%rip)
+; CHECK-NEXT: movl $1, g_38(%rip)
; CHECK-NEXT: movl $1, %esi
; CHECK-NEXT: jmp .LBB0_3
; CHECK-NEXT: .LBB0_1: # %entry.if.end_crit_edge
-; CHECK-NEXT: movl {{.*}}(%rip), %esi
+; CHECK-NEXT: movl g_38(%rip), %esi
; CHECK-NEXT: .LBB0_3: # %if.end
; CHECK-NEXT: movl $.L.str, %edi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq printf
+; CHECK-NEXT: callq printf at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll b/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
index 5578d2e897fda..9ca733abbb084 100644
--- a/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
+++ b/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
@@ -17,8 +17,8 @@ target triple = "x86_64-unknown-linux-gnu"
define dso_local i32 @main() nounwind uwtable {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq {{.*}}(%rip), %rsi
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq i(%rip), %rsi
+; CHECK-NEXT: movq j(%rip), %rax
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: shrq $8, %rdx
; CHECK-NEXT: movsbl %al, %ecx
@@ -32,7 +32,7 @@ define dso_local i32 @main() nounwind uwtable {
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movd %eax, %xmm0
; CHECK-NEXT: pinsrb $1, %ecx, %xmm0
-; CHECK-NEXT: pextrw $0, %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: pextrw $0, %xmm0, res(%rip)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll b/llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
index 49e69aeab5109..fa811f02bd9af 100644
--- a/llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
@@ -4,17 +4,19 @@
define void @test_amx() {
; CHECK-LABEL: test_amx:
; CHECK: # %bb.0:
- call void @llvm.x86.tdpbssd(i8 3, i8 4, i8 7)
; CHECK-NEXT: tdpbssd %tmm7, %tmm4, %tmm3
+; CHECK-NEXT: tdpbsud %tmm7, %tmm4, %tmm3
+; CHECK-NEXT: tdpbusd %tmm7, %tmm0, %tmm3
+; CHECK-NEXT: tdpbuud %tmm1, %tmm4, %tmm3
+; CHECK-NEXT: tilerelease
+; CHECK-NEXT: retq
+ call void @llvm.x86.tdpbssd(i8 3, i8 4, i8 7)
call void @llvm.x86.tdpbsud(i8 3, i8 4, i8 7)
-; CHECK-NEXT: tdpbsud %tmm7, %tmm4, %tmm3
call void @llvm.x86.tdpbusd(i8 3, i8 0, i8 7)
-; CHECK-NEXT: tdpbusd %tmm7, %tmm0, %tmm3
call void @llvm.x86.tdpbuud(i8 3, i8 4, i8 1)
-; CHECK-NEXT: tdpbuud %tmm1, %tmm4, %tmm3
ret void
}
diff --git a/llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll b/llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
index 6b8e040abb9ab..9792f8b19af45 100644
--- a/llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
@@ -4,26 +4,28 @@
define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
; CHECK-LABEL: test_amx:
; CHECK: # %bb.0:
- call void @llvm.x86.ldtilecfg(i8* %pointer)
; CHECK-NEXT: ldtilecfg (%rdi)
+; CHECK-NEXT: sttilecfg (%rdi)
+; CHECK-NEXT: tilerelease
+; CHECK-NEXT: tilezero %tmm3
+; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm3
+; CHECK-NEXT: tileloaddt1 (%rsi,%rdx), %tmm3
+; CHECK-NEXT: tilestored %tmm3, (%rsi,%rdx)
+; CHECK-NEXT: tilerelease
+; CHECK-NEXT: retq
+ call void @llvm.x86.ldtilecfg(i8* %pointer)
call void @llvm.x86.sttilecfg(i8* %pointer)
-; CHECK-NEXT: sttilecfg (%rdi)
call void @llvm.x86.tilerelease()
-; CHECK-NEXT: tilerelease
call void @llvm.x86.tilezero(i8 3)
-; CHECK-NEXT: tilezero %tmm3
call void @llvm.x86.tileloadd64(i8 3, i8* %base, i64 %stride)
-; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm3
call void @llvm.x86.tileloaddt164(i8 3, i8* %base, i64 %stride)
-; CHECK-NEXT: tileloaddt1 (%rsi,%rdx), %tmm3
call void @llvm.x86.tilestored64(i8 3, i8* %base, i64 %stride)
-; CHECK-NEXT: tilestored %tmm3, (%rsi,%rdx)
ret void
}
diff --git a/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll b/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
index 75c44810551de..0519b6036db17 100644
--- a/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
+++ b/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
@@ -27,7 +27,7 @@ define cc 11 i32 @caller(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
; CHECK-NEXT: movl %ebx, %edi
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload
; CHECK-NEXT: movl %ebp, %esi
-; CHECK-NEXT: calll callee
+; CHECK-NEXT: calll callee at PLT
; CHECK-NEXT: leal (%eax,%ebx), %esi
; CHECK-NEXT: addl %ebp, %esi
; CHECK-NEXT: addl $12, %esp
diff --git a/llvm/test/CodeGen/X86/GlobalISel/fconstant.ll b/llvm/test/CodeGen/X86/GlobalISel/fconstant.ll
index 0b73b77307406..b3b247fac5ab1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/fconstant.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/fconstant.ll
@@ -8,7 +8,7 @@
define void @test_float(float* %a , float %b) {
; CHECK64_SMALL-LABEL: test_float:
; CHECK64_SMALL: # %bb.0: # %entry
-; CHECK64_SMALL-NEXT: movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
+; CHECK64_SMALL-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK64_SMALL-NEXT: addss %xmm0, %xmm1
; CHECK64_SMALL-NEXT: movd %xmm1, %eax
; CHECK64_SMALL-NEXT: movl %eax, (%rdi)
@@ -16,7 +16,7 @@ define void @test_float(float* %a , float %b) {
;
; CHECK64_LARGE-LABEL: test_float:
; CHECK64_LARGE: # %bb.0: # %entry
-; CHECK64_LARGE-NEXT: movabsq $.LCPI0_0, %rax
+; CHECK64_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; CHECK64_LARGE-NEXT: addss (%rax), %xmm0
; CHECK64_LARGE-NEXT: movd %xmm0, %eax
; CHECK64_LARGE-NEXT: movl %eax, (%rdi)
@@ -24,9 +24,9 @@ define void @test_float(float* %a , float %b) {
;
; CHECK32-LABEL: test_float:
; CHECK32: # %bb.0: # %entry
-; CHECK32-NEXT: movl 4(%esp), %eax
-; CHECK32-NEXT: movl 8(%esp), %ecx
-; CHECK32-NEXT: movss .LCPI0_0, %xmm0 # xmm0 = mem[0],zero,zero,zero
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK32-NEXT: movd %ecx, %xmm1
; CHECK32-NEXT: addss %xmm0, %xmm1
; CHECK32-NEXT: movd %xmm1, %ecx
diff --git a/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll b/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll
index 96bf593013011..f4f19352546ae 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll
@@ -9,7 +9,7 @@
define i32* @allocai32() {
; X64-LABEL: allocai32:
; X64: # %bb.0:
-; X64-NEXT: leaq -4(%rsp), %rax
+; X64-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
; X64-NEXT: retq
;
; X32-LABEL: allocai32:
@@ -23,7 +23,7 @@ define i32* @allocai32() {
;
; X32ABI-LABEL: allocai32:
; X32ABI: # %bb.0:
-; X32ABI-NEXT: leal -4(%rsp), %eax
+; X32ABI-NEXT: leal -{{[0-9]+}}(%rsp), %eax
; X32ABI-NEXT: retq
%ptr1 = alloca i32
ret i32* %ptr1
diff --git a/llvm/test/CodeGen/X86/PR40322.ll b/llvm/test/CodeGen/X86/PR40322.ll
index 22bf1822c65af..eee360d1ea033 100644
--- a/llvm/test/CodeGen/X86/PR40322.ll
+++ b/llvm/test/CodeGen/X86/PR40322.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-windows-gnu | FileCheck %s --check-prefix=CHECK-MINGW-X86
%struct.as = type { i32* }
diff --git a/llvm/test/CodeGen/X86/SwitchLowering.ll b/llvm/test/CodeGen/X86/SwitchLowering.ll
index 8439e3c7254c4..1c9477bf964f6 100644
--- a/llvm/test/CodeGen/X86/SwitchLowering.ll
+++ b/llvm/test/CodeGen/X86/SwitchLowering.ll
@@ -28,7 +28,7 @@ define i8* @FindChar(i8* %CurPtr) {
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
-; CHECK-NEXT: calll foo
+; CHECK-NEXT: calll foo at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: addl %edi, %esi
diff --git a/llvm/test/CodeGen/X86/TruncAssertZext.ll b/llvm/test/CodeGen/X86/TruncAssertZext.ll
index 5a7081437c302..38f4bcd2a2307 100644
--- a/llvm/test/CodeGen/X86/TruncAssertZext.ll
+++ b/llvm/test/CodeGen/X86/TruncAssertZext.ll
@@ -17,7 +17,7 @@ define i64 @main() {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: movabsq $-4294967041, %rcx # imm = 0xFFFFFFFF000000FF
; CHECK-NEXT: andq %rax, %rcx
; CHECK-NEXT: movl %ecx, %ecx
diff --git a/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll b/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll
index c29f7e8115847..ef601b9a5ad5b 100644
--- a/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll
+++ b/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll
@@ -35,7 +35,7 @@ define void @foo(i1 zeroext, i32) nounwind {
; X86-NEXT: leal (%eax,%eax,4), %eax
; X86-NEXT: leal 20(,%eax,4), %eax
; X86-NEXT: pushl %eax
-; X86-NEXT: calll bar
+; X86-NEXT: calll bar at PLT
; X86-NEXT: addl $4, %esp
; X86-NEXT: jmp .LBB0_2
;
@@ -55,7 +55,7 @@ define void @foo(i1 zeroext, i32) nounwind {
; X64-NEXT: cltq
; X64-NEXT: shlq $2, %rax
; X64-NEXT: leaq (%rax,%rax,4), %rdi
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: jmp .LBB0_2
br i1 %0, label %9, label %3
diff --git a/llvm/test/CodeGen/X86/alias-static-alloca.ll b/llvm/test/CodeGen/X86/alias-static-alloca.ll
index 01d5e506f6da8..ceb69830c8876 100644
--- a/llvm/test/CodeGen/X86/alias-static-alloca.ll
+++ b/llvm/test/CodeGen/X86/alias-static-alloca.ll
@@ -9,10 +9,10 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT: movl %esi, -8(%rsp)
-; CHECK-NEXT: movl %ecx, -16(%rsp)
-; CHECK-NEXT: movl %edi, -4(%rsp)
-; CHECK-NEXT: movl %edx, -12(%rsp)
+; CHECK-NEXT: movl %esi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl %edi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: leal (%rdi,%rsi), %eax
; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: addl %ecx, %eax
diff --git a/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll b/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll
index 7db20187d45d0..f9df99693288e 100644
--- a/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll
+++ b/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll
@@ -43,7 +43,7 @@ define void @test_statepoint(i32 addrspace(1)* %ptr) gc "statepoint-example" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: #noautopadding
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: #autopadding
; CHECK-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/alloca-overaligned.ll b/llvm/test/CodeGen/X86/alloca-overaligned.ll
index 8ac50d8eb82f2..263df8c8b8dd4 100644
--- a/llvm/test/CodeGen/X86/alloca-overaligned.ll
+++ b/llvm/test/CodeGen/X86/alloca-overaligned.ll
@@ -9,7 +9,7 @@ define void @test_natural() "no-realign-stack" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rsp, %rdi
-; CHECK-NEXT: callq capture
+; CHECK-NEXT: callq capture at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -29,7 +29,7 @@ define void @test_realign() {
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $64, %rsp
; CHECK-NEXT: movq %rsp, %rdi
-; CHECK-NEXT: callq capture
+; CHECK-NEXT: callq capture at PLT
; CHECK-NEXT: movq %rbp, %rsp
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: .cfi_def_cfa %rsp, 8
@@ -45,7 +45,7 @@ define void @test_norealign() "no-realign-stack" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rsp, %rdi
-; CHECK-NEXT: callq capture
+; CHECK-NEXT: callq capture at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/atomic-fp.ll b/llvm/test/CodeGen/X86/atomic-fp.ll
index a87da8428e0ae..9a58bf200a44a 100644
--- a/llvm/test/CodeGen/X86/atomic-fp.ll
+++ b/llvm/test/CodeGen/X86/atomic-fp.ll
@@ -200,7 +200,7 @@ define dso_local void @fadd_32g() nounwind {
; X86-SSE1-NEXT: movl glob32, %eax
; X86-SSE1-NEXT: movl %eax, (%esp)
; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE1-NEXT: addss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE1-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, glob32
@@ -224,15 +224,15 @@ define dso_local void @fadd_32g() nounwind {
; X64-SSE-LABEL: fadd_32g:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-SSE-NEXT: addss {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT: movss %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: addss glob32(%rip), %xmm0
+; X64-SSE-NEXT: movss %xmm0, glob32(%rip)
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: fadd_32g:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT: vmovss %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vaddss glob32(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vmovss %xmm0, glob32(%rip)
; X64-AVX-NEXT: retq
%i = load atomic i32, i32* bitcast (float* @glob32 to i32*) monotonic, align 4
%f = bitcast i32 %i to float
@@ -296,7 +296,7 @@ define dso_local void @fadd_64g() nounwind {
; X86-SSE2-NEXT: andl $-8, %esp
; X86-SSE2-NEXT: subl $8, %esp
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movsd %xmm0, (%esp)
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movlps %xmm0, glob64
@@ -311,7 +311,7 @@ define dso_local void @fadd_64g() nounwind {
; X86-AVX-NEXT: andl $-8, %esp
; X86-AVX-NEXT: subl $8, %esp
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X86-AVX-NEXT: vaddsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovsd %xmm0, (%esp)
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vmovlps %xmm0, glob64
@@ -322,15 +322,15 @@ define dso_local void @fadd_64g() nounwind {
; X64-SSE-LABEL: fadd_64g:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X64-SSE-NEXT: addsd {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT: movsd %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: addsd glob64(%rip), %xmm0
+; X64-SSE-NEXT: movsd %xmm0, glob64(%rip)
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: fadd_64g:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X64-AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT: vmovsd %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vaddsd glob64(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vmovsd %xmm0, glob64(%rip)
; X64-AVX-NEXT: retq
%i = load atomic i64, i64* bitcast (double* @glob64 to i64*) monotonic, align 8
%f = bitcast i64 %i to double
@@ -361,7 +361,7 @@ define dso_local void @fadd_32imm() nounwind {
; X86-SSE1-NEXT: movl -559038737, %eax
; X86-SSE1-NEXT: movl %eax, (%esp)
; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE1-NEXT: addss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE1-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, -559038737
@@ -459,7 +459,7 @@ define dso_local void @fadd_64imm() nounwind {
; X86-SSE2-NEXT: andl $-8, %esp
; X86-SSE2-NEXT: subl $8, %esp
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movsd %xmm0, (%esp)
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movlps %xmm0, -559038737
@@ -474,7 +474,7 @@ define dso_local void @fadd_64imm() nounwind {
; X86-AVX-NEXT: andl $-8, %esp
; X86-AVX-NEXT: subl $8, %esp
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X86-AVX-NEXT: vaddsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovsd %xmm0, (%esp)
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vmovlps %xmm0, -559038737
@@ -526,7 +526,7 @@ define dso_local void @fadd_32stack() nounwind {
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, (%esp)
; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE1-NEXT: addss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE1-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp)
@@ -628,7 +628,7 @@ define dso_local void @fadd_64stack() nounwind {
; X86-SSE2-NEXT: andl $-8, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movsd %xmm0, (%esp)
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
@@ -643,7 +643,7 @@ define dso_local void @fadd_64stack() nounwind {
; X86-AVX-NEXT: andl $-8, %esp
; X86-AVX-NEXT: subl $16, %esp
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X86-AVX-NEXT: vaddsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovsd %xmm0, (%esp)
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
diff --git a/llvm/test/CodeGen/X86/atomic-idempotent.ll b/llvm/test/CodeGen/X86/atomic-idempotent.ll
index 3ca0b808f2622..290414c39ef93 100644
--- a/llvm/test/CodeGen/X86/atomic-idempotent.ll
+++ b/llvm/test/CodeGen/X86/atomic-idempotent.ll
@@ -170,7 +170,7 @@ define i128 @or128(i128* %p) {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: xorl %esi, %esi
; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: callq __sync_fetch_and_or_16
+; X64-NEXT: callq __sync_fetch_and_or_16 at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: .cfi_def_cfa_offset 8
; X64-NEXT: retq
@@ -508,7 +508,7 @@ define void @or128_nouse_seq_cst(i128* %p) {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: xorl %esi, %esi
; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: callq __sync_fetch_and_or_16
+; X64-NEXT: callq __sync_fetch_and_or_16 at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .cfi_def_cfa_offset 8
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll b/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
index a918f6d2b64f7..3abed46f75d05 100644
--- a/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
+++ b/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
@@ -58,7 +58,6 @@ define i64 @atomic_max_i64() nounwind {
; PIC-NEXT: popl %edi
; PIC-NEXT: popl %ebx
; PIC-NEXT: retl
-; PIC-NEXT: ## -- End function
entry:
%max = atomicrmw max i64* @sc64, i64 5 acquire
ret i64 %max
@@ -112,7 +111,6 @@ define i64 @atomic_min_i64() nounwind {
; PIC-NEXT: popl %esi
; PIC-NEXT: popl %ebx
; PIC-NEXT: retl
-; PIC-NEXT: ## -- End function
entry:
%min = atomicrmw min i64* @sc64, i64 6 acquire
ret i64 %min
@@ -172,7 +170,6 @@ define i64 @atomic_umax_i64() nounwind {
; PIC-NEXT: popl %edi
; PIC-NEXT: popl %ebx
; PIC-NEXT: retl
-; PIC-NEXT: ## -- End function
entry:
%umax = atomicrmw umax i64* @sc64, i64 7 acquire
ret i64 %umax
@@ -226,7 +223,6 @@ define i64 @atomic_umin_i64() nounwind {
; PIC-NEXT: popl %esi
; PIC-NEXT: popl %ebx
; PIC-NEXT: retl
-; PIC-NEXT: ## -- End function
entry:
%umin = atomicrmw umin i64* @sc64, i64 8 acquire
ret i64 %umin
@@ -289,8 +285,6 @@ define void @tf_bug(i8* %ptr) nounwind {
; PIC-NEXT: popl %edi
; PIC-NEXT: popl %ebx
; PIC-NEXT: retl
-; PIC-NEXT: ## -- End function
-; PIC-NEXT: .zerofill __DATA,__bss,_id,8,3 ## @id
entry:
%tmp1 = atomicrmw add i64* @id, i64 1 seq_cst
%tmp2 = add i64 %tmp1, 1
diff --git a/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll b/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
index a3028e9ac7bb7..20d0016385da9 100644
--- a/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
+++ b/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
@@ -14,7 +14,7 @@ define void @store_fp128(fp128* %fptr, fp128 %v) {
; X64-NOSSE: # %bb.0:
; X64-NOSSE-NEXT: pushq %rax
; X64-NOSSE-NEXT: .cfi_def_cfa_offset 16
-; X64-NOSSE-NEXT: callq __sync_lock_test_and_set_16
+; X64-NOSSE-NEXT: callq __sync_lock_test_and_set_16 at PLT
; X64-NOSSE-NEXT: popq %rax
; X64-NOSSE-NEXT: .cfi_def_cfa_offset 8
; X64-NOSSE-NEXT: retq
@@ -26,7 +26,7 @@ define void @store_fp128(fp128* %fptr, fp128 %v) {
; X64-SSE-NEXT: movaps %xmm0, (%rsp)
; X64-SSE-NEXT: movq (%rsp), %rsi
; X64-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; X64-SSE-NEXT: callq __sync_lock_test_and_set_16
+; X64-SSE-NEXT: callq __sync_lock_test_and_set_16 at PLT
; X64-SSE-NEXT: addq $24, %rsp
; X64-SSE-NEXT: .cfi_def_cfa_offset 8
; X64-SSE-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/atomic-non-integer.ll b/llvm/test/CodeGen/X86/atomic-non-integer.ll
index a95a7fad5ce67..231b0776b7cf1 100644
--- a/llvm/test/CodeGen/X86/atomic-non-integer.ll
+++ b/llvm/test/CodeGen/X86/atomic-non-integer.ll
@@ -172,7 +172,7 @@ define void @store_fp128(fp128* %fptr, fp128 %v) {
; X64-SSE-NEXT: movaps %xmm0, (%rsp)
; X64-SSE-NEXT: movq (%rsp), %rsi
; X64-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; X64-SSE-NEXT: callq __sync_lock_test_and_set_16
+; X64-SSE-NEXT: callq __sync_lock_test_and_set_16 at PLT
; X64-SSE-NEXT: addq $24, %rsp
; X64-SSE-NEXT: .cfi_def_cfa_offset 8
; X64-SSE-NEXT: retq
@@ -184,7 +184,7 @@ define void @store_fp128(fp128* %fptr, fp128 %v) {
; X64-AVX-NEXT: vmovaps %xmm0, (%rsp)
; X64-AVX-NEXT: movq (%rsp), %rsi
; X64-AVX-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; X64-AVX-NEXT: callq __sync_lock_test_and_set_16
+; X64-AVX-NEXT: callq __sync_lock_test_and_set_16 at PLT
; X64-AVX-NEXT: addq $24, %rsp
; X64-AVX-NEXT: .cfi_def_cfa_offset 8
; X64-AVX-NEXT: retq
@@ -483,7 +483,7 @@ define fp128 @load_fp128(fp128* %fptr) {
; X64-SSE-NEXT: xorl %edx, %edx
; X64-SSE-NEXT: xorl %ecx, %ecx
; X64-SSE-NEXT: xorl %r8d, %r8d
-; X64-SSE-NEXT: callq __sync_val_compare_and_swap_16
+; X64-SSE-NEXT: callq __sync_val_compare_and_swap_16 at PLT
; X64-SSE-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movq %rax, (%rsp)
; X64-SSE-NEXT: movaps (%rsp), %xmm0
@@ -499,7 +499,7 @@ define fp128 @load_fp128(fp128* %fptr) {
; X64-AVX-NEXT: xorl %edx, %edx
; X64-AVX-NEXT: xorl %ecx, %ecx
; X64-AVX-NEXT: xorl %r8d, %r8d
-; X64-AVX-NEXT: callq __sync_val_compare_and_swap_16
+; X64-AVX-NEXT: callq __sync_val_compare_and_swap_16 at PLT
; X64-AVX-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
; X64-AVX-NEXT: movq %rax, (%rsp)
; X64-AVX-NEXT: vmovaps (%rsp), %xmm0
diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll
index f5eaa6f2409a8..5cfb7a3320c7e 100644
--- a/llvm/test/CodeGen/X86/atomic-unordered.ll
+++ b/llvm/test/CodeGen/X86/atomic-unordered.ll
@@ -321,7 +321,7 @@ define i256 @load_i256(i256* %ptr) {
; CHECK-O0-NEXT: movl $32, %edi
; CHECK-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; CHECK-O0-NEXT: xorl %ecx, %ecx
-; CHECK-O0-NEXT: callq __atomic_load
+; CHECK-O0-NEXT: callq __atomic_load at PLT
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; CHECK-O0-NEXT: movq {{[0-9]+}}(%rsp), %rcx
@@ -347,7 +347,7 @@ define i256 @load_i256(i256* %ptr) {
; CHECK-O3-NEXT: movq %rsp, %rdx
; CHECK-O3-NEXT: movl $32, %edi
; CHECK-O3-NEXT: xorl %ecx, %ecx
-; CHECK-O3-NEXT: callq __atomic_load
+; CHECK-O3-NEXT: callq __atomic_load at PLT
; CHECK-O3-NEXT: vmovups (%rsp), %ymm0
; CHECK-O3-NEXT: vmovups %ymm0, (%rbx)
; CHECK-O3-NEXT: movq %rbx, %rax
@@ -377,7 +377,7 @@ define void @store_i256(i256* %ptr, i256 %v) {
; CHECK-O0-NEXT: movq %r8, {{[0-9]+}}(%rsp)
; CHECK-O0-NEXT: movl $32, %edi
; CHECK-O0-NEXT: xorl %ecx, %ecx
-; CHECK-O0-NEXT: callq __atomic_store
+; CHECK-O0-NEXT: callq __atomic_store at PLT
; CHECK-O0-NEXT: addq $40, %rsp
; CHECK-O0-NEXT: .cfi_def_cfa_offset 8
; CHECK-O0-NEXT: retq
@@ -395,7 +395,7 @@ define void @store_i256(i256* %ptr, i256 %v) {
; CHECK-O3-NEXT: movl $32, %edi
; CHECK-O3-NEXT: movq %rax, %rsi
; CHECK-O3-NEXT: xorl %ecx, %ecx
-; CHECK-O3-NEXT: callq __atomic_store
+; CHECK-O3-NEXT: callq __atomic_store at PLT
; CHECK-O3-NEXT: addq $40, %rsp
; CHECK-O3-NEXT: .cfi_def_cfa_offset 8
; CHECK-O3-NEXT: retq
@@ -2379,7 +2379,7 @@ define i64 @fold_constant(i64 %arg) {
; CHECK-O3-LABEL: fold_constant:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movq %rdi, %rax
-; CHECK-O3-NEXT: addq {{.*}}(%rip), %rax
+; CHECK-O3-NEXT: addq Constant(%rip), %rax
; CHECK-O3-NEXT: retq
%v = load atomic i64, i64* @Constant unordered, align 8
%ret = add i64 %v, %arg
@@ -2389,14 +2389,14 @@ define i64 @fold_constant(i64 %arg) {
define i64 @fold_constant_clobber(i64* %p, i64 %arg) {
; CHECK-O0-LABEL: fold_constant_clobber:
; CHECK-O0: # %bb.0:
-; CHECK-O0-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-O0-NEXT: movq Constant(%rip), %rax
; CHECK-O0-NEXT: movq $5, (%rdi)
; CHECK-O0-NEXT: addq %rsi, %rax
; CHECK-O0-NEXT: retq
;
; CHECK-O3-CUR-LABEL: fold_constant_clobber:
; CHECK-O3-CUR: # %bb.0:
-; CHECK-O3-CUR-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-O3-CUR-NEXT: movq Constant(%rip), %rax
; CHECK-O3-CUR-NEXT: movq $5, (%rdi)
; CHECK-O3-CUR-NEXT: addq %rsi, %rax
; CHECK-O3-CUR-NEXT: retq
@@ -2404,7 +2404,7 @@ define i64 @fold_constant_clobber(i64* %p, i64 %arg) {
; CHECK-O3-EX-LABEL: fold_constant_clobber:
; CHECK-O3-EX: # %bb.0:
; CHECK-O3-EX-NEXT: movq %rsi, %rax
-; CHECK-O3-EX-NEXT: addq {{.*}}(%rip), %rax
+; CHECK-O3-EX-NEXT: addq Constant(%rip), %rax
; CHECK-O3-EX-NEXT: movq $5, (%rdi)
; CHECK-O3-EX-NEXT: retq
%v = load atomic i64, i64* @Constant unordered, align 8
@@ -2416,14 +2416,14 @@ define i64 @fold_constant_clobber(i64* %p, i64 %arg) {
define i64 @fold_constant_fence(i64 %arg) {
; CHECK-O0-LABEL: fold_constant_fence:
; CHECK-O0: # %bb.0:
-; CHECK-O0-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-O0-NEXT: movq Constant(%rip), %rax
; CHECK-O0-NEXT: mfence
; CHECK-O0-NEXT: addq %rdi, %rax
; CHECK-O0-NEXT: retq
;
; CHECK-O3-CUR-LABEL: fold_constant_fence:
; CHECK-O3-CUR: # %bb.0:
-; CHECK-O3-CUR-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-O3-CUR-NEXT: movq Constant(%rip), %rax
; CHECK-O3-CUR-NEXT: mfence
; CHECK-O3-CUR-NEXT: addq %rdi, %rax
; CHECK-O3-CUR-NEXT: retq
@@ -2431,7 +2431,7 @@ define i64 @fold_constant_fence(i64 %arg) {
; CHECK-O3-EX-LABEL: fold_constant_fence:
; CHECK-O3-EX: # %bb.0:
; CHECK-O3-EX-NEXT: movq %rdi, %rax
-; CHECK-O3-EX-NEXT: addq {{.*}}(%rip), %rax
+; CHECK-O3-EX-NEXT: addq Constant(%rip), %rax
; CHECK-O3-EX-NEXT: mfence
; CHECK-O3-EX-NEXT: retq
%v = load atomic i64, i64* @Constant unordered, align 8
diff --git a/llvm/test/CodeGen/X86/atomic128.ll b/llvm/test/CodeGen/X86/atomic128.ll
index b71afe2b249d5..ce973aac091c5 100644
--- a/llvm/test/CodeGen/X86/atomic128.ll
+++ b/llvm/test/CodeGen/X86/atomic128.ll
@@ -91,7 +91,7 @@ define void @cmpxchg16b_global_with_offset() nounwind {
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx
-; CHECK-NEXT: lock cmpxchg16b _cmpxchg16b_global+{{.*}}(%rip)
+; CHECK-NEXT: lock cmpxchg16b _cmpxchg16b_global+16(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -138,8 +138,8 @@ define void @fetch_and_nand(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB2_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -206,8 +206,8 @@ define void @fetch_and_or(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB3_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -274,8 +274,8 @@ define void @fetch_and_add(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB4_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -342,8 +342,8 @@ define void @fetch_and_sub(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB5_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -413,8 +413,8 @@ define void @fetch_and_min(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB6_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -484,8 +484,8 @@ define void @fetch_and_max(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB7_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -555,8 +555,8 @@ define void @fetch_and_umin(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB8_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
@@ -626,8 +626,8 @@ define void @fetch_and_umax(i128* %p, i128 %bits) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB9_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, _var(%rip)
+; CHECK-NEXT: movq %rdx, _var+8(%rip)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/atomic32.ll b/llvm/test/CodeGen/X86/atomic32.ll
index 565dd13a1bb40..e2255993a4975 100644
--- a/llvm/test/CodeGen/X86/atomic32.ll
+++ b/llvm/test/CodeGen/X86/atomic32.ll
@@ -10,11 +10,11 @@
define void @atomic_fetch_add32() nounwind {
; X64-LABEL: atomic_fetch_add32:
; X64: # %bb.0: # %entry
-; X64-NEXT: lock incl {{.*}}(%rip)
-; X64-NEXT: lock addl $3, {{.*}}(%rip)
+; X64-NEXT: lock incl sc32(%rip)
+; X64-NEXT: lock addl $3, sc32(%rip)
; X64-NEXT: movl $5, %eax
-; X64-NEXT: lock xaddl %eax, {{.*}}(%rip)
-; X64-NEXT: lock addl %eax, {{.*}}(%rip)
+; X64-NEXT: lock xaddl %eax, sc32(%rip)
+; X64-NEXT: lock addl %eax, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_add32:
@@ -36,11 +36,11 @@ entry:
define void @atomic_fetch_sub32() nounwind {
; X64-LABEL: atomic_fetch_sub32:
; X64: # %bb.0:
-; X64-NEXT: lock decl {{.*}}(%rip)
-; X64-NEXT: lock subl $3, {{.*}}(%rip)
+; X64-NEXT: lock decl sc32(%rip)
+; X64-NEXT: lock subl $3, sc32(%rip)
; X64-NEXT: movl $-5, %eax
-; X64-NEXT: lock xaddl %eax, {{.*}}(%rip)
-; X64-NEXT: lock subl %eax, {{.*}}(%rip)
+; X64-NEXT: lock xaddl %eax, sc32(%rip)
+; X64-NEXT: lock subl %eax, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_sub32:
@@ -61,7 +61,7 @@ define void @atomic_fetch_sub32() nounwind {
define void @atomic_fetch_and32() nounwind {
; X64-LABEL: atomic_fetch_and32:
; X64: # %bb.0:
-; X64-NEXT: lock andl $3, {{.*}}(%rip)
+; X64-NEXT: lock andl $3, sc32(%rip)
; X64-NEXT: movl sc32, %eax
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: .LBB2_1: # %atomicrmw.start
@@ -69,7 +69,7 @@ define void @atomic_fetch_and32() nounwind {
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andl $5, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: testb $1, %cl
@@ -78,7 +78,7 @@ define void @atomic_fetch_and32() nounwind {
; X64-NEXT: jmp .LBB2_1
; X64-NEXT: .LBB2_2: # %atomicrmw.end
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
-; X64-NEXT: lock andl %eax, {{.*}}(%rip)
+; X64-NEXT: lock andl %eax, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_and32:
@@ -113,7 +113,7 @@ define void @atomic_fetch_and32() nounwind {
define void @atomic_fetch_or32() nounwind {
; X64-LABEL: atomic_fetch_or32:
; X64: # %bb.0:
-; X64-NEXT: lock orl $3, {{.*}}(%rip)
+; X64-NEXT: lock orl $3, sc32(%rip)
; X64-NEXT: movl sc32, %eax
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: .LBB3_1: # %atomicrmw.start
@@ -121,7 +121,7 @@ define void @atomic_fetch_or32() nounwind {
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: orl $5, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: testb $1, %cl
@@ -130,7 +130,7 @@ define void @atomic_fetch_or32() nounwind {
; X64-NEXT: jmp .LBB3_1
; X64-NEXT: .LBB3_2: # %atomicrmw.end
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
-; X64-NEXT: lock orl %eax, {{.*}}(%rip)
+; X64-NEXT: lock orl %eax, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_or32:
@@ -165,7 +165,7 @@ define void @atomic_fetch_or32() nounwind {
define void @atomic_fetch_xor32() nounwind {
; X64-LABEL: atomic_fetch_xor32:
; X64: # %bb.0:
-; X64-NEXT: lock xorl $3, {{.*}}(%rip)
+; X64-NEXT: lock xorl $3, sc32(%rip)
; X64-NEXT: movl sc32, %eax
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: .LBB4_1: # %atomicrmw.start
@@ -173,7 +173,7 @@ define void @atomic_fetch_xor32() nounwind {
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: xorl $5, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: testb $1, %cl
@@ -182,7 +182,7 @@ define void @atomic_fetch_xor32() nounwind {
; X64-NEXT: jmp .LBB4_1
; X64-NEXT: .LBB4_2: # %atomicrmw.end
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
-; X64-NEXT: lock xorl %eax, {{.*}}(%rip)
+; X64-NEXT: lock xorl %eax, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_xor32:
@@ -228,7 +228,7 @@ define void @atomic_fetch_nand32(i32 %x) nounwind {
; X64-NEXT: andl %edx, %ecx
; X64-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: notl %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
@@ -279,7 +279,7 @@ define void @atomic_fetch_max32(i32 %x) nounwind {
; X64-NEXT: subl %ecx, %edx
; X64-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: cmovgl %eax, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
@@ -398,7 +398,7 @@ define void @atomic_fetch_min32(i32 %x) nounwind {
; X64-NEXT: subl %ecx, %edx
; X64-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: cmovlel %eax, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
@@ -517,7 +517,7 @@ define void @atomic_fetch_umax32(i32 %x) nounwind {
; X64-NEXT: subl %ecx, %edx
; X64-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: cmoval %eax, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
@@ -636,7 +636,7 @@ define void @atomic_fetch_umin32(i32 %x) nounwind {
; X64-NEXT: subl %ecx, %edx
; X64-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; X64-NEXT: cmovbel %eax, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
@@ -746,7 +746,7 @@ define void @atomic_fetch_cmpxchg32() nounwind {
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: movl $1, %ecx
-; X64-NEXT: lock cmpxchgl %ecx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_cmpxchg32:
@@ -762,7 +762,7 @@ define void @atomic_fetch_cmpxchg32() nounwind {
define void @atomic_fetch_store32(i32 %x) nounwind {
; X64-LABEL: atomic_fetch_store32:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, {{.*}}(%rip)
+; X64-NEXT: movl %edi, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_store32:
@@ -777,7 +777,7 @@ define void @atomic_fetch_store32(i32 %x) nounwind {
define void @atomic_fetch_swap32(i32 %x) nounwind {
; X64-LABEL: atomic_fetch_swap32:
; X64: # %bb.0:
-; X64-NEXT: xchgl %edi, {{.*}}(%rip)
+; X64-NEXT: xchgl %edi, sc32(%rip)
; X64-NEXT: retq
;
; X86-LABEL: atomic_fetch_swap32:
@@ -793,7 +793,7 @@ define void @atomic_fetch_swapf32(float %x) nounwind {
; X64-LABEL: atomic_fetch_swapf32:
; X64: # %bb.0:
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: xchgl %eax, {{.*}}(%rip)
+; X64-NEXT: xchgl %eax, fsc32(%rip)
; X64-NEXT: retq
;
; X86-CMOV-LABEL: atomic_fetch_swapf32:
diff --git a/llvm/test/CodeGen/X86/atomic64.ll b/llvm/test/CodeGen/X86/atomic64.ll
index 42745baa554f6..bd8a115f1826e 100644
--- a/llvm/test/CodeGen/X86/atomic64.ll
+++ b/llvm/test/CodeGen/X86/atomic64.ll
@@ -8,11 +8,11 @@
define void @atomic_fetch_add64() nounwind {
; X64-LABEL: atomic_fetch_add64:
; X64: # %bb.0: # %entry
-; X64-NEXT: lock incq {{.*}}(%rip)
-; X64-NEXT: lock addq $3, {{.*}}(%rip)
+; X64-NEXT: lock incq sc64(%rip)
+; X64-NEXT: lock addq $3, sc64(%rip)
; X64-NEXT: movl $5, %eax
-; X64-NEXT: lock xaddq %rax, {{.*}}(%rip)
-; X64-NEXT: lock addq %rax, {{.*}}(%rip)
+; X64-NEXT: lock xaddq %rax, sc64(%rip)
+; X64-NEXT: lock addq %rax, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_add64:
@@ -24,21 +24,21 @@ define void @atomic_fetch_add64() nounwind {
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $1, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_add_8
+; I486-NEXT: calll __atomic_fetch_add_8 at PLT
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $3, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_add_8
+; I486-NEXT: calll __atomic_fetch_add_8 at PLT
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $5, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_add_8
+; I486-NEXT: calll __atomic_fetch_add_8 at PLT
; I486-NEXT: movl %eax, %ecx
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
@@ -46,7 +46,7 @@ define void @atomic_fetch_add64() nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_add_8
+; I486-NEXT: calll __atomic_fetch_add_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
entry:
@@ -60,11 +60,11 @@ entry:
define void @atomic_fetch_sub64() nounwind {
; X64-LABEL: atomic_fetch_sub64:
; X64: # %bb.0:
-; X64-NEXT: lock decq {{.*}}(%rip)
-; X64-NEXT: lock subq $3, {{.*}}(%rip)
+; X64-NEXT: lock decq sc64(%rip)
+; X64-NEXT: lock subq $3, sc64(%rip)
; X64-NEXT: movq $-5, %rax
-; X64-NEXT: lock xaddq %rax, {{.*}}(%rip)
-; X64-NEXT: lock subq %rax, {{.*}}(%rip)
+; X64-NEXT: lock xaddq %rax, sc64(%rip)
+; X64-NEXT: lock subq %rax, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_sub64:
@@ -76,21 +76,21 @@ define void @atomic_fetch_sub64() nounwind {
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $1, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_sub_8
+; I486-NEXT: calll __atomic_fetch_sub_8 at PLT
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $3, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_sub_8
+; I486-NEXT: calll __atomic_fetch_sub_8 at PLT
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $5, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_sub_8
+; I486-NEXT: calll __atomic_fetch_sub_8 at PLT
; I486-NEXT: movl %eax, %ecx
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
@@ -98,7 +98,7 @@ define void @atomic_fetch_sub64() nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_sub_8
+; I486-NEXT: calll __atomic_fetch_sub_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
%t1 = atomicrmw sub i64* @sc64, i64 1 acquire
@@ -111,7 +111,7 @@ define void @atomic_fetch_sub64() nounwind {
define void @atomic_fetch_and64() nounwind {
; X64-LABEL: atomic_fetch_and64:
; X64: # %bb.0:
-; X64-NEXT: lock andq $3, {{.*}}(%rip)
+; X64-NEXT: lock andq $3, sc64(%rip)
; X64-NEXT: movq sc64, %rax
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: .LBB2_1: # %atomicrmw.start
@@ -120,7 +120,7 @@ define void @atomic_fetch_and64() nounwind {
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andl $5, %ecx
; X64-NEXT: # kill: def $rcx killed $ecx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: testb $1, %cl
@@ -129,7 +129,7 @@ define void @atomic_fetch_and64() nounwind {
; X64-NEXT: jmp .LBB2_1
; X64-NEXT: .LBB2_2: # %atomicrmw.end
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; X64-NEXT: lock andq %rax, {{.*}}(%rip)
+; X64-NEXT: lock andq %rax, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_and64:
@@ -141,14 +141,14 @@ define void @atomic_fetch_and64() nounwind {
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $3, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_and_8
+; I486-NEXT: calll __atomic_fetch_and_8 at PLT
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $5, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_and_8
+; I486-NEXT: calll __atomic_fetch_and_8 at PLT
; I486-NEXT: movl %eax, %ecx
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
@@ -156,7 +156,7 @@ define void @atomic_fetch_and64() nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_and_8
+; I486-NEXT: calll __atomic_fetch_and_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
%t1 = atomicrmw and i64* @sc64, i64 3 acquire
@@ -168,7 +168,7 @@ define void @atomic_fetch_and64() nounwind {
define void @atomic_fetch_or64() nounwind {
; X64-LABEL: atomic_fetch_or64:
; X64: # %bb.0:
-; X64-NEXT: lock orq $3, {{.*}}(%rip)
+; X64-NEXT: lock orq $3, sc64(%rip)
; X64-NEXT: movq sc64, %rax
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: .LBB3_1: # %atomicrmw.start
@@ -176,7 +176,7 @@ define void @atomic_fetch_or64() nounwind {
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; X64-NEXT: movq %rax, %rcx
; X64-NEXT: orq $5, %rcx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: testb $1, %cl
@@ -185,7 +185,7 @@ define void @atomic_fetch_or64() nounwind {
; X64-NEXT: jmp .LBB3_1
; X64-NEXT: .LBB3_2: # %atomicrmw.end
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; X64-NEXT: lock orq %rax, {{.*}}(%rip)
+; X64-NEXT: lock orq %rax, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_or64:
@@ -197,14 +197,14 @@ define void @atomic_fetch_or64() nounwind {
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $3, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_or_8
+; I486-NEXT: calll __atomic_fetch_or_8 at PLT
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $5, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_or_8
+; I486-NEXT: calll __atomic_fetch_or_8 at PLT
; I486-NEXT: movl %eax, %ecx
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
@@ -212,7 +212,7 @@ define void @atomic_fetch_or64() nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_or_8
+; I486-NEXT: calll __atomic_fetch_or_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
%t1 = atomicrmw or i64* @sc64, i64 3 acquire
@@ -224,7 +224,7 @@ define void @atomic_fetch_or64() nounwind {
define void @atomic_fetch_xor64() nounwind {
; X64-LABEL: atomic_fetch_xor64:
; X64: # %bb.0:
-; X64-NEXT: lock xorq $3, {{.*}}(%rip)
+; X64-NEXT: lock xorq $3, sc64(%rip)
; X64-NEXT: movq sc64, %rax
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: .LBB4_1: # %atomicrmw.start
@@ -232,7 +232,7 @@ define void @atomic_fetch_xor64() nounwind {
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; X64-NEXT: movq %rax, %rcx
; X64-NEXT: xorq $5, %rcx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: testb $1, %cl
@@ -241,7 +241,7 @@ define void @atomic_fetch_xor64() nounwind {
; X64-NEXT: jmp .LBB4_1
; X64-NEXT: .LBB4_2: # %atomicrmw.end
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; X64-NEXT: lock xorq %rax, {{.*}}(%rip)
+; X64-NEXT: lock xorq %rax, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_xor64:
@@ -253,14 +253,14 @@ define void @atomic_fetch_xor64() nounwind {
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $3, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_xor_8
+; I486-NEXT: calll __atomic_fetch_xor_8 at PLT
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $0, 8(%eax)
; I486-NEXT: movl $5, 4(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_xor_8
+; I486-NEXT: calll __atomic_fetch_xor_8 at PLT
; I486-NEXT: movl %eax, %ecx
; I486-NEXT: leal sc64, %eax
; I486-NEXT: movl %esp, %eax
@@ -268,7 +268,7 @@ define void @atomic_fetch_xor64() nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_xor_8
+; I486-NEXT: calll __atomic_fetch_xor_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
%t1 = atomicrmw xor i64* @sc64, i64 3 acquire
@@ -291,7 +291,7 @@ define void @atomic_fetch_nand64(i64 %x) nounwind {
; X64-NEXT: andq %rdx, %rcx
; X64-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: notq %rcx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
@@ -311,7 +311,7 @@ define void @atomic_fetch_nand64(i64 %x) nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_fetch_nand_8
+; I486-NEXT: calll __atomic_fetch_nand_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
%t1 = atomicrmw nand i64* @sc64, i64 %x acquire
@@ -332,7 +332,7 @@ define void @atomic_fetch_max64(i64 %x) nounwind {
; X64-NEXT: subq %rcx, %rdx
; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: cmovgq %rax, %rcx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
@@ -392,7 +392,7 @@ define void @atomic_fetch_max64(i64 %x) nounwind {
; I486-NEXT: movl $2, 20(%eax)
; I486-NEXT: movl $2, 16(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_compare_exchange_8
+; I486-NEXT: calll __atomic_compare_exchange_8 at PLT
; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -425,7 +425,7 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
; X64-NEXT: subq %rcx, %rdx
; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: cmovleq %rax, %rcx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
@@ -485,7 +485,7 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
; I486-NEXT: movl $2, 20(%eax)
; I486-NEXT: movl $2, 16(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_compare_exchange_8
+; I486-NEXT: calll __atomic_compare_exchange_8 at PLT
; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -518,7 +518,7 @@ define void @atomic_fetch_umax64(i64 %x) nounwind {
; X64-NEXT: subq %rcx, %rdx
; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: cmovaq %rax, %rcx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
@@ -578,7 +578,7 @@ define void @atomic_fetch_umax64(i64 %x) nounwind {
; I486-NEXT: movl $2, 20(%eax)
; I486-NEXT: movl $2, 16(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_compare_exchange_8
+; I486-NEXT: calll __atomic_compare_exchange_8 at PLT
; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -611,7 +611,7 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
; X64-NEXT: subq %rcx, %rdx
; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: cmovbeq %rax, %rcx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
@@ -671,7 +671,7 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
; I486-NEXT: movl $2, 20(%eax)
; I486-NEXT: movl $2, 16(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_compare_exchange_8
+; I486-NEXT: calll __atomic_compare_exchange_8 at PLT
; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -696,7 +696,7 @@ define void @atomic_fetch_cmpxchg64() nounwind {
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: # kill: def $rax killed $eax
; X64-NEXT: movl $1, %ecx
-; X64-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
+; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_cmpxchg64:
@@ -716,7 +716,7 @@ define void @atomic_fetch_cmpxchg64() nounwind {
; I486-NEXT: movl $0, 12(%eax)
; I486-NEXT: movl $1, 8(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_compare_exchange_8
+; I486-NEXT: calll __atomic_compare_exchange_8 at PLT
; I486-NEXT: movl %ebp, %esp
; I486-NEXT: popl %ebp
; I486-NEXT: retl
@@ -727,7 +727,7 @@ define void @atomic_fetch_cmpxchg64() nounwind {
define void @atomic_fetch_store64(i64 %x) nounwind {
; X64-LABEL: atomic_fetch_store64:
; X64: # %bb.0:
-; X64-NEXT: movq %rdi, {{.*}}(%rip)
+; X64-NEXT: movq %rdi, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_store64:
@@ -741,7 +741,7 @@ define void @atomic_fetch_store64(i64 %x) nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $3, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_store_8
+; I486-NEXT: calll __atomic_store_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
store atomic i64 %x, i64* @sc64 release, align 8
@@ -751,7 +751,7 @@ define void @atomic_fetch_store64(i64 %x) nounwind {
define void @atomic_fetch_swap64(i64 %x) nounwind {
; X64-LABEL: atomic_fetch_swap64:
; X64: # %bb.0:
-; X64-NEXT: xchgq %rdi, {{.*}}(%rip)
+; X64-NEXT: xchgq %rdi, sc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_swap64:
@@ -765,7 +765,7 @@ define void @atomic_fetch_swap64(i64 %x) nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $sc64, (%eax)
-; I486-NEXT: calll __atomic_exchange_8
+; I486-NEXT: calll __atomic_exchange_8 at PLT
; I486-NEXT: addl $16, %esp
; I486-NEXT: retl
%t1 = atomicrmw xchg i64* @sc64, i64 %x acquire
@@ -776,7 +776,7 @@ define void @atomic_fetch_swapf64(double %x) nounwind {
; X64-LABEL: atomic_fetch_swapf64:
; X64: # %bb.0:
; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: xchgq %rax, {{.*}}(%rip)
+; X64-NEXT: xchgq %rax, fsc64(%rip)
; X64-NEXT: retq
;
; I486-LABEL: atomic_fetch_swapf64:
@@ -795,7 +795,7 @@ define void @atomic_fetch_swapf64(double %x) nounwind {
; I486-NEXT: movl %ecx, 4(%eax)
; I486-NEXT: movl $2, 12(%eax)
; I486-NEXT: movl $fsc64, (%eax)
-; I486-NEXT: calll __atomic_exchange_8
+; I486-NEXT: calll __atomic_exchange_8 at PLT
; I486-NEXT: movl %ebp, %esp
; I486-NEXT: popl %ebp
; I486-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/atomicf128.ll b/llvm/test/CodeGen/X86/atomicf128.ll
index 1fc5a0eaf7327..e4e5e7ea916e7 100644
--- a/llvm/test/CodeGen/X86/atomicf128.ll
+++ b/llvm/test/CodeGen/X86/atomicf128.ll
@@ -13,7 +13,7 @@ define void @atomic_fetch_swapf128(fp128 %x) nounwind {
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rbx
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
-; CHECK-NEXT: movq _fsc128@{{.*}}(%rip), %rsi
+; CHECK-NEXT: movq _fsc128 at GOTPCREL(%rip), %rsi
; CHECK-NEXT: movq (%rsi), %rax
; CHECK-NEXT: movq 8(%rsi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
@@ -30,7 +30,7 @@ define void @atomic_fetch_swapf128(fp128 %x) nounwind {
; NOSSE-NEXT: pushq %rbx
; NOSSE-NEXT: movq %rsi, %rcx
; NOSSE-NEXT: movq %rdi, %rbx
-; NOSSE-NEXT: movq _fsc128@{{.*}}(%rip), %rsi
+; NOSSE-NEXT: movq _fsc128 at GOTPCREL(%rip), %rsi
; NOSSE-NEXT: movq (%rsi), %rax
; NOSSE-NEXT: movq 8(%rsi), %rdx
; NOSSE-NEXT: .p2align 4, 0x90
diff --git a/llvm/test/CodeGen/X86/avg.ll b/llvm/test/CodeGen/X86/avg.ll
index 9866cf5c0e1da..c4590ae1d052c 100644
--- a/llvm/test/CodeGen/X86/avg.ll
+++ b/llvm/test/CodeGen/X86/avg.ll
@@ -980,14 +980,14 @@ define void @avg_v4i8_const(<4 x i8>* %a) nounwind {
; SSE2-LABEL: avg_v4i8_const:
; SSE2: # %bb.0:
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2-NEXT: pavgb {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movd %xmm0, (%rax)
; SSE2-NEXT: retq
;
; AVX-LABEL: avg_v4i8_const:
; AVX: # %bb.0:
; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vpavgb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovd %xmm0, (%rax)
; AVX-NEXT: retq
%1 = load <4 x i8>, <4 x i8>* %a
@@ -1003,14 +1003,14 @@ define void @avg_v8i8_const(<8 x i8>* %a) nounwind {
; SSE2-LABEL: avg_v8i8_const:
; SSE2: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: pavgb {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movq %xmm0, (%rax)
; SSE2-NEXT: retq
;
; AVX-LABEL: avg_v8i8_const:
; AVX: # %bb.0:
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vpavgb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovq %xmm0, (%rax)
; AVX-NEXT: retq
%1 = load <8 x i8>, <8 x i8>* %a
@@ -1026,14 +1026,14 @@ define void @avg_v16i8_const(<16 x i8>* %a) nounwind {
; SSE2-LABEL: avg_v16i8_const:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pavgb {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqu %xmm0, (%rax)
; SSE2-NEXT: retq
;
; AVX-LABEL: avg_v16i8_const:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqa (%rdi), %xmm0
-; AVX-NEXT: vpavgb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovdqu %xmm0, (%rax)
; AVX-NEXT: retq
%1 = load <16 x i8>, <16 x i8>* %a
@@ -1069,7 +1069,7 @@ define void @avg_v32i8_const(<32 x i8>* %a) nounwind {
; AVX2-LABEL: avg_v32i8_const:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
-; AVX2-NEXT: vpavgb {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, (%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -1077,7 +1077,7 @@ define void @avg_v32i8_const(<32 x i8>* %a) nounwind {
; AVX512-LABEL: avg_v32i8_const:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa (%rdi), %ymm0
-; AVX512-NEXT: vpavgb {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: vmovdqu %ymm0, (%rax)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
@@ -1144,7 +1144,7 @@ define void @avg_v64i8_const(<64 x i8>* %a) nounwind {
; AVX512BW-LABEL: avg_v64i8_const:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
-; AVX512BW-NEXT: vpavgb {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -1161,14 +1161,14 @@ define void @avg_v4i16_const(<4 x i16>* %a) nounwind {
; SSE2-LABEL: avg_v4i16_const:
; SSE2: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: pavgw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movq %xmm0, (%rax)
; SSE2-NEXT: retq
;
; AVX-LABEL: avg_v4i16_const:
; AVX: # %bb.0:
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vpavgw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovq %xmm0, (%rax)
; AVX-NEXT: retq
%1 = load <4 x i16>, <4 x i16>* %a
@@ -1184,14 +1184,14 @@ define void @avg_v8i16_const(<8 x i16>* %a) nounwind {
; SSE2-LABEL: avg_v8i16_const:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pavgw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqu %xmm0, (%rax)
; SSE2-NEXT: retq
;
; AVX-LABEL: avg_v8i16_const:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqa (%rdi), %xmm0
-; AVX-NEXT: vpavgw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovdqu %xmm0, (%rax)
; AVX-NEXT: retq
%1 = load <8 x i16>, <8 x i16>* %a
@@ -1226,7 +1226,7 @@ define void @avg_v16i16_const(<16 x i16>* %a) nounwind {
; AVX2-LABEL: avg_v16i16_const:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
-; AVX2-NEXT: vpavgw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, (%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -1234,7 +1234,7 @@ define void @avg_v16i16_const(<16 x i16>* %a) nounwind {
; AVX512-LABEL: avg_v16i16_const:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa (%rdi), %ymm0
-; AVX512-NEXT: vpavgw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: vmovdqu %ymm0, (%rax)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
@@ -1302,7 +1302,7 @@ define void @avg_v32i16_const(<32 x i16>* %a) nounwind {
; AVX512BW-LABEL: avg_v32i16_const:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
-; AVX512BW-NEXT: vpavgw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -1889,7 +1889,7 @@ define void @not_avg_v16i8_wide_constants(<16 x i8>* %a, <16 x i8>* %b) nounwind
; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],xmm13[1],xmm6[2],xmm13[2],xmm6[3],xmm13[3],xmm6[4],xmm13[4],xmm6[5],xmm13[5],xmm6[6],xmm13[6],xmm6[7],xmm13[7]
; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,0,0]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm14[0],xmm5[1],xmm14[1],xmm5[2],xmm14[2],xmm5[3],xmm14[3],xmm5[4],xmm14[4],xmm5[5],xmm14[5],xmm5[6],xmm14[6],xmm5[7],xmm14[7]
; SSE2-NEXT: pslldq {{.*#+}} xmm5 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm5[0,1,2,3,4,5]
diff --git a/llvm/test/CodeGen/X86/avoid-sfb.ll b/llvm/test/CodeGen/X86/avoid-sfb.ll
index 5c914286a25c8..e3573c549ec96 100644
--- a/llvm/test/CodeGen/X86/avoid-sfb.ll
+++ b/llvm/test/CodeGen/X86/avoid-sfb.ll
@@ -841,13 +841,13 @@ define void @test_limit_all(%struct.S* noalias %s1, %struct.S* nocapture %s2, i
; CHECK-NEXT: movq %rsi, %r12
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl %r9d, 12(%rdi)
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: cmpl $18, %ebp
; CHECK-NEXT: jl .LBB9_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %ebp, 4(%rbx)
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: movups (%r15), %xmm0
; CHECK-NEXT: movups %xmm0, (%r14)
@@ -888,13 +888,13 @@ define void @test_limit_all(%struct.S* noalias %s1, %struct.S* nocapture %s2, i
; DISABLED-NEXT: movq %rsi, %r12
; DISABLED-NEXT: movq %rdi, %rbx
; DISABLED-NEXT: movl %r9d, 12(%rdi)
-; DISABLED-NEXT: callq bar
+; DISABLED-NEXT: callq bar at PLT
; DISABLED-NEXT: cmpl $18, %ebp
; DISABLED-NEXT: jl .LBB9_2
; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %ebp, 4(%rbx)
; DISABLED-NEXT: movq %rbx, %rdi
-; DISABLED-NEXT: callq bar
+; DISABLED-NEXT: callq bar at PLT
; DISABLED-NEXT: .LBB9_2: # %if.end
; DISABLED-NEXT: movups (%r15), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r14)
@@ -935,13 +935,13 @@ define void @test_limit_all(%struct.S* noalias %s1, %struct.S* nocapture %s2, i
; CHECK-AVX2-NEXT: movq %rsi, %r12
; CHECK-AVX2-NEXT: movq %rdi, %rbx
; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi)
-; CHECK-AVX2-NEXT: callq bar
+; CHECK-AVX2-NEXT: callq bar at PLT
; CHECK-AVX2-NEXT: cmpl $18, %ebp
; CHECK-AVX2-NEXT: jl .LBB9_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %ebp, 4(%rbx)
; CHECK-AVX2-NEXT: movq %rbx, %rdi
-; CHECK-AVX2-NEXT: callq bar
+; CHECK-AVX2-NEXT: callq bar at PLT
; CHECK-AVX2-NEXT: .LBB9_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r15), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%r14)
@@ -982,13 +982,13 @@ define void @test_limit_all(%struct.S* noalias %s1, %struct.S* nocapture %s2, i
; CHECK-AVX512-NEXT: movq %rsi, %r12
; CHECK-AVX512-NEXT: movq %rdi, %rbx
; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi)
-; CHECK-AVX512-NEXT: callq bar
+; CHECK-AVX512-NEXT: callq bar at PLT
; CHECK-AVX512-NEXT: cmpl $18, %ebp
; CHECK-AVX512-NEXT: jl .LBB9_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl %ebp, 4(%rbx)
; CHECK-AVX512-NEXT: movq %rbx, %rdi
-; CHECK-AVX512-NEXT: callq bar
+; CHECK-AVX512-NEXT: callq bar at PLT
; CHECK-AVX512-NEXT: .LBB9_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r15), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%r14)
@@ -1056,7 +1056,7 @@ define void @test_limit_one_pred(%struct.S* noalias %s1, %struct.S* nocapture %s
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %edx, 4(%rbx)
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: .LBB10_2: # %if.end
; CHECK-NEXT: movups (%r12), %xmm0
; CHECK-NEXT: movups %xmm0, (%r15)
@@ -1104,7 +1104,7 @@ define void @test_limit_one_pred(%struct.S* noalias %s1, %struct.S* nocapture %s
; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %edx, 4(%rbx)
; DISABLED-NEXT: movq %rbx, %rdi
-; DISABLED-NEXT: callq bar
+; DISABLED-NEXT: callq bar at PLT
; DISABLED-NEXT: .LBB10_2: # %if.end
; DISABLED-NEXT: movups (%r15), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r14)
@@ -1148,7 +1148,7 @@ define void @test_limit_one_pred(%struct.S* noalias %s1, %struct.S* nocapture %s
; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %edx, 4(%rbx)
; CHECK-AVX2-NEXT: movq %rbx, %rdi
-; CHECK-AVX2-NEXT: callq bar
+; CHECK-AVX2-NEXT: callq bar at PLT
; CHECK-AVX2-NEXT: .LBB10_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r12), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%r15)
@@ -1196,7 +1196,7 @@ define void @test_limit_one_pred(%struct.S* noalias %s1, %struct.S* nocapture %s
; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl %edx, 4(%rbx)
; CHECK-AVX512-NEXT: movq %rbx, %rdi
-; CHECK-AVX512-NEXT: callq bar
+; CHECK-AVX512-NEXT: callq bar at PLT
; CHECK-AVX512-NEXT: .LBB10_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r12), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%r15)
diff --git a/llvm/test/CodeGen/X86/avx-arith.ll b/llvm/test/CodeGen/X86/avx-arith.ll
index 6f535038bb2de..53579e3f325d5 100644
--- a/llvm/test/CodeGen/X86/avx-arith.ll
+++ b/llvm/test/CodeGen/X86/avx-arith.ll
@@ -14,7 +14,7 @@ entry:
define <4 x double> @addpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: addpd256fold:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
%add.i = fadd <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
@@ -34,7 +34,7 @@ entry:
define <8 x float> @addps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: addps256fold:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
%add.i = fadd <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
@@ -96,7 +96,7 @@ entry:
define <4 x double> @mulpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: mulpd256fold:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vmulpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
%mul.i = fmul <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
@@ -116,7 +116,7 @@ entry:
define <8 x float> @mulps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: mulps256fold:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
%mul.i = fmul <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
@@ -136,7 +136,7 @@ entry:
define <4 x double> @divpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: divpd256fold:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vdivpd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vdivpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
%div.i = fdiv <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
@@ -156,7 +156,7 @@ entry:
define <8 x float> @divps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: divps256fold:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vdivps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
%div.i = fdiv <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
diff --git a/llvm/test/CodeGen/X86/avx-basic.ll b/llvm/test/CodeGen/X86/avx-basic.ll
index 67b029104b403..3333b735abf06 100644
--- a/llvm/test/CodeGen/X86/avx-basic.ll
+++ b/llvm/test/CodeGen/X86/avx-basic.ll
@@ -9,7 +9,7 @@ define void @zero128() nounwind ssp {
; CHECK-LABEL: zero128:
; CHECK: ## %bb.0:
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; CHECK-NEXT: movq _z@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _z at GOTPCREL(%rip), %rax
; CHECK-NEXT: vmovaps %xmm0, (%rax)
; CHECK-NEXT: retq
store <4 x float> zeroinitializer, <4 x float>* @z, align 16
@@ -20,9 +20,9 @@ define void @zero256() nounwind ssp {
; CHECK-LABEL: zero256:
; CHECK: ## %bb.0:
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; CHECK-NEXT: movq _x@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _x at GOTPCREL(%rip), %rax
; CHECK-NEXT: vmovaps %ymm0, (%rax)
-; CHECK-NEXT: movq _y@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _y at GOTPCREL(%rip), %rax
; CHECK-NEXT: vmovaps %ymm0, (%rax)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/avx-brcond.ll b/llvm/test/CodeGen/X86/avx-brcond.ll
index 62f2778ac5d23..facaef2a2998a 100644
--- a/llvm/test/CodeGen/X86/avx-brcond.ll
+++ b/llvm/test/CodeGen/X86/avx-brcond.ll
@@ -10,11 +10,11 @@ define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: vptest %ymm0, %ymm0
; CHECK-NEXT: jne LBB0_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: vaddps LCPI0_0, %xmm1, %xmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_2: ## %bb2
-; CHECK-NEXT: vdivps LCPI0_0, %xmm1, %xmm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
entry:
@@ -42,11 +42,11 @@ define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: vptest %ymm0, %ymm0
; CHECK-NEXT: jne LBB1_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: vaddps LCPI1_0, %xmm1, %xmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
; CHECK-NEXT: LBB1_2: ## %bb2
-; CHECK-NEXT: vdivps LCPI1_0, %xmm1, %xmm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
entry:
@@ -74,11 +74,11 @@ define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: vptest %ymm0, %ymm0
; CHECK-NEXT: jae LBB2_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: vaddps LCPI2_0, %xmm1, %xmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
; CHECK-NEXT: LBB2_2: ## %bb2
-; CHECK-NEXT: vdivps LCPI2_0, %xmm1, %xmm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
entry:
@@ -106,11 +106,11 @@ define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: vptest %ymm0, %ymm0
; CHECK-NEXT: jae LBB3_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: vaddps LCPI3_0, %xmm1, %xmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
; CHECK-NEXT: LBB3_2: ## %bb2
-; CHECK-NEXT: vdivps LCPI3_0, %xmm1, %xmm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
entry:
@@ -138,11 +138,11 @@ define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: vptest %ymm0, %ymm0
; CHECK-NEXT: jne LBB4_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: vaddps LCPI4_0, %xmm1, %xmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
; CHECK-NEXT: LBB4_2: ## %bb2
-; CHECK-NEXT: vdivps LCPI4_0, %xmm1, %xmm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
entry:
@@ -170,11 +170,11 @@ define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: vptest %ymm0, %ymm0
; CHECK-NEXT: je LBB5_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: vaddps LCPI5_0, %xmm1, %xmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
; CHECK-NEXT: LBB5_2: ## %bb2
-; CHECK-NEXT: vdivps LCPI5_0, %xmm1, %xmm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/avx-cmp.ll b/llvm/test/CodeGen/X86/avx-cmp.ll
index 621ea2ce32f97..502bbf3f5d118 100644
--- a/llvm/test/CodeGen/X86/avx-cmp.ll
+++ b/llvm/test/CodeGen/X86/avx-cmp.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
define <8 x i32> @cmp00(<8 x float> %a, <8 x float> %b) nounwind {
@@ -49,7 +49,7 @@ define void @render(double %a0) nounwind {
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: vmovsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: vucomisd {{\.LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: jne .LBB2_5
; CHECK-NEXT: jnp .LBB2_2
; CHECK-NEXT: .LBB2_5: # %if.then
diff --git a/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
index 7fff7e117b833..2bcfdcbae8ec5 100644
--- a/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
@@ -645,8 +645,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9]
-; X86-AVX-NEXT: vmovhpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: # xmm1 = xmm1[0],mem[0]
; X86-AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0x58,0xc1]
; X86-AVX-NEXT: vmovupd %xmm0, (%eax) # encoding: [0xc5,0xf9,0x11,0x00]
@@ -656,8 +656,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9]
-; X86-AVX512VL-NEXT: vmovhpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: # xmm1 = xmm1[0],mem[0]
; X86-AVX512VL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1]
; X86-AVX512VL-NEXT: vmovupd %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x00]
@@ -666,8 +666,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X64-AVX-LABEL: test_x86_sse2_storeu_pd:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9]
-; X64-AVX-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: # xmm1 = xmm1[0],mem[0]
; X64-AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0x58,0xc1]
; X64-AVX-NEXT: vmovupd %xmm0, (%rdi) # encoding: [0xc5,0xf9,0x11,0x07]
@@ -676,8 +676,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X64-AVX512VL-LABEL: test_x86_sse2_storeu_pd:
; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9]
-; X64-AVX512VL-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: # xmm1 = xmm1[0],mem[0]
; X64-AVX512VL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1]
; X64-AVX512VL-NEXT: vmovupd %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x07]
diff --git a/llvm/test/CodeGen/X86/avx-load-store.ll b/llvm/test/CodeGen/X86/avx-load-store.ll
index 7bd255c130259..2528399c43325 100644
--- a/llvm/test/CodeGen/X86/avx-load-store.ll
+++ b/llvm/test/CodeGen/X86/avx-load-store.ll
@@ -18,7 +18,7 @@ define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>*
; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; CHECK-NEXT: vmovaps (%rdx), %ymm2
; CHECK-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
-; CHECK-NEXT: callq dummy
+; CHECK-NEXT: callq dummy at PLT
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; CHECK-NEXT: vmovaps %ymm0, (%rbx)
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
@@ -44,7 +44,7 @@ define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>*
; CHECK_O0-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; CHECK_O0-NEXT: vmovdqa (%rdx), %ymm2
; CHECK_O0-NEXT: vmovups %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; CHECK_O0-NEXT: callq dummy
+; CHECK_O0-NEXT: callq dummy at PLT
; CHECK_O0-NEXT: vmovups (%rsp), %ymm2 # 32-byte Reload
; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
diff --git a/llvm/test/CodeGen/X86/avx-logic.ll b/llvm/test/CodeGen/X86/avx-logic.ll
index a1a008f0c8a99..0081023df33fb 100644
--- a/llvm/test/CodeGen/X86/avx-logic.ll
+++ b/llvm/test/CodeGen/X86/avx-logic.ll
@@ -23,7 +23,7 @@ entry:
define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; ANY-LABEL: andpd256fold:
; ANY: # %bb.0: # %entry
-; ANY-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; ANY-NEXT: retq
@@ -52,7 +52,7 @@ entry:
define <8 x float> @andps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
; ANY-LABEL: andps256fold:
; ANY: # %bb.0: # %entry
-; ANY-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %y to <8 x i32>
@@ -81,7 +81,7 @@ entry:
define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; ANY-LABEL: xorpd256fold:
; ANY: # %bb.0: # %entry
-; ANY-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; ANY-NEXT: retq
@@ -110,7 +110,7 @@ entry:
define <8 x float> @xorps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
; ANY-LABEL: xorps256fold:
; ANY: # %bb.0: # %entry
-; ANY-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %y to <8 x i32>
@@ -139,7 +139,7 @@ entry:
define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; ANY-LABEL: orpd256fold:
; ANY: # %bb.0: # %entry
-; ANY-NEXT: vorpd {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; ANY-NEXT: retq
@@ -168,7 +168,7 @@ entry:
define <8 x float> @orps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
; ANY-LABEL: orps256fold:
; ANY: # %bb.0: # %entry
-; ANY-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %y to <8 x i32>
@@ -275,7 +275,7 @@ define <2 x i64> @vpand(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ss
define <4 x i32> @and_xor_splat1_v4i32(<4 x i32> %x) nounwind {
; AVX1-LABEL: and_xor_splat1_v4i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandnps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vandnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; INT256-LABEL: and_xor_splat1_v4i32:
@@ -291,7 +291,7 @@ define <4 x i32> @and_xor_splat1_v4i32(<4 x i32> %x) nounwind {
define <4 x i64> @and_xor_splat1_v4i64(<4 x i64> %x) nounwind {
; AVX1-LABEL: and_xor_splat1_v4i64:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandnps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; INT256-LABEL: and_xor_splat1_v4i64:
@@ -326,7 +326,7 @@ define <8 x i32> @and_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z
; INT256-LABEL: and_disguised_i8_elts:
; INT256: # %bb.0:
; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
-; INT256-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; INT256-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; INT256-NEXT: retq
%a = add <8 x i32> %x, %y
@@ -354,7 +354,7 @@ define <8 x i32> @andn_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %
; INT256-LABEL: andn_disguised_i8_elts:
; INT256: # %bb.0:
; INT256-NEXT: vpaddd %ymm0, %ymm1, %ymm0
-; INT256-NEXT: vpandn {{.*}}(%rip), %ymm0, %ymm0
+; INT256-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; INT256-NEXT: retq
%add = add <8 x i32> %y, %x
@@ -393,7 +393,7 @@ define <8 x i32> @andn_variable_mask_operand_no_concat(<8 x i32> %x, <8 x i32> %
define <8 x i32> @andn_constant_mask_operand_no_concat(<8 x i32> %x, <8 x i32> %y) {
; AVX1-LABEL: andn_constant_mask_operand_no_concat:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandnps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpaddd %xmm2, %xmm3, %xmm2
@@ -403,7 +403,7 @@ define <8 x i32> @andn_constant_mask_operand_no_concat(<8 x i32> %x, <8 x i32> %
;
; INT256-LABEL: andn_constant_mask_operand_no_concat:
; INT256: # %bb.0:
-; INT256-NEXT: vpandn {{.*}}(%rip), %ymm0, %ymm0
+; INT256-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; INT256-NEXT: retq
%xor = xor <8 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
diff --git a/llvm/test/CodeGen/X86/avx-shift.ll b/llvm/test/CodeGen/X86/avx-shift.ll
index 1d5ec2d124d76..8d825782c1f82 100644
--- a/llvm/test/CodeGen/X86/avx-shift.ll
+++ b/llvm/test/CodeGen/X86/avx-shift.ll
@@ -205,7 +205,7 @@ define <8 x i32> @vshift08_add(<8 x i32> %a, <8 x i32> %y) {
define <4 x i32> @vshift13(<4 x i32> %in) {
; CHECK-LABEL: vshift13:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4>
ret <4 x i32> %T
diff --git a/llvm/test/CodeGen/X86/avx-trunc.ll b/llvm/test/CodeGen/X86/avx-trunc.ll
index 1b1a9b2ded133..ba41141a6e665 100644
--- a/llvm/test/CodeGen/X86/avx-trunc.ll
+++ b/llvm/test/CodeGen/X86/avx-trunc.ll
@@ -29,7 +29,7 @@ define <8 x i16> @trunc_32_16(<8 x i32> %A) nounwind uwtable readnone ssp{
define <16 x i8> @trunc_16_8(<16 x i16> %A) nounwind uwtable readnone ssp{
; CHECK-LABEL: trunc_16_8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/avx-vperm2x128.ll b/llvm/test/CodeGen/X86/avx-vperm2x128.ll
index 71c3cf9eabe4d..91264ee2917e9 100644
--- a/llvm/test/CodeGen/X86/avx-vperm2x128.ll
+++ b/llvm/test/CodeGen/X86/avx-vperm2x128.ll
@@ -539,7 +539,7 @@ define <4 x double> @ld0_hi0_lo1_4f64(<4 x double> * %pa, <4 x double> %b) nounw
; AVX1-LABEL: ld0_hi0_lo1_4f64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vperm2f128 $3, (%rdi), %ymm0, %ymm0 # ymm0 = mem[2,3],ymm0[0,1]
-; AVX1-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ld0_hi0_lo1_4f64:
@@ -559,7 +559,7 @@ define <4 x double> @ld1_hi0_hi1_4f64(<4 x double> %a, <4 x double> * %pb) nounw
; AVX1-LABEL: ld1_hi0_hi1_4f64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vperm2f128 $49, (%rdi), %ymm0, %ymm0 # ymm0 = ymm0[2,3],mem[2,3]
-; AVX1-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ld1_hi0_hi1_4f64:
@@ -579,7 +579,7 @@ define <8 x float> @ld0_hi0_lo1_8f32(<8 x float> * %pa, <8 x float> %b) nounwind
; AVX1-LABEL: ld0_hi0_lo1_8f32:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vperm2f128 $3, (%rdi), %ymm0, %ymm0 # ymm0 = mem[2,3],ymm0[0,1]
-; AVX1-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ld0_hi0_lo1_8f32:
@@ -599,7 +599,7 @@ define <8 x float> @ld1_hi0_hi1_8f32(<8 x float> %a, <8 x float> * %pb) nounwind
; AVX1-LABEL: ld1_hi0_hi1_8f32:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vperm2f128 $49, (%rdi), %ymm0, %ymm0 # ymm0 = ymm0[2,3],mem[2,3]
-; AVX1-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ld1_hi0_hi1_8f32:
@@ -619,15 +619,15 @@ define <4 x i64> @ld0_hi0_lo1_4i64(<4 x i64> * %pa, <4 x i64> %b) nounwind uwtab
; AVX1-LABEL: ld0_hi0_lo1_4i64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ld0_hi0_lo1_4i64:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vperm2i128 $3, (%rdi), %ymm0, %ymm0 # ymm0 = mem[2,3],ymm0[0,1]
-; AVX2-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
entry:
%a = load <4 x i64>, <4 x i64> * %pa
@@ -640,16 +640,16 @@ define <4 x i64> @ld1_hi0_hi1_4i64(<4 x i64> %a, <4 x i64> * %pb) nounwind uwtab
; AVX1-LABEL: ld1_hi0_hi1_4i64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ld1_hi0_hi1_4i64:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vperm2i128 $49, (%rdi), %ymm0, %ymm0 # ymm0 = ymm0[2,3],mem[2,3]
-; AVX2-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
entry:
%b = load <4 x i64>, <4 x i64> * %pb
@@ -670,7 +670,7 @@ define <8 x i32> @ld0_hi0_lo1_8i32(<8 x i32> * %pa, <8 x i32> %b) nounwind uwtab
; AVX2-LABEL: ld0_hi0_lo1_8i32:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vperm2i128 $3, (%rdi), %ymm0, %ymm0 # ymm0 = mem[2,3],ymm0[0,1]
-; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
entry:
%a = load <8 x i32>, <8 x i32> * %pa
@@ -692,7 +692,7 @@ define <8 x i32> @ld1_hi0_hi1_8i32(<8 x i32> %a, <8 x i32> * %pb) nounwind uwtab
; AVX2-LABEL: ld1_hi0_hi1_8i32:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vperm2i128 $49, (%rdi), %ymm0, %ymm0 # ymm0 = ymm0[2,3],mem[2,3]
-; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
entry:
%b = load <8 x i32>, <8 x i32> * %pb
diff --git a/llvm/test/CodeGen/X86/avx1-logical-load-folding.ll b/llvm/test/CodeGen/X86/avx1-logical-load-folding.ll
index 0871b9663e3ce..cb39bc3a49495 100644
--- a/llvm/test/CodeGen/X86/avx1-logical-load-folding.ll
+++ b/llvm/test/CodeGen/X86/avx1-logical-load-folding.ll
@@ -9,14 +9,14 @@ define void @test1(float* %A, float* %C) #0 {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT: vandps LCPI0_0, %xmm0, %xmm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl
;
; X64-LABEL: test1:
; X64: ## %bb.0:
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vmovss %xmm0, (%rsi)
; X64-NEXT: retq
%tmp1 = bitcast float* %A to <8 x float>*
@@ -36,14 +36,14 @@ define void @test2(float* %A, float* %C) #0 {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovaps (%ecx), %xmm0
-; X86-NEXT: vorps LCPI1_0, %xmm0, %xmm0
+; X86-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl
;
; X64-LABEL: test2:
; X64: ## %bb.0:
; X64-NEXT: vmovaps (%rdi), %xmm0
-; X64-NEXT: vorps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vmovss %xmm0, (%rsi)
; X64-NEXT: retq
%tmp1 = bitcast float* %A to <8 x float>*
@@ -63,14 +63,14 @@ define void @test3(float* %A, float* %C) #0 {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovaps (%ecx), %xmm0
-; X86-NEXT: vxorps LCPI2_0, %xmm0, %xmm0
+; X86-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl
;
; X64-LABEL: test3:
; X64: ## %bb.0:
; X64-NEXT: vmovaps (%rdi), %xmm0
-; X64-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vmovss %xmm0, (%rsi)
; X64-NEXT: retq
%tmp1 = bitcast float* %A to <8 x float>*
@@ -89,14 +89,14 @@ define void @test4(float* %A, float* %C) #0 {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovaps (%ecx), %xmm0
-; X86-NEXT: vandnps LCPI3_0, %xmm0, %xmm0
+; X86-NEXT: vandnps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl
;
; X64-LABEL: test4:
; X64: ## %bb.0:
; X64-NEXT: vmovaps (%rdi), %xmm0
-; X64-NEXT: vandnps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vmovss %xmm0, (%rsi)
; X64-NEXT: retq
%tmp1 = bitcast float* %A to <8 x float>*
diff --git a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
index c0f080e8fb9b2..06cab2910ba94 100644
--- a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
@@ -25,28 +25,28 @@ define <16 x i16> @test_x86_avx2_packssdw_fold() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X86-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packssdw_fold:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X64-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
@@ -74,28 +74,28 @@ define <32 x i8> @test_x86_avx2_packsswb_fold() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packsswb_fold:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
@@ -123,28 +123,28 @@ define <32 x i8> @test_x86_avx2_packuswb_fold() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packuswb_fold:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
@@ -753,28 +753,28 @@ define <16 x i16> @test_x86_avx2_packusdw_fold() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packusdw_fold:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
@@ -1025,26 +1025,26 @@ define <4 x i32> @test_x86_avx2_psllv_d_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X86-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295]
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X86-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
@@ -1053,26 +1053,26 @@ define <4 x i32> @test_x86_avx2_psllv_d_const() {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X64-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295]
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X64-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
@@ -1103,29 +1103,29 @@ define <8 x i32> @test_x86_avx2_psllv_d_256_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d_256_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
@@ -1133,29 +1133,29 @@ define <8 x i32> @test_x86_avx2_psllv_d_256_const() {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d_256_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res0 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>)
@@ -1184,36 +1184,36 @@ define <2 x i64> @test_x86_avx2_psllv_q_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,0,4294967295,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4294967295,4294967295]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4294967295,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psllv_q_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,18446744073709551615]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,18446744073709551615]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,18446744073709551615]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> <i64 4, i64 -1>, <2 x i64> <i64 1, i64 -1>)
ret <2 x i64> %res
@@ -1240,36 +1240,36 @@ define <4 x i64> @test_x86_avx2_psllv_q_256_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,0,4,0,4,0,4294967295,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q_256_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4294967295,4294967295]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4294967295,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psllv_q_256_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,4,4,18446744073709551615]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q_256_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,18446744073709551615]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,18446744073709551615]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 -1>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)
ret <4 x i64> %res
@@ -1296,29 +1296,29 @@ define <4 x i32> @test_x86_avx2_psrlv_d_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295]
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
@@ -1326,29 +1326,29 @@ define <4 x i32> @test_x86_avx2_psrlv_d_const() {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295]
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res0 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)
@@ -1378,29 +1378,29 @@ define <8 x i32> @test_x86_avx2_psrlv_d_256_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
@@ -1408,29 +1408,29 @@ define <8 x i32> @test_x86_avx2_psrlv_d_256_const() {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res0 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>)
@@ -1460,36 +1460,36 @@ define <2 x i64> @test_x86_avx2_psrlv_q_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,0,4,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4,0]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psrlv_q_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,4]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> <i64 4, i64 4>, <2 x i64> <i64 1, i64 -1>)
ret <2 x i64> %res
@@ -1517,36 +1517,36 @@ define <4 x i64> @test_x86_avx2_psrlv_q_256_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,0,4,0,4,0,4,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4,0]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psrlv_q_256_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpbroadcastq {{.*#+}} ymm0 = [4,4,4,4]
; X64-AVX-NEXT: # encoding: [0xc4,0xe2,0x7d,0x59,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vpbroadcastq {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4]
+; X64-AVX512VL-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4]
; X64-AVX512VL-NEXT: # encoding: [0xc4,0xe2,0x7d,0x59,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 4>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)
ret <4 x i64> %res
@@ -1573,36 +1573,36 @@ define <4 x i32> @test_x86_avx2_psrav_d_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psrav_d_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)
ret <4 x i32> %res
@@ -1628,36 +1628,36 @@ define <8 x i32> @test_x86_avx2_psrav_d_256_const() {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X86-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)
ret <8 x i32> %res
diff --git a/llvm/test/CodeGen/X86/avx2-nontemporal.ll b/llvm/test/CodeGen/X86/avx2-nontemporal.ll
index f0d8f9c6931a5..5b8de704f75a3 100644
--- a/llvm/test/CodeGen/X86/avx2-nontemporal.ll
+++ b/llvm/test/CodeGen/X86/avx2-nontemporal.ll
@@ -15,21 +15,21 @@ define i32 @f(<8 x float> %A, i8* %B, <4 x double> %C, <4 x i64> %E, <8 x i32> %
; X32-NEXT: movl 8(%ebp), %ecx
; X32-NEXT: movl 136(%ebp), %edx
; X32-NEXT: movl (%edx), %eax
-; X32-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vmovntps %ymm0, (%ecx)
-; X32-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm0
+; X32-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm0
; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx)
-; X32-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X32-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntpd %ymm0, (%ecx)
-; X32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm5, %ymm0
+; X32-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm5, %ymm0
; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx)
-; X32-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %ymm4, %ymm0
+; X32-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm4, %ymm0
; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx)
-; X32-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm0
+; X32-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm0
; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx)
; X32-NEXT: movl %ebp, %esp
@@ -40,21 +40,21 @@ define i32 @f(<8 x float> %A, i8* %B, <4 x double> %C, <4 x i64> %E, <8 x i32> %
; X64-LABEL: f:
; X64: # %bb.0:
; X64-NEXT: movl (%rsi), %eax
-; X64-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vmovntps %ymm0, (%rdi)
-; X64-NEXT: vpaddq {{.*}}(%rip), %ymm2, %ymm0
+; X64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0
; X64-NEXT: addl (%rsi), %eax
; X64-NEXT: vmovntdq %ymm0, (%rdi)
-; X64-NEXT: vaddpd {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: addl (%rsi), %eax
; X64-NEXT: vmovntpd %ymm0, (%rdi)
-; X64-NEXT: vpaddd {{.*}}(%rip), %ymm3, %ymm0
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm0
; X64-NEXT: addl (%rsi), %eax
; X64-NEXT: vmovntdq %ymm0, (%rdi)
-; X64-NEXT: vpaddw {{.*}}(%rip), %ymm4, %ymm0
+; X64-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm0
; X64-NEXT: addl (%rsi), %eax
; X64-NEXT: vmovntdq %ymm0, (%rdi)
-; X64-NEXT: vpaddb {{.*}}(%rip), %ymm5, %ymm0
+; X64-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm0
; X64-NEXT: addl (%rsi), %eax
; X64-NEXT: vmovntdq %ymm0, (%rdi)
; X64-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/avx2-shift.ll b/llvm/test/CodeGen/X86/avx2-shift.ll
index bb6eceff081c8..5ad02eed8d958 100644
--- a/llvm/test/CodeGen/X86/avx2-shift.ll
+++ b/llvm/test/CodeGen/X86/avx2-shift.ll
@@ -424,13 +424,13 @@ define <32 x i8> @shl9(<32 x i8> %A) nounwind {
; X32-LABEL: shl9:
; X32: # %bb.0:
; X32-NEXT: vpsllw $3, %ymm0, %ymm0
-; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: shl9:
; X64: # %bb.0:
; X64-NEXT: vpsllw $3, %ymm0, %ymm0
-; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B
@@ -440,13 +440,13 @@ define <32 x i8> @shr9(<32 x i8> %A) nounwind {
; X32-LABEL: shr9:
; X32: # %bb.0:
; X32-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: shr9:
; X64: # %bb.0:
; X64-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B
@@ -472,7 +472,7 @@ define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
; X32-LABEL: sra_v32i8:
; X32: # %bb.0:
; X32-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vmovdqa {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X32-NEXT: vpxor %ymm1, %ymm0, %ymm0
; X32-NEXT: vpsubb %ymm1, %ymm0, %ymm0
@@ -481,7 +481,7 @@ define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
; X64-LABEL: sra_v32i8:
; X64: # %bb.0:
; X64-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vmovdqa {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X64-NEXT: vpxor %ymm1, %ymm0, %ymm0
; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/avx2-vbroadcast.ll b/llvm/test/CodeGen/X86/avx2-vbroadcast.ll
index edae4f094c9b6..f81fec9f7f50f 100644
--- a/llvm/test/CodeGen/X86/avx2-vbroadcast.ll
+++ b/llvm/test/CodeGen/X86/avx2-vbroadcast.ll
@@ -598,12 +598,12 @@ define <8 x i32> @V111(<8 x i32> %in) nounwind uwtable readnone ssp {
;
; X32-AVX512VL-LABEL: V111:
; X32-AVX512VL: ## %bb.0: ## %entry
-; X32-AVX512VL-NEXT: vpaddd LCPI29_0{1to8}, %ymm0, %ymm0
+; X32-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X32-AVX512VL-NEXT: retl
;
; X64-AVX512VL-LABEL: V111:
; X64-AVX512VL: ## %bb.0: ## %entry
-; X64-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-AVX512VL-NEXT: retq
entry:
%g = add <8 x i32> %in, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
@@ -625,12 +625,12 @@ define <8 x float> @V113(<8 x float> %in) nounwind uwtable readnone ssp {
;
; X32-AVX512VL-LABEL: V113:
; X32-AVX512VL: ## %bb.0: ## %entry
-; X32-AVX512VL-NEXT: vaddps LCPI30_0{1to8}, %ymm0, %ymm0
+; X32-AVX512VL-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X32-AVX512VL-NEXT: retl
;
; X64-AVX512VL-LABEL: V113:
; X64-AVX512VL: ## %bb.0: ## %entry
-; X64-AVX512VL-NEXT: vaddps {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-AVX512VL-NEXT: retq
entry:
%g = fadd <8 x float> %in, <float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000>
diff --git a/llvm/test/CodeGen/X86/avx2-vbroadcasti128.ll b/llvm/test/CodeGen/X86/avx2-vbroadcasti128.ll
index d88d62dfd322f..4d1d3ffdb956e 100644
--- a/llvm/test/CodeGen/X86/avx2-vbroadcasti128.ll
+++ b/llvm/test/CodeGen/X86/avx2-vbroadcasti128.ll
@@ -7,13 +7,13 @@ define <4 x double> @test_broadcast_2f64_4f64(<2 x double> *%p) nounwind {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_2f64_4f64:
; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = load <2 x double>, <2 x double> *%p
%2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
@@ -26,13 +26,13 @@ define <4 x i64> @test_broadcast_2i64_4i64(<2 x i64> *%p) nounwind {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_2i64_4i64:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = load <2 x i64>, <2 x i64> *%p
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
@@ -45,13 +45,13 @@ define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_4f32_8f32:
; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = load <4 x float>, <4 x float> *%p
%2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -64,13 +64,13 @@ define <8 x i32> @test_broadcast_4i32_8i32(<4 x i32> *%p) nounwind {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_4i32_8i32:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = load <4 x i32>, <4 x i32> *%p
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -83,13 +83,13 @@ define <16 x i16> @test_broadcast_8i16_16i16(<8 x i16> *%p) nounwind {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_8i16_16i16:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = load <8 x i16>, <8 x i16> *%p
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -102,13 +102,13 @@ define <32 x i8> @test_broadcast_16i8_32i8(<16 x i8> *%p) nounwind {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_16i8_32i8:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = load <16 x i8>, <16 x i8> *%p
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -122,14 +122,14 @@ define <4 x double> @test_broadcast_2f64_4f64_reuse(<2 x double>* %p0, <2 x doub
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X32-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X32-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovapd %xmm1, (%eax)
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_2f64_4f64_reuse:
; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X64-NEXT: vaddpd {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovapd %xmm1, (%rsi)
; X64-NEXT: retq
%1 = load <2 x double>, <2 x double>* %p0
@@ -145,14 +145,14 @@ define <4 x i64> @test_broadcast_2i64_4i64_reuse(<2 x i64>* %p0, <2 x i64>* %p1)
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X32-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X32-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_2i64_4i64_reuse:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X64-NEXT: vpaddq {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi)
; X64-NEXT: retq
%1 = load <2 x i64>, <2 x i64>* %p0
@@ -168,14 +168,14 @@ define <8 x float> @test_broadcast_4f32_8f32_reuse(<4 x float>* %p0, <4 x float>
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X32-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X32-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovaps %xmm1, (%eax)
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_4f32_8f32_reuse:
; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X64-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovaps %xmm1, (%rsi)
; X64-NEXT: retq
%1 = load <4 x float>, <4 x float>* %p0
@@ -191,14 +191,14 @@ define <8 x i32> @test_broadcast_4i32_8i32_reuse(<4 x i32>* %p0, <4 x i32>* %p1)
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X32-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_4i32_8i32_reuse:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X64-NEXT: vpaddd {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi)
; X64-NEXT: retq
%1 = load <4 x i32>, <4 x i32>* %p0
@@ -214,14 +214,14 @@ define <16 x i16> @test_broadcast_8i16_16i16_reuse(<8 x i16> *%p0, <8 x i16> *%p
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X32-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X32-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_8i16_16i16_reuse:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X64-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi)
; X64-NEXT: retq
%1 = load <8 x i16>, <8 x i16> *%p0
@@ -237,14 +237,14 @@ define <32 x i8> @test_broadcast_16i8_32i8_reuse(<16 x i8> *%p0, <16 x i8> *%p1)
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X32-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X32-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl
;
; X64-LABEL: test_broadcast_16i8_32i8_reuse:
; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
-; X64-NEXT: vpaddb {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi)
; X64-NEXT: retq
%1 = load <16 x i8>, <16 x i8> *%p0
diff --git a/llvm/test/CodeGen/X86/avx512-any_extend_load.ll b/llvm/test/CodeGen/X86/avx512-any_extend_load.ll
index db5f8c244eee2..017c8d6aad495 100644
--- a/llvm/test/CodeGen/X86/avx512-any_extend_load.ll
+++ b/llvm/test/CodeGen/X86/avx512-any_extend_load.ll
@@ -7,7 +7,7 @@ define void @any_extend_load_v8i64(<8 x i8> * %ptr) {
; ALL-LABEL: any_extend_load_v8i64:
; ALL: # %bb.0:
; ALL-NEXT: vpmovzxbq {{.*#+}} zmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero,mem[4],zero,zero,zero,zero,zero,zero,zero,mem[5],zero,zero,zero,zero,zero,zero,zero,mem[6],zero,zero,zero,zero,zero,zero,zero,mem[7],zero,zero,zero,zero,zero,zero,zero
-; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; ALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; ALL-NEXT: vpmovqb %zmm0, (%rdi)
; ALL-NEXT: vzeroupper
; ALL-NEXT: retq
@@ -34,7 +34,7 @@ define void @any_extend_load_v8i32(<8 x i8> * %ptr) {
; SKX-LABEL: any_extend_load_v8i32:
; SKX: # %bb.0:
; SKX-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
-; SKX-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; SKX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; SKX-NEXT: vpmovdb %ymm0, (%rdi)
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
@@ -51,7 +51,7 @@ define void @any_extend_load_v8i16(<8 x i8> * %ptr) {
; KNL-LABEL: any_extend_load_v8i16:
; KNL: # %bb.0:
; KNL-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; KNL-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
; KNL-NEXT: vmovq %xmm0, (%rdi)
; KNL-NEXT: retq
@@ -59,7 +59,7 @@ define void @any_extend_load_v8i16(<8 x i8> * %ptr) {
; SKX-LABEL: any_extend_load_v8i16:
; SKX: # %bb.0:
; SKX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; SKX-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: vpmovwb %xmm0, (%rdi)
; SKX-NEXT: retq
%wide.load = load <8 x i8>, <8 x i8>* %ptr, align 1
diff --git a/llvm/test/CodeGen/X86/avx512-arith.ll b/llvm/test/CodeGen/X86/avx512-arith.ll
index 58953e287e0a6..70ab2b92531fe 100644
--- a/llvm/test/CodeGen/X86/avx512-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512-arith.ll
@@ -18,7 +18,7 @@ entry:
define <8 x double> @addpd512fold(<8 x double> %y) {
; CHECK-LABEL: addpd512fold:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vaddpd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
entry:
%add.i = fadd <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.800000e+00, double 2.300000e+00, double 1.200000e+00>
@@ -38,7 +38,7 @@ entry:
define <16 x float> @addps512fold(<16 x float> %y) {
; CHECK-LABEL: addps512fold:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vaddps {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
entry:
%add.i = fadd <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 4.500000e+00, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
@@ -224,13 +224,13 @@ define <4 x i64> @imulq256_bcast(<4 x i64> %x) {
; AVX512DQ-LABEL: imulq256_bcast:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512DQ-NEXT: vpmullq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512DQ-NEXT: retq
;
; SKX-LABEL: imulq256_bcast:
; SKX: # %bb.0:
-; SKX-NEXT: vpmullq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; SKX-NEXT: retq
%z = mul <4 x i64> %x, <i64 1337, i64 1337, i64 1337, i64 1337>
ret <4 x i64>%z
@@ -332,7 +332,7 @@ define <2 x i64> @imulq128_bcast(<2 x i64> %x) {
;
; SKX-LABEL: imulq128_bcast:
; SKX: # %bb.0:
-; SKX-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: retq
%z = mul <2 x i64> %x, <i64 8086, i64 8086>
ret <2 x i64>%z
@@ -351,7 +351,7 @@ entry:
define <8 x double> @mulpd512fold(<8 x double> %y) {
; CHECK-LABEL: mulpd512fold:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmulpd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vmulpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
entry:
%mul.i = fmul <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
@@ -371,7 +371,7 @@ entry:
define <16 x float> @mulps512fold(<16 x float> %y) {
; CHECK-LABEL: mulps512fold:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmulps {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
entry:
%mul.i = fmul <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
@@ -391,7 +391,7 @@ entry:
define <8 x double> @divpd512fold(<8 x double> %y) {
; CHECK-LABEL: divpd512fold:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vdivpd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vdivpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
entry:
%div.i = fdiv <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
@@ -411,7 +411,7 @@ entry:
define <16 x float> @divps512fold(<16 x float> %y) {
; CHECK-LABEL: divps512fold:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vdivps {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
entry:
%div.i = fdiv <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000>
@@ -440,7 +440,7 @@ define <8 x i64> @vpaddq_fold_test(<8 x i64> %i, <8 x i64>* %j) nounwind {
define <8 x i64> @vpaddq_broadcast_test(<8 x i64> %i) nounwind {
; CHECK-LABEL: vpaddq_broadcast_test:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq
%x = add <8 x i64> %i, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
ret <8 x i64> %x
@@ -486,7 +486,7 @@ define <16 x i32> @vpaddd_fold_test(<16 x i32> %i, <16 x i32>* %j) nounwind {
define <16 x i32> @vpaddd_broadcast_test(<16 x i32> %i) nounwind {
; CHECK-LABEL: vpaddd_broadcast_test:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; CHECK-NEXT: retq
%x = add <16 x i32> %i, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
ret <16 x i32> %x
@@ -533,7 +533,7 @@ define <16 x i32> @vpaddd_mask_broadcast_test(<16 x i32> %i, <16 x i32> %mask1)
; CHECK-LABEL: vpaddd_mask_broadcast_test:
; CHECK: # %bb.0:
; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 {%k1}
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%x = add <16 x i32> %i, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
@@ -558,7 +558,7 @@ define <16 x i32> @vpaddd_maskz_broadcast_test(<16 x i32> %i, <16 x i32> %mask1)
; CHECK-LABEL: vpaddd_maskz_broadcast_test:
; CHECK: # %bb.0:
; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%x = add <16 x i32> %i, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
@@ -648,7 +648,7 @@ define <8 x double> @sqrtE(<8 x double> %a) nounwind {
define <16 x float> @fadd_broadcast(<16 x float> %a) nounwind {
; CHECK-LABEL: fadd_broadcast:
; CHECK: # %bb.0:
-; CHECK-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; CHECK-NEXT: retq
%b = fadd <16 x float> %a, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
ret <16 x float> %b
@@ -657,7 +657,7 @@ define <16 x float> @fadd_broadcast(<16 x float> %a) nounwind {
define <8 x i64> @addq_broadcast(<8 x i64> %a) nounwind {
; CHECK-LABEL: addq_broadcast:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq
%b = add <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
ret <8 x i64> %b
@@ -666,27 +666,27 @@ define <8 x i64> @addq_broadcast(<8 x i64> %a) nounwind {
define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {
; AVX512F-LABEL: orq_broadcast:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vporq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512F-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: orq_broadcast:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vporq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: orq_broadcast:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vporq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: orq_broadcast:
; AVX512DQ: # %bb.0:
-; AVX512DQ-NEXT: vorpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512DQ-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; SKX-LABEL: orq_broadcast:
; SKX: # %bb.0:
-; SKX-NEXT: vorpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; SKX-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; SKX-NEXT: retq
%b = or <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
ret <8 x i64> %b
@@ -1033,27 +1033,27 @@ define <8 x double> @test_maskz_broadcast_vaddpd(<8 x double> %i, double* %j,
define <16 x float> @test_fxor(<16 x float> %a) {
; AVX512F-LABEL: test_fxor:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512F-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: test_fxor:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512VL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: test_fxor:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_fxor:
; AVX512DQ: # %bb.0:
-; AVX512DQ-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512DQ-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; SKX-LABEL: test_fxor:
; SKX: # %bb.0:
-; SKX-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: retq
%res = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a
@@ -1069,7 +1069,7 @@ define <8 x float> @test_fxor_8f32(<8 x float> %a) {
;
; AVX512VL-LABEL: test_fxor_8f32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpxord {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512VL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: test_fxor_8f32:
@@ -1086,7 +1086,7 @@ define <8 x float> @test_fxor_8f32(<8 x float> %a) {
;
; SKX-LABEL: test_fxor_8f32:
; SKX: # %bb.0:
-; SKX-NEXT: vxorps {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; SKX-NEXT: retq
%res = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a
ret <8 x float>%res
@@ -1095,27 +1095,27 @@ define <8 x float> @test_fxor_8f32(<8 x float> %a) {
define <8 x double> @fabs_v8f64(<8 x double> %p)
; AVX512F-LABEL: fabs_v8f64:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: fabs_v8f64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: fabs_v8f64:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: fabs_v8f64:
; AVX512DQ: # %bb.0:
-; AVX512DQ-NEXT: vandpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512DQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; SKX-LABEL: fabs_v8f64:
; SKX: # %bb.0:
-; SKX-NEXT: vandpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; SKX-NEXT: retq
{
%t = call <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
@@ -1126,27 +1126,27 @@ declare <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
define <16 x float> @fabs_v16f32(<16 x float> %p)
; AVX512F-LABEL: fabs_v16f32:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512F-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: fabs_v16f32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: fabs_v16f32:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: fabs_v16f32:
; AVX512DQ: # %bb.0:
-; AVX512DQ-NEXT: vandps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; SKX-LABEL: fabs_v16f32:
; SKX: # %bb.0:
-; SKX-NEXT: vandps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: retq
{
%t = call <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
diff --git a/llvm/test/CodeGen/X86/avx512-bugfix-23634.ll b/llvm/test/CodeGen/X86/avx512-bugfix-23634.ll
index 97356854da620..53f705eb6d7a5 100644
--- a/llvm/test/CodeGen/X86/avx512-bugfix-23634.ll
+++ b/llvm/test/CodeGen/X86/avx512-bugfix-23634.ll
@@ -15,7 +15,7 @@ define void @f_fu(float* %ret, float* %aa, float %b) {
; CHECK-NEXT: vpsrad $1, %zmm2, %zmm2
; CHECK-NEXT: movw $-21846, %ax ## imm = 0xAAAA
; CHECK-NEXT: kmovw %eax, %k1
-; CHECK-NEXT: vmovdqa32 {{.*}}(%rip), %zmm1 {%k1}
+; CHECK-NEXT: vmovdqa32 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
; CHECK-NEXT: vpaddd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vcvtdq2ps %zmm0, %zmm0
diff --git a/llvm/test/CodeGen/X86/avx512-calling-conv.ll b/llvm/test/CodeGen/X86/avx512-calling-conv.ll
index 515787e98ecee..b6efdd7c6989a 100644
--- a/llvm/test/CodeGen/X86/avx512-calling-conv.ll
+++ b/llvm/test/CodeGen/X86/avx512-calling-conv.ll
@@ -274,7 +274,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: ## kill: def $xmm0 killed $xmm0 killed $ymm0
; KNL-NEXT: callq _func8xi1
-; KNL-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: popq %rax
; KNL-NEXT: retq
;
@@ -286,7 +286,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; SKX-NEXT: vpmovm2w %k0, %xmm0
; SKX-NEXT: vzeroupper
; SKX-NEXT: callq _func8xi1
-; SKX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: popq %rax
; SKX-NEXT: retq
;
@@ -298,7 +298,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: ## kill: def $xmm0 killed $xmm0 killed $ymm0
; KNL_X32-NEXT: calll _func8xi1
-; KNL_X32-NEXT: vandps LCPI7_0, %xmm0, %xmm0
+; KNL_X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; KNL_X32-NEXT: addl $12, %esp
; KNL_X32-NEXT: retl
;
@@ -310,7 +310,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; FASTISEL-NEXT: vpmovm2w %k0, %xmm0
; FASTISEL-NEXT: vzeroupper
; FASTISEL-NEXT: callq _func8xi1
-; FASTISEL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; FASTISEL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FASTISEL-NEXT: popq %rax
; FASTISEL-NEXT: retq
%cmpRes = icmp sgt <8 x i32>%a, %b
diff --git a/llvm/test/CodeGen/X86/avx512-cmp.ll b/llvm/test/CodeGen/X86/avx512-cmp.ll
index e3d35129f5545..c9f15724fa115 100644
--- a/llvm/test/CodeGen/X86/avx512-cmp.ll
+++ b/llvm/test/CodeGen/X86/avx512-cmp.ll
@@ -71,7 +71,7 @@ define float @test5(float %p) #0 {
; ALL-NEXT: LBB3_1: ## %if.end
; ALL-NEXT: vcmpltss %xmm0, %xmm1, %k1
; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; ALL-NEXT: vmovss {{.*}}(%rip), %xmm0 {%k1}
+; ALL-NEXT: vmovss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1}
; ALL-NEXT: retq
entry:
%cmp = fcmp oeq float %p, 0.000000e+00
diff --git a/llvm/test/CodeGen/X86/avx512-cvt.ll b/llvm/test/CodeGen/X86/avx512-cvt.ll
index e98885e31c9df..5d7940b2fa7ce 100644
--- a/llvm/test/CodeGen/X86/avx512-cvt.ll
+++ b/llvm/test/CodeGen/X86/avx512-cvt.ll
@@ -322,10 +322,10 @@ define <8 x double> @ulto8f64(<8 x i64> %a) {
; NODQ-LABEL: ulto8f64:
; NODQ: # %bb.0:
; NODQ-NEXT: vpbroadcastq {{.*#+}} zmm1 = [4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200]
-; NODQ-NEXT: vpternlogq $248, {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; NODQ-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; NODQ-NEXT: vpsrlq $32, %zmm0, %zmm0
-; NODQ-NEXT: vporq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; NODQ-NEXT: vsubpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; NODQ-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; NODQ-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; NODQ-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; NODQ-NEXT: retq
;
@@ -1944,7 +1944,7 @@ define <8 x float> @ubto8f32(<8 x i32> %a) {
; VL: # %bb.0:
; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; VL-NEXT: vpcmpgtd %ymm0, %ymm1, %ymm0
-; VL-NEXT: vpandd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; VL-NEXT: retq
%mask = icmp slt <8 x i32> %a, zeroinitializer
%1 = uitofp <8 x i1> %mask to <8 x float>
@@ -1975,7 +1975,7 @@ define <4 x float> @ubto4f32(<4 x i32> %a) {
; VL: # %bb.0:
; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; VL-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
-; VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; VL-NEXT: retq
%mask = icmp slt <4 x i32> %a, zeroinitializer
%1 = uitofp <4 x i1> %mask to <4 x float>
@@ -2006,7 +2006,7 @@ define <2 x float> @ubto2f32(<2 x i32> %a) {
; VL: # %bb.0:
; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; VL-NEXT: vpandnd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; VL-NEXT: vpandnd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; VL-NEXT: retq
%mask = icmp ne <2 x i32> %a, zeroinitializer
%1 = uitofp <2 x i1> %mask to <2 x float>
@@ -2027,7 +2027,7 @@ define <2 x double> @ubto2f64(<2 x i32> %a) {
; VL: # %bb.0:
; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; VL-NEXT: vpandnd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; VL-NEXT: vpandnd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; VL-NEXT: vcvtdq2pd %xmm0, %xmm0
; VL-NEXT: retq
%mask = icmp ne <2 x i32> %a, zeroinitializer
diff --git a/llvm/test/CodeGen/X86/avx512-ext.ll b/llvm/test/CodeGen/X86/avx512-ext.ll
index fc1ba049c6912..aed158f98d95a 100644
--- a/llvm/test/CodeGen/X86/avx512-ext.ll
+++ b/llvm/test/CodeGen/X86/avx512-ext.ll
@@ -2907,13 +2907,13 @@ define <64 x i8> @zext_64xi1_to_64xi8(<64 x i8> %x, <64 x i8> %y) #0 {
; KNL-NEXT: vpcmpeqb %ymm2, %ymm3, %ymm2
; KNL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; KNL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: zext_64xi1_to_64xi8:
; SKX: # %bb.0:
; SKX-NEXT: vpcmpeqb %zmm1, %zmm0, %k1
-; SKX-NEXT: vmovdqu8 {{.*}}(%rip), %zmm0 {%k1} {z}
+; SKX-NEXT: vmovdqu8 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k1} {z}
; SKX-NEXT: retq
;
; AVX512DQNOBW-LABEL: zext_64xi1_to_64xi8:
@@ -2923,7 +2923,7 @@ define <64 x i8> @zext_64xi1_to_64xi8(<64 x i8> %x, <64 x i8> %y) #0 {
; AVX512DQNOBW-NEXT: vpcmpeqb %ymm2, %ymm3, %ymm2
; AVX512DQNOBW-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512DQNOBW-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; AVX512DQNOBW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512DQNOBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512DQNOBW-NEXT: retq
%mask = icmp eq <64 x i8> %x, %y
%1 = zext <64 x i1> %mask to <64 x i8>
@@ -2938,7 +2938,7 @@ define <32 x i16> @zext_32xi1_to_32xi16(<32 x i16> %x, <32 x i16> %y) #0 {
; KNL-NEXT: vpcmpeqw %ymm2, %ymm3, %ymm2
; KNL-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; KNL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: zext_32xi1_to_32xi16:
@@ -2955,7 +2955,7 @@ define <32 x i16> @zext_32xi1_to_32xi16(<32 x i16> %x, <32 x i16> %y) #0 {
; AVX512DQNOBW-NEXT: vpcmpeqw %ymm2, %ymm3, %ymm2
; AVX512DQNOBW-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; AVX512DQNOBW-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; AVX512DQNOBW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512DQNOBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512DQNOBW-NEXT: retq
%mask = icmp eq <32 x i16> %x, %y
%1 = zext <32 x i1> %mask to <32 x i16>
@@ -2986,13 +2986,13 @@ define <32 x i8> @zext_32xi1_to_32xi8(<32 x i16> %x, <32 x i16> %y) #0 {
; KNL-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero
; KNL-NEXT: vpmovdb %zmm1, %xmm1
; KNL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: retq
;
; SKX-LABEL: zext_32xi1_to_32xi8:
; SKX: # %bb.0:
; SKX-NEXT: vpcmpeqw %zmm1, %zmm0, %k1
-; SKX-NEXT: vmovdqu8 {{.*}}(%rip), %ymm0 {%k1} {z}
+; SKX-NEXT: vmovdqu8 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k1} {z}
; SKX-NEXT: retq
;
; AVX512DQNOBW-LABEL: zext_32xi1_to_32xi8:
@@ -3006,7 +3006,7 @@ define <32 x i8> @zext_32xi1_to_32xi8(<32 x i16> %x, <32 x i16> %y) #0 {
; AVX512DQNOBW-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero
; AVX512DQNOBW-NEXT: vpmovdb %zmm1, %xmm1
; AVX512DQNOBW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512DQNOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512DQNOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512DQNOBW-NEXT: retq
%mask = icmp eq <32 x i16> %x, %y
%1 = zext <32 x i1> %mask to <32 x i8>
@@ -3033,7 +3033,7 @@ define <4 x i32> @zext_4xi1_to_4x32(<4 x i8> %x, <4 x i8> %y) #0 {
; AVX512DQNOBW: # %bb.0:
; AVX512DQNOBW-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX512DQNOBW-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; AVX512DQNOBW-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512DQNOBW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512DQNOBW-NEXT: retq
%mask = icmp eq <4 x i8> %x, %y
%1 = zext <4 x i1> %mask to <4 x i32>
@@ -3045,7 +3045,7 @@ define <2 x i64> @zext_2xi1_to_2xi64(<2 x i8> %x, <2 x i8> %y) #0 {
; KNL: # %bb.0:
; KNL-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; KNL-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: retq
;
; SKX-LABEL: zext_2xi1_to_2xi64:
@@ -3059,7 +3059,7 @@ define <2 x i64> @zext_2xi1_to_2xi64(<2 x i8> %x, <2 x i8> %y) #0 {
; AVX512DQNOBW: # %bb.0:
; AVX512DQNOBW-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX512DQNOBW-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
-; AVX512DQNOBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512DQNOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512DQNOBW-NEXT: retq
%mask = icmp eq <2 x i8> %x, %y
%1 = zext <2 x i1> %mask to <2 x i64>
diff --git a/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll b/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll
index 9502ec95d0928..d77ec7bda4ead 100644
--- a/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll
+++ b/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll
@@ -17,7 +17,7 @@ define void @gather_mask_dps(<16 x i32> %ind, <16 x float> %src, i16 %mask, i8*
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherdps (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterdps %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -33,7 +33,7 @@ define void @gather_mask_dpd(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %b
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherdpd (%rsi,%ymm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vscatterdpd %zmm1, (%rdx,%ymm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -49,7 +49,7 @@ define void @gather_mask_qps(<8 x i64> %ind, <8 x float> %src, i8 %mask, i8* %ba
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherqps (%rsi,%zmm0,4), %ymm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterqps %ymm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -65,7 +65,7 @@ define void @gather_mask_qpd(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %b
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherqpd (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterqpd %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -93,7 +93,7 @@ define void @gather_mask_dd(<16 x i32> %ind, <16 x i32> %src, i16 %mask, i8* %ba
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherdd (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vpscatterdd %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -109,7 +109,7 @@ define void @gather_mask_qd(<8 x i64> %ind, <8 x i32> %src, i8 %mask, i8* %base,
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherqd (%rsi,%zmm0,4), %ymm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vpscatterqd %ymm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -125,7 +125,7 @@ define void @gather_mask_qq(<8 x i64> %ind, <8 x i64> %src, i8 %mask, i8* %base,
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherqq (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vpscatterqq %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -141,7 +141,7 @@ define void @gather_mask_dq(<8 x i32> %ind, <8 x i64> %src, i8 %mask, i8* %base,
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherdq (%rsi,%ymm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vpscatterdq %zmm1, (%rdx,%ymm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -258,7 +258,7 @@ define void @gather_qps(<8 x i64> %ind, <8 x float> %src, i8* %base, i8* %stbuf)
; CHECK-NEXT: kxnorw %k0, %k0, %k1
; CHECK-NEXT: kxnorw %k0, %k0, %k2
; CHECK-NEXT: vgatherqps (%rdi,%zmm0,4), %ymm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterqps %ymm1, (%rsi,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll b/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
index 1bddfd962285d..609cd1a4ed4ee 100644
--- a/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
+++ b/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
@@ -7,7 +7,7 @@ define dso_local void @gather_mask_dps(<16 x i32> %ind, <16 x float> %src, i16 %
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherdps (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterdps %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -24,7 +24,7 @@ define dso_local void @gather_mask_dpd(<8 x i32> %ind, <8 x double> %src, i8 %ma
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherdpd (%rsi,%ymm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vscatterdpd %zmm1, (%rdx,%ymm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -41,7 +41,7 @@ define dso_local void @gather_mask_qps(<8 x i64> %ind, <8 x float> %src, i8 %mas
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherqps (%rsi,%zmm0,4), %ymm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterqps %ymm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -58,7 +58,7 @@ define dso_local void @gather_mask_qpd(<8 x i64> %ind, <8 x double> %src, i8 %ma
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vgatherqpd (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterqpd %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -78,7 +78,7 @@ define dso_local void @gather_mask_dd(<16 x i32> %ind, <16 x i32> %src, i16 %mas
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherdd (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vpscatterdd %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -95,7 +95,7 @@ define dso_local void @gather_mask_qd(<8 x i64> %ind, <8 x i32> %src, i8 %mask,
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherqd (%rsi,%zmm0,4), %ymm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vpscatterqd %ymm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -112,7 +112,7 @@ define dso_local void @gather_mask_qq(<8 x i64> %ind, <8 x i64> %src, i8 %mask,
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherqq (%rsi,%zmm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vpscatterqq %zmm1, (%rdx,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -129,7 +129,7 @@ define dso_local void @gather_mask_dq(<8 x i32> %ind, <8 x i64> %src, i8 %mask,
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: kmovq %k1, %k2
; CHECK-NEXT: vpgatherdq (%rsi,%ymm0,4), %zmm1 {%k2}
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vpscatterdq %zmm1, (%rdx,%ymm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -255,7 +255,7 @@ define dso_local void @gather_qps(<8 x i64> %ind, <8 x float> %src, i8* %base, i
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT: kxnorw %k0, %k0, %k2
; CHECK-NEXT: vgatherqps (%rdi,%zmm0,4), %ymm1 {%k2}
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: vscatterqps %ymm1, (%rsi,%zmm0,4) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/avx512-insert-extract.ll b/llvm/test/CodeGen/X86/avx512-insert-extract.ll
index ea7f928d09be3..7274d8335129c 100644
--- a/llvm/test/CodeGen/X86/avx512-insert-extract.ll
+++ b/llvm/test/CodeGen/X86/avx512-insert-extract.ll
@@ -1657,7 +1657,7 @@ define i32 @test_insertelement_variable_v32i1(<32 x i8> %a, i8 %b, i32 %index) {
; SKX-NEXT: testb %dil, %dil
; SKX-NEXT: setne %al
; SKX-NEXT: vpbroadcastb %esi, %ymm0
-; SKX-NEXT: vpcmpeqb {{.*}}(%rip), %ymm0, %k1
+; SKX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k1
; SKX-NEXT: vpmovm2b %k0, %ymm0
; SKX-NEXT: vpbroadcastb %eax, %ymm0 {%k1}
; SKX-NEXT: vpsllw $7, %ymm0, %ymm0
@@ -1726,7 +1726,7 @@ define i64 @test_insertelement_variable_v64i1(<64 x i8> %a, i8 %b, i32 %index) {
; SKX-NEXT: testb %dil, %dil
; SKX-NEXT: setne %al
; SKX-NEXT: vpbroadcastb %esi, %zmm0
-; SKX-NEXT: vpcmpeqb {{.*}}(%rip), %zmm0, %k1
+; SKX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k1
; SKX-NEXT: vpmovm2b %k0, %zmm0
; SKX-NEXT: vpbroadcastb %eax, %zmm0 {%k1}
; SKX-NEXT: vpsllw $7, %zmm0, %zmm0
diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
index e78ba264d7cc5..667af6579e794 100644
--- a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
@@ -1840,7 +1840,7 @@ define <2 x double> @test_mm_cvtu64_sd(<2 x double> %__A, i64 %__B) {
; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
; X86-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
-; X86-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; X86-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
; X86-NEXT: vaddsd %xmm1, %xmm2, %xmm1
; X86-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
@@ -1888,7 +1888,7 @@ define <4 x float> @test_mm_cvtu64_ss(<4 x float> %__A, i64 %__B) {
; X86-NEXT: vmovq %xmm1, {{[0-9]+}}(%esp)
; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll {{[0-9]+}}(%esp)
-; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: fstps {{[0-9]+}}(%esp)
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
@@ -3118,13 +3118,13 @@ entry:
define <8 x double> @test_mm512_fmsub_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fmsub_round_pd:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
+; X86-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
; X86-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fmsub_round_pd:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2
+; X64-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
; X64-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq
entry:
@@ -3178,13 +3178,13 @@ entry:
define <8 x double> @test_mm512_fnmadd_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fnmadd_round_pd:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
+; X86-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fnmadd_round_pd:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; X64-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq
entry:
@@ -3349,13 +3349,13 @@ entry:
define <8 x double> @test_mm512_fmsub_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fmsub_pd:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
+; X86-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
; X86-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fmsub_pd:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2
+; X64-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
; X64-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq
entry:
@@ -3409,13 +3409,13 @@ entry:
define <8 x double> @test_mm512_fnmadd_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fnmadd_pd:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
+; X86-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fnmadd_pd:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; X64-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq
entry:
@@ -3582,13 +3582,13 @@ entry:
define <16 x float> @test_mm512_fmsub_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fmsub_round_ps:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
+; X86-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
; X86-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fmsub_round_ps:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2
+; X64-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
; X64-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq
entry:
@@ -3642,13 +3642,13 @@ entry:
define <16 x float> @test_mm512_fnmadd_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fnmadd_round_ps:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
+; X86-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fnmadd_round_ps:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; X64-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; X64-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq
entry:
@@ -3813,13 +3813,13 @@ entry:
define <16 x float> @test_mm512_fmsub_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fmsub_ps:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
+; X86-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
; X86-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fmsub_ps:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2
+; X64-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
; X64-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq
entry:
@@ -3873,13 +3873,13 @@ entry:
define <16 x float> @test_mm512_fnmadd_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fnmadd_ps:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
+; X86-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fnmadd_ps:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; X64-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; X64-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq
entry:
@@ -4046,13 +4046,13 @@ entry:
define <8 x double> @test_mm512_fmsubadd_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fmsubadd_round_pd:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
+; X86-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
; X86-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fmsubadd_round_pd:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2
+; X64-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
; X64-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq
entry:
@@ -4323,13 +4323,13 @@ entry:
define <16 x float> @test_mm512_fmsubadd_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fmsubadd_round_ps:
; X86: # %bb.0: # %entry
-; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
+; X86-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
; X86-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: test_mm512_fmsubadd_round_ps:
; X64: # %bb.0: # %entry
-; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2
+; X64-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
; X64-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
index e2d5a3b60f5f5..40a6ec8aa5f34 100644
--- a/llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
+++ b/llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
@@ -5265,14 +5265,14 @@ define <16 x float>@test_int_x86_avx512_mask_vpermilvar_ps_512_constant_pool(<16
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ## encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermilps {{.*#+}} zmm2 {%k1} = zmm0[2,3,0,1,7,6,5,4,9,8,11,10,12,13,14,15]
; X86-NEXT: ## encoding: [0x62,0xf2,0x7d,0x49,0x0c,0x15,A,A,A,A]
-; X86-NEXT: ## fixup A - offset: 6, value: LCPI299_0, kind: FK_Data_4
+; X86-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpermilps {{.*#+}} zmm1 {%k1} {z} = zmm0[1,0,3,2,4,5,6,7,9,8,11,10,12,13,14,15]
; X86-NEXT: ## encoding: [0x62,0xf2,0x7d,0xc9,0x0c,0x0d,A,A,A,A]
-; X86-NEXT: ## fixup A - offset: 6, value: LCPI299_1, kind: FK_Data_4
+; X86-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vaddps %zmm1, %zmm2, %zmm1 ## encoding: [0x62,0xf1,0x6c,0x48,0x58,0xc9]
; X86-NEXT: vpermilps {{.*#+}} zmm0 = zmm0[1,0,3,2,4,5,6,7,10,11,8,9,14,15,13,12]
; X86-NEXT: ## encoding: [0x62,0xf2,0x7d,0x48,0x0c,0x05,A,A,A,A]
-; X86-NEXT: ## fixup A - offset: 6, value: LCPI299_2, kind: FK_Data_4
+; X86-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vaddps %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x58,0xc1]
; X86-NEXT: retl ## encoding: [0xc3]
;
@@ -5281,14 +5281,14 @@ define <16 x float>@test_int_x86_avx512_mask_vpermilvar_ps_512_constant_pool(<16
; X64-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; X64-NEXT: vpermilps {{.*#+}} zmm2 {%k1} = zmm0[2,3,0,1,7,6,5,4,9,8,11,10,12,13,14,15]
; X64-NEXT: ## encoding: [0x62,0xf2,0x7d,0x49,0x0c,0x15,A,A,A,A]
-; X64-NEXT: ## fixup A - offset: 6, value: LCPI299_0-4, kind: reloc_riprel_4byte
+; X64-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpermilps {{.*#+}} zmm1 {%k1} {z} = zmm0[1,0,3,2,4,5,6,7,9,8,11,10,12,13,14,15]
; X64-NEXT: ## encoding: [0x62,0xf2,0x7d,0xc9,0x0c,0x0d,A,A,A,A]
-; X64-NEXT: ## fixup A - offset: 6, value: LCPI299_1-4, kind: reloc_riprel_4byte
+; X64-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vaddps %zmm1, %zmm2, %zmm1 ## encoding: [0x62,0xf1,0x6c,0x48,0x58,0xc9]
; X64-NEXT: vpermilps {{.*#+}} zmm0 = zmm0[1,0,3,2,4,5,6,7,10,11,8,9,14,15,13,12]
; X64-NEXT: ## encoding: [0x62,0xf2,0x7d,0x48,0x0c,0x05,A,A,A,A]
-; X64-NEXT: ## fixup A - offset: 6, value: LCPI299_2-4, kind: reloc_riprel_4byte
+; X64-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vaddps %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x58,0xc1]
; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x float> @llvm.x86.avx512.mask.vpermilvar.ps.512(<16 x float> %x0, <16 x i32> <i32 2, i32 3, i32 0, i32 1, i32 3, i32 2, i32 1, i32 0, i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3>, <16 x float> %x2, i16 %x3)
diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics.ll b/llvm/test/CodeGen/X86/avx512-intrinsics.ll
index 818cd76946dbc..41e21e9b40c7b 100644
--- a/llvm/test/CodeGen/X86/avx512-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512-intrinsics.ll
@@ -7109,18 +7109,18 @@ define <16 x i32> @test_x86_avx512_psllv_d_512_const() {
; X64-LABEL: test_x86_avx512_psllv_d_512_const:
; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0]
-; X64-NEXT: vpsllvd {{.*}}(%rip), %zmm0, %zmm0
+; X64-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
-; X64-NEXT: vpsllvd {{.*}}(%rip), %zmm1, %zmm1
+; X64-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X64-NEXT: retq
;
; X86-LABEL: test_x86_avx512_psllv_d_512_const:
; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0]
-; X86-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
+; X86-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
-; X86-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
+; X86-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X86-NEXT: retl
%res0 = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)
@@ -7182,18 +7182,18 @@ define <8 x i64> @test_x86_avx512_psllv_q_512_const() {
; X64-LABEL: test_x86_avx512_psllv_q_512_const:
; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,18446744073709551615,3,7,18446744073709551615,0]
-; X64-NEXT: vpsllvq {{.*}}(%rip), %zmm0, %zmm0
+; X64-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,18446744073709551615]
-; X64-NEXT: vpsllvq {{.*}}(%rip), %zmm1, %zmm1
+; X64-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X64-NEXT: retq
;
; X86-LABEL: test_x86_avx512_psllv_q_512_const:
; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,0,9,0,0,0,4294967295,4294967295,3,0,7,0,4294967295,4294967295,0,0]
-; X86-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
+; X86-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,0,4,0,4,0,4,0,4,0,4,0,4,0,4294967295,4294967295]
-; X86-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
+; X86-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X86-NEXT: retl
%res0 = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>)
@@ -7357,18 +7357,18 @@ define <16 x i32> @test_x86_avx512_psrlv_d_512_const() {
; X64-LABEL: test_x86_avx512_psrlv_d_512_const:
; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0]
-; X64-NEXT: vpsrlvd {{.*}}(%rip), %zmm0, %zmm0
+; X64-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
-; X64-NEXT: vpsrlvd {{.*}}(%rip), %zmm1, %zmm1
+; X64-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X64-NEXT: retq
;
; X86-LABEL: test_x86_avx512_psrlv_d_512_const:
; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0]
-; X86-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
+; X86-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
-; X86-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
+; X86-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X86-NEXT: retl
%res0 = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)
@@ -7430,18 +7430,18 @@ define <8 x i64> @test_x86_avx512_psrlv_q_512_const() {
; X64-LABEL: test_x86_avx512_psrlv_q_512_const:
; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,18446744073709551615,3,7,18446744073709551615,0]
-; X64-NEXT: vpsrlvq {{.*}}(%rip), %zmm0, %zmm0
+; X64-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,18446744073709551615]
-; X64-NEXT: vpsrlvq {{.*}}(%rip), %zmm1, %zmm1
+; X64-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X64-NEXT: retq
;
; X86-LABEL: test_x86_avx512_psrlv_q_512_const:
; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,0,9,0,0,0,4294967295,4294967295,3,0,7,0,4294967295,4294967295,0,0]
-; X86-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
+; X86-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,0,4,0,4,0,4,0,4,0,4,0,4,0,4294967295,4294967295]
-; X86-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
+; X86-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X86-NEXT: retl
%res0 = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>)
diff --git a/llvm/test/CodeGen/X86/avx512-logic.ll b/llvm/test/CodeGen/X86/avx512-logic.ll
index b8f6c50ee344b..ac35c5639cc85 100644
--- a/llvm/test/CodeGen/X86/avx512-logic.ll
+++ b/llvm/test/CodeGen/X86/avx512-logic.ll
@@ -6,7 +6,7 @@
define <16 x i32> @vpandd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vpandd:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; ALL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; ALL-NEXT: vpandd %zmm1, %zmm0, %zmm0
; ALL-NEXT: retq
entry:
@@ -20,7 +20,7 @@ entry:
define <16 x i32> @vpandnd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vpandnd:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; ALL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; ALL-NEXT: vpandnd %zmm0, %zmm1, %zmm0
; ALL-NEXT: retq
entry:
@@ -36,7 +36,7 @@ entry:
define <16 x i32> @vpord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vpord:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; ALL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; ALL-NEXT: vpord %zmm1, %zmm0, %zmm0
; ALL-NEXT: retq
entry:
@@ -50,7 +50,7 @@ entry:
define <16 x i32> @vpxord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vpxord:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; ALL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; ALL-NEXT: vpxord %zmm1, %zmm0, %zmm0
; ALL-NEXT: retq
entry:
@@ -64,7 +64,7 @@ entry:
define <8 x i64> @vpandq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vpandq:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; ALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; ALL-NEXT: vpandq %zmm1, %zmm0, %zmm0
; ALL-NEXT: retq
entry:
@@ -77,7 +77,7 @@ entry:
define <8 x i64> @vpandnq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vpandnq:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; ALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; ALL-NEXT: vpandnq %zmm0, %zmm1, %zmm0
; ALL-NEXT: retq
entry:
@@ -91,7 +91,7 @@ entry:
define <8 x i64> @vporq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vporq:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; ALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; ALL-NEXT: vporq %zmm1, %zmm0, %zmm0
; ALL-NEXT: retq
entry:
@@ -104,7 +104,7 @@ entry:
define <8 x i64> @vpxorq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
; ALL-LABEL: vpxorq:
; ALL: ## %bb.0: ## %entry
-; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; ALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; ALL-NEXT: vpxorq %zmm1, %zmm0, %zmm0
; ALL-NEXT: retq
entry:
@@ -118,12 +118,12 @@ entry:
define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {
; KNL-LABEL: orq_broadcast:
; KNL: ## %bb.0:
-; KNL-NEXT: vporq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; KNL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: orq_broadcast:
; SKX: ## %bb.0:
-; SKX-NEXT: vorpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; SKX-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; SKX-NEXT: retq
%b = or <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
ret <8 x i64> %b
@@ -889,7 +889,7 @@ define <16 x i32> @ternlog_xor_andn(<16 x i32> %x, <16 x i32> %y, <16 x i32> %z)
define <16 x i32> @ternlog_or_and_mask(<16 x i32> %x, <16 x i32> %y) {
; ALL-LABEL: ternlog_or_and_mask:
; ALL: ## %bb.0:
-; ALL-NEXT: vpternlogd $236, {{.*}}(%rip), %zmm1, %zmm0
+; ALL-NEXT: vpternlogd $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; ALL-NEXT: retq
%a = and <16 x i32> %x, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
%b = or <16 x i32> %a, %y
@@ -899,7 +899,7 @@ define <16 x i32> @ternlog_or_and_mask(<16 x i32> %x, <16 x i32> %y) {
define <8 x i64> @ternlog_xor_and_mask(<8 x i64> %x, <8 x i64> %y) {
; ALL-LABEL: ternlog_xor_and_mask:
; ALL: ## %bb.0:
-; ALL-NEXT: vpternlogq $108, {{.*}}(%rip), %zmm1, %zmm0
+; ALL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; ALL-NEXT: retq
%a = and <8 x i64> %x, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
%b = xor <8 x i64> %a, %y
@@ -911,14 +911,14 @@ define <16 x i32> @ternlog_maskz_or_and_mask(<16 x i32> %x, <16 x i32> %y, <16 x
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
-; KNL-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: vpord %zmm1, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskz_or_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %zmm2, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; SKX-NEXT: vorps %zmm1, %zmm0, %zmm0 {%k1} {z}
; SKX-NEXT: retq
%m = icmp slt <16 x i32> %mask, zeroinitializer
@@ -933,14 +933,14 @@ define <8 x i64> @ternlog_maskz_xor_and_mask(<8 x i64> %x, <8 x i64> %y, <8 x i6
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: vpxorq %zmm1, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskz_xor_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %zmm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %zmm0, %zmm0
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; SKX-NEXT: vxorpd %zmm1, %zmm0, %zmm0 {%k1} {z}
; SKX-NEXT: retq
%m = icmp slt <8 x i64> %mask, zeroinitializer
@@ -955,14 +955,14 @@ define <16 x i32> @ternlog_maskx_or_and_mask(<16 x i32> %x, <16 x i32> %y, <16 x
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm2
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
; KNL-NEXT: vpord %zmm1, %zmm2, %zmm0 {%k1}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskx_or_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %zmm2, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm2
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
; SKX-NEXT: vorps %zmm1, %zmm2, %zmm0 {%k1}
; SKX-NEXT: retq
%m = icmp slt <16 x i32> %mask, zeroinitializer
@@ -977,7 +977,7 @@ define <16 x i32> @ternlog_masky_or_and_mask(<16 x i32> %x, <16 x i32> %y, <16 x
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
-; KNL-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: vpord %zmm1, %zmm0, %zmm1 {%k1}
; KNL-NEXT: vmovdqa64 %zmm1, %zmm0
; KNL-NEXT: retq
@@ -985,7 +985,7 @@ define <16 x i32> @ternlog_masky_or_and_mask(<16 x i32> %x, <16 x i32> %y, <16 x
; SKX-LABEL: ternlog_masky_or_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %zmm2, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; SKX-NEXT: vorps %zmm1, %zmm0, %zmm1 {%k1}
; SKX-NEXT: vmovaps %zmm1, %zmm0
; SKX-NEXT: retq
@@ -1001,14 +1001,14 @@ define <8 x i64> @ternlog_maskx_xor_and_mask(<8 x i64> %x, <8 x i64> %y, <8 x i6
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
-; KNL-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm2
+; KNL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
; KNL-NEXT: vpxorq %zmm1, %zmm2, %zmm0 {%k1}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskx_xor_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %zmm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %zmm0, %zmm2
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
; SKX-NEXT: vxorpd %zmm1, %zmm2, %zmm0 {%k1}
; SKX-NEXT: retq
%m = icmp slt <8 x i64> %mask, zeroinitializer
@@ -1023,7 +1023,7 @@ define <8 x i64> @ternlog_masky_xor_and_mask(<8 x i64> %x, <8 x i64> %y, <8 x i6
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: vpxorq %zmm1, %zmm0, %zmm1 {%k1}
; KNL-NEXT: vmovdqa64 %zmm1, %zmm0
; KNL-NEXT: retq
@@ -1031,7 +1031,7 @@ define <8 x i64> @ternlog_masky_xor_and_mask(<8 x i64> %x, <8 x i64> %y, <8 x i6
; SKX-LABEL: ternlog_masky_xor_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %zmm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %zmm0, %zmm0
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; SKX-NEXT: vxorpd %zmm1, %zmm0, %zmm1 {%k1}
; SKX-NEXT: vmovapd %zmm1, %zmm0
; SKX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll
index c9f29a6890862..c6535a2a00435 100644
--- a/llvm/test/CodeGen/X86/avx512-mask-op.ll
+++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll
@@ -1841,9 +1841,9 @@ define void @store_v16i1(<16 x i1> %c , <16 x i1>* %ptr) {
define void @f1(i32 %c) {
; CHECK-LABEL: f1:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: movzbl {{.*}}(%rip), %edi
+; CHECK-NEXT: movzbl _f1.v(%rip), %edi
; CHECK-NEXT: xorl $1, %edi
-; CHECK-NEXT: movb %dil, {{.*}}(%rip)
+; CHECK-NEXT: movb %dil, _f1.v(%rip)
; CHECK-NEXT: jmp _f2 ## TAILCALL
;
; X86-LABEL: f1:
@@ -1909,27 +1909,27 @@ define void @store_i8_i1(i8 %x, i1 *%y) {
define <32 x i16> @test_build_vec_v32i1(<32 x i16> %x) {
; KNL-LABEL: test_build_vec_v32i1:
; KNL: ## %bb.0:
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: test_build_vec_v32i1:
; SKX: ## %bb.0:
-; SKX-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_build_vec_v32i1:
; AVX512BW: ## %bb.0:
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_build_vec_v32i1:
; AVX512DQ: ## %bb.0:
-; AVX512DQ-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; X86-LABEL: test_build_vec_v32i1:
; X86: ## %bb.0:
-; X86-NEXT: vandps LCPI40_0, %zmm0, %zmm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: retl
%ret = select <32 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false>, <32 x i16> %x, <32 x i16> zeroinitializer
ret <32 x i16> %ret
@@ -1938,7 +1938,7 @@ define <32 x i16> @test_build_vec_v32i1(<32 x i16> %x) {
define <32 x i16> @test_build_vec_v32i1_optsize(<32 x i16> %x) optsize {
; KNL-LABEL: test_build_vec_v32i1_optsize:
; KNL: ## %bb.0:
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: test_build_vec_v32i1_optsize:
@@ -1957,7 +1957,7 @@ define <32 x i16> @test_build_vec_v32i1_optsize(<32 x i16> %x) optsize {
;
; AVX512DQ-LABEL: test_build_vec_v32i1_optsize:
; AVX512DQ: ## %bb.0:
-; AVX512DQ-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; X86-LABEL: test_build_vec_v32i1_optsize:
@@ -1973,7 +1973,7 @@ define <32 x i16> @test_build_vec_v32i1_optsize(<32 x i16> %x) optsize {
define <32 x i16> @test_build_vec_v32i1_pgso(<32 x i16> %x) !prof !14 {
; KNL-LABEL: test_build_vec_v32i1_pgso:
; KNL: ## %bb.0:
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: test_build_vec_v32i1_pgso:
@@ -1992,7 +1992,7 @@ define <32 x i16> @test_build_vec_v32i1_pgso(<32 x i16> %x) !prof !14 {
;
; AVX512DQ-LABEL: test_build_vec_v32i1_pgso:
; AVX512DQ: ## %bb.0:
-; AVX512DQ-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; X86-LABEL: test_build_vec_v32i1_pgso:
@@ -2008,27 +2008,27 @@ define <32 x i16> @test_build_vec_v32i1_pgso(<32 x i16> %x) !prof !14 {
define <64 x i8> @test_build_vec_v64i1(<64 x i8> %x) {
; KNL-LABEL: test_build_vec_v64i1:
; KNL: ## %bb.0:
-; KNL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; KNL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: test_build_vec_v64i1:
; SKX: ## %bb.0:
-; SKX-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_build_vec_v64i1:
; AVX512BW: ## %bb.0:
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_build_vec_v64i1:
; AVX512DQ: ## %bb.0:
-; AVX512DQ-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
; X86-LABEL: test_build_vec_v64i1:
; X86: ## %bb.0:
-; X86-NEXT: vandps LCPI43_0, %zmm0, %zmm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: retl
%ret = select <64 x i1> <i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false>, <64 x i8> %x, <64 x i8> zeroinitializer
ret <64 x i8> %ret
diff --git a/llvm/test/CodeGen/X86/avx512-rotate.ll b/llvm/test/CodeGen/X86/avx512-rotate.ll
index 7f69c5011f48a..be1fc5ee21eb1 100644
--- a/llvm/test/CodeGen/X86/avx512-rotate.ll
+++ b/llvm/test/CodeGen/X86/avx512-rotate.ll
@@ -255,7 +255,7 @@ define <16 x i32> @test_fold_rol_v16i32(<16 x i32> %x0, <16 x i32> %x1) {
; CHECK-LABEL: test_fold_rol_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastd {{.*#+}} zmm0 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; CHECK-NEXT: vprolvd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
%res0 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <16 x i32> zeroinitializer, i16 -1)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.prolv.d.512(<16 x i32> %res0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, <16 x i32> zeroinitializer, i16 -1)
@@ -266,7 +266,7 @@ define <8 x i64> @test_fold_ror_v8i64() {
; CHECK-LABEL: test_fold_ror_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastq {{.*#+}} zmm0 = [1,1,1,1,1,1,1,1]
-; CHECK-NEXT: vprorvq {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vprorvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
%res0 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 undef, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, <8 x i64> zeroinitializer, i8 -1)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64> %res0, <8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, <8 x i64> zeroinitializer, i8 -1)
@@ -277,7 +277,7 @@ define <16 x i32> @test_fold_ror_v16i32(<16 x i32> %x0, <16 x i32> %x1) {
; CHECK-LABEL: test_fold_ror_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastd {{.*#+}} zmm0 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; CHECK-NEXT: vprorvd {{.*}}(%rip), %zmm0, %zmm0
+; CHECK-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
%res0 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <16 x i32> zeroinitializer, i16 -1)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32> %res0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, <16 x i32> zeroinitializer, i16 -1)
diff --git a/llvm/test/CodeGen/X86/avx512-trunc.ll b/llvm/test/CodeGen/X86/avx512-trunc.ll
index a589ebe01abce..43dff5bc236ae 100644
--- a/llvm/test/CodeGen/X86/avx512-trunc.ll
+++ b/llvm/test/CodeGen/X86/avx512-trunc.ll
@@ -581,7 +581,7 @@ define void @trunc_wb_128_mem(<8 x i16> %i, <8 x i8>* %res) #0 {
define void @usat_trunc_wb_256_mem(<16 x i16> %i, <16 x i8>* %res) {
; KNL-LABEL: usat_trunc_wb_256_mem:
; KNL: ## %bb.0:
-; KNL-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; KNL-NEXT: vpmovdb %zmm0, (%rdi)
; KNL-NEXT: vzeroupper
@@ -602,7 +602,7 @@ define void @usat_trunc_wb_256_mem(<16 x i16> %i, <16 x i8>* %res) {
define <16 x i8> @usat_trunc_wb_256(<16 x i16> %i) {
; KNL-LABEL: usat_trunc_wb_256:
; KNL: ## %bb.0:
-; KNL-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; KNL-NEXT: vpmovdb %zmm0, %xmm0
; KNL-NEXT: vzeroupper
@@ -622,7 +622,7 @@ define <16 x i8> @usat_trunc_wb_256(<16 x i16> %i) {
define void @usat_trunc_wb_128_mem(<8 x i16> %i, <8 x i8>* %res) {
; KNL-LABEL: usat_trunc_wb_128_mem:
; KNL: ## %bb.0:
-; KNL-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovq %xmm0, (%rdi)
; KNL-NEXT: retq
@@ -731,7 +731,7 @@ define <16 x i16> @usat_trunc_dw_512(<16 x i32> %i) {
define <8 x i8> @usat_trunc_wb_128(<8 x i16> %i) {
; KNL-LABEL: usat_trunc_wb_128:
; KNL: ## %bb.0:
-; KNL-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; KNL-NEXT: retq
;
@@ -1008,8 +1008,8 @@ define <16 x i16> @smax_usat_trunc_dw_512(<16 x i32> %i) {
define void @negative_test1_smax_usat_trunc_wb_256_mem(<16 x i16> %i, <16 x i8>* %res) {
; KNL-LABEL: negative_test1_smax_usat_trunc_wb_256_mem:
; KNL: ## %bb.0:
-; KNL-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
-; KNL-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; KNL-NEXT: vpmovdb %zmm0, (%rdi)
; KNL-NEXT: vzeroupper
@@ -1017,8 +1017,8 @@ define void @negative_test1_smax_usat_trunc_wb_256_mem(<16 x i16> %i, <16 x i8>*
;
; SKX-LABEL: negative_test1_smax_usat_trunc_wb_256_mem:
; SKX: ## %bb.0:
-; SKX-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
-; SKX-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
+; SKX-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; SKX-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; SKX-NEXT: vpmovwb %ymm0, (%rdi)
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
@@ -1034,8 +1034,8 @@ define void @negative_test1_smax_usat_trunc_wb_256_mem(<16 x i16> %i, <16 x i8>*
define void @negative_test2_smax_usat_trunc_wb_256_mem(<16 x i16> %i, <16 x i8>* %res) {
; KNL-LABEL: negative_test2_smax_usat_trunc_wb_256_mem:
; KNL: ## %bb.0:
-; KNL-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
-; KNL-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; KNL-NEXT: vpmovdb %zmm0, (%rdi)
; KNL-NEXT: vzeroupper
@@ -1043,8 +1043,8 @@ define void @negative_test2_smax_usat_trunc_wb_256_mem(<16 x i16> %i, <16 x i8>*
;
; SKX-LABEL: negative_test2_smax_usat_trunc_wb_256_mem:
; SKX: ## %bb.0:
-; SKX-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
-; SKX-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
+; SKX-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; SKX-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; SKX-NEXT: vpmovwb %ymm0, (%rdi)
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/avx512-vbroadcast.ll b/llvm/test/CodeGen/X86/avx512-vbroadcast.ll
index 966d7655f49a5..5802502f25618 100644
--- a/llvm/test/CodeGen/X86/avx512-vbroadcast.ll
+++ b/llvm/test/CodeGen/X86/avx512-vbroadcast.ll
@@ -402,7 +402,7 @@ define <16 x float> @broadcast_ss_spill(float %x) {
; ALL-NEXT: .cfi_def_cfa_offset 32
; ALL-NEXT: vaddss %xmm0, %xmm0, %xmm0
; ALL-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; ALL-NEXT: callq func_f32
+; ALL-NEXT: callq func_f32 at PLT
; ALL-NEXT: vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload
; ALL-NEXT: addq $24, %rsp
; ALL-NEXT: .cfi_def_cfa_offset 8
@@ -422,7 +422,7 @@ define <8 x double> @broadcast_sd_spill(double %x) {
; ALL-NEXT: .cfi_def_cfa_offset 32
; ALL-NEXT: vaddsd %xmm0, %xmm0, %xmm0
; ALL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
-; ALL-NEXT: callq func_f64
+; ALL-NEXT: callq func_f64 at PLT
; ALL-NEXT: vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload
; ALL-NEXT: addq $24, %rsp
; ALL-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/avx512-vbroadcasti128.ll b/llvm/test/CodeGen/X86/avx512-vbroadcasti128.ll
index 8e800f2a44a3d..4e3340e4aedcf 100644
--- a/llvm/test/CodeGen/X86/avx512-vbroadcasti128.ll
+++ b/llvm/test/CodeGen/X86/avx512-vbroadcasti128.ll
@@ -11,7 +11,7 @@ define <4 x double> @test_broadcast_2f64_4f64(<2 x double> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_2f64_4f64:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-AVX512-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: retq
%1 = load <2 x double>, <2 x double> *%p
%2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
@@ -23,7 +23,7 @@ define <4 x i64> @test_broadcast_2i64_4i64(<2 x i64> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_2i64_4i64:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-AVX512-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: retq
%1 = load <2 x i64>, <2 x i64> *%p
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
@@ -35,7 +35,7 @@ define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_4f32_8f32:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-AVX512-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: retq
%1 = load <4 x float>, <4 x float> *%p
%2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -47,7 +47,7 @@ define <8 x i32> @test_broadcast_4i32_8i32(<4 x i32> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_4i32_8i32:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-AVX512-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: retq
%1 = load <4 x i32>, <4 x i32> *%p
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -59,7 +59,7 @@ define <16 x i16> @test_broadcast_8i16_16i16(<8 x i16> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_8i16_16i16:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-AVX512-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: retq
%1 = load <8 x i16>, <8 x i16> *%p
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -71,7 +71,7 @@ define <32 x i8> @test_broadcast_16i8_32i8(<16 x i8> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_16i8_32i8:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-AVX512-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: retq
%1 = load <16 x i8>, <16 x i8> *%p
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -87,7 +87,7 @@ define <8 x double> @test_broadcast_2f64_8f64(<2 x double> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_2f64_8f64:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcastf32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vaddpd {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <2 x double>, <2 x double> *%p
%2 = shufflevector <2 x double> %1, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
@@ -99,7 +99,7 @@ define <8 x i64> @test_broadcast_2i64_8i64(<2 x i64> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_2i64_8i64:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <2 x i64>, <2 x i64> *%p
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
@@ -111,7 +111,7 @@ define <16 x float> @test_broadcast_4f32_16f32(<4 x float> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_4f32_16f32:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcastf32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vaddps {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <4 x float>, <4 x float> *%p
%2 = shufflevector <4 x float> %1, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -123,7 +123,7 @@ define <16 x i32> @test_broadcast_4i32_16i32(<4 x i32> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_4i32_16i32:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <4 x i32>, <4 x i32> *%p
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -135,24 +135,24 @@ define <32 x i16> @test_broadcast_8i16_32i16(<8 x i16> *%p) nounwind {
; X64-AVX512VL-LABEL: test_broadcast_8i16_32i16:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512VL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm1
+; X64-AVX512VL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; X64-AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
-; X64-AVX512VL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512BWVL-LABEL: test_broadcast_8i16_32i16:
; X64-AVX512BWVL: ## %bb.0:
; X64-AVX512BWVL-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512BWVL-NEXT: vpaddw {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512BWVL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512BWVL-NEXT: retq
;
; X64-AVX512DQVL-LABEL: test_broadcast_8i16_32i16:
; X64-AVX512DQVL: ## %bb.0:
; X64-AVX512DQVL-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512DQVL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm1
+; X64-AVX512DQVL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; X64-AVX512DQVL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
-; X64-AVX512DQVL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQVL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQVL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512DQVL-NEXT: retq
%1 = load <8 x i16>, <8 x i16> *%p
@@ -165,24 +165,24 @@ define <64 x i8> @test_broadcast_16i8_64i8(<16 x i8> *%p) nounwind {
; X64-AVX512VL-LABEL: test_broadcast_16i8_64i8:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512VL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm1
+; X64-AVX512VL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; X64-AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
-; X64-AVX512VL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512BWVL-LABEL: test_broadcast_16i8_64i8:
; X64-AVX512BWVL: ## %bb.0:
; X64-AVX512BWVL-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512BWVL-NEXT: vpaddb {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512BWVL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512BWVL-NEXT: retq
;
; X64-AVX512DQVL-LABEL: test_broadcast_16i8_64i8:
; X64-AVX512DQVL: ## %bb.0:
; X64-AVX512DQVL-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
-; X64-AVX512DQVL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm1
+; X64-AVX512DQVL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; X64-AVX512DQVL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
-; X64-AVX512DQVL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQVL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQVL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512DQVL-NEXT: retq
%1 = load <16 x i8>, <16 x i8> *%p
diff --git a/llvm/test/CodeGen/X86/avx512-vbroadcasti256.ll b/llvm/test/CodeGen/X86/avx512-vbroadcasti256.ll
index 33b3ddba0fcc5..c945d180bbea2 100644
--- a/llvm/test/CodeGen/X86/avx512-vbroadcasti256.ll
+++ b/llvm/test/CodeGen/X86/avx512-vbroadcasti256.ll
@@ -7,7 +7,7 @@ define <8 x double> @test_broadcast_4f64_8f64(<4 x double> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_4f64_8f64:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcastf64x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vaddpd {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <4 x double>, <4 x double> *%p
%2 = shufflevector <4 x double> %1, <4 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -19,7 +19,7 @@ define <8 x i64> @test_broadcast_4i64_8i64(<4 x i64> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_4i64_8i64:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <4 x i64>, <4 x i64> *%p
%2 = shufflevector <4 x i64> %1, <4 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -31,7 +31,7 @@ define <16 x float> @test_broadcast_8f32_16f32(<8 x float> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_8f32_16f32:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcastf64x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vaddps {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <8 x float>, <8 x float> *%p
%2 = shufflevector <8 x float> %1, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -43,7 +43,7 @@ define <16 x i32> @test_broadcast_8i32_16i32(<8 x i32> *%p) nounwind {
; X64-AVX512-LABEL: test_broadcast_8i32_16i32:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512-NEXT: retq
%1 = load <8 x i32>, <8 x i32> *%p
%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -55,22 +55,22 @@ define <32 x i16> @test_broadcast_16i16_32i16(<16 x i16> *%p) nounwind {
; X64-AVX512VL-LABEL: test_broadcast_16i16_32i16:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovdqa (%rdi), %ymm0
-; X64-AVX512VL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm1
-; X64-AVX512VL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; X64-AVX512VL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512BWVL-LABEL: test_broadcast_16i16_32i16:
; X64-AVX512BWVL: ## %bb.0:
; X64-AVX512BWVL-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3]
-; X64-AVX512BWVL-NEXT: vpaddw {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512BWVL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512BWVL-NEXT: retq
;
; X64-AVX512DQVL-LABEL: test_broadcast_16i16_32i16:
; X64-AVX512DQVL: ## %bb.0:
; X64-AVX512DQVL-NEXT: vmovdqa (%rdi), %ymm0
-; X64-AVX512DQVL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm1
-; X64-AVX512DQVL-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQVL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; X64-AVX512DQVL-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQVL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512DQVL-NEXT: retq
%1 = load <16 x i16>, <16 x i16> *%p
@@ -83,22 +83,22 @@ define <64 x i8> @test_broadcast_32i8_64i8(<32 x i8> *%p) nounwind {
; X64-AVX512VL-LABEL: test_broadcast_32i8_64i8:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovdqa (%rdi), %ymm0
-; X64-AVX512VL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm1
-; X64-AVX512VL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; X64-AVX512VL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512BWVL-LABEL: test_broadcast_32i8_64i8:
; X64-AVX512BWVL: ## %bb.0:
; X64-AVX512BWVL-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3]
-; X64-AVX512BWVL-NEXT: vpaddb {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512BWVL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512BWVL-NEXT: retq
;
; X64-AVX512DQVL-LABEL: test_broadcast_32i8_64i8:
; X64-AVX512DQVL: ## %bb.0:
; X64-AVX512DQVL-NEXT: vmovdqa (%rdi), %ymm0
-; X64-AVX512DQVL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm1
-; X64-AVX512DQVL-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQVL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; X64-AVX512DQVL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQVL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; X64-AVX512DQVL-NEXT: retq
%1 = load <32 x i8>, <32 x i8> *%p
diff --git a/llvm/test/CodeGen/X86/avx512-vec-cmp.ll b/llvm/test/CodeGen/X86/avx512-vec-cmp.ll
index 7dcae9a2d24ac..3c4b0cc984f31 100644
--- a/llvm/test/CodeGen/X86/avx512-vec-cmp.ll
+++ b/llvm/test/CodeGen/X86/avx512-vec-cmp.ll
@@ -1192,8 +1192,8 @@ define <2 x i64> @test45(<2 x i16> %x, <2 x i16> %y) #0 {
; AVX512-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x75,0xc1]
; AVX512-NEXT: vpmovzxwq %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x34,0xc0]
; AVX512-NEXT: ## xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
-; AVX512-NEXT: ## fixup A - offset: 4, value: LCPI59_0-4, kind: reloc_riprel_4byte
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
+; AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; AVX512-NEXT: retq ## encoding: [0xc3]
;
; SKX-LABEL: test45:
@@ -1213,8 +1213,8 @@ define <2 x i64> @test46(<2 x float> %x, <2 x float> %y) #0 {
; AVX512-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0xc2,0xc1,0x00]
; AVX512-NEXT: vpermilps $212, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x04,0xc0,0xd4]
; AVX512-NEXT: ## xmm0 = xmm0[0,1,1,3]
-; AVX512-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x54,0x05,A,A,A,A]
-; AVX512-NEXT: ## fixup A - offset: 4, value: LCPI60_0-4, kind: reloc_riprel_4byte
+; AVX512-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x54,0x05,A,A,A,A]
+; AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; AVX512-NEXT: retq ## encoding: [0xc3]
;
; SKX-LABEL: test46:
@@ -1457,8 +1457,8 @@ define void @half_vec_compare(<2 x half>* %x, <2 x i8>* %y) {
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf3,0x7d,0xc9,0x25,0xc0,0xff]
; KNL-NEXT: vpmovdw %zmm0, %ymm0 ## encoding: [0x62,0xf2,0x7e,0x48,0x33,0xc0]
; KNL-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x63,0xc0]
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
-; KNL-NEXT: ## fixup A - offset: 4, value: LCPI68_0-4, kind: reloc_riprel_4byte
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
+; KNL-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; KNL-NEXT: vpextrw $0, %xmm0, (%rsi) ## encoding: [0xc4,0xe3,0x79,0x15,0x06,0x00]
; KNL-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; KNL-NEXT: retq ## encoding: [0xc3]
@@ -1487,8 +1487,8 @@ define void @half_vec_compare(<2 x half>* %x, <2 x i8>* %y) {
; AVX512BW-NEXT: korw %k1, %k0, %k0 ## encoding: [0xc5,0xfc,0x45,0xc1]
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0 ## encoding: [0x62,0xf2,0xfe,0x48,0x28,0xc0]
; AVX512BW-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x63,0xc0]
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
-; AVX512BW-NEXT: ## fixup A - offset: 4, value: LCPI68_0-4, kind: reloc_riprel_4byte
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
+; AVX512BW-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; AVX512BW-NEXT: vpextrw $0, %xmm0, (%rsi) ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x15,0x06,0x00]
; AVX512BW-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; AVX512BW-NEXT: retq ## encoding: [0xc3]
@@ -1518,8 +1518,8 @@ define void @half_vec_compare(<2 x half>* %x, <2 x i8>* %y) {
; SKX-NEXT: korw %k0, %k1, %k0 ## encoding: [0xc5,0xf4,0x45,0xc0]
; SKX-NEXT: vpmovm2w %k0, %xmm0 ## encoding: [0x62,0xf2,0xfe,0x08,0x28,0xc0]
; SKX-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x63,0xc0]
-; SKX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
-; SKX-NEXT: ## fixup A - offset: 4, value: LCPI68_0-4, kind: reloc_riprel_4byte
+; SKX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdb,0x05,A,A,A,A]
+; SKX-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; SKX-NEXT: vpextrw $0, %xmm0, (%rsi) ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x15,0x06,0x00]
; SKX-NEXT: retq ## encoding: [0xc3]
entry:
@@ -1537,7 +1537,7 @@ define <8 x i64> @cmp_swap_bug(<16 x i8>* %x, <8 x i64> %y, <8 x i64> %z) {
; KNL-NEXT: vmovdqa (%rdi), %xmm2 ## encoding: [0xc5,0xf9,0x6f,0x17]
; KNL-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
; KNL-NEXT: ## encoding: [0xc4,0xe2,0x69,0x00,0x15,A,A,A,A]
-; KNL-NEXT: ## fixup A - offset: 5, value: LCPI69_0-4, kind: reloc_riprel_4byte
+; KNL-NEXT: ## fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3 ## encoding: [0xc5,0xe1,0xef,0xdb]
; KNL-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2 ## encoding: [0xc5,0xe1,0x64,0xd2]
; KNL-NEXT: vpmovsxbd %xmm2, %zmm2 ## encoding: [0x62,0xf2,0x7d,0x48,0x21,0xd2]
@@ -1550,7 +1550,7 @@ define <8 x i64> @cmp_swap_bug(<16 x i8>* %x, <8 x i64> %y, <8 x i64> %z) {
; AVX512BW-NEXT: vmovdqa (%rdi), %xmm2 ## encoding: [0xc5,0xf9,0x6f,0x17]
; AVX512BW-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
; AVX512BW-NEXT: ## encoding: [0xc4,0xe2,0x69,0x00,0x15,A,A,A,A]
-; AVX512BW-NEXT: ## fixup A - offset: 5, value: LCPI69_0-4, kind: reloc_riprel_4byte
+; AVX512BW-NEXT: ## fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; AVX512BW-NEXT: vpmovb2m %zmm2, %k1 ## encoding: [0x62,0xf2,0x7e,0x48,0x29,0xca]
; AVX512BW-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0x64,0xc0]
; AVX512BW-NEXT: retq ## encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll b/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
index 462730a8f6c89..97d558cdb8984 100644
--- a/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
@@ -1292,18 +1292,18 @@ define <32 x i16> @test_x86_avx512_psrlv_w_512_const() optsize {
; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsrlvw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_x86_avx512_psrlv_w_512_const:
; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res1 = call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <32 x i16> %res1
@@ -1410,18 +1410,18 @@ define <32 x i16>@test_int_x86_avx512_mask_psrav32_hi_const(<32 x i16> %x0, <32
; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51]
; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsravw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_psrav32_hi_const:
; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51]
; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsravw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%1 = call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> <i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51>, <32 x i16> <i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49>)
ret <32 x i16> %1
@@ -1575,18 +1575,18 @@ define <32 x i16> @test_x86_avx512_psllv_w_512_const() optsize {
; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsllvw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_x86_avx512_psllv_w_512_const:
; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res1 = call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <32 x i16> %res1
diff --git a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
index 03f1a2d51330f..7742d96247cf3 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
@@ -2153,20 +2153,20 @@ define <8 x i16>@test_int_x86_avx512_maskz_psrlv8_hi(<8 x i16> %x0, <8 x i16> %x
define <8 x i16> @test_int_x86_avx512_psrlv_w_128_const() optsize {
; X86-LABEL: test_int_x86_avx512_psrlv_w_128_const:
; X86: # %bb.0:
-; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
+; X86-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsrlvw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_psrlv_w_128_const:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
+; X64-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <8 x i16> %res
@@ -2177,20 +2177,20 @@ declare <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16>, <8 x i16>)
define <16 x i16> @test_int_x86_avx512_psrlv_w_256_const() optsize {
; X86-LABEL: test_int_x86_avx512_psrlv_w_256_const:
; X86: # %bb.0:
-; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
+; X86-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsrlvw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_psrlv_w_256_const:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
+; X64-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsrlvw {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <16 x i16> %res
@@ -2397,20 +2397,20 @@ define <8 x i16>@test_int_x86_avx512_maskz_psllv8_hi(<8 x i16> %x0, <8 x i16> %x
define <8 x i16> @test_int_x86_avx512_psllv_w_128_const() optsize {
; X86-LABEL: test_int_x86_avx512_psllv_w_128_const:
; X86: # %bb.0:
-; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
+; X86-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsllvw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_psllv_w_128_const:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
+; X64-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <8 x i16> %res
@@ -2422,20 +2422,20 @@ declare <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16>, <8 x i16>)
define <16 x i16> @test_int_x86_avx512_psllv_w_256_const() optsize {
; X86-LABEL: test_int_x86_avx512_psllv_w_256_const:
; X86: # %bb.0:
-; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
+; X86-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsllvw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_psllv_w_256_const:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
+; X64-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <16 x i16> %res
diff --git a/llvm/test/CodeGen/X86/avx512vbmi2-funnel-shifts.ll b/llvm/test/CodeGen/X86/avx512vbmi2-funnel-shifts.ll
index d00297a408a68..6330f1022fc46 100644
--- a/llvm/test/CodeGen/X86/avx512vbmi2-funnel-shifts.ll
+++ b/llvm/test/CodeGen/X86/avx512vbmi2-funnel-shifts.ll
@@ -5,12 +5,12 @@
define <8 x i64> @avx512_funnel_shift_q_512(<8 x i64> %a0, <8 x i64> %a1) {
; X86-LABEL: avx512_funnel_shift_q_512:
; X86: # %bb.0:
-; X86-NEXT: vpshldvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
+; X86-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_q_512:
; X64: # %bb.0:
-; X64-NEXT: vpshldvq {{.*}}(%rip), %zmm1, %zmm0
+; X64-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; X64-NEXT: retq
%1 = shl <8 x i64> %a0, <i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33>
%2 = lshr <8 x i64> %a1, <i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31>
@@ -32,12 +32,12 @@ define <8 x i64> @avx512_funnel_shift_q_512_splat(<8 x i64> %a0, <8 x i64> %a1)
define <16 x i32> @avx512_funnel_shift_d_512(<16 x i32> %a0, <16 x i32> %a1) {
; X86-LABEL: avx512_funnel_shift_d_512:
; X86: # %bb.0:
-; X86-NEXT: vpshldvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
+; X86-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_d_512:
; X64: # %bb.0:
-; X64-NEXT: vpshldvd {{.*}}(%rip), %zmm1, %zmm0
+; X64-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; X64-NEXT: retq
%1 = shl <16 x i32> %a0, <i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17>
%2 = lshr <16 x i32> %a1, <i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15>
@@ -59,12 +59,12 @@ define <16 x i32> @avx512_funnel_shift_d_512_splat(<16 x i32> %a0, <16 x i32> %a
define <32 x i16> @avx512_funnel_shift_w_512(<32 x i16> %a0, <32 x i16> %a1) {
; X86-LABEL: avx512_funnel_shift_w_512:
; X86: # %bb.0:
-; X86-NEXT: vpshldvw {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
+; X86-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_w_512:
; X64: # %bb.0:
-; X64-NEXT: vpshldvw {{.*}}(%rip), %zmm1, %zmm0
+; X64-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; X64-NEXT: retq
%1 = shl <32 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9>
%2 = lshr <32 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7>
diff --git a/llvm/test/CodeGen/X86/avx512vbmi2vl-funnel-shifts.ll b/llvm/test/CodeGen/X86/avx512vbmi2vl-funnel-shifts.ll
index 588039ea78bf8..dbb94a7c3985b 100644
--- a/llvm/test/CodeGen/X86/avx512vbmi2vl-funnel-shifts.ll
+++ b/llvm/test/CodeGen/X86/avx512vbmi2vl-funnel-shifts.ll
@@ -5,12 +5,12 @@
define <2 x i64> @avx512_funnel_shift_q_128(<2 x i64> %a0, <2 x i64> %a1) {
; X86-LABEL: avx512_funnel_shift_q_128:
; X86: # %bb.0:
-; X86-NEXT: vpshldvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
+; X86-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_q_128:
; X64: # %bb.0:
-; X64-NEXT: vpshldvq {{.*}}(%rip), %xmm1, %xmm0
+; X64-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; X64-NEXT: retq
%1 = shl <2 x i64> %a0, <i64 31, i64 33>
%2 = lshr <2 x i64> %a1, <i64 33, i64 31>
@@ -21,12 +21,12 @@ define <2 x i64> @avx512_funnel_shift_q_128(<2 x i64> %a0, <2 x i64> %a1) {
define <4 x i64> @avx512_funnel_shift_q_256(<4 x i64> %a0, <4 x i64> %a1) {
; X86-LABEL: avx512_funnel_shift_q_256:
; X86: # %bb.0:
-; X86-NEXT: vpshldvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X86-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_q_256:
; X64: # %bb.0:
-; X64-NEXT: vpshldvq {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: retq
%1 = shl <4 x i64> %a0, <i64 31, i64 33, i64 31, i64 33>
%2 = lshr <4 x i64> %a1, <i64 33, i64 31, i64 33, i64 31>
@@ -59,12 +59,12 @@ define <4 x i64> @avx512_funnel_shift_q_256_splat(<4 x i64> %a0, <4 x i64> %a1)
define <4 x i32> @avx512_funnel_shift_d_128(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: avx512_funnel_shift_d_128:
; X86: # %bb.0:
-; X86-NEXT: vpshldvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
+; X86-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_d_128:
; X64: # %bb.0:
-; X64-NEXT: vpshldvd {{.*}}(%rip), %xmm1, %xmm0
+; X64-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; X64-NEXT: retq
%1 = shl <4 x i32> %a0, <i32 15, i32 17, i32 15, i32 17>
%2 = lshr <4 x i32> %a1, <i32 17, i32 15, i32 17, i32 15>
@@ -75,12 +75,12 @@ define <4 x i32> @avx512_funnel_shift_d_128(<4 x i32> %a0, <4 x i32> %a1) {
define <8 x i32> @avx512_funnel_shift_d_256(<8 x i32> %a0, <8 x i32> %a1) {
; X86-LABEL: avx512_funnel_shift_d_256:
; X86: # %bb.0:
-; X86-NEXT: vpshldvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X86-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_d_256:
; X64: # %bb.0:
-; X64-NEXT: vpshldvd {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: retq
%1 = shl <8 x i32> %a0, <i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17>
%2 = lshr <8 x i32> %a1, <i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15>
@@ -113,12 +113,12 @@ define <8 x i32> @avx512_funnel_shift_d_256_splat(<8 x i32> %a0, <8 x i32> %a1)
define <8 x i16> @avx512_funnel_shift_w_128(<8 x i16> %a0, <8 x i16> %a1) {
; X86-LABEL: avx512_funnel_shift_w_128:
; X86: # %bb.0:
-; X86-NEXT: vpshldvw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
+; X86-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_w_128:
; X64: # %bb.0:
-; X64-NEXT: vpshldvw {{.*}}(%rip), %xmm1, %xmm0
+; X64-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; X64-NEXT: retq
%1 = shl <8 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9>
%2 = lshr <8 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7>
@@ -129,12 +129,12 @@ define <8 x i16> @avx512_funnel_shift_w_128(<8 x i16> %a0, <8 x i16> %a1) {
define <16 x i16> @avx512_funnel_shift_w_256(<16 x i16> %a0, <16 x i16> %a1) {
; X86-LABEL: avx512_funnel_shift_w_256:
; X86: # %bb.0:
-; X86-NEXT: vpshldvw {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
+; X86-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: avx512_funnel_shift_w_256:
; X64: # %bb.0:
-; X64-NEXT: vpshldvw {{.*}}(%rip), %ymm1, %ymm0
+; X64-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-NEXT: retq
%1 = shl <16 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9>
%2 = lshr <16 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7>
diff --git a/llvm/test/CodeGen/X86/avx512vl-arith.ll b/llvm/test/CodeGen/X86/avx512vl-arith.ll
index 9c6de82cba078..b36799be36e55 100644
--- a/llvm/test/CodeGen/X86/avx512vl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-arith.ll
@@ -25,8 +25,8 @@ define <4 x i64> @vpaddq256_fold_test(<4 x i64> %i, <4 x i64>* %j) nounwind {
define <4 x i64> @vpaddq256_broadcast_test(<4 x i64> %i) nounwind {
; CHECK-LABEL: vpaddq256_broadcast_test:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x38,0xd4,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI2_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x38,0xd4,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%x = add <4 x i64> %i, <i64 2, i64 2, i64 2, i64 2>
ret <4 x i64> %x
@@ -66,8 +66,8 @@ define <8 x i32> @vpaddd256_fold_test(<8 x i32> %i, <8 x i32>* %j) nounwind {
define <8 x i32> @vpaddd256_broadcast_test(<8 x i32> %i) nounwind {
; CHECK-LABEL: vpaddd256_broadcast_test:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xfe,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI6_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xfe,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%x = add <8 x i32> %i, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
ret <8 x i32> %x
@@ -114,8 +114,8 @@ define <8 x i32> @vpaddd256_mask_broadcast_test(<8 x i32> %i, <8 x i32> %mask1)
; CHECK-LABEL: vpaddd256_mask_broadcast_test:
; CHECK: ## %bb.0:
; CHECK-NEXT: vptestmd %ymm1, %ymm1, %k1 ## encoding: [0x62,0xf2,0x75,0x28,0x27,0xc9]
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xfe,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI10_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xfe,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%mask = icmp ne <8 x i32> %mask1, zeroinitializer
%x = add <8 x i32> %i, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
@@ -140,8 +140,8 @@ define <8 x i32> @vpaddd256_maskz_broadcast_test(<8 x i32> %i, <8 x i32> %mask1)
; CHECK-LABEL: vpaddd256_maskz_broadcast_test:
; CHECK: ## %bb.0:
; CHECK-NEXT: vptestmd %ymm1, %ymm1, %k1 ## encoding: [0x62,0xf2,0x75,0x28,0x27,0xc9]
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xfe,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI12_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xfe,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%mask = icmp ne <8 x i32> %mask1, zeroinitializer
%x = add <8 x i32> %i, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
@@ -189,8 +189,8 @@ entry:
define <4 x double> @test_fold_vaddpd_256(<4 x double> %y) {
; CHECK-LABEL: test_fold_vaddpd_256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x58,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 4, value: LCPI17_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x58,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
entry:
%add.i = fadd <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 4.500000e+00, double 5.600000e+00>
@@ -200,8 +200,8 @@ entry:
define <8 x float> @test_broadcast_vaddpd_256(<8 x float> %a) nounwind {
; CHECK-LABEL: test_broadcast_vaddpd_256:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vaddps {{.*}}(%rip){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7c,0x38,0x58,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI18_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7c,0x38,0x58,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%b = fadd <8 x float> %a, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
ret <8 x float> %b
@@ -491,8 +491,8 @@ define <4 x i32> @vpaddd128_fold_test(<4 x i32> %i, <4 x i32>* %j) nounwind {
define <4 x i32> @vpaddd128_broadcast_test(<4 x i32> %i) nounwind {
; CHECK-LABEL: vpaddd128_broadcast_test:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xfe,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI42_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xfe,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%x = add <4 x i32> %i, <i32 6, i32 6, i32 6, i32 6>
ret <4 x i32> %x
@@ -539,8 +539,8 @@ define <4 x i32> @vpaddd128_mask_broadcast_test(<4 x i32> %i, <4 x i32> %mask1)
; CHECK-LABEL: vpaddd128_mask_broadcast_test:
; CHECK: ## %bb.0:
; CHECK-NEXT: vptestmd %xmm1, %xmm1, %k1 ## encoding: [0x62,0xf2,0x75,0x08,0x27,0xc9]
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xfe,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI46_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xfe,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
%x = add <4 x i32> %i, <i32 7, i32 7, i32 7, i32 7>
@@ -565,8 +565,8 @@ define <4 x i32> @vpaddd128_maskz_broadcast_test(<4 x i32> %i, <4 x i32> %mask1)
; CHECK-LABEL: vpaddd128_maskz_broadcast_test:
; CHECK: ## %bb.0:
; CHECK-NEXT: vptestmd %xmm1, %xmm1, %k1 ## encoding: [0x62,0xf2,0x75,0x08,0x27,0xc9]
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xfe,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI48_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xfe,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
%x = add <4 x i32> %i, <i32 8, i32 8, i32 8, i32 8>
@@ -614,8 +614,8 @@ entry:
define <2 x double> @test_fold_vaddpd_128(<2 x double> %y) {
; CHECK-LABEL: test_fold_vaddpd_128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vaddpd {{.*}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 4, value: LCPI53_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
entry:
%add.i = fadd <2 x double> %y, <double 4.500000e+00, double 3.400000e+00>
@@ -625,8 +625,8 @@ entry:
define <4 x float> @test_broadcast_vaddpd_128(<4 x float> %a) nounwind {
; CHECK-LABEL: test_broadcast_vaddpd_128:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7c,0x18,0x58,0x05,A,A,A,A]
-; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI54_0-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7c,0x18,0x58,0x05,A,A,A,A]
+; CHECK-NEXT: ## fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq ## encoding: [0xc3]
%b = fadd <4 x float> %a, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
ret <4 x float> %b
diff --git a/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
index fd90a9fd1baa3..4cd20f87c146c 100644
--- a/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
@@ -1905,13 +1905,13 @@ define <2 x i64> @test_mm_mask_set1_epi32(<2 x i64> %__O, i8 zeroext %__M) {
; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1
-; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 {%k1}
+; X86-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 {%k1}
; X86-NEXT: retl
;
; X64-LABEL: test_mm_mask_set1_epi32:
; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1
-; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1}
+; X64-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1}
; X64-NEXT: retq
entry:
%0 = bitcast <2 x i64> %__O to <4 x i32>
@@ -1927,13 +1927,13 @@ define <2 x i64> @test_mm_maskz_set1_epi32(i8 zeroext %__M) {
; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1
-; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 {%k1} {z}
+; X86-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 {%k1} {z}
; X86-NEXT: retl
;
; X64-LABEL: test_mm_maskz_set1_epi32:
; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1
-; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z}
+; X64-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1} {z}
; X64-NEXT: retq
entry:
%0 = bitcast i8 %__M to <8 x i1>
@@ -1948,13 +1948,13 @@ define <4 x i64> @test_mm256_mask_set1_epi32(<4 x i64> %__O, i8 zeroext %__M) {
; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1
-; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 {%k1}
+; X86-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 {%k1}
; X86-NEXT: retl
;
; X64-LABEL: test_mm256_mask_set1_epi32:
; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1
-; X64-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1}
+; X64-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k1}
; X64-NEXT: retq
entry:
%0 = bitcast <4 x i64> %__O to <8 x i32>
@@ -1969,13 +1969,13 @@ define <4 x i64> @test_mm256_maskz_set1_epi32(i8 zeroext %__M) {
; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1
-; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 {%k1} {z}
+; X86-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 {%k1} {z}
; X86-NEXT: retl
;
; X64-LABEL: test_mm256_maskz_set1_epi32:
; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1
-; X64-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z}
+; X64-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k1} {z}
; X64-NEXT: retq
entry:
%0 = bitcast i8 %__M to <8 x i1>
diff --git a/llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
index 1fef7ad034e67..4102c2854e9c4 100644
--- a/llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
@@ -7321,20 +7321,20 @@ define <8 x i32>@test_int_x86_avx512_maskz_psrav8_si(<8 x i32> %x0, <8 x i32> %x
define <8 x i32>@test_int_x86_avx512_mask_psrav8_si_const() {
; X86-LABEL: test_int_x86_avx512_mask_psrav8_si_const:
; X86: # %bb.0:
-; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X86-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_psrav8_si_const:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X64-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>, <8 x i32> zeroinitializer, i8 -1)
ret <8 x i32> %res
@@ -8632,20 +8632,20 @@ define <2 x i64>@test_int_x86_avx512_maskz_psrav_q_128(<2 x i64> %x0, <2 x i64>
define <2 x i64>@test_int_x86_avx512_mask_psrav_q_128_const(i8 %x3) {
; X86-LABEL: test_int_x86_avx512_mask_psrav_q_128_const:
; X86: # %bb.0:
-; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,0,4294967287,4294967295]
+; X86-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,0,4294967287,4294967295]
; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
-; X86-NEXT: vpsravq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpsravq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_psrav_q_128_const:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,18446744073709551607]
+; X64-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,18446744073709551607]
; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; X64-NEXT: vpsravq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpsravq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> <i64 2, i64 -9>, <2 x i64> <i64 1, i64 90>, <2 x i64> zeroinitializer, i8 -1)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/X86/avx512vl-logic.ll b/llvm/test/CodeGen/X86/avx512vl-logic.ll
index 48ab5bf22313d..72de9adcbd361 100644
--- a/llvm/test/CodeGen/X86/avx512vl-logic.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-logic.ll
@@ -7,7 +7,7 @@
define <8 x i32> @vpandd256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandd256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; CHECK-NEXT: vpand %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
@@ -20,7 +20,7 @@ entry:
define <8 x i32> @vpandnd256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandnd256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm1
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm1
; CHECK-NEXT: vpandn %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
@@ -34,7 +34,7 @@ entry:
define <8 x i32> @vpord256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpord256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; CHECK-NEXT: vpor %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
@@ -47,7 +47,7 @@ entry:
define <8 x i32> @vpxord256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpxord256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; CHECK-NEXT: vpxor %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
@@ -60,7 +60,7 @@ entry:
define <4 x i64> @vpandq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandq256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; CHECK-NEXT: vpand %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
@@ -73,7 +73,7 @@ entry:
define <4 x i64> @vpandnq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandnq256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; CHECK-NEXT: vpandn %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq
entry:
@@ -87,7 +87,7 @@ entry:
define <4 x i64> @vporq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vporq256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; CHECK-NEXT: vpor %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
@@ -100,7 +100,7 @@ entry:
define <4 x i64> @vpxorq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpxorq256:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; CHECK-NEXT: vpxor %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
entry:
@@ -115,7 +115,7 @@ entry:
define <4 x i32> @vpandd128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandd128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -128,7 +128,7 @@ entry:
define <4 x i32> @vpandnd128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandnd128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -142,7 +142,7 @@ entry:
define <4 x i32> @vpord128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpord128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -155,7 +155,7 @@ entry:
define <4 x i32> @vpxord128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpxord128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -168,7 +168,7 @@ entry:
define <2 x i64> @vpandq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -181,7 +181,7 @@ entry:
define <2 x i64> @vpandnq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandnq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -195,7 +195,7 @@ entry:
define <2 x i64> @vporq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vporq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -208,7 +208,7 @@ entry:
define <2 x i64> @vpxorq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpxorq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -991,7 +991,7 @@ define <4 x i32> @ternlog_xor_andn(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
define <4 x i32> @ternlog_or_and_mask(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: ternlog_or_and_mask:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogd $236, {{.*}}(%rip), %xmm1, %xmm0
+; CHECK-NEXT: vpternlogd $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; CHECK-NEXT: retq
%a = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
%b = or <4 x i32> %a, %y
@@ -1001,7 +1001,7 @@ define <4 x i32> @ternlog_or_and_mask(<4 x i32> %x, <4 x i32> %y) {
define <8 x i32> @ternlog_or_and_mask_ymm(<8 x i32> %x, <8 x i32> %y) {
; CHECK-LABEL: ternlog_or_and_mask_ymm:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogd $236, {{.*}}(%rip), %ymm1, %ymm0
+; CHECK-NEXT: vpternlogd $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; CHECK-NEXT: retq
%a = and <8 x i32> %x, <i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216>
%b = or <8 x i32> %a, %y
@@ -1011,7 +1011,7 @@ define <8 x i32> @ternlog_or_and_mask_ymm(<8 x i32> %x, <8 x i32> %y) {
define <2 x i64> @ternlog_xor_and_mask(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: ternlog_xor_and_mask:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0
+; CHECK-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; CHECK-NEXT: retq
%a = and <2 x i64> %x, <i64 1099511627775, i64 1099511627775>
%b = xor <2 x i64> %a, %y
@@ -1021,7 +1021,7 @@ define <2 x i64> @ternlog_xor_and_mask(<2 x i64> %x, <2 x i64> %y) {
define <4 x i64> @ternlog_xor_and_mask_ymm(<4 x i64> %x, <4 x i64> %y) {
; CHECK-LABEL: ternlog_xor_and_mask_ymm:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogq $108, {{.*}}(%rip), %ymm1, %ymm0
+; CHECK-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; CHECK-NEXT: retq
%a = and <4 x i64> %x, <i64 72057594037927935, i64 72057594037927935, i64 72057594037927935, i64 72057594037927935>
%b = xor <4 x i64> %a, %y
@@ -1033,14 +1033,14 @@ define <4 x i32> @ternlog_maskz_or_and_mask(<4 x i32> %x, <4 x i32> %y, <4 x i32
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL-NEXT: vpcmpgtd %xmm3, %xmm2, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: vpord %xmm1, %xmm0, %xmm0 {%k1} {z}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskz_or_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %xmm3, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: vorps %xmm1, %xmm0, %xmm0 {%k1} {z}
; SKX-NEXT: retq
%m = icmp slt <4 x i32> %mask, zeroinitializer
@@ -1055,14 +1055,14 @@ define <8 x i32> @ternlog_maskz_or_and_mask_ymm(<8 x i32> %x, <8 x i32> %y, <8 x
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtd %ymm2, %ymm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpord %ymm1, %ymm0, %ymm0 {%k1} {z}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskz_or_and_mask_ymm:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %ymm2, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; SKX-NEXT: vorps %ymm1, %ymm0, %ymm0 {%k1} {z}
; SKX-NEXT: retq
%m = icmp slt <8 x i32> %mask, zeroinitializer
@@ -1077,14 +1077,14 @@ define <2 x i64> @ternlog_maskz_xor_and_mask(<2 x i64> %x, <2 x i64> %y, <2 x i6
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %xmm2, %xmm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: vpxorq %xmm1, %xmm0, %xmm0 {%k1} {z}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskz_xor_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %xmm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: vxorpd %xmm1, %xmm0, %xmm0 {%k1} {z}
; SKX-NEXT: retq
%m = icmp slt <2 x i64> %mask, zeroinitializer
@@ -1099,14 +1099,14 @@ define <4 x i64> @ternlog_maskz_xor_and_mask_ymm(<4 x i64> %x, <4 x i64> %y, <4
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %ymm2, %ymm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpxorq %ymm1, %ymm0, %ymm0 {%k1} {z}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskz_xor_and_mask_ymm:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %ymm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; SKX-NEXT: vxorpd %ymm1, %ymm0, %ymm0 {%k1} {z}
; SKX-NEXT: retq
%m = icmp slt <4 x i64> %mask, zeroinitializer
@@ -1121,14 +1121,14 @@ define <4 x i32> @ternlog_maskx_or_and_mask(<4 x i32> %x, <4 x i32> %y, <4 x i32
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL-NEXT: vpcmpgtd %xmm3, %xmm2, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm2
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; KNL-NEXT: vpord %xmm1, %xmm2, %xmm0 {%k1}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskx_or_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %xmm3, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm2
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; SKX-NEXT: vorps %xmm1, %xmm2, %xmm0 {%k1}
; SKX-NEXT: retq
%m = icmp slt <4 x i32> %mask, zeroinitializer
@@ -1143,14 +1143,14 @@ define <8 x i32> @ternlog_maskx_or_and_mask_ymm(<8 x i32> %x, <8 x i32> %y, <8 x
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtd %ymm2, %ymm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm2
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; KNL-NEXT: vpord %ymm1, %ymm2, %ymm0 {%k1}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskx_or_and_mask_ymm:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %ymm2, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm2
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; SKX-NEXT: vorps %ymm1, %ymm2, %ymm0 {%k1}
; SKX-NEXT: retq
%m = icmp slt <8 x i32> %mask, zeroinitializer
@@ -1165,14 +1165,14 @@ define <2 x i64> @ternlog_maskx_xor_and_mask(<2 x i64> %x, <2 x i64> %y, <2 x i6
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %xmm2, %xmm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm2
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; KNL-NEXT: vpxorq %xmm1, %xmm2, %xmm0 {%k1}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskx_xor_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %xmm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm2
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; SKX-NEXT: vxorpd %xmm1, %xmm2, %xmm0 {%k1}
; SKX-NEXT: retq
%m = icmp slt <2 x i64> %mask, zeroinitializer
@@ -1187,14 +1187,14 @@ define <4 x i64> @ternlog_maskx_xor_and_mask_ymm(<4 x i64> %x, <4 x i64> %y, <4
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %ymm2, %ymm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm2
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; KNL-NEXT: vpxorq %ymm1, %ymm2, %ymm0 {%k1}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_maskx_xor_and_mask_ymm:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %ymm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm2
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; SKX-NEXT: vxorpd %ymm1, %ymm2, %ymm0 {%k1}
; SKX-NEXT: retq
%m = icmp slt <4 x i64> %mask, zeroinitializer
@@ -1209,7 +1209,7 @@ define <4 x i32> @ternlog_masky_or_and_mask(<4 x i32> %x, <4 x i32> %y, <4 x i32
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL-NEXT: vpcmpgtd %xmm3, %xmm2, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: vpord %xmm1, %xmm0, %xmm1 {%k1}
; KNL-NEXT: vmovdqa %xmm1, %xmm0
; KNL-NEXT: retq
@@ -1217,7 +1217,7 @@ define <4 x i32> @ternlog_masky_or_and_mask(<4 x i32> %x, <4 x i32> %y, <4 x i32
; SKX-LABEL: ternlog_masky_or_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %xmm3, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: vorps %xmm1, %xmm0, %xmm1 {%k1}
; SKX-NEXT: vmovaps %xmm1, %xmm0
; SKX-NEXT: retq
@@ -1233,14 +1233,14 @@ define <8 x i32> @ternlog_masky_or_and_mask_ymm(<8 x i32> %x, <8 x i32> %y, <8 x
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtd %ymm2, %ymm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm2
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; KNL-NEXT: vpord %ymm1, %ymm2, %ymm0 {%k1}
; KNL-NEXT: retq
;
; SKX-LABEL: ternlog_masky_or_and_mask_ymm:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovd2m %ymm2, %k1
-; SKX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm2
+; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; SKX-NEXT: vorps %ymm1, %ymm2, %ymm0 {%k1}
; SKX-NEXT: retq
%m = icmp slt <8 x i32> %mask, zeroinitializer
@@ -1255,7 +1255,7 @@ define <2 x i64> @ternlog_masky_xor_and_mask(<2 x i64> %x, <2 x i64> %y, <2 x i6
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %xmm2, %xmm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: vpxorq %xmm1, %xmm0, %xmm1 {%k1}
; KNL-NEXT: vmovdqa %xmm1, %xmm0
; KNL-NEXT: retq
@@ -1263,7 +1263,7 @@ define <2 x i64> @ternlog_masky_xor_and_mask(<2 x i64> %x, <2 x i64> %y, <2 x i6
; SKX-LABEL: ternlog_masky_xor_and_mask:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %xmm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: vxorpd %xmm1, %xmm0, %xmm1 {%k1}
; SKX-NEXT: vmovapd %xmm1, %xmm0
; SKX-NEXT: retq
@@ -1279,7 +1279,7 @@ define <4 x i64> @ternlog_masky_xor_and_mask_ymm(<4 x i64> %x, <4 x i64> %y, <4
; KNL: ## %bb.0:
; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vpcmpgtq %ymm2, %ymm3, %k1
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; KNL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpxorq %ymm1, %ymm0, %ymm1 {%k1}
; KNL-NEXT: vmovdqa %ymm1, %ymm0
; KNL-NEXT: retq
@@ -1287,7 +1287,7 @@ define <4 x i64> @ternlog_masky_xor_and_mask_ymm(<4 x i64> %x, <4 x i64> %y, <4
; SKX-LABEL: ternlog_masky_xor_and_mask_ymm:
; SKX: ## %bb.0:
; SKX-NEXT: vpmovq2m %ymm2, %k1
-; SKX-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0
+; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; SKX-NEXT: vxorpd %ymm1, %ymm0, %ymm1 {%k1}
; SKX-NEXT: vmovapd %ymm1, %ymm0
; SKX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/avx512vl-vbroadcast.ll b/llvm/test/CodeGen/X86/avx512vl-vbroadcast.ll
index 13d6f2993f8b7..892beccd351ce 100644
--- a/llvm/test/CodeGen/X86/avx512vl-vbroadcast.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-vbroadcast.ll
@@ -9,7 +9,7 @@ define <8 x float> @_256_broadcast_ss_spill(float %x) {
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq func_f32
+; CHECK-NEXT: callq func_f32 at PLT
; CHECK-NEXT: vbroadcastss (%rsp), %ymm0 # 16-byte Folded Reload
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -28,7 +28,7 @@ define <4 x float> @_128_broadcast_ss_spill(float %x) {
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq func_f32
+; CHECK-NEXT: callq func_f32 at PLT
; CHECK-NEXT: vbroadcastss (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -48,7 +48,7 @@ define <4 x double> @_256_broadcast_sd_spill(double %x) {
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq func_f64
+; CHECK-NEXT: callq func_f64 at PLT
; CHECK-NEXT: vbroadcastsd (%rsp), %ymm0 # 16-byte Folded Reload
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/backpropmask.ll b/llvm/test/CodeGen/X86/backpropmask.ll
index 602c2b7154e38..f246665acf7eb 100644
--- a/llvm/test/CodeGen/X86/backpropmask.ll
+++ b/llvm/test/CodeGen/X86/backpropmask.ll
@@ -13,12 +13,12 @@
define dso_local void @PR37667() {
; CHECK-LABEL: PR37667:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl b(%rip), %eax
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl {{.*}}(%rip)
-; CHECK-NEXT: orl {{.*}}(%rip), %edx
+; CHECK-NEXT: divl d(%rip)
+; CHECK-NEXT: orl c(%rip), %edx
; CHECK-NEXT: movzbl %dl, %eax
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, a(%rip)
; CHECK-NEXT: retq
%t0 = load i32, i32* @c, align 4
%t1 = load i32, i32* @b, align 4
@@ -35,10 +35,10 @@ define dso_local void @PR37060() {
; CHECK: # %bb.0:
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl {{.*}}(%rip)
-; CHECK-NEXT: xorl {{.*}}(%rip), %edx
+; CHECK-NEXT: idivl c(%rip)
+; CHECK-NEXT: xorl b(%rip), %edx
; CHECK-NEXT: movzbl %dl, %eax
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, a(%rip)
; CHECK-NEXT: retq
%t0 = load i32, i32* @c, align 4
%rem = srem i32 -1, %t0
diff --git a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
index 7ffcb0979ff0b..6558afc4eda28 100644
--- a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
+++ b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
@@ -209,10 +209,10 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -255,10 +255,10 @@ define <8 x i32> @ext_i8_8i32(i8 %a0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -303,10 +303,10 @@ define <16 x i16> @ext_i16_16i16(i16 %a0) {
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -353,7 +353,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0) {
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[2,2,3,3,4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,1,4,4,5,5]
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9241421688590303745,9241421688590303745]
; AVX1-NEXT: # xmm2 = mem[0,0]
@@ -422,15 +422,15 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: retq
;
@@ -483,15 +483,15 @@ define <16 x i32> @ext_i16_16i32(i16 %a0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
index 854f496ee07d5..d24d26f830733 100644
--- a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
+++ b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
@@ -181,7 +181,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0) {
; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: pcmpeqb %xmm1, %xmm0
; SSE2-NEXT: psrlw $7, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: ext_i16_16i8:
@@ -192,7 +192,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0) {
; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: pcmpeqb %xmm1, %xmm0
; SSSE3-NEXT: psrlw $7, %xmm0
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; AVX1-LABEL: ext_i16_16i8:
@@ -204,7 +204,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ext_i16_16i8:
@@ -215,13 +215,13 @@ define <16 x i8> @ext_i16_16i8(i16 %a0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: ext_i16_16i8:
; AVX512F: # %bb.0:
; AVX512F-NEXT: kmovw %edi, %k1
-; AVX512F-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
+; AVX512F-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
@@ -229,7 +229,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0) {
; AVX512VLBW-LABEL: ext_i16_16i8:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: kmovd %edi, %k1
-; AVX512VLBW-NEXT: vmovdqu8 {{.*}}(%rip), %xmm0 {%k1} {z}
+; AVX512VLBW-NEXT: vmovdqu8 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1} {z}
; AVX512VLBW-NEXT: retq
%1 = bitcast i16 %a0 to <16 x i1>
%2 = zext <16 x i1> %1 to <16 x i8>
@@ -265,11 +265,11 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpsrlq $63, %xmm1, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlq $63, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
@@ -324,11 +324,11 @@ define <8 x i32> @ext_i8_8i32(i8 %a0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpsrld $31, %xmm1, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
@@ -385,11 +385,11 @@ define <16 x i16> @ext_i16_16i16(i16 %a0) {
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpsrlw $15, %xmm1, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $15, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
@@ -452,7 +452,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0) {
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[2,2,3,3,4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,1,4,4,5,5]
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9241421688590303745,9241421688590303745]
; AVX1-NEXT: # xmm2 = mem[0,0]
@@ -475,7 +475,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $7, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: ext_i32_32i8:
@@ -494,7 +494,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0) {
; AVX512VLBW-LABEL: ext_i32_32i8:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: kmovd %edi, %k1
-; AVX512VLBW-NEXT: vmovdqu8 {{.*}}(%rip), %ymm0 {%k1} {z}
+; AVX512VLBW-NEXT: vmovdqu8 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k1} {z}
; AVX512VLBW-NEXT: retq
%1 = bitcast i32 %a0 to <32 x i1>
%2 = zext <32 x i1> %1 to <32 x i8>
@@ -545,18 +545,18 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $63, %xmm2, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlq $63, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; AVX1-NEXT: vpsrlq $63, %xmm2, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlq $63, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: retq
@@ -624,18 +624,18 @@ define <16 x i32> @ext_i16_16i32(i16 %a0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX1-NEXT: vpsrld $31, %xmm2, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; AVX1-NEXT: vpsrld $31, %xmm2, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrld $31, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: retq
@@ -880,7 +880,7 @@ define <64 x i8> @ext_i64_64i8(i64 %a0) {
; AVX512VLBW-LABEL: ext_i64_64i8:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: kmovq %rdi, %k1
-; AVX512VLBW-NEXT: vmovdqu8 {{.*}}(%rip), %zmm0 {%k1} {z}
+; AVX512VLBW-NEXT: vmovdqu8 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k1} {z}
; AVX512VLBW-NEXT: retq
%1 = bitcast i64 %a0 to <64 x i1>
%2 = zext <64 x i1> %1 to <64 x i8>
diff --git a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
index b4fb48ade63bb..65bc3166a6dc2 100644
--- a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
+++ b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
@@ -142,7 +142,7 @@ define <16 x i1> @bitcast_i16_16i1(i16 zeroext %a0) {
; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: pcmpeqb %xmm1, %xmm0
; SSE2-NEXT: psrlw $7, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: bitcast_i16_16i1:
@@ -153,7 +153,7 @@ define <16 x i1> @bitcast_i16_16i1(i16 zeroext %a0) {
; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: pcmpeqb %xmm1, %xmm0
; SSSE3-NEXT: psrlw $7, %xmm0
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; AVX1-LABEL: bitcast_i16_16i1:
@@ -165,7 +165,7 @@ define <16 x i1> @bitcast_i16_16i1(i16 zeroext %a0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: bitcast_i16_16i1:
@@ -176,7 +176,7 @@ define <16 x i1> @bitcast_i16_16i1(i16 zeroext %a0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: bitcast_i16_16i1:
@@ -203,7 +203,7 @@ define <32 x i1> @bitcast_i32_32i1(i32 %a0) {
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[2,2,3,3,4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,1,4,4,5,5]
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9241421688590303745,9241421688590303745]
; AVX1-NEXT: # xmm2 = mem[0,0]
@@ -226,7 +226,7 @@ define <32 x i1> @bitcast_i32_32i1(i32 %a0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $7, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: bitcast_i32_32i1:
diff --git a/llvm/test/CodeGen/X86/bitcast-setcc-128.ll b/llvm/test/CodeGen/X86/bitcast-setcc-128.ll
index 98fd5fc0cfe2e..7622e9b503558 100644
--- a/llvm/test/CodeGen/X86/bitcast-setcc-128.ll
+++ b/llvm/test/CodeGen/X86/bitcast-setcc-128.ll
@@ -515,7 +515,7 @@ define i64 @v16i8_widened_with_ones(<16 x i8> %a, <16 x i8> %b) {
; AVX2-LABEL: v16i8_widened_with_ones:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vinserti128 $1, {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vinserti128 $1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0
; AVX2-NEXT: vpmovmskb %ymm0, %ecx
; AVX2-NEXT: movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000
diff --git a/llvm/test/CodeGen/X86/bitreverse.ll b/llvm/test/CodeGen/X86/bitreverse.ll
index e10f67d146397..3a98ff23c3972 100644
--- a/llvm/test/CodeGen/X86/bitreverse.ll
+++ b/llvm/test/CodeGen/X86/bitreverse.ll
@@ -59,27 +59,27 @@ define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) nounwind {
; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: movdqa %xmm0, %xmm1
; X64-NEXT: psllw $4, %xmm1
-; X64-NEXT: pand {{.*}}(%rip), %xmm1
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: psrlw $4, %xmm0
-; X64-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X64-NEXT: pand %xmm0, %xmm1
; X64-NEXT: psllw $2, %xmm1
-; X64-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: psrlw $2, %xmm0
; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; X64-NEXT: pand %xmm0, %xmm1
; X64-NEXT: paddb %xmm1, %xmm1
-; X64-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: psrlw $1, %xmm0
; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: retq
;
; X86XOP-LABEL: test_bitreverse_v2i16:
; X86XOP: # %bb.0:
-; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: retl
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
ret <2 x i16> %b
@@ -155,7 +155,7 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
; X86XOP-LABEL: test_bitreverse_i64:
; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: vpextrd $1, %xmm0, %edx
; X86XOP-NEXT: retl
@@ -213,7 +213,7 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
; X86XOP-LABEL: test_bitreverse_i32:
; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: retl
%b = call i32 @llvm.bitreverse.i32(i32 %a)
@@ -272,7 +272,7 @@ define i24 @test_bitreverse_i24(i24 %a) nounwind {
; X86XOP-LABEL: test_bitreverse_i24:
; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: shrl $8, %eax
; X86XOP-NEXT: retl
@@ -332,7 +332,7 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind {
; X86XOP-LABEL: test_bitreverse_i16:
; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: # kill: def $ax killed $ax killed $eax
; X86XOP-NEXT: retl
@@ -383,7 +383,7 @@ define i8 @test_bitreverse_i8(i8 %a) {
; X86XOP-LABEL: test_bitreverse_i8:
; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: # kill: def $al killed $al killed $eax
; X86XOP-NEXT: retl
@@ -436,7 +436,7 @@ define i4 @test_bitreverse_i4(i4 %a) {
; X86XOP-LABEL: test_bitreverse_i4:
; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: shrb $4, %al
; X86XOP-NEXT: # kill: def $al killed $al killed $eax
diff --git a/llvm/test/CodeGen/X86/bittest-intrin.ll b/llvm/test/CodeGen/X86/bittest-intrin.ll
index 4ccd7d6a2c482..5931762513dd3 100644
--- a/llvm/test/CodeGen/X86/bittest-intrin.ll
+++ b/llvm/test/CodeGen/X86/bittest-intrin.ll
@@ -11,31 +11,31 @@ define void @test32(i32* %base, i32 %idx) {
; CHECK-NEXT: #APP
; CHECK-NEXT: btl %edx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: btcl %edx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: btrl %edx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: btsl %edx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: lock btrl %edx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: lock btsl %edx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: lock btsl %edx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: retq
entry:
%0 = tail call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
@@ -62,27 +62,27 @@ define void @test64(i64* %base, i64 %idx) {
; CHECK-NEXT: #APP
; CHECK-NEXT: btq %rdx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: btcq %rdx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: btrq %rdx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: btsq %rdx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: lock btrq %rdx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: lock btsq %rdx, (%rcx)
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb sink(%rip)
; CHECK-NEXT: retq
entry:
%0 = tail call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
diff --git a/llvm/test/CodeGen/X86/bool-zext.ll b/llvm/test/CodeGen/X86/bool-zext.ll
index cbc259c235b1f..539be245eb1d0 100644
--- a/llvm/test/CodeGen/X86/bool-zext.ll
+++ b/llvm/test/CodeGen/X86/bool-zext.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s -check-prefix=X64
-; It's not necessary to zero-extend the arg because it is specified 'zeroext'.
+; It's not necessary to zero-extend the arg because it is specified 'zeroext'.
define void @bar1(i1 zeroext %v1) nounwind ssp {
; X32-LABEL: bar1:
; X32: # %bb.0:
@@ -44,13 +44,13 @@ define void @bar2(i8 zeroext %v1) nounwind ssp {
define zeroext i1 @bar3() nounwind ssp {
; X32-LABEL: bar3:
; X32: # %bb.0:
-; X32-NEXT: calll foo2
+; X32-NEXT: calll foo2 at PLT
; X32-NEXT: retl
;
; X64-LABEL: bar3:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo2
+; X64-NEXT: callq foo2 at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
%call = call i1 @foo2() nounwind
diff --git a/llvm/test/CodeGen/X86/brcond.ll b/llvm/test/CodeGen/X86/brcond.ll
index c7ccfe9f0d5c2..c2a580a37c8db 100644
--- a/llvm/test/CodeGen/X86/brcond.ll
+++ b/llvm/test/CodeGen/X86/brcond.ll
@@ -64,7 +64,7 @@ define float @test4(float %x, float %y) nounwind readnone optsize ssp {
; CHECK-NEXT: jne LBB1_1
; CHECK-NEXT: jnp LBB1_2
; CHECK-NEXT: LBB1_1: ## %bb1
-; CHECK-NEXT: addsd LCPI1_0, %xmm0
+; CHECK-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: LBB1_2: ## %bb2
; CHECK-NEXT: cvtsd2ss %xmm0, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp)
@@ -98,11 +98,11 @@ define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: ptest %xmm0, %xmm0
; CHECK-NEXT: jne LBB2_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: addps LCPI2_0, %xmm1
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
; CHECK-NEXT: LBB2_2: ## %bb2
-; CHECK-NEXT: divps LCPI2_0, %xmm1
+; CHECK-NEXT: divps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
@@ -130,11 +130,11 @@ define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: ptest %xmm0, %xmm0
; CHECK-NEXT: jne LBB3_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: addps LCPI3_0, %xmm1
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
; CHECK-NEXT: LBB3_2: ## %bb2
-; CHECK-NEXT: divps LCPI3_0, %xmm1
+; CHECK-NEXT: divps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
@@ -162,11 +162,11 @@ define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: ptest %xmm0, %xmm0
; CHECK-NEXT: jae LBB4_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: addps LCPI4_0, %xmm1
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
; CHECK-NEXT: LBB4_2: ## %bb2
-; CHECK-NEXT: divps LCPI4_0, %xmm1
+; CHECK-NEXT: divps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
@@ -194,11 +194,11 @@ define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: ptest %xmm0, %xmm0
; CHECK-NEXT: jae LBB5_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: addps LCPI5_0, %xmm1
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
; CHECK-NEXT: LBB5_2: ## %bb2
-; CHECK-NEXT: divps LCPI5_0, %xmm1
+; CHECK-NEXT: divps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
@@ -226,11 +226,11 @@ define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: ptest %xmm0, %xmm0
; CHECK-NEXT: jne LBB6_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: addps LCPI6_0, %xmm1
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
; CHECK-NEXT: LBB6_2: ## %bb2
-; CHECK-NEXT: divps LCPI6_0, %xmm1
+; CHECK-NEXT: divps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
@@ -258,11 +258,11 @@ define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-NEXT: ptest %xmm0, %xmm0
; CHECK-NEXT: je LBB7_2
; CHECK-NEXT: ## %bb.1: ## %bb1
-; CHECK-NEXT: addps LCPI7_0, %xmm1
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
; CHECK-NEXT: LBB7_2: ## %bb2
-; CHECK-NEXT: divps LCPI7_0, %xmm1
+; CHECK-NEXT: divps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/break-anti-dependencies.ll b/llvm/test/CodeGen/X86/break-anti-dependencies.ll
index 4867acf6728de..88b20a4bda451 100644
--- a/llvm/test/CodeGen/X86/break-anti-dependencies.ll
+++ b/llvm/test/CodeGen/X86/break-anti-dependencies.ll
@@ -9,18 +9,18 @@ define void @goo(double* %r, double* %p, double* %q) nounwind {
; none-LABEL: goo:
; none: # %bb.0: # %entry
; none-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; none-NEXT: addsd {{.*}}(%rip), %xmm0
-; none-NEXT: mulsd {{.*}}(%rip), %xmm0
-; none-NEXT: addsd {{.*}}(%rip), %xmm0
-; none-NEXT: mulsd {{.*}}(%rip), %xmm0
-; none-NEXT: addsd {{.*}}(%rip), %xmm0
+; none-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; none-NEXT: cvttsd2si %xmm0, %eax
; none-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; none-NEXT: addsd {{.*}}(%rip), %xmm0
-; none-NEXT: mulsd {{.*}}(%rip), %xmm0
-; none-NEXT: addsd {{.*}}(%rip), %xmm0
-; none-NEXT: mulsd {{.*}}(%rip), %xmm0
-; none-NEXT: addsd {{.*}}(%rip), %xmm0
+; none-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; none-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; none-NEXT: cvttsd2si %xmm0, %ecx
; none-NEXT: cmpl %eax, %ecx
; none-NEXT: jge .LBB0_2
@@ -34,16 +34,16 @@ define void @goo(double* %r, double* %p, double* %q) nounwind {
; critical: # %bb.0: # %entry
; critical-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; critical-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
-; critical-NEXT: addsd {{.*}}(%rip), %xmm0
-; critical-NEXT: addsd {{.*}}(%rip), %xmm1
-; critical-NEXT: mulsd {{.*}}(%rip), %xmm0
-; critical-NEXT: mulsd {{.*}}(%rip), %xmm1
-; critical-NEXT: addsd {{.*}}(%rip), %xmm0
-; critical-NEXT: addsd {{.*}}(%rip), %xmm1
-; critical-NEXT: mulsd {{.*}}(%rip), %xmm0
-; critical-NEXT: mulsd {{.*}}(%rip), %xmm1
-; critical-NEXT: addsd {{.*}}(%rip), %xmm0
-; critical-NEXT: addsd {{.*}}(%rip), %xmm1
+; critical-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; critical-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; critical-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; critical-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; critical-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; critical-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; critical-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; critical-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; critical-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; critical-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; critical-NEXT: cvttsd2si %xmm0, %eax
; critical-NEXT: cvttsd2si %xmm1, %ecx
; critical-NEXT: cmpl %ecx, %eax
diff --git a/llvm/test/CodeGen/X86/break-false-dep.ll b/llvm/test/CodeGen/X86/break-false-dep.ll
index 7dd3bf11d57a7..e1537b7b23b90 100644
--- a/llvm/test/CodeGen/X86/break-false-dep.ll
+++ b/llvm/test/CodeGen/X86/break-false-dep.ll
@@ -473,11 +473,11 @@ define dso_local void @loopdep3() {
; SSE-WIN-NEXT: .seh_savexmm %xmm6, 0
; SSE-WIN-NEXT: .seh_endprologue
; SSE-WIN-NEXT: xorl %r9d, %r9d
-; SSE-WIN-NEXT: leaq {{.*}}(%rip), %r8
-; SSE-WIN-NEXT: leaq {{.*}}(%rip), %r10
-; SSE-WIN-NEXT: leaq {{.*}}(%rip), %r11
-; SSE-WIN-NEXT: leaq {{.*}}(%rip), %rax
-; SSE-WIN-NEXT: leaq {{.*}}(%rip), %rdx
+; SSE-WIN-NEXT: leaq v(%rip), %r8
+; SSE-WIN-NEXT: leaq x(%rip), %r10
+; SSE-WIN-NEXT: leaq y(%rip), %r11
+; SSE-WIN-NEXT: leaq z(%rip), %rax
+; SSE-WIN-NEXT: leaq w(%rip), %rdx
; SSE-WIN-NEXT: .p2align 4, 0x90
; SSE-WIN-NEXT: .LBB8_1: # %for.cond1.preheader
; SSE-WIN-NEXT: # =>This Loop Header: Depth=1
@@ -549,11 +549,11 @@ define dso_local void @loopdep3() {
; AVX-NEXT: .seh_savexmm %xmm6, 0
; AVX-NEXT: .seh_endprologue
; AVX-NEXT: xorl %r9d, %r9d
-; AVX-NEXT: leaq {{.*}}(%rip), %r8
-; AVX-NEXT: leaq {{.*}}(%rip), %r10
-; AVX-NEXT: leaq {{.*}}(%rip), %r11
-; AVX-NEXT: leaq {{.*}}(%rip), %rax
-; AVX-NEXT: leaq {{.*}}(%rip), %rdx
+; AVX-NEXT: leaq v(%rip), %r8
+; AVX-NEXT: leaq x(%rip), %r10
+; AVX-NEXT: leaq y(%rip), %r11
+; AVX-NEXT: leaq z(%rip), %rax
+; AVX-NEXT: leaq w(%rip), %rdx
; AVX-NEXT: .p2align 4, 0x90
; AVX-NEXT: .LBB8_1: # %for.cond1.preheader
; AVX-NEXT: # =>This Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll b/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
index 6ce20f18d4436..e8b4390fe2420 100644
--- a/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
+++ b/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
@@ -128,7 +128,7 @@ define <32 x i8> @f32xi8_i16(<32 x i8> %a) {
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f32xi8_i16:
@@ -145,7 +145,7 @@ define <32 x i8> @f32xi8_i16(<32 x i8> %a) {
; AVX-64-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f32xi8_i16:
@@ -168,7 +168,7 @@ define <32 x i8> @f32xi8_i32(<32 x i8> %a) {
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f32xi8_i32:
@@ -185,7 +185,7 @@ define <32 x i8> @f32xi8_i32(<32 x i8> %a) {
; AVX-64-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f32xi8_i32:
@@ -209,7 +209,7 @@ define <32 x i8> @f32xi8_i64(<32 x i8> %a) {
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f32xi8_i64:
@@ -227,7 +227,7 @@ define <32 x i8> @f32xi8_i64(<32 x i8> %a) {
; AVX-64-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f32xi8_i64:
@@ -250,7 +250,7 @@ define <32 x i8> @f32xi8_i128(<32 x i8> %a) {
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f32xi8_i128:
@@ -268,7 +268,7 @@ define <32 x i8> @f32xi8_i128(<32 x i8> %a) {
; AVX-64-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f32xi8_i128:
@@ -716,7 +716,7 @@ define <16 x i16> @f16xi16_i32(<16 x i16> %a) {
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f16xi16_i32:
@@ -733,7 +733,7 @@ define <16 x i16> @f16xi16_i32(<16 x i16> %a) {
; AVX-64-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f16xi16_i32:
@@ -757,7 +757,7 @@ define <16 x i16> @f16xi16_i64(<16 x i16> %a) {
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f16xi16_i64:
@@ -775,7 +775,7 @@ define <16 x i16> @f16xi16_i64(<16 x i16> %a) {
; AVX-64-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f16xi16_i64:
@@ -798,7 +798,7 @@ define <16 x i16> @f16xi16_i128(<16 x i16> %a) {
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f16xi16_i128:
@@ -816,7 +816,7 @@ define <16 x i16> @f16xi16_i128(<16 x i16> %a) {
; AVX-64-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f16xi16_i128:
@@ -1161,7 +1161,7 @@ define <8 x i32> @f8xi32_i64(<8 x i32> %a) {
; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f8xi32_i64:
@@ -1179,7 +1179,7 @@ define <8 x i32> @f8xi32_i64(<8 x i32> %a) {
; AVX-64-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f8xi32_i64:
@@ -1202,7 +1202,7 @@ define <8 x i32> @f8xi32_i128(<8 x i32> %a) {
; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f8xi32_i128:
@@ -1220,7 +1220,7 @@ define <8 x i32> @f8xi32_i128(<8 x i32> %a) {
; AVX-64-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f8xi32_i128:
@@ -1386,7 +1386,7 @@ define <4 x i64> @f4xi64_i128(<4 x i64> %a) {
; AVX-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl
;
; ALL32-LABEL: f4xi64_i128:
@@ -1404,7 +1404,7 @@ define <4 x i64> @f4xi64_i128(<4 x i64> %a) {
; AVX-64-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-64-NEXT: retq
;
; ALL64-LABEL: f4xi64_i128:
diff --git a/llvm/test/CodeGen/X86/bswap.ll b/llvm/test/CodeGen/X86/bswap.ll
index 71497f06d7ed4..ad07122b5b7b1 100644
--- a/llvm/test/CodeGen/X86/bswap.ll
+++ b/llvm/test/CodeGen/X86/bswap.ll
@@ -165,7 +165,7 @@ define i64 @not_bswap() {
;
; CHECK64-LABEL: not_bswap:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK64-NEXT: movzwl var16(%rip), %eax
; CHECK64-NEXT: movq %rax, %rcx
; CHECK64-NEXT: shrq $8, %rcx
; CHECK64-NEXT: shlq $8, %rax
@@ -196,7 +196,7 @@ define i64 @not_useful_bswap() {
;
; CHECK64-LABEL: not_useful_bswap:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: movzbl {{.*}}(%rip), %eax
+; CHECK64-NEXT: movzbl var8(%rip), %eax
; CHECK64-NEXT: shlq $8, %rax
; CHECK64-NEXT: retq
%init = load i8, i8* @var8
@@ -224,7 +224,7 @@ define i64 @finally_useful_bswap() {
;
; CHECK64-LABEL: finally_useful_bswap:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK64-NEXT: movzwl var16(%rip), %eax
; CHECK64-NEXT: bswapq %rax
; CHECK64-NEXT: shrq $48, %rax
; CHECK64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/bt.ll b/llvm/test/CodeGen/X86/bt.ll
index 59df366c6e4a2..b3c7db976b6b3 100644
--- a/llvm/test/CodeGen/X86/bt.ll
+++ b/llvm/test/CodeGen/X86/bt.ll
@@ -29,7 +29,7 @@ define void @test2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB0_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB0_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -39,7 +39,7 @@ define void @test2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB0_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB0_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -67,7 +67,7 @@ define void @test2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: # %bb.2: # %UnifiedReturnBlock
; X86-NEXT: retl
; X86-NEXT: .LBB1_1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: retl
;
; X64-LABEL: test2b:
@@ -78,7 +78,7 @@ define void @test2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: retq
; X64-NEXT: .LBB1_1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
entry:
@@ -103,7 +103,7 @@ define void @atest2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB2_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB2_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -113,7 +113,7 @@ define void @atest2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB2_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB2_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -141,7 +141,7 @@ define void @atest2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: # %bb.2: # %UnifiedReturnBlock
; X86-NEXT: retl
; X86-NEXT: .LBB3_1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: retl
;
; X64-LABEL: atest2b:
@@ -152,7 +152,7 @@ define void @atest2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: retq
; X64-NEXT: .LBB3_1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
entry:
@@ -179,7 +179,7 @@ define void @test3(i32 %x, i32 %n) nounwind {
; X86-NEXT: # %bb.2: # %UnifiedReturnBlock
; X86-NEXT: retl
; X86-NEXT: .LBB4_1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: retl
;
; X64-LABEL: test3:
@@ -190,7 +190,7 @@ define void @test3(i32 %x, i32 %n) nounwind {
; X64-NEXT: retq
; X64-NEXT: .LBB4_1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
entry:
@@ -217,7 +217,7 @@ define void @test3b(i32 %x, i32 %n) nounwind {
; X86-NEXT: # %bb.2: # %UnifiedReturnBlock
; X86-NEXT: retl
; X86-NEXT: .LBB5_1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: retl
;
; X64-LABEL: test3b:
@@ -228,7 +228,7 @@ define void @test3b(i32 %x, i32 %n) nounwind {
; X64-NEXT: retq
; X64-NEXT: .LBB5_1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
entry:
@@ -253,7 +253,7 @@ define void @testne2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB6_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB6_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -263,7 +263,7 @@ define void @testne2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB6_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB6_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -289,7 +289,7 @@ define void @testne2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB7_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB7_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -299,7 +299,7 @@ define void @testne2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB7_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB7_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -325,7 +325,7 @@ define void @atestne2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB8_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB8_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -335,7 +335,7 @@ define void @atestne2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB8_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB8_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -361,7 +361,7 @@ define void @atestne2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB9_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB9_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -371,7 +371,7 @@ define void @atestne2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB9_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB9_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -397,7 +397,7 @@ define void @testne3(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB10_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB10_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -407,7 +407,7 @@ define void @testne3(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB10_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB10_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -433,7 +433,7 @@ define void @testne3b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB11_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB11_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -443,7 +443,7 @@ define void @testne3b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB11_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB11_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -469,7 +469,7 @@ define void @query2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB12_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB12_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -479,7 +479,7 @@ define void @query2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB12_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB12_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -505,7 +505,7 @@ define void @query2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB13_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB13_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -515,7 +515,7 @@ define void @query2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB13_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB13_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -541,7 +541,7 @@ define void @aquery2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB14_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB14_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -551,7 +551,7 @@ define void @aquery2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB14_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB14_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -577,7 +577,7 @@ define void @aquery2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB15_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB15_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -587,7 +587,7 @@ define void @aquery2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB15_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB15_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -613,7 +613,7 @@ define void @query3(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB16_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB16_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -623,7 +623,7 @@ define void @query3(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB16_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB16_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -649,7 +649,7 @@ define void @query3b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB17_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB17_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -659,7 +659,7 @@ define void @query3b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB17_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB17_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -685,7 +685,7 @@ define void @query3x(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB18_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB18_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -695,7 +695,7 @@ define void @query3x(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB18_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB18_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -721,7 +721,7 @@ define void @query3bx(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB19_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB19_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -731,7 +731,7 @@ define void @query3bx(i32 %x, i32 %n) nounwind {
; X64-NEXT: jae .LBB19_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB19_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -757,7 +757,7 @@ define void @queryne2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB20_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB20_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -767,7 +767,7 @@ define void @queryne2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB20_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB20_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -793,7 +793,7 @@ define void @queryne2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB21_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB21_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -803,7 +803,7 @@ define void @queryne2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB21_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB21_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -829,7 +829,7 @@ define void @aqueryne2(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB22_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB22_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -839,7 +839,7 @@ define void @aqueryne2(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB22_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB22_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -865,7 +865,7 @@ define void @aqueryne2b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB23_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB23_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -875,7 +875,7 @@ define void @aqueryne2b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB23_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB23_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -901,7 +901,7 @@ define void @queryne3(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB24_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB24_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -911,7 +911,7 @@ define void @queryne3(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB24_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB24_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -937,7 +937,7 @@ define void @queryne3b(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB25_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB25_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -947,7 +947,7 @@ define void @queryne3b(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB25_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB25_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -973,7 +973,7 @@ define void @queryne3x(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB26_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB26_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -983,7 +983,7 @@ define void @queryne3x(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB26_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB26_2: # %UnifiedReturnBlock
; X64-NEXT: retq
@@ -1009,7 +1009,7 @@ define void @queryne3bx(i32 %x, i32 %n) nounwind {
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB27_2
; X86-NEXT: # %bb.1: # %bb
-; X86-NEXT: calll foo
+; X86-NEXT: calll foo at PLT
; X86-NEXT: .LBB27_2: # %UnifiedReturnBlock
; X86-NEXT: retl
;
@@ -1019,7 +1019,7 @@ define void @queryne3bx(i32 %x, i32 %n) nounwind {
; X64-NEXT: jb .LBB27_2
; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: pushq %rax
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .LBB27_2: # %UnifiedReturnBlock
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/bug37521.ll b/llvm/test/CodeGen/X86/bug37521.ll
index 9481fc1cd986f..c842b7fd6ea3f 100644
--- a/llvm/test/CodeGen/X86/bug37521.ll
+++ b/llvm/test/CodeGen/X86/bug37521.ll
@@ -9,15 +9,15 @@ define void @foo() #0 {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: movq a+{{.*}}(%rip), %r9
-; CHECK-NEXT: movq a+{{.*}}(%rip), %r8
-; CHECK-NEXT: movq a+{{.*}}(%rip), %rcx
-; CHECK-NEXT: movq a+{{.*}}(%rip), %rdx
-; CHECK-NEXT: movq a+{{.*}}(%rip), %rsi
-; CHECK-NEXT: movq {{.*}}(%rip), %rdi
-; CHECK-NEXT: vmovaps a+{{.*}}(%rip), %xmm0
+; CHECK-NEXT: movq a+40(%rip), %r9
+; CHECK-NEXT: movq a+32(%rip), %r8
+; CHECK-NEXT: movq a+24(%rip), %rcx
+; CHECK-NEXT: movq a+16(%rip), %rdx
+; CHECK-NEXT: movq a+8(%rip), %rsi
+; CHECK-NEXT: movq a(%rip), %rdi
+; CHECK-NEXT: vmovaps a+48(%rip), %xmm0
; CHECK-NEXT: vmovups %xmm0, (%rsp)
-; CHECK-NEXT: callq goo
+; CHECK-NEXT: callq goo at PLT
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: retq
%k = bitcast <16 x float>* @a to <2 x i256>*
diff --git a/llvm/test/CodeGen/X86/byval.ll b/llvm/test/CodeGen/X86/byval.ll
index 0e5f63cbdbf50..2037c9e5a3c4c 100644
--- a/llvm/test/CodeGen/X86/byval.ll
+++ b/llvm/test/CodeGen/X86/byval.ll
@@ -8,13 +8,13 @@
define i64 @f(%struct.s* byval(%struct.s) %a) {
; X64-LABEL: f:
; X64: # %bb.0: # %entry
-; X64-NEXT: movq 8(%rsp), %rax
+; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax
; X64-NEXT: retq
;
; X86-LABEL: f:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl 4(%esp), %eax
-; X86-NEXT: movl 8(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: retl
entry:
%tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0
diff --git a/llvm/test/CodeGen/X86/byval2.ll b/llvm/test/CodeGen/X86/byval2.ll
index 181b17793149d..704b9dad9374b 100644
--- a/llvm/test/CodeGen/X86/byval2.ll
+++ b/llvm/test/CodeGen/X86/byval2.ll
@@ -20,12 +20,12 @@ define void @g(i64 %a, i64 %b, i64 %c) nounwind {
; X64-NEXT: movq %rsp, %rdi
; X64-NEXT: movq %rbx, %rsi
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: movl $17, %ecx
; X64-NEXT: movq %rsp, %rdi
; X64-NEXT: movq %rbx, %rsi
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: addq $288, %rsp # imm = 0x120
; X64-NEXT: popq %rbx
; X64-NEXT: retq
@@ -56,12 +56,12 @@ define void @g(i64 %a, i64 %b, i64 %c) nounwind {
; X86-NEXT: movl %esp, %edi
; X86-NEXT: movl %ebx, %esi
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: movl $34, %ecx
; X86-NEXT: movl %esp, %edi
; X86-NEXT: movl %ebx, %esi
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/byval3.ll b/llvm/test/CodeGen/X86/byval3.ll
index 80f2ec7fd52ce..384e07842467d 100644
--- a/llvm/test/CodeGen/X86/byval3.ll
+++ b/llvm/test/CodeGen/X86/byval3.ll
@@ -27,14 +27,14 @@ define void @g(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) nounwind {
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
; X64-NEXT: movl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: movl %eax, {{[0-9]+}}(%rsp)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: movl $16, %ecx
; X64-NEXT: movq %rsp, %rdi
; X64-NEXT: movq %rbx, %rsi
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
; X64-NEXT: movl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: movl %eax, {{[0-9]+}}(%rsp)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: addq $288, %rsp # imm = 0x120
; X64-NEXT: popq %rbx
; X64-NEXT: retq
@@ -65,12 +65,12 @@ define void @g(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) nounwind {
; X86-NEXT: movl %esp, %edi
; X86-NEXT: movl %ebx, %esi
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: movl $33, %ecx
; X86-NEXT: movl %esp, %edi
; X86-NEXT: movl %ebx, %esi
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/byval4.ll b/llvm/test/CodeGen/X86/byval4.ll
index 9e6be9bd86c67..c5c8c20dcc86d 100644
--- a/llvm/test/CodeGen/X86/byval4.ll
+++ b/llvm/test/CodeGen/X86/byval4.ll
@@ -32,14 +32,14 @@ define void @g(i16 signext %a1, i16 signext %a2, i16 signext %a3,
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: movw %ax, {{[0-9]+}}(%rsp)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: movl $16, %ecx
; X64-NEXT: movq %rsp, %rdi
; X64-NEXT: movq %rbx, %rsi
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: movw %ax, {{[0-9]+}}(%rsp)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: addq $288, %rsp # imm = 0x120
; X64-NEXT: popq %rbx
; X64-NEXT: retq
@@ -72,14 +72,14 @@ define void @g(i16 signext %a1, i16 signext %a2, i16 signext %a3,
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movw %ax, {{[0-9]+}}(%esp)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: movl $32, %ecx
; X86-NEXT: movl %esp, %edi
; X86-NEXT: movl %ebx, %esi
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movw %ax, {{[0-9]+}}(%esp)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/byval5.ll b/llvm/test/CodeGen/X86/byval5.ll
index c976d0d814e7c..75f7d3e3cd9cf 100644
--- a/llvm/test/CodeGen/X86/byval5.ll
+++ b/llvm/test/CodeGen/X86/byval5.ll
@@ -40,14 +40,14 @@ define void @g(i8 signext %a1, i8 signext %a2, i8 signext %a3, i8 signext %a
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
; X64-NEXT: movb {{[0-9]+}}(%rsp), %al
; X64-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: movl $16, %ecx
; X64-NEXT: movq %rsp, %rdi
; X64-NEXT: movq %rbx, %rsi
; X64-NEXT: rep;movsq (%rsi), %es:(%rdi)
; X64-NEXT: movb {{[0-9]+}}(%rsp), %al
; X64-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; X64-NEXT: callq f
+; X64-NEXT: callq f at PLT
; X64-NEXT: addq $272, %rsp # imm = 0x110
; X64-NEXT: popq %rbx
; X64-NEXT: retq
@@ -80,14 +80,14 @@ define void @g(i8 signext %a1, i8 signext %a2, i8 signext %a3, i8 signext %a
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: movb %al, {{[0-9]+}}(%esp)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: movl $32, %ecx
; X86-NEXT: movl %esp, %edi
; X86-NEXT: movl %ebx, %esi
; X86-NEXT: rep;movsl (%esi), %es:(%edi)
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: movb %al, {{[0-9]+}}(%esp)
-; X86-NEXT: calll f
+; X86-NEXT: calll f at PLT
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/byval6.ll b/llvm/test/CodeGen/X86/byval6.ll
index 09f31527a2226..e9da495bdc24a 100644
--- a/llvm/test/CodeGen/X86/byval6.ll
+++ b/llvm/test/CodeGen/X86/byval6.ll
@@ -24,7 +24,7 @@ define i32 @main() nounwind {
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl $3
-; CHECK-NEXT: calll bar
+; CHECK-NEXT: calll bar at PLT
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: movl B+20, %eax
; CHECK-NEXT: movl B+16, %ecx
@@ -39,7 +39,7 @@ define i32 @main() nounwind {
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl $3
-; CHECK-NEXT: calll baz
+; CHECK-NEXT: calll baz at PLT
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/byval7.ll b/llvm/test/CodeGen/X86/byval7.ll
index 35a7c768721b6..61878aefa3727 100644
--- a/llvm/test/CodeGen/X86/byval7.ll
+++ b/llvm/test/CodeGen/X86/byval7.ll
@@ -21,7 +21,7 @@ define i32 @main() nounwind {
; CHECK-NEXT: movl $36, %ecx
; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
; CHECK-NEXT: movl $1, (%esp)
-; CHECK-NEXT: calll t
+; CHECK-NEXT: calll t at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: leal -8(%ebp), %esp
; CHECK-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll b/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
index afadf4ea13286..fc3303f7a0c89 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
@@ -32,14 +32,14 @@ define i32 @foo(i32 %arg, i32 (i8*)* %arg3) nounwind {
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %bb8
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: callq *%r14
; CHECK-NEXT: movq %r15, %rdi
-; CHECK-NEXT: callq hoge
+; CHECK-NEXT: callq hoge at PLT
; CHECK-NEXT: movq %r12, %rdi
-; CHECK-NEXT: callq hoge
+; CHECK-NEXT: callq hoge at PLT
; CHECK-NEXT: testb %r13b, %r13b
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.3: # %bb15
@@ -49,7 +49,7 @@ define i32 @foo(i32 %arg, i32 (i8*)* %arg3) nounwind {
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.4: # %bb17
-; CHECK-NEXT: callq widget
+; CHECK-NEXT: callq widget at PLT
; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: .LBB0_5: # %bb18
; CHECK-NEXT: movw $0, 14(%rbx)
diff --git a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
index 768405104f1ab..00b0e3385e31a 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
@@ -27,7 +27,7 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind {
; CHECK-NEXT: jne .LBB0_10
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT: cmpl $0, {{.*}}(%rip)
+; CHECK-NEXT: cmpl $0, e(%rip)
; CHECK-NEXT: # implicit-def: $ebx
; CHECK-NEXT: # implicit-def: $r14d
; CHECK-NEXT: je .LBB0_4
@@ -59,7 +59,7 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind {
; CHECK-NEXT: jmp .LBB0_10
; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: # %bb.8: # %if.then20.critedge
-; CHECK-NEXT: movl {{.*}}(%rip), %edi
+; CHECK-NEXT: movl j(%rip), %edi
; CHECK-NEXT: movslq %eax, %rcx
; CHECK-NEXT: movl $1, %esi
; CHECK-NEXT: movq %r15, %rdx
diff --git a/llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll b/llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll
index 4074991bab8de..c4cb4ada5dc7c 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll
@@ -26,8 +26,8 @@ define i64 @early_ioremap_pmd(i64 %addr) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movabsq $9223372036854771712, %rdx # imm = 0x7FFFFFFFFFFFF000
; CHECK-NEXT: andq %rax, %rdx
-; CHECK-NEXT: movb {{.*}}(%rip), %al
-; CHECK-NEXT: movq {{.*}}(%rip), %rcx
+; CHECK-NEXT: movb pgdir_shift(%rip), %al
+; CHECK-NEXT: movq page_offset_base(%rip), %rcx
; CHECK-NEXT: shrxq %rax, %rdi, %rax
; CHECK-NEXT: addq %rcx, %rdx
; CHECK-NEXT: andl $511, %eax # imm = 0x1FF
diff --git a/llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll b/llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll
index 54ff2e308675b..e12c4f1dfb26e 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll
@@ -20,7 +20,7 @@ define void @test1(i8* %arg, i8** %mem) nounwind {
; CHECK-NEXT: .LBB0_1: # %loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq (%r14), %rbx
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
diff --git a/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll b/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll
index 1c987381bf341..f1eb9f5d263cc 100644
--- a/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll
+++ b/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll
@@ -53,7 +53,7 @@ define dso_local i32 @foo2() local_unnamed_addr #0 {
; CHECK-LABEL: foo2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: endbr64
-; CHECK-NEXT: movl {{.*}}(%rip), %ecx
+; CHECK-NEXT: movl bzx(%rip), %ecx
; CHECK-NEXT: addl %ecx, %ecx
; CHECK-NEXT: movl $217112837, %eax # imm = 0xCF0E105
; CHECK-NEXT: notl %eax
@@ -76,7 +76,7 @@ define dso_local nonnull i32* @foo3() local_unnamed_addr #0 {
; CHECK-NEXT: endbr64
; CHECK-NEXT: movl $217112837, %eax # imm = 0xCF0E105
; CHECK-NEXT: notl %eax
-; CHECK-NEXT: andl %eax, {{.*}}(%rip)
+; CHECK-NEXT: andl %eax, czx(%rip)
; CHECK-NEXT: movl $czx, %eax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/cgp-usubo.ll b/llvm/test/CodeGen/X86/cgp-usubo.ll
index ab82d9809724a..e28e6dc9f7b19 100644
--- a/llvm/test/CodeGen/X86/cgp-usubo.ll
+++ b/llvm/test/CodeGen/X86/cgp-usubo.ll
@@ -177,7 +177,7 @@ define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) nounwi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: cmpq %rsi, %rbx
; CHECK-NEXT: setb %dil
-; CHECK-NEXT: callq call
+; CHECK-NEXT: callq call at PLT
; CHECK-NEXT: subq %r15, %rbx
; CHECK-NEXT: jae .LBB9_2
; CHECK-NEXT: # %bb.4: # %end
diff --git a/llvm/test/CodeGen/X86/clear-highbits.ll b/llvm/test/CodeGen/X86/clear-highbits.ll
index 93e34254a32a0..58054dcaaac9b 100644
--- a/llvm/test/CodeGen/X86/clear-highbits.ll
+++ b/llvm/test/CodeGen/X86/clear-highbits.ll
@@ -996,7 +996,7 @@ define i32 @oneuse32(i32 %val, i32 %numhighbits) nounwind {
; X86-NOBMI2-NEXT: movl $-1, %esi
; X86-NOBMI2-NEXT: shrl %cl, %esi
; X86-NOBMI2-NEXT: movl %esi, (%esp)
-; X86-NOBMI2-NEXT: calll use32
+; X86-NOBMI2-NEXT: calll use32 at PLT
; X86-NOBMI2-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-NOBMI2-NEXT: movl %esi, %eax
; X86-NOBMI2-NEXT: addl $8, %esp
@@ -1011,7 +1011,7 @@ define i32 @oneuse32(i32 %val, i32 %numhighbits) nounwind {
; X86-BMI2-NEXT: movl $-1, %ecx
; X86-BMI2-NEXT: shrxl %eax, %ecx, %esi
; X86-BMI2-NEXT: movl %esi, (%esp)
-; X86-BMI2-NEXT: calll use32
+; X86-BMI2-NEXT: calll use32 at PLT
; X86-BMI2-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-BMI2-NEXT: movl %esi, %eax
; X86-BMI2-NEXT: addl $8, %esp
@@ -1029,7 +1029,7 @@ define i32 @oneuse32(i32 %val, i32 %numhighbits) nounwind {
; X64-NOBMI2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI2-NEXT: shrl %cl, %ebp
; X64-NOBMI2-NEXT: movl %ebp, %edi
-; X64-NOBMI2-NEXT: callq use32
+; X64-NOBMI2-NEXT: callq use32 at PLT
; X64-NOBMI2-NEXT: andl %ebx, %ebp
; X64-NOBMI2-NEXT: movl %ebp, %eax
; X64-NOBMI2-NEXT: addq $8, %rsp
@@ -1046,7 +1046,7 @@ define i32 @oneuse32(i32 %val, i32 %numhighbits) nounwind {
; X64-BMI2-NEXT: movl $-1, %eax
; X64-BMI2-NEXT: shrxl %esi, %eax, %ebp
; X64-BMI2-NEXT: movl %ebp, %edi
-; X64-BMI2-NEXT: callq use32
+; X64-BMI2-NEXT: callq use32 at PLT
; X64-BMI2-NEXT: andl %ebx, %ebp
; X64-BMI2-NEXT: movl %ebp, %eax
; X64-BMI2-NEXT: addq $8, %rsp
@@ -1078,7 +1078,7 @@ define i64 @oneuse64(i64 %val, i64 %numhighbits) nounwind {
; X86-FALLBACK0-NEXT: subl $8, %esp
; X86-FALLBACK0-NEXT: pushl %edi
; X86-FALLBACK0-NEXT: pushl %esi
-; X86-FALLBACK0-NEXT: calll use64
+; X86-FALLBACK0-NEXT: calll use64 at PLT
; X86-FALLBACK0-NEXT: addl $16, %esp
; X86-FALLBACK0-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-FALLBACK0-NEXT: andl {{[0-9]+}}(%esp), %edi
@@ -1105,7 +1105,7 @@ define i64 @oneuse64(i64 %val, i64 %numhighbits) nounwind {
; X86-FALLBACK1-NEXT: subl $8, %esp
; X86-FALLBACK1-NEXT: pushl %edi
; X86-FALLBACK1-NEXT: pushl %esi
-; X86-FALLBACK1-NEXT: calll use64
+; X86-FALLBACK1-NEXT: calll use64 at PLT
; X86-FALLBACK1-NEXT: addl $16, %esp
; X86-FALLBACK1-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-FALLBACK1-NEXT: andl {{[0-9]+}}(%esp), %edi
@@ -1132,7 +1132,7 @@ define i64 @oneuse64(i64 %val, i64 %numhighbits) nounwind {
; X86-FALLBACK2-NEXT: subl $8, %esp
; X86-FALLBACK2-NEXT: pushl %edi
; X86-FALLBACK2-NEXT: pushl %esi
-; X86-FALLBACK2-NEXT: calll use64
+; X86-FALLBACK2-NEXT: calll use64 at PLT
; X86-FALLBACK2-NEXT: addl $16, %esp
; X86-FALLBACK2-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-FALLBACK2-NEXT: andl {{[0-9]+}}(%esp), %edi
@@ -1158,7 +1158,7 @@ define i64 @oneuse64(i64 %val, i64 %numhighbits) nounwind {
; X86-BMI2-NEXT: subl $8, %esp
; X86-BMI2-NEXT: pushl %edi
; X86-BMI2-NEXT: pushl %esi
-; X86-BMI2-NEXT: calll use64
+; X86-BMI2-NEXT: calll use64 at PLT
; X86-BMI2-NEXT: addl $16, %esp
; X86-BMI2-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-BMI2-NEXT: andl {{[0-9]+}}(%esp), %edi
@@ -1180,7 +1180,7 @@ define i64 @oneuse64(i64 %val, i64 %numhighbits) nounwind {
; X64-NOBMI2-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI2-NEXT: shrq %cl, %rbx
; X64-NOBMI2-NEXT: movq %rbx, %rdi
-; X64-NOBMI2-NEXT: callq use64
+; X64-NOBMI2-NEXT: callq use64 at PLT
; X64-NOBMI2-NEXT: andq %r14, %rbx
; X64-NOBMI2-NEXT: movq %rbx, %rax
; X64-NOBMI2-NEXT: addq $8, %rsp
@@ -1197,7 +1197,7 @@ define i64 @oneuse64(i64 %val, i64 %numhighbits) nounwind {
; X64-BMI2-NEXT: movq $-1, %rax
; X64-BMI2-NEXT: shrxq %rsi, %rax, %rbx
; X64-BMI2-NEXT: movq %rbx, %rdi
-; X64-BMI2-NEXT: callq use64
+; X64-BMI2-NEXT: callq use64 at PLT
; X64-BMI2-NEXT: andq %r14, %rbx
; X64-BMI2-NEXT: movq %rbx, %rax
; X64-BMI2-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/clear-lowbits.ll b/llvm/test/CodeGen/X86/clear-lowbits.ll
index 3e56865c8c934..d677dc41e4847 100644
--- a/llvm/test/CodeGen/X86/clear-lowbits.ll
+++ b/llvm/test/CodeGen/X86/clear-lowbits.ll
@@ -1621,7 +1621,7 @@ define i32 @oneuse32(i32 %val, i32 %numlowbits) nounwind {
; X86-NOBMI2-NEXT: movl $-1, %esi
; X86-NOBMI2-NEXT: shll %cl, %esi
; X86-NOBMI2-NEXT: movl %esi, (%esp)
-; X86-NOBMI2-NEXT: calll use32
+; X86-NOBMI2-NEXT: calll use32 at PLT
; X86-NOBMI2-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-NOBMI2-NEXT: movl %esi, %eax
; X86-NOBMI2-NEXT: addl $8, %esp
@@ -1636,7 +1636,7 @@ define i32 @oneuse32(i32 %val, i32 %numlowbits) nounwind {
; X86-BMI2-NEXT: movl $-1, %ecx
; X86-BMI2-NEXT: shlxl %eax, %ecx, %esi
; X86-BMI2-NEXT: movl %esi, (%esp)
-; X86-BMI2-NEXT: calll use32
+; X86-BMI2-NEXT: calll use32 at PLT
; X86-BMI2-NEXT: andl {{[0-9]+}}(%esp), %esi
; X86-BMI2-NEXT: movl %esi, %eax
; X86-BMI2-NEXT: addl $8, %esp
@@ -1654,7 +1654,7 @@ define i32 @oneuse32(i32 %val, i32 %numlowbits) nounwind {
; X64-NOBMI2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI2-NEXT: shll %cl, %ebp
; X64-NOBMI2-NEXT: movl %ebp, %edi
-; X64-NOBMI2-NEXT: callq use32
+; X64-NOBMI2-NEXT: callq use32 at PLT
; X64-NOBMI2-NEXT: andl %ebx, %ebp
; X64-NOBMI2-NEXT: movl %ebp, %eax
; X64-NOBMI2-NEXT: addq $8, %rsp
@@ -1671,7 +1671,7 @@ define i32 @oneuse32(i32 %val, i32 %numlowbits) nounwind {
; X64-BMI2-NEXT: movl $-1, %eax
; X64-BMI2-NEXT: shlxl %esi, %eax, %ebp
; X64-BMI2-NEXT: movl %ebp, %edi
-; X64-BMI2-NEXT: callq use32
+; X64-BMI2-NEXT: callq use32 at PLT
; X64-BMI2-NEXT: andl %ebx, %ebp
; X64-BMI2-NEXT: movl %ebp, %eax
; X64-BMI2-NEXT: addq $8, %rsp
@@ -1706,7 +1706,7 @@ define i64 @oneuse64(i64 %val, i64 %numlowbits) nounwind {
; X86-NOBMI2-NEXT: subl $8, %esp
; X86-NOBMI2-NEXT: pushl %esi
; X86-NOBMI2-NEXT: pushl %edi
-; X86-NOBMI2-NEXT: calll use64
+; X86-NOBMI2-NEXT: calll use64 at PLT
; X86-NOBMI2-NEXT: addl $16, %esp
; X86-NOBMI2-NEXT: andl {{[0-9]+}}(%esp), %edi
; X86-NOBMI2-NEXT: andl {{[0-9]+}}(%esp), %esi
@@ -1737,7 +1737,7 @@ define i64 @oneuse64(i64 %val, i64 %numlowbits) nounwind {
; X86-BMI2-NEXT: subl $8, %esp
; X86-BMI2-NEXT: pushl %esi
; X86-BMI2-NEXT: pushl %edi
-; X86-BMI2-NEXT: calll use64
+; X86-BMI2-NEXT: calll use64 at PLT
; X86-BMI2-NEXT: addl $16, %esp
; X86-BMI2-NEXT: andl {{[0-9]+}}(%esp), %edi
; X86-BMI2-NEXT: andl {{[0-9]+}}(%esp), %esi
@@ -1759,7 +1759,7 @@ define i64 @oneuse64(i64 %val, i64 %numlowbits) nounwind {
; X64-NOBMI2-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI2-NEXT: shlq %cl, %rbx
; X64-NOBMI2-NEXT: movq %rbx, %rdi
-; X64-NOBMI2-NEXT: callq use64
+; X64-NOBMI2-NEXT: callq use64 at PLT
; X64-NOBMI2-NEXT: andq %r14, %rbx
; X64-NOBMI2-NEXT: movq %rbx, %rax
; X64-NOBMI2-NEXT: addq $8, %rsp
@@ -1776,7 +1776,7 @@ define i64 @oneuse64(i64 %val, i64 %numlowbits) nounwind {
; X64-BMI2-NEXT: movq $-1, %rax
; X64-BMI2-NEXT: shlxq %rsi, %rax, %rbx
; X64-BMI2-NEXT: movq %rbx, %rdi
-; X64-BMI2-NEXT: callq use64
+; X64-BMI2-NEXT: callq use64 at PLT
; X64-BMI2-NEXT: andq %r14, %rbx
; X64-BMI2-NEXT: movq %rbx, %rax
; X64-BMI2-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll b/llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll
index d81b3b1a55db7..24a710f734ae8 100644
--- a/llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll
+++ b/llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll
@@ -11,7 +11,7 @@
define <2 x i64> @_clearupper2xi64a(<2 x i64>) nounwind {
; SSE2-LABEL: _clearupper2xi64a:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE42-LABEL: _clearupper2xi64a:
@@ -78,7 +78,7 @@ define <4 x i64> @_clearupper4xi64a(<4 x i64>) nounwind {
define <4 x i32> @_clearupper4xi32a(<4 x i32>) nounwind {
; SSE2-LABEL: _clearupper4xi32a:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE42-LABEL: _clearupper4xi32a:
@@ -128,7 +128,7 @@ define <8 x i32> @_clearupper8xi32a(<8 x i32>) nounwind {
;
; AVX1-LABEL: _clearupper8xi32a:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: _clearupper8xi32a:
@@ -174,12 +174,12 @@ define <8 x i32> @_clearupper8xi32a(<8 x i32>) nounwind {
define <8 x i16> @_clearupper8xi16a(<8 x i16>) nounwind {
; SSE-LABEL: _clearupper8xi16a:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: _clearupper8xi16a:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x0 = extractelement <8 x i16> %0, i32 0
%x1 = extractelement <8 x i16> %0, i32 1
@@ -226,7 +226,7 @@ define <16 x i16> @_clearupper16xi16a(<16 x i16>) nounwind {
;
; AVX-LABEL: _clearupper16xi16a:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
%x0 = extractelement <16 x i16> %0, i32 0
%x1 = extractelement <16 x i16> %0, i32 1
@@ -298,12 +298,12 @@ define <16 x i16> @_clearupper16xi16a(<16 x i16>) nounwind {
define <16 x i8> @_clearupper16xi8a(<16 x i8>) nounwind {
; SSE-LABEL: _clearupper16xi8a:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: _clearupper16xi8a:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x0 = extractelement <16 x i8> %0, i32 0
%x1 = extractelement <16 x i8> %0, i32 1
@@ -382,7 +382,7 @@ define <32 x i8> @_clearupper32xi8a(<32 x i8>) nounwind {
;
; AVX-LABEL: _clearupper32xi8a:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
%x0 = extractelement <32 x i8> %0, i32 0
%x1 = extractelement <32 x i8> %0, i32 1
@@ -518,7 +518,7 @@ define <32 x i8> @_clearupper32xi8a(<32 x i8>) nounwind {
define <2 x i64> @_clearupper2xi64b(<2 x i64>) nounwind {
; SSE2-LABEL: _clearupper2xi64b:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE42-LABEL: _clearupper2xi64b:
@@ -571,7 +571,7 @@ define <4 x i64> @_clearupper4xi64b(<4 x i64>) nounwind {
define <4 x i32> @_clearupper4xi32b(<4 x i32>) nounwind {
; SSE2-LABEL: _clearupper4xi32b:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE42-LABEL: _clearupper4xi32b:
@@ -611,7 +611,7 @@ define <8 x i32> @_clearupper8xi32b(<8 x i32>) nounwind {
;
; AVX1-LABEL: _clearupper8xi32b:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: _clearupper8xi32b:
@@ -635,12 +635,12 @@ define <8 x i32> @_clearupper8xi32b(<8 x i32>) nounwind {
define <8 x i16> @_clearupper8xi16b(<8 x i16>) nounwind {
; SSE-LABEL: _clearupper8xi16b:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: _clearupper8xi16b:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x8 = bitcast <8 x i16> %0 to <16 x i8>
%r0 = insertelement <16 x i8> %x8, i8 zeroinitializer, i32 1
@@ -665,7 +665,7 @@ define <16 x i16> @_clearupper16xi16b(<16 x i16>) nounwind {
;
; AVX-LABEL: _clearupper16xi16b:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
%x8 = bitcast <16 x i16> %0 to <32 x i8>
%r0 = insertelement <32 x i8> %x8, i8 zeroinitializer, i32 1
@@ -1213,7 +1213,7 @@ define <32 x i8> @_clearupper32xi8b(<32 x i8>) nounwind {
define <2 x i64> @_clearupper2xi64c(<2 x i64>) nounwind {
; SSE2-LABEL: _clearupper2xi64c:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE42-LABEL: _clearupper2xi64c:
@@ -1258,7 +1258,7 @@ define <4 x i64> @_clearupper4xi64c(<4 x i64>) nounwind {
define <4 x i32> @_clearupper4xi32c(<4 x i32>) nounwind {
; SSE2-LABEL: _clearupper4xi32c:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE42-LABEL: _clearupper4xi32c:
@@ -1293,7 +1293,7 @@ define <8 x i32> @_clearupper8xi32c(<8 x i32>) nounwind {
;
; AVX1-LABEL: _clearupper8xi32c:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: _clearupper8xi32c:
@@ -1308,12 +1308,12 @@ define <8 x i32> @_clearupper8xi32c(<8 x i32>) nounwind {
define <8 x i16> @_clearupper8xi16c(<8 x i16>) nounwind {
; SSE-LABEL: _clearupper8xi16c:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: _clearupper8xi16c:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%r = and <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, %0
ret <8 x i16> %r
@@ -1329,7 +1329,7 @@ define <16 x i16> @_clearupper16xi16c(<16 x i16>) nounwind {
;
; AVX-LABEL: _clearupper16xi16c:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
%r = and <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, %0
ret <16 x i16> %r
@@ -1338,12 +1338,12 @@ define <16 x i16> @_clearupper16xi16c(<16 x i16>) nounwind {
define <16 x i8> @_clearupper16xi8c(<16 x i8>) nounwind {
; SSE-LABEL: _clearupper16xi8c:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: _clearupper16xi8c:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%r = and <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, %0
ret <16 x i8> %r
@@ -1359,7 +1359,7 @@ define <32 x i8> @_clearupper32xi8c(<32 x i8>) nounwind {
;
; AVX-LABEL: _clearupper32xi8c:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
%r = and <32 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, %0
ret <32 x i8> %r
diff --git a/llvm/test/CodeGen/X86/cmov-double.ll b/llvm/test/CodeGen/X86/cmov-double.ll
index b63a35fff5ba0..a4ded55ca7576 100644
--- a/llvm/test/CodeGen/X86/cmov-double.ll
+++ b/llvm/test/CodeGen/X86/cmov-double.ll
@@ -54,7 +54,7 @@ define dso_local i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4)
; CHECK-NEXT: setb %dl
; CHECK-NEXT: orb %cl, %dl
; CHECK-NEXT: movzbl %dl, %ecx
-; CHECK-NEXT: movl %ecx, {{.*}}(%rip)
+; CHECK-NEXT: movl %ecx, var32(%rip)
; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: cmovel %r8d, %eax
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/cmov-fp.ll b/llvm/test/CodeGen/X86/cmov-fp.ll
index 9af5483b95c06..749b96e25b4ca 100644
--- a/llvm/test/CodeGen/X86/cmov-fp.ll
+++ b/llvm/test/CodeGen/X86/cmov-fp.ll
@@ -32,7 +32,7 @@ define double @test1(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -43,7 +43,7 @@ define double @test1(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -54,7 +54,7 @@ define double @test1(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: ja .LBB0_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -95,7 +95,7 @@ define double @test2(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnb %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -106,7 +106,7 @@ define double @test2(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnb %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -117,7 +117,7 @@ define double @test2(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jae .LBB1_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -158,7 +158,7 @@ define double @test3(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovb %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -169,7 +169,7 @@ define double @test3(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovb %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -180,7 +180,7 @@ define double @test3(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jb .LBB2_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -221,7 +221,7 @@ define double @test4(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -232,7 +232,7 @@ define double @test4(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -243,7 +243,7 @@ define double @test4(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jbe .LBB3_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -286,7 +286,7 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setg %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -299,7 +299,7 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setg %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -310,7 +310,7 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jg .LBB4_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -353,7 +353,7 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setge %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -366,7 +366,7 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setge %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -377,7 +377,7 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jge .LBB5_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -420,7 +420,7 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setl %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -433,7 +433,7 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setl %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -444,7 +444,7 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jl .LBB6_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -487,7 +487,7 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setle %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -500,7 +500,7 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setle %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -511,7 +511,7 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jle .LBB7_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -565,7 +565,7 @@ define float @test9(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -576,7 +576,7 @@ define float @test9(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: ja .LBB8_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -630,7 +630,7 @@ define float @test10(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnb %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -641,7 +641,7 @@ define float @test10(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jae .LBB9_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -695,7 +695,7 @@ define float @test11(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovb %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -706,7 +706,7 @@ define float @test11(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jb .LBB10_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -760,7 +760,7 @@ define float @test12(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -771,7 +771,7 @@ define float @test12(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jbe .LBB11_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -827,7 +827,7 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setg %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -838,7 +838,7 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jg .LBB12_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -894,7 +894,7 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setge %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -905,7 +905,7 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jge .LBB13_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -961,7 +961,7 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setl %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -972,7 +972,7 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jl .LBB14_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1028,7 +1028,7 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setle %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1039,7 +1039,7 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jle .LBB15_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1058,7 +1058,7 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovnbe %st(1), %st
@@ -1070,7 +1070,7 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1081,7 +1081,7 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1092,7 +1092,7 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: ja .LBB16_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1111,7 +1111,7 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovnb %st(1), %st
@@ -1123,7 +1123,7 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnb %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1134,7 +1134,7 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnb %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1145,7 +1145,7 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jae .LBB17_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1164,7 +1164,7 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovb %st(1), %st
@@ -1176,7 +1176,7 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovb %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1187,7 +1187,7 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovb %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1198,7 +1198,7 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jb .LBB18_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1217,7 +1217,7 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovbe %st(1), %st
@@ -1229,7 +1229,7 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1240,7 +1240,7 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1251,7 +1251,7 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jbe .LBB19_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1270,7 +1270,7 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setg %al
@@ -1286,7 +1286,7 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setg %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1299,7 +1299,7 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setg %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1310,7 +1310,7 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jg .LBB20_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1330,7 +1330,7 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setge %al
@@ -1346,7 +1346,7 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setge %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1359,7 +1359,7 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setge %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1370,7 +1370,7 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jge .LBB21_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1389,7 +1389,7 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setl %al
@@ -1405,7 +1405,7 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setl %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1418,7 +1418,7 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setl %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1429,7 +1429,7 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jl .LBB22_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
@@ -1448,7 +1448,7 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setle %al
@@ -1464,7 +1464,7 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setle %al
; NOSSE2-NEXT: testb %al, %al
-; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1)
@@ -1477,7 +1477,7 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setle %al
; NOSSE1-NEXT: testb %al, %al
-; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOSSE1-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1)
@@ -1488,7 +1488,7 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; NOCMOV-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jle .LBB23_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
diff --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll
index f584356333b3a..1f4d6d8c6ac57 100644
--- a/llvm/test/CodeGen/X86/cmov.ll
+++ b/llvm/test/CodeGen/X86/cmov.ll
@@ -79,17 +79,17 @@ define i1 @test4() nounwind {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: movsbl {{.*}}(%rip), %edx
+; CHECK-NEXT: movsbl g_3(%rip), %edx
; CHECK-NEXT: movzbl %dl, %ecx
; CHECK-NEXT: shrl $7, %ecx
; CHECK-NEXT: xorb $1, %cl
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: sarl %cl, %edx
-; CHECK-NEXT: movb {{.*}}(%rip), %al
+; CHECK-NEXT: movb g_96(%rip), %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB3_2
; CHECK-NEXT: # %bb.1: # %bb.i.i.i
-; CHECK-NEXT: movb {{.*}}(%rip), %cl
+; CHECK-NEXT: movb g_100(%rip), %cl
; CHECK-NEXT: .LBB3_2: # %func_4.exit.i
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: testb %dl, %dl
@@ -102,11 +102,11 @@ define i1 @test4() nounwind {
; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne .LBB3_5
; CHECK-NEXT: # %bb.4: # %bb.i.i
-; CHECK-NEXT: movb {{.*}}(%rip), %cl
+; CHECK-NEXT: movb g_100(%rip), %cl
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: .LBB3_5: # %func_1.exit
-; CHECK-NEXT: movb %cl, {{.*}}(%rip)
+; CHECK-NEXT: movb %cl, g_96(%rip)
; CHECK-NEXT: movzbl %cl, %esi
; CHECK-NEXT: movl $_2E_str, %edi
; CHECK-NEXT: xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/cmovcmov.ll b/llvm/test/CodeGen/X86/cmovcmov.ll
index 374da4468223a..f19b3991b2cb7 100644
--- a/llvm/test/CodeGen/X86/cmovcmov.ll
+++ b/llvm/test/CodeGen/X86/cmovcmov.ll
@@ -320,7 +320,7 @@ define dso_local void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) nounwi
; CMOV-NEXT: cmovlel %ecx, %eax
; CMOV-NEXT: testl %edi, %edi
; CMOV-NEXT: cmovnel %ecx, %eax
-; CMOV-NEXT: movb %al, {{.*}}(%rip)
+; CMOV-NEXT: movb %al, g8(%rip)
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: no_cascade_opt:
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index bda450137d025..9fab66af97f55 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -107,13 +107,13 @@ entry:
define dso_local i32 @test5(double %A) nounwind {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ucomisd {{.*}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: ja .LBB5_3 # encoding: [0x77,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: ucomisd {{.*}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: jb .LBB5_3 # encoding: [0x72,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
; CHECK-NEXT: # %bb.2: # %bb12
@@ -386,7 +386,7 @@ define dso_local void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) {
; CHECK-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02]
; CHECK-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
; CHECK-NEXT: # imm = 0xFFFFFF
-; CHECK-NEXT: setne {{.*}}(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A]
+; CHECK-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
diff --git a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll
index 0e59af308ce87..bace90cbcccbd 100644
--- a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll
+++ b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll
@@ -39,7 +39,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind {
; 32-GOOD-RA-NEXT: subl $8, %esp
; 32-GOOD-RA-NEXT: pushl %edx
; 32-GOOD-RA-NEXT: pushl %eax
-; 32-GOOD-RA-NEXT: calll bar
+; 32-GOOD-RA-NEXT: calll bar at PLT
; 32-GOOD-RA-NEXT: addl $16, %esp
; 32-GOOD-RA-NEXT: testb %bl, %bl
; 32-GOOD-RA-NEXT: jne .LBB0_3
@@ -70,7 +70,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind {
; 32-FAST-RA-NEXT: subl $8, %esp
; 32-FAST-RA-NEXT: pushl %edx
; 32-FAST-RA-NEXT: pushl %eax
-; 32-FAST-RA-NEXT: calll bar
+; 32-FAST-RA-NEXT: calll bar at PLT
; 32-FAST-RA-NEXT: addl $16, %esp
; 32-FAST-RA-NEXT: testb %bl, %bl
; 32-FAST-RA-NEXT: jne .LBB0_3
@@ -93,7 +93,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind {
; 64-ALL-NEXT: lock cmpxchgq %rdx, (%rdi)
; 64-ALL-NEXT: setne %bl
; 64-ALL-NEXT: movq %rax, %rdi
-; 64-ALL-NEXT: callq bar
+; 64-ALL-NEXT: callq bar at PLT
; 64-ALL-NEXT: testb %bl, %bl
; 64-ALL-NEXT: jne .LBB0_2
; 64-ALL-NEXT: # %bb.1: # %t
@@ -218,7 +218,7 @@ define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) nounwind {
; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx
; 32-GOOD-RA-NEXT: lock cmpxchgl %esi, (%ecx)
; 32-GOOD-RA-NEXT: sete %bl
-; 32-GOOD-RA-NEXT: calll foo
+; 32-GOOD-RA-NEXT: calll foo at PLT
; 32-GOOD-RA-NEXT: testb %bl, %bl
; 32-GOOD-RA-NEXT: jne .LBB2_2
; 32-GOOD-RA-NEXT: # %bb.1: # %entry
@@ -240,7 +240,7 @@ define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) nounwind {
; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
; 32-FAST-RA-NEXT: lock cmpxchgl %esi, (%ecx)
; 32-FAST-RA-NEXT: sete %bl
-; 32-FAST-RA-NEXT: calll foo
+; 32-FAST-RA-NEXT: calll foo at PLT
; 32-FAST-RA-NEXT: testb %bl, %bl
; 32-FAST-RA-NEXT: jne .LBB2_2
; 32-FAST-RA-NEXT: # %bb.1: # %entry
@@ -261,7 +261,7 @@ define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) nounwind {
; 64-ALL-NEXT: movl %esi, %eax
; 64-ALL-NEXT: lock cmpxchgl %edx, (%rdi)
; 64-ALL-NEXT: sete %bpl
-; 64-ALL-NEXT: callq foo
+; 64-ALL-NEXT: callq foo at PLT
; 64-ALL-NEXT: testb %bpl, %bpl
; 64-ALL-NEXT: cmovnel %ebx, %eax
; 64-ALL-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll b/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
index d9c83756c3454..c769d83caab9c 100644
--- a/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
+++ b/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
@@ -32,13 +32,13 @@ define void @cmpxchg_flow(i128* %addr, i128 %desired, i128 %new) {
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne .LBB1_2
; CHECK-NEXT: # %bb.1: # %true
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB1_2: # %false
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/cmpxchg8b.ll b/llvm/test/CodeGen/X86/cmpxchg8b.ll
index 85f882ae54dd2..7b15426022c91 100644
--- a/llvm/test/CodeGen/X86/cmpxchg8b.ll
+++ b/llvm/test/CodeGen/X86/cmpxchg8b.ll
@@ -44,7 +44,7 @@ define void @t1(i64* nocapture %p) nounwind ssp {
; I486-NEXT: pushl $1
; I486-NEXT: pushl %ecx
; I486-NEXT: pushl %eax
-; I486-NEXT: calll __atomic_compare_exchange_8
+; I486-NEXT: calll __atomic_compare_exchange_8 at PLT
; I486-NEXT: addl $24, %esp
; I486-NEXT: movl %ebp, %esp
; I486-NEXT: popl %ebp
diff --git a/llvm/test/CodeGen/X86/coalescer-remat.ll b/llvm/test/CodeGen/X86/coalescer-remat.ll
index bad5cec33ecd4..ee3d4274692d0 100644
--- a/llvm/test/CodeGen/X86/coalescer-remat.ll
+++ b/llvm/test/CodeGen/X86/coalescer-remat.ll
@@ -10,8 +10,8 @@ define i32 @main() nounwind {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl $1, %ecx
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
-; CHECK-NEXT: leaq {{.*}}(%rip), %rdi
+; CHECK-NEXT: lock cmpxchgq %rcx, _val(%rip)
+; CHECK-NEXT: leaq LC(%rip), %rdi
; CHECK-NEXT: movq %rax, %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq _printf
diff --git a/llvm/test/CodeGen/X86/code-model-elf-memset.ll b/llvm/test/CodeGen/X86/code-model-elf-memset.ll
index df48470e8d533..b3b0f99029ad0 100644
--- a/llvm/test/CodeGen/X86/code-model-elf-memset.ll
+++ b/llvm/test/CodeGen/X86/code-model-elf-memset.ll
@@ -57,7 +57,7 @@ define i32 @main() #0 {
; LARGE-PIC-NEXT: subq $424, %rsp # imm = 0x1A8
; LARGE-PIC-NEXT: .cfi_def_cfa_offset 432
; LARGE-PIC-NEXT: .L0$pb:
-; LARGE-PIC-NEXT: leaq .L0${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L0$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L0$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movl $0, {{[0-9]+}}(%rsp)
diff --git a/llvm/test/CodeGen/X86/code-model-elf.ll b/llvm/test/CodeGen/X86/code-model-elf.ll
index dee7605e541e7..383092167b555 100644
--- a/llvm/test/CodeGen/X86/code-model-elf.ll
+++ b/llvm/test/CodeGen/X86/code-model-elf.ll
@@ -58,12 +58,12 @@ define dso_local i32* @lea_static_data() #0 {
;
; SMALL-PIC-LABEL: lea_static_data:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: leaq {{.*}}(%rip), %rax
+; SMALL-PIC-NEXT: leaq static_data(%rip), %rax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: lea_static_data:
; MEDIUM-PIC: # %bb.0:
-; MEDIUM-PIC-NEXT: leaq {{.*}}(%rip), %rcx
+; MEDIUM-PIC-NEXT: leaq _GLOBAL_OFFSET_TABLE_(%rip), %rcx
; MEDIUM-PIC-NEXT: movabsq $static_data at GOTOFF, %rax
; MEDIUM-PIC-NEXT: addq %rcx, %rax
; MEDIUM-PIC-NEXT: retq
@@ -71,7 +71,7 @@ define dso_local i32* @lea_static_data() #0 {
; LARGE-PIC-LABEL: lea_static_data:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L0$pb:
-; LARGE-PIC-NEXT: leaq .L0${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L0$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L0$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $static_data at GOTOFF, %rax
@@ -98,12 +98,12 @@ define dso_local i32* @lea_global_data() #0 {
;
; SMALL-PIC-LABEL: lea_global_data:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: leaq {{.*}}(%rip), %rax
+; SMALL-PIC-NEXT: leaq global_data(%rip), %rax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: lea_global_data:
; MEDIUM-PIC: # %bb.0:
-; MEDIUM-PIC-NEXT: leaq {{.*}}(%rip), %rcx
+; MEDIUM-PIC-NEXT: leaq _GLOBAL_OFFSET_TABLE_(%rip), %rcx
; MEDIUM-PIC-NEXT: movabsq $global_data at GOTOFF, %rax
; MEDIUM-PIC-NEXT: addq %rcx, %rax
; MEDIUM-PIC-NEXT: retq
@@ -111,7 +111,7 @@ define dso_local i32* @lea_global_data() #0 {
; LARGE-PIC-LABEL: lea_global_data:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L1$pb:
-; LARGE-PIC-NEXT: leaq .L1${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L1$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L1$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $global_data at GOTOFF, %rax
@@ -123,12 +123,12 @@ define dso_local i32* @lea_global_data() #0 {
define dso_local i32* @lea_extern_data() #0 {
; SMALL-STATIC-LABEL: lea_extern_data:
; SMALL-STATIC: # %bb.0:
-; SMALL-STATIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; SMALL-STATIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; SMALL-STATIC-NEXT: retq
;
; MEDIUM-STATIC-LABEL: lea_extern_data:
; MEDIUM-STATIC: # %bb.0:
-; MEDIUM-STATIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; MEDIUM-STATIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; MEDIUM-STATIC-NEXT: retq
;
; LARGE-STATIC-LABEL: lea_extern_data:
@@ -138,18 +138,18 @@ define dso_local i32* @lea_extern_data() #0 {
;
; SMALL-PIC-LABEL: lea_extern_data:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; SMALL-PIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: lea_extern_data:
; MEDIUM-PIC: # %bb.0:
-; MEDIUM-PIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; MEDIUM-PIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; MEDIUM-PIC-NEXT: retq
;
; LARGE-PIC-LABEL: lea_extern_data:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L2$pb:
-; LARGE-PIC-NEXT: leaq .L2${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L2$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L2$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $extern_data at GOT, %rax
@@ -161,7 +161,7 @@ define dso_local i32* @lea_extern_data() #0 {
define dso_local i32 @load_global_data() #0 {
; SMALL-STATIC-LABEL: load_global_data:
; SMALL-STATIC: # %bb.0:
-; SMALL-STATIC-NEXT: movl global_data+{{.*}}(%rip), %eax
+; SMALL-STATIC-NEXT: movl global_data+8(%rip), %eax
; SMALL-STATIC-NEXT: retq
;
; MEDIUM-STATIC-LABEL: load_global_data:
@@ -178,12 +178,12 @@ define dso_local i32 @load_global_data() #0 {
;
; SMALL-PIC-LABEL: load_global_data:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: movl global_data+{{.*}}(%rip), %eax
+; SMALL-PIC-NEXT: movl global_data+8(%rip), %eax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: load_global_data:
; MEDIUM-PIC: # %bb.0:
-; MEDIUM-PIC-NEXT: leaq {{.*}}(%rip), %rax
+; MEDIUM-PIC-NEXT: leaq _GLOBAL_OFFSET_TABLE_(%rip), %rax
; MEDIUM-PIC-NEXT: movabsq $global_data at GOTOFF, %rcx
; MEDIUM-PIC-NEXT: movl 8(%rax,%rcx), %eax
; MEDIUM-PIC-NEXT: retq
@@ -191,7 +191,7 @@ define dso_local i32 @load_global_data() #0 {
; LARGE-PIC-LABEL: load_global_data:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L3$pb:
-; LARGE-PIC-NEXT: leaq .L3${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L3$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L3$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $global_data at GOTOFF, %rax
@@ -204,13 +204,13 @@ define dso_local i32 @load_global_data() #0 {
define dso_local i32 @load_extern_data() #0 {
; SMALL-STATIC-LABEL: load_extern_data:
; SMALL-STATIC: # %bb.0:
-; SMALL-STATIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; SMALL-STATIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; SMALL-STATIC-NEXT: movl 8(%rax), %eax
; SMALL-STATIC-NEXT: retq
;
; MEDIUM-STATIC-LABEL: load_extern_data:
; MEDIUM-STATIC: # %bb.0:
-; MEDIUM-STATIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; MEDIUM-STATIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; MEDIUM-STATIC-NEXT: movl 8(%rax), %eax
; MEDIUM-STATIC-NEXT: retq
;
@@ -222,20 +222,20 @@ define dso_local i32 @load_extern_data() #0 {
;
; SMALL-PIC-LABEL: load_extern_data:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; SMALL-PIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; SMALL-PIC-NEXT: movl 8(%rax), %eax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: load_extern_data:
; MEDIUM-PIC: # %bb.0:
-; MEDIUM-PIC-NEXT: movq extern_data@{{.*}}(%rip), %rax
+; MEDIUM-PIC-NEXT: movq extern_data at GOTPCREL(%rip), %rax
; MEDIUM-PIC-NEXT: movl 8(%rax), %eax
; MEDIUM-PIC-NEXT: retq
;
; LARGE-PIC-LABEL: load_extern_data:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L4$pb:
-; LARGE-PIC-NEXT: leaq .L4${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L4$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L4$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $extern_data at GOT, %rax
@@ -280,7 +280,7 @@ define dso_local void ()* @lea_static_fn() #0 {
;
; SMALL-PIC-LABEL: lea_static_fn:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: leaq {{.*}}(%rip), %rax
+; SMALL-PIC-NEXT: leaq static_fn(%rip), %rax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: lea_static_fn:
@@ -291,7 +291,7 @@ define dso_local void ()* @lea_static_fn() #0 {
; LARGE-PIC-LABEL: lea_static_fn:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L7$pb:
-; LARGE-PIC-NEXT: leaq .L7${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L7$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L7$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $static_fn at GOTOFF, %rax
@@ -318,7 +318,7 @@ define dso_local void ()* @lea_global_fn() #0 {
;
; SMALL-PIC-LABEL: lea_global_fn:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: leaq {{.*}}(%rip), %rax
+; SMALL-PIC-NEXT: leaq global_fn(%rip), %rax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: lea_global_fn:
@@ -329,7 +329,7 @@ define dso_local void ()* @lea_global_fn() #0 {
; LARGE-PIC-LABEL: lea_global_fn:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L8$pb:
-; LARGE-PIC-NEXT: leaq .L8${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L8$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L8$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $global_fn at GOTOFF, %rax
@@ -341,12 +341,12 @@ define dso_local void ()* @lea_global_fn() #0 {
define dso_local void ()* @lea_extern_fn() #0 {
; SMALL-STATIC-LABEL: lea_extern_fn:
; SMALL-STATIC: # %bb.0:
-; SMALL-STATIC-NEXT: movq extern_fn@{{.*}}(%rip), %rax
+; SMALL-STATIC-NEXT: movq extern_fn at GOTPCREL(%rip), %rax
; SMALL-STATIC-NEXT: retq
;
; MEDIUM-STATIC-LABEL: lea_extern_fn:
; MEDIUM-STATIC: # %bb.0:
-; MEDIUM-STATIC-NEXT: movq extern_fn@{{.*}}(%rip), %rax
+; MEDIUM-STATIC-NEXT: movq extern_fn at GOTPCREL(%rip), %rax
; MEDIUM-STATIC-NEXT: retq
;
; LARGE-STATIC-LABEL: lea_extern_fn:
@@ -356,18 +356,18 @@ define dso_local void ()* @lea_extern_fn() #0 {
;
; SMALL-PIC-LABEL: lea_extern_fn:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: movq extern_fn@{{.*}}(%rip), %rax
+; SMALL-PIC-NEXT: movq extern_fn at GOTPCREL(%rip), %rax
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: lea_extern_fn:
; MEDIUM-PIC: # %bb.0:
-; MEDIUM-PIC-NEXT: movq extern_fn@{{.*}}(%rip), %rax
+; MEDIUM-PIC-NEXT: movq extern_fn at GOTPCREL(%rip), %rax
; MEDIUM-PIC-NEXT: retq
;
; LARGE-PIC-LABEL: lea_extern_fn:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L9$pb:
-; LARGE-PIC-NEXT: leaq .L9${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L9$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L9$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq $extern_fn at GOT, %rax
@@ -402,7 +402,7 @@ define dso_local void ()* @lea_extern_fn() #0 {
define dso_local i32 @load_thread_data() #0 {
; CHECK-LABEL: load_thread_data:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq thread_data@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq thread_data at GOTTPOFF(%rip), %rax
; CHECK-NEXT: movl %fs:(%rax), %eax
; CHECK-NEXT: retq
%1 = load i32, i32* @thread_data, align 4
@@ -412,40 +412,40 @@ define dso_local i32 @load_thread_data() #0 {
define dso_local float @load_constant_pool(float %x) #0 {
; SMALL-STATIC-LABEL: load_constant_pool:
; SMALL-STATIC: # %bb.0:
-; SMALL-STATIC-NEXT: addss {{.*}}(%rip), %xmm0
+; SMALL-STATIC-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SMALL-STATIC-NEXT: retq
;
; MEDIUM-STATIC-LABEL: load_constant_pool:
; MEDIUM-STATIC: # %bb.0:
-; MEDIUM-STATIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; MEDIUM-STATIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; MEDIUM-STATIC-NEXT: addss (%rax), %xmm0
; MEDIUM-STATIC-NEXT: retq
;
; LARGE-STATIC-LABEL: load_constant_pool:
; LARGE-STATIC: # %bb.0:
-; LARGE-STATIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; LARGE-STATIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE-STATIC-NEXT: addss (%rax), %xmm0
; LARGE-STATIC-NEXT: retq
;
; SMALL-PIC-LABEL: load_constant_pool:
; SMALL-PIC: # %bb.0:
-; SMALL-PIC-NEXT: addss {{.*}}(%rip), %xmm0
+; SMALL-PIC-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SMALL-PIC-NEXT: retq
;
; MEDIUM-PIC-LABEL: load_constant_pool:
; MEDIUM-PIC: # %bb.0:
-; MEDIUM-PIC-NEXT: leaq {{.*}}(%rip), %rax
-; MEDIUM-PIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}@GOTOFF, %rcx
+; MEDIUM-PIC-NEXT: leaq _GLOBAL_OFFSET_TABLE_(%rip), %rax
+; MEDIUM-PIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rcx
; MEDIUM-PIC-NEXT: addss (%rax,%rcx), %xmm0
; MEDIUM-PIC-NEXT: retq
;
; LARGE-PIC-LABEL: load_constant_pool:
; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L11$pb:
-; LARGE-PIC-NEXT: leaq .L11${{.*}}(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L11$pb(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L11$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
-; LARGE-PIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
+; LARGE-PIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
; LARGE-PIC-NEXT: addss (%rcx,%rax), %xmm0
; LARGE-PIC-NEXT: retq
%a = fadd float %x, 1.0
diff --git a/llvm/test/CodeGen/X86/combine-abs.ll b/llvm/test/CodeGen/X86/combine-abs.ll
index 4ff9fef148fa7..1ad12cca4cb06 100644
--- a/llvm/test/CodeGen/X86/combine-abs.ll
+++ b/llvm/test/CodeGen/X86/combine-abs.ll
@@ -163,12 +163,12 @@ define <4 x i64> @combine_v4i64_abs_abs(<4 x i64> %a) {
define <16 x i8> @combine_v16i8_abs_constant(<16 x i8> %a) {
; SSE-LABEL: combine_v16i8_abs_constant:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_v16i8_abs_constant:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = insertelement <16 x i8> undef, i8 15, i32 0
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/X86/combine-add-ssat.ll b/llvm/test/CodeGen/X86/combine-add-ssat.ll
index 7a88fc8328b10..48f5d6c760963 100644
--- a/llvm/test/CodeGen/X86/combine-add-ssat.ll
+++ b/llvm/test/CodeGen/X86/combine-add-ssat.ll
@@ -92,12 +92,12 @@ define i32 @combine_constant_i32(i32 %a0) {
define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) {
; SSE-LABEL: combine_constant_v8i16:
; SSE: # %bb.0:
-; SSE-NEXT: paddsw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_constant_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddsw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0)
ret <8 x i16> %res
diff --git a/llvm/test/CodeGen/X86/combine-add-usat.ll b/llvm/test/CodeGen/X86/combine-add-usat.ll
index ae3d8758d5612..02937ea84f05f 100644
--- a/llvm/test/CodeGen/X86/combine-add-usat.ll
+++ b/llvm/test/CodeGen/X86/combine-add-usat.ll
@@ -88,12 +88,12 @@ define i32 @combine_constant_i32(i32 %a0) {
define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) {
; SSE-LABEL: combine_constant_v8i16:
; SSE: # %bb.0:
-; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_constant_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0)
ret <8 x i16> %1
diff --git a/llvm/test/CodeGen/X86/combine-add.ll b/llvm/test/CodeGen/X86/combine-add.ll
index 1d20fcf33d742..81b38334cacb7 100644
--- a/llvm/test/CodeGen/X86/combine-add.ll
+++ b/llvm/test/CodeGen/X86/combine-add.ll
@@ -212,14 +212,14 @@ define <4 x i32> @combine_vec_add_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32>
; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm1
; SSE-NEXT: psubd %xmm1, %xmm0
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_add_sub_sub:
; AVX: # %bb.0:
; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = sub <4 x i32> %a, %b
%2 = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %d
@@ -231,8 +231,8 @@ define <4 x i32> @combine_vec_add_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32>
define <4 x i32> @combine_vec_add_uniquebits(<4 x i32> %a, <4 x i32> %b) {
; SSE-LABEL: combine_vec_add_uniquebits:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/combine-and.ll b/llvm/test/CodeGen/X86/combine-and.ll
index 462374c4862d5..9f26983795754 100644
--- a/llvm/test/CodeGen/X86/combine-and.ll
+++ b/llvm/test/CodeGen/X86/combine-and.ll
@@ -302,7 +302,7 @@ define <16 x i8> @PR34620(<16 x i8> %a0, <16 x i8> %a1) {
; CHECK-LABEL: PR34620:
; CHECK: # %bb.0:
; CHECK-NEXT: psrlw $1, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: retq
%1 = lshr <16 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
diff --git a/llvm/test/CodeGen/X86/combine-bextr.ll b/llvm/test/CodeGen/X86/combine-bextr.ll
index 8744beb1e20ec..c36723732b5cb 100644
--- a/llvm/test/CodeGen/X86/combine-bextr.ll
+++ b/llvm/test/CodeGen/X86/combine-bextr.ll
@@ -40,8 +40,8 @@ define float @bextr_uitofp(i32 %x, i32 %y) {
; X32-NEXT: movl $3855, %eax # imm = 0xF0F
; X32-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm0
-; X32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X32-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: cvtsd2ss %xmm0, %xmm0
; X32-NEXT: movss %xmm0, (%esp)
; X32-NEXT: flds (%esp)
diff --git a/llvm/test/CodeGen/X86/combine-bitreverse.ll b/llvm/test/CodeGen/X86/combine-bitreverse.ll
index 1875c3f889f07..a9bcf394048be 100644
--- a/llvm/test/CodeGen/X86/combine-bitreverse.ll
+++ b/llvm/test/CodeGen/X86/combine-bitreverse.ll
@@ -51,23 +51,23 @@ define <4 x i32> @test_demandedbits_bitreverse(<4 x i32> %a0) nounwind {
; X86-NEXT: packuswb %xmm2, %xmm0
; X86-NEXT: movdqa %xmm0, %xmm1
; X86-NEXT: psllw $4, %xmm1
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: psrlw $4, %xmm0
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: por %xmm1, %xmm0
; X86-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-NEXT: pand %xmm0, %xmm1
; X86-NEXT: psllw $2, %xmm1
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: psrlw $2, %xmm0
; X86-NEXT: por %xmm1, %xmm0
; X86-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; X86-NEXT: pand %xmm0, %xmm1
; X86-NEXT: paddb %xmm1, %xmm1
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: psrlw $1, %xmm0
; X86-NEXT: por %xmm1, %xmm0
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: test_demandedbits_bitreverse:
@@ -82,7 +82,7 @@ define <4 x i32> @test_demandedbits_bitreverse(<4 x i32> %a0) nounwind {
; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15]
; X64-NEXT: vpshufb %xmm0, %xmm1, %xmm0
; X64-NEXT: vpor %xmm0, %xmm2, %xmm0
-; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%b = or <4 x i32> %a0, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
%c = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %b)
diff --git a/llvm/test/CodeGen/X86/combine-bitselect.ll b/llvm/test/CodeGen/X86/combine-bitselect.ll
index 614d134173e7b..27cbf6e6e7d94 100644
--- a/llvm/test/CodeGen/X86/combine-bitselect.ll
+++ b/llvm/test/CodeGen/X86/combine-bitselect.ll
@@ -13,33 +13,33 @@
define <2 x i64> @bitselect_v2i64_rr(<2 x i64>, <2 x i64>) {
; SSE-LABEL: bitselect_v2i64_rr:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; XOP-LABEL: bitselect_v2i64_rr:
; XOP: # %bb.0:
-; XOP-NEXT: vpcmov {{.*}}(%rip), %xmm0, %xmm1, %xmm0
+; XOP-NEXT: vpcmov {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq
;
; AVX-LABEL: bitselect_v2i64_rr:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
;
; AVX512F-LABEL: bitselect_v2i64_rr:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: bitselect_v2i64_rr:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: retq
%3 = and <2 x i64> %0, <i64 4294967296, i64 12884901890>
%4 = and <2 x i64> %1, <i64 -4294967297, i64 -12884901891>
@@ -51,37 +51,37 @@ define <2 x i64> @bitselect_v2i64_rm(<2 x i64>, <2 x i64>* nocapture readonly) {
; SSE-LABEL: bitselect_v2i64_rm:
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; XOP-LABEL: bitselect_v2i64_rm:
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %xmm1
-; XOP-NEXT: vpcmov {{.*}}(%rip), %xmm0, %xmm1, %xmm0
+; XOP-NEXT: vpcmov {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq
;
; AVX-LABEL: bitselect_v2i64_rm:
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm1
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
;
; AVX512F-LABEL: bitselect_v2i64_rm:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: bitselect_v2i64_rm:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm1
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: retq
%3 = load <2 x i64>, <2 x i64>* %1
%4 = and <2 x i64> %0, <i64 8589934593, i64 3>
@@ -94,37 +94,37 @@ define <2 x i64> @bitselect_v2i64_mr(<2 x i64>* nocapture readonly, <2 x i64>) {
; SSE-LABEL: bitselect_v2i64_mr:
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; XOP-LABEL: bitselect_v2i64_mr:
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %xmm1
-; XOP-NEXT: vpcmov {{.*}}(%rip), %xmm0, %xmm1, %xmm0
+; XOP-NEXT: vpcmov {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq
;
; AVX-LABEL: bitselect_v2i64_mr:
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm1
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
;
; AVX512F-LABEL: bitselect_v2i64_mr:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: bitselect_v2i64_mr:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm1
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: retq
%3 = load <2 x i64>, <2 x i64>* %0
%4 = and <2 x i64> %3, <i64 12884901890, i64 4294967296>
@@ -138,8 +138,8 @@ define <2 x i64> @bitselect_v2i64_mm(<2 x i64>* nocapture readonly, <2 x i64>* n
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm1
; SSE-NEXT: movaps (%rsi), %xmm0
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -154,8 +154,8 @@ define <2 x i64> @bitselect_v2i64_mm(<2 x i64>* nocapture readonly, <2 x i64>* n
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm0
; AVX-NEXT: vmovaps (%rsi), %xmm1
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
;
@@ -163,8 +163,8 @@ define <2 x i64> @bitselect_v2i64_mm(<2 x i64>* nocapture readonly, <2 x i64>* n
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm0
; AVX512F-NEXT: vmovaps (%rsi), %xmm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: retq
;
@@ -295,36 +295,36 @@ define <2 x i64> @bitselect_v2i64_broadcast_rrm(<2 x i64> %a0, <2 x i64> %a1, i6
define <4 x i64> @bitselect_v4i64_rr(<4 x i64>, <4 x i64>) {
; SSE-LABEL: bitselect_v4i64_rr:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
-; SSE-NEXT: andps {{.*}}(%rip), %xmm3
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE-NEXT: orps %xmm3, %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm2
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: orps %xmm2, %xmm0
; SSE-NEXT: retq
;
; XOP-LABEL: bitselect_v4i64_rr:
; XOP: # %bb.0:
-; XOP-NEXT: vpcmov {{.*}}(%rip), %ymm0, %ymm1, %ymm0
+; XOP-NEXT: vpcmov {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1, %ymm0
; XOP-NEXT: retq
;
; AVX-LABEL: bitselect_v4i64_rr:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
;
; AVX512F-LABEL: bitselect_v4i64_rr:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: bitselect_v4i64_rr:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VL-NEXT: retq
%3 = and <4 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890>
%4 = and <4 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891>
@@ -352,29 +352,29 @@ define <4 x i64> @bitselect_v4i64_rm(<4 x i64>, <4 x i64>* nocapture readonly) {
; XOP-LABEL: bitselect_v4i64_rm:
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %ymm1
-; XOP-NEXT: vpcmov {{.*}}(%rip), %ymm0, %ymm1, %ymm0
+; XOP-NEXT: vpcmov {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1, %ymm0
; XOP-NEXT: retq
;
; AVX-LABEL: bitselect_v4i64_rm:
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %ymm1
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
;
; AVX512F-LABEL: bitselect_v4i64_rm:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %ymm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: bitselect_v4i64_rm:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %ymm1
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VL-NEXT: retq
%3 = load <4 x i64>, <4 x i64>* %1
%4 = and <4 x i64> %0, <i64 8589934593, i64 3, i64 8589934593, i64 3>
@@ -403,29 +403,29 @@ define <4 x i64> @bitselect_v4i64_mr(<4 x i64>* nocapture readonly, <4 x i64>) {
; XOP-LABEL: bitselect_v4i64_mr:
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %ymm1
-; XOP-NEXT: vpcmov {{.*}}(%rip), %ymm0, %ymm1, %ymm0
+; XOP-NEXT: vpcmov {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1, %ymm0
; XOP-NEXT: retq
;
; AVX-LABEL: bitselect_v4i64_mr:
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %ymm1
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
;
; AVX512F-LABEL: bitselect_v4i64_mr:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %ymm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: bitselect_v4i64_mr:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %ymm1
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VL-NEXT: retq
%3 = load <4 x i64>, <4 x i64>* %0
%4 = and <4 x i64> %3, <i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296>
@@ -460,8 +460,8 @@ define <4 x i64> @bitselect_v4i64_mm(<4 x i64>* nocapture readonly, <4 x i64>* n
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %ymm0
; AVX-NEXT: vmovaps (%rsi), %ymm1
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
;
@@ -469,8 +469,8 @@ define <4 x i64> @bitselect_v4i64_mm(<4 x i64>* nocapture readonly, <4 x i64>* n
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %ymm0
; AVX512F-NEXT: vmovaps (%rsi), %ymm1
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: retq
;
@@ -653,7 +653,7 @@ define <8 x i64> @bitselect_v8i64_rr(<8 x i64>, <8 x i64>) {
;
; AVX512-LABEL: bitselect_v8i64_rr:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512-NEXT: retq
%3 = and <8 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890, i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890>
%4 = and <8 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891>
@@ -715,7 +715,7 @@ define <8 x i64> @bitselect_v8i64_rm(<8 x i64>, <8 x i64>* nocapture readonly) {
; AVX512-LABEL: bitselect_v8i64_rm:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa64 (%rdi), %zmm1
-; AVX512-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512-NEXT: retq
%3 = load <8 x i64>, <8 x i64>* %1
%4 = and <8 x i64> %0, <i64 8589934593, i64 3, i64 8589934593, i64 3, i64 8589934593, i64 3, i64 8589934593, i64 3>
@@ -778,7 +778,7 @@ define <8 x i64> @bitselect_v8i64_mr(<8 x i64>* nocapture readonly, <8 x i64>) {
; AVX512-LABEL: bitselect_v8i64_mr:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa64 (%rdi), %zmm1
-; AVX512-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512-NEXT: retq
%3 = load <8 x i64>, <8 x i64>* %0
%4 = and <8 x i64> %3, <i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296>
@@ -982,7 +982,7 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
; SSE-NEXT: pcmpeqd %xmm0, %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [12,12,12,12]
; SSE-NEXT: pcmpeqd %xmm1, %xmm0
-; SSE-NEXT: pcmpeqd {{.*}}(%rip), %xmm1
+; SSE-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: pand %xmm2, %xmm1
; SSE-NEXT: pandn %xmm0, %xmm2
; SSE-NEXT: por %xmm1, %xmm2
@@ -993,8 +993,8 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
; XOP: # %bb.0: # %bb
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpcomneqd %xmm2, %xmm0, %xmm0
-; XOP-NEXT: vpcomeqd {{.*}}(%rip), %xmm1, %xmm2
-; XOP-NEXT: vpcomeqd {{.*}}(%rip), %xmm1, %xmm1
+; XOP-NEXT: vpcomeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
+; XOP-NEXT: vpcomeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; XOP-NEXT: retq
;
@@ -1002,8 +1002,8 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
; AVX1: # %bb.0: # %bb
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm2
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
; AVX1-NEXT: retq
;
@@ -1022,8 +1022,8 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
; AVX512F: # %bb.0: # %bb
; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512F-NEXT: vpcmpeqd {{.*}}(%rip){1to16}, %zmm1, %k1
-; AVX512F-NEXT: vpcmpeqd {{.*}}(%rip){1to16}, %zmm1, %k2
+; AVX512F-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %k1
+; AVX512F-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %k2
; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0 {%k2}
; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 {%k1}
; AVX512F-NEXT: korw %k0, %k1, %k1
@@ -1034,8 +1034,8 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
;
; AVX512VL-LABEL: bitselect_v4i1_loop:
; AVX512VL: # %bb.0: # %bb
-; AVX512VL-NEXT: vpcmpeqd {{.*}}(%rip){1to4}, %xmm1, %k1
-; AVX512VL-NEXT: vpcmpeqd {{.*}}(%rip){1to4}, %xmm1, %k2
+; AVX512VL-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %k1
+; AVX512VL-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %k2
; AVX512VL-NEXT: vptestnmd %xmm0, %xmm0, %k0 {%k2}
; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1 {%k1}
; AVX512VL-NEXT: korw %k0, %k1, %k1
diff --git a/llvm/test/CodeGen/X86/combine-concatvectors.ll b/llvm/test/CodeGen/X86/combine-concatvectors.ll
index 40568d2388949..1a8d8d9e73ece 100644
--- a/llvm/test/CodeGen/X86/combine-concatvectors.ll
+++ b/llvm/test/CodeGen/X86/combine-concatvectors.ll
@@ -26,7 +26,7 @@ define void @d(i1 %cmp) {
; CHECK: # %bb.0: # %bar
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq fun
+; CHECK-NEXT: callq fun at PLT
bar:
%val = call { i8, double } @fun()
%extr = extractvalue { i8, double } %val, 1
diff --git a/llvm/test/CodeGen/X86/combine-fabs.ll b/llvm/test/CodeGen/X86/combine-fabs.ll
index 1635040052394..e668c87003202 100644
--- a/llvm/test/CodeGen/X86/combine-fabs.ll
+++ b/llvm/test/CodeGen/X86/combine-fabs.ll
@@ -40,7 +40,7 @@ define <4 x float> @combine_vec_fabs_constant() {
define float @combine_fabs_fabs(float %a) {
; SSE-LABEL: combine_fabs_fabs:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_fabs_fabs:
@@ -56,7 +56,7 @@ define float @combine_fabs_fabs(float %a) {
define <4 x float> @combine_vec_fabs_fabs(<4 x float> %a) {
; SSE-LABEL: combine_vec_fabs_fabs:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fabs_fabs:
@@ -73,7 +73,7 @@ define <4 x float> @combine_vec_fabs_fabs(<4 x float> %a) {
define float @combine_fabs_fneg(float %a) {
; SSE-LABEL: combine_fabs_fneg:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_fabs_fneg:
@@ -89,7 +89,7 @@ define float @combine_fabs_fneg(float %a) {
define <4 x float> @combine_vec_fabs_fneg(<4 x float> %a) {
; SSE-LABEL: combine_vec_fabs_fneg:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fabs_fneg:
@@ -106,7 +106,7 @@ define <4 x float> @combine_vec_fabs_fneg(<4 x float> %a) {
define float @combine_fabs_fcopysign(float %a, float %b) {
; SSE-LABEL: combine_fabs_fcopysign:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_fabs_fcopysign:
@@ -122,7 +122,7 @@ define float @combine_fabs_fcopysign(float %a, float %b) {
define <4 x float> @combine_vec_fabs_fcopysign(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: combine_vec_fabs_fcopysign:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fabs_fcopysign:
diff --git a/llvm/test/CodeGen/X86/combine-fcopysign.ll b/llvm/test/CodeGen/X86/combine-fcopysign.ll
index 987c4db3176ea..d38fd817f6242 100644
--- a/llvm/test/CodeGen/X86/combine-fcopysign.ll
+++ b/llvm/test/CodeGen/X86/combine-fcopysign.ll
@@ -11,7 +11,7 @@
define <4 x float> @combine_vec_fcopysign_pos_constant0(<4 x float> %x) {
; SSE-LABEL: combine_vec_fcopysign_pos_constant0:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fcopysign_pos_constant0:
@@ -26,7 +26,7 @@ define <4 x float> @combine_vec_fcopysign_pos_constant0(<4 x float> %x) {
define <4 x float> @combine_vec_fcopysign_pos_constant1(<4 x float> %x) {
; SSE-LABEL: combine_vec_fcopysign_pos_constant1:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fcopysign_pos_constant1:
@@ -41,7 +41,7 @@ define <4 x float> @combine_vec_fcopysign_pos_constant1(<4 x float> %x) {
define <4 x float> @combine_vec_fcopysign_fabs_sgn(<4 x float> %x, <4 x float> %y) {
; SSE-LABEL: combine_vec_fcopysign_fabs_sgn:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fcopysign_fabs_sgn:
@@ -58,7 +58,7 @@ define <4 x float> @combine_vec_fcopysign_fabs_sgn(<4 x float> %x, <4 x float> %
define <4 x float> @combine_vec_fcopysign_neg_constant0(<4 x float> %x) {
; SSE-LABEL: combine_vec_fcopysign_neg_constant0:
; SSE: # %bb.0:
-; SSE-NEXT: orps {{.*}}(%rip), %xmm0
+; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fcopysign_neg_constant0:
@@ -73,7 +73,7 @@ define <4 x float> @combine_vec_fcopysign_neg_constant0(<4 x float> %x) {
define <4 x float> @combine_vec_fcopysign_neg_constant1(<4 x float> %x) {
; SSE-LABEL: combine_vec_fcopysign_neg_constant1:
; SSE: # %bb.0:
-; SSE-NEXT: orps {{.*}}(%rip), %xmm0
+; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fcopysign_neg_constant1:
@@ -88,7 +88,7 @@ define <4 x float> @combine_vec_fcopysign_neg_constant1(<4 x float> %x) {
define <4 x float> @combine_vec_fcopysign_fneg_fabs_sgn(<4 x float> %x, <4 x float> %y) {
; SSE-LABEL: combine_vec_fcopysign_fneg_fabs_sgn:
; SSE: # %bb.0:
-; SSE-NEXT: orps {{.*}}(%rip), %xmm0
+; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_fcopysign_fneg_fabs_sgn:
@@ -106,8 +106,8 @@ define <4 x float> @combine_vec_fcopysign_fneg_fabs_sgn(<4 x float> %x, <4 x flo
define <4 x float> @combine_vec_fcopysign_fabs_mag(<4 x float> %x, <4 x float> %y) {
; SSE-LABEL: combine_vec_fcopysign_fabs_mag:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -128,8 +128,8 @@ define <4 x float> @combine_vec_fcopysign_fabs_mag(<4 x float> %x, <4 x float> %
define <4 x float> @combine_vec_fcopysign_fneg_mag(<4 x float> %x, <4 x float> %y) {
; SSE-LABEL: combine_vec_fcopysign_fneg_mag:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -150,8 +150,8 @@ define <4 x float> @combine_vec_fcopysign_fneg_mag(<4 x float> %x, <4 x float> %
define <4 x float> @combine_vec_fcopysign_fcopysign_mag(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
; SSE-LABEL: combine_vec_fcopysign_fcopysign_mag:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -172,8 +172,8 @@ define <4 x float> @combine_vec_fcopysign_fcopysign_mag(<4 x float> %x, <4 x flo
define <4 x float> @combine_vec_fcopysign_fcopysign_sgn(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
; SSE-LABEL: combine_vec_fcopysign_fcopysign_sgn:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm2
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orps %xmm2, %xmm0
; SSE-NEXT: retq
;
@@ -228,8 +228,8 @@ define <4 x float> @combine_vec_fcopysign_fptrunc_sgn(<4 x float> %x, <4 x doubl
; SSE-NEXT: cvtpd2ps %xmm2, %xmm2
; SSE-NEXT: cvtpd2ps %xmm1, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; SSE-NEXT: andpd {{.*}}(%rip), %xmm1
-; SSE-NEXT: andpd {{.*}}(%rip), %xmm0
+; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/combine-multiplies.ll b/llvm/test/CodeGen/X86/combine-multiplies.ll
index 73f9642a2197f..f460e47bc2b6c 100644
--- a/llvm/test/CodeGen/X86/combine-multiplies.ll
+++ b/llvm/test/CodeGen/X86/combine-multiplies.ll
@@ -116,7 +116,7 @@ define void @testCombineMultiplies_splat(<4 x i32> %v1) nounwind {
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [242,242,242,242]
; CHECK-NEXT: paddd %xmm0, %xmm2
-; CHECK-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movdqa %xmm2, v2
; CHECK-NEXT: movdqa %xmm0, v3
; CHECK-NEXT: movdqa %xmm1, x
@@ -151,7 +151,7 @@ define void @testCombineMultiplies_non_splat(<4 x i32> %v1) nounwind {
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [242,726,1452,2420]
; CHECK-NEXT: paddd %xmm0, %xmm2
-; CHECK-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movdqa %xmm2, v2
; CHECK-NEXT: movdqa %xmm0, v3
; CHECK-NEXT: movdqa %xmm1, x
diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll
index 2d7ab3db84598..135abbfeacdd4 100644
--- a/llvm/test/CodeGen/X86/combine-or.ll
+++ b/llvm/test/CodeGen/X86/combine-or.ll
@@ -435,8 +435,8 @@ define <4 x i32> @test2f(<4 x i32> %a, <4 x i32> %b) {
define <2 x i64> @or_and_v2i64(<2 x i64> %a0) {
; CHECK-LABEL: or_and_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%1 = and <2 x i64> %a0, <i64 7, i64 7>
%2 = or <2 x i64> %1, <i64 3, i64 3>
@@ -446,8 +446,8 @@ define <2 x i64> @or_and_v2i64(<2 x i64> %a0) {
define <4 x i32> @or_and_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: or_and_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%1 = and <4 x i32> %a0, <i32 1, i32 3, i32 5, i32 7>
%2 = or <4 x i32> %1, <i32 3, i32 2, i32 15, i32 2>
diff --git a/llvm/test/CodeGen/X86/combine-pmuldq.ll b/llvm/test/CodeGen/X86/combine-pmuldq.ll
index ae619ab590ecc..ffbac1affc481 100644
--- a/llvm/test/CodeGen/X86/combine-pmuldq.ll
+++ b/llvm/test/CodeGen/X86/combine-pmuldq.ll
@@ -140,13 +140,13 @@ define <8 x i64> @combine_zext_pmuludq_256(<8 x i32> %a) {
; AVX512VL-LABEL: combine_zext_pmuludq_256:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero
-; AVX512VL-NEXT: vpmuludq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512VL-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512DQVL-LABEL: combine_zext_pmuludq_256:
; AVX512DQVL: # %bb.0:
; AVX512DQVL-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero
-; AVX512DQVL-NEXT: vpmuludq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512DQVL-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512DQVL-NEXT: retq
%1 = zext <8 x i32> %a to <8 x i64>
%2 = mul nuw nsw <8 x i64> %1, <i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883>
@@ -214,7 +214,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; SSE-NEXT: psubd %xmm3, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
; SSE-NEXT: paddd %xmm1, %xmm2
@@ -241,7 +241,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
@@ -258,7 +258,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; AVX2-NEXT: vmovdqa (%rdi), %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1645975491,344322273,2164392969,1916962805]
; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm3
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX2-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; AVX2-NEXT: vpmuludq %xmm2, %xmm4, %xmm2
; AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
@@ -271,7 +271,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %edi
; AVX2-NEXT: vpextrd $1, %xmm0, %esi
; AVX2-NEXT: vpextrd $2, %xmm0, %edx
@@ -283,7 +283,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [1645975491,344322273,2164392969,1916962805]
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm3
+; AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; AVX512VL-NEXT: vpmuludq %xmm2, %xmm4, %xmm2
; AVX512VL-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
@@ -296,7 +296,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
; AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vmovd %xmm0, %edi
; AVX512VL-NEXT: vpextrd $1, %xmm0, %esi
; AVX512VL-NEXT: vpextrd $2, %xmm0, %edx
@@ -308,7 +308,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; AVX512DQVL-NEXT: vmovdqa (%rdi), %xmm0
; AVX512DQVL-NEXT: vmovdqa {{.*#+}} xmm1 = [1645975491,344322273,2164392969,1916962805]
; AVX512DQVL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; AVX512DQVL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm3
+; AVX512DQVL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX512DQVL-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; AVX512DQVL-NEXT: vpmuludq %xmm2, %xmm4, %xmm2
; AVX512DQVL-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
@@ -321,7 +321,7 @@ define i32 @PR43159(<4 x i32>* %a0) {
; AVX512DQVL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512DQVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
; AVX512DQVL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX512DQVL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512DQVL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512DQVL-NEXT: vmovd %xmm0, %edi
; AVX512DQVL-NEXT: vpextrd $1, %xmm0, %esi
; AVX512DQVL-NEXT: vpextrd $2, %xmm0, %edx
diff --git a/llvm/test/CodeGen/X86/combine-srem.ll b/llvm/test/CodeGen/X86/combine-srem.ll
index b08bb5b4dbdac..38ee6624e05aa 100644
--- a/llvm/test/CodeGen/X86/combine-srem.ll
+++ b/llvm/test/CodeGen/X86/combine-srem.ll
@@ -73,7 +73,7 @@ define <4 x i32> @combine_vec_srem_by_minsigned(<4 x i32> %x) {
; SSE-NEXT: psrad $31, %xmm1
; SSE-NEXT: psrld $1, %xmm1
; SSE-NEXT: paddd %xmm0, %xmm1
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psubd %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -82,7 +82,7 @@ define <4 x i32> @combine_vec_srem_by_minsigned(<4 x i32> %x) {
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -151,12 +151,12 @@ define <4 x i32> @combine_vec_srem_dupe(<4 x i32> %x) {
define <4 x i32> @combine_vec_srem_by_pos0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_srem_by_pos0:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: combine_vec_srem_by_pos0:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_srem_by_pos0:
@@ -172,12 +172,12 @@ define <4 x i32> @combine_vec_srem_by_pos0(<4 x i32> %x) {
define <4 x i32> @combine_vec_srem_by_pos1(<4 x i32> %x) {
; SSE-LABEL: combine_vec_srem_by_pos1:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_srem_by_pos1:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
%2 = srem <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>
@@ -192,7 +192,7 @@ define <4 x i32> @combine_vec_srem_by_pow2a(<4 x i32> %x) {
; SSE-NEXT: psrad $31, %xmm1
; SSE-NEXT: psrld $30, %xmm1
; SSE-NEXT: paddd %xmm0, %xmm1
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psubd %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -201,7 +201,7 @@ define <4 x i32> @combine_vec_srem_by_pow2a(<4 x i32> %x) {
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; AVX1-NEXT: vpsrld $30, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -268,7 +268,7 @@ define <4 x i32> @combine_vec_srem_by_pow2b(<4 x i32> %x) {
; SSE-NEXT: psrad $2, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
-; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psubd %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -287,14 +287,14 @@ define <4 x i32> @combine_vec_srem_by_pow2b(<4 x i32> %x) {
; AVX1-NEXT: vpsrad $2, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_srem_by_pow2b:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3]
; AVX2-NEXT: vpsravd %xmm2, %xmm1, %xmm1
@@ -332,7 +332,7 @@ define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
; SSE-NEXT: psrad $1, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
-; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: paddd %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: retq
@@ -355,17 +355,17 @@ define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
; AVX1-NEXT: vpsrad $1, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_srem_by_pow2b_neg:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm1, %xmm1
-; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
%1 = srem <4 x i32> %x, <i32 -2, i32 -4, i32 -8, i32 -16>
diff --git a/llvm/test/CodeGen/X86/combine-sub.ll b/llvm/test/CodeGen/X86/combine-sub.ll
index eb333dcd16847..0dd390d612e4f 100644
--- a/llvm/test/CodeGen/X86/combine-sub.ll
+++ b/llvm/test/CodeGen/X86/combine-sub.ll
@@ -30,12 +30,12 @@ define <4 x i32> @combine_vec_sub_self(<4 x i32> %a) {
define <4 x i32> @combine_vec_sub_constant(<4 x i32> %x) {
; SSE-LABEL: combine_vec_sub_constant:
; SSE: # %bb.0:
-; SSE-NEXT: psubd {{.*}}(%rip), %xmm0
+; SSE-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sub_constant:
; AVX: # %bb.0:
-; AVX-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = sub <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
ret <4 x i32> %1
@@ -245,14 +245,14 @@ define i32 @combine_sub_xor_consts(i32 %x) {
define <4 x i32> @combine_vec_sub_xor_consts(<4 x i32> %x) {
; SSE-LABEL: combine_vec_sub_xor_consts:
; SSE: # %bb.0:
-; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sub_xor_consts:
; AVX: # %bb.0:
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%xor = xor <4 x i32> %x, <i32 28, i32 29, i32 -1, i32 -31>
%sub = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %xor
diff --git a/llvm/test/CodeGen/X86/combine-udiv.ll b/llvm/test/CodeGen/X86/combine-udiv.ll
index c6e741540999d..b9ca5621edc59 100644
--- a/llvm/test/CodeGen/X86/combine-udiv.ll
+++ b/llvm/test/CodeGen/X86/combine-udiv.ll
@@ -212,12 +212,12 @@ define <4 x i32> @combine_vec_udiv_by_pow2b(<4 x i32> %x) {
;
; AVX2-LABEL: combine_vec_udiv_by_pow2b:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_by_pow2b:
; XOP: # %bb.0:
-; XOP-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
%1 = udiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
ret <4 x i32> %1
@@ -299,7 +299,7 @@ define <4 x i32> @combine_vec_udiv_by_pow2c(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
; SSE2-LABEL: combine_vec_udiv_by_shl_pow2a:
; SSE2: # %bb.0:
-; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrld %xmm2, %xmm3
@@ -320,7 +320,7 @@ define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
;
; SSE41-LABEL: combine_vec_udiv_by_shl_pow2a:
; SSE41: # %bb.0:
-; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm2, %xmm3
@@ -340,7 +340,7 @@ define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
;
; AVX1-LABEL: combine_vec_udiv_by_shl_pow2a:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
@@ -376,7 +376,7 @@ define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
; SSE2-LABEL: combine_vec_udiv_by_shl_pow2b:
; SSE2: # %bb.0:
-; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrld %xmm2, %xmm3
@@ -397,7 +397,7 @@ define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
;
; SSE41-LABEL: combine_vec_udiv_by_shl_pow2b:
; SSE41: # %bb.0:
-; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm2, %xmm3
@@ -417,7 +417,7 @@ define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
;
; AVX1-LABEL: combine_vec_udiv_by_shl_pow2b:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
@@ -434,7 +434,7 @@ define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
;
; AVX2-LABEL: combine_vec_udiv_by_shl_pow2b:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -476,7 +476,7 @@ define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
;
; AVX-LABEL: combine_vec_udiv_uniform:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -485,7 +485,7 @@ define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
;
; XOP-LABEL: combine_vec_udiv_uniform:
; XOP: # %bb.0:
-; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -505,14 +505,14 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; SSE2-NEXT: psrlw $3, %xmm3
; SSE2-NEXT: pandn %xmm3, %xmm1
; SSE2-NEXT: por %xmm2, %xmm1
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubw %xmm1, %xmm0
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: paddw %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,0,0,65535,65535,0]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pandn %xmm0, %xmm2
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq
@@ -522,9 +522,9 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $3, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
-; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: psubw %xmm1, %xmm0
-; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: paddw %xmm1, %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = <4096,2048,8,u,u,2,2,u>
; SSE41-NEXT: pmulhuw %xmm0, %xmm1
@@ -535,22 +535,22 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; AVX: # %bb.0:
; AVX-NEXT: vpsrlw $3, %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]
; AVX-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_nonuniform:
; XOP: # %bb.0:
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm1
-; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
-; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
%1 = udiv <8 x i16> %x, <i16 23, i16 34, i16 -23, i16 56, i16 128, i16 -1, i16 -256, i16 -32768>
ret <8 x i16> %1
@@ -565,8 +565,8 @@ define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -575,8 +575,8 @@ define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3,4,5,6,7]
-; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
-; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -584,15 +584,15 @@ define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
; AVX: # %bb.0:
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_nonuniform2:
; XOP: # %bb.0:
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
-; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
%1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41>
ret <8 x i16> %1
@@ -606,25 +606,25 @@ define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) {
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: psrlw $1, %xmm0
; SSE-NEXT: paddw %xmm1, %xmm0
-; SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_nonuniform3:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_nonuniform3:
; XOP: # %bb.0:
-; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
%1 = udiv <8 x i16> %x, <i16 7, i16 23, i16 25, i16 27, i16 31, i16 47, i16 63, i16 127>
ret <8 x i16> %1
@@ -638,11 +638,11 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: psrlw $7, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
@@ -652,11 +652,11 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm2, %xmm2
; SSE41-NEXT: psrlw $7, %xmm2
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
@@ -665,11 +665,11 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; AVX-LABEL: combine_vec_udiv_nonuniform4:
; AVX: # %bb.0:
; AVX-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX-NEXT: vpackuswb %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
@@ -677,7 +677,7 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; XOP-LABEL: combine_vec_udiv_nonuniform4:
; XOP: # %bb.0:
; XOP-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; XOP-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; XOP-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpperm {{.*#+}} xmm1 = xmm1[1,3,5,7,9,11,13,15],xmm2[1,3,5,7,9,11,13,15]
; XOP-NEXT: movl $249, %eax
@@ -698,12 +698,12 @@ define <8 x i16> @pr38477(<8 x i16> %a0) {
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,65535,65535,65535,65535,65535]
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psubw %xmm1, %xmm0
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: paddw %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535,65535,65535,0,65535]
; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm0, %xmm3
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm3, %xmm2
; SSE2-NEXT: por %xmm2, %xmm0
@@ -715,7 +715,7 @@ define <8 x i16> @pr38477(<8 x i16> %a0) {
; SSE41-NEXT: pmulhuw %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psubw %xmm2, %xmm1
-; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: paddw %xmm2, %xmm1
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <u,1024,1024,16,4,1024,u,4096>
; SSE41-NEXT: pmulhuw %xmm1, %xmm2
@@ -726,22 +726,22 @@ define <8 x i16> @pr38477(<8 x i16> %a0) {
;
; AVX-LABEL: pr38477:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm2
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm2, %xmm2
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vpaddw %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm2
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4,5],xmm1[6],xmm2[7]
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; AVX-NEXT: retq
;
; XOP-LABEL: pr38477:
; XOP: # %bb.0:
-; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm2, %xmm2
+; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-NEXT: vpaddw %xmm1, %xmm2, %xmm1
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm1, %xmm1
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; XOP-NEXT: retq
%1 = udiv <8 x i16> %a0, <i16 1, i16 119, i16 73, i16 -111, i16 -3, i16 118, i16 32, i16 31>
diff --git a/llvm/test/CodeGen/X86/combine-umax.ll b/llvm/test/CodeGen/X86/combine-umax.ll
index 3c644a52e88af..16a177cf0c988 100644
--- a/llvm/test/CodeGen/X86/combine-umax.ll
+++ b/llvm/test/CodeGen/X86/combine-umax.ll
@@ -10,28 +10,28 @@
define <8 x i16> @test_v8i16_nosignbit(<8 x i16> %a, <8 x i16> %b) {
; SSE2-LABEL: test_v8i16_nosignbit:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pminsw %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: test_v8i16_nosignbit:
; SSE41: # %bb.0:
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: psrlw $1, %xmm1
; SSE41-NEXT: pminuw %xmm1, %xmm0
; SSE41-NEXT: retq
;
; SSE42-LABEL: test_v8i16_nosignbit:
; SSE42: # %bb.0:
-; SSE42-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE42-NEXT: psrlw $1, %xmm1
; SSE42-NEXT: pminuw %xmm1, %xmm0
; SSE42-NEXT: retq
;
; AVX-LABEL: test_v8i16_nosignbit:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1
; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/combine-umin.ll b/llvm/test/CodeGen/X86/combine-umin.ll
index 1be72ad667993..6399b6b148ac0 100644
--- a/llvm/test/CodeGen/X86/combine-umin.ll
+++ b/llvm/test/CodeGen/X86/combine-umin.ll
@@ -27,28 +27,28 @@ declare i8 @llvm.umin.i8(i8, i8)
define <8 x i16> @test_v8i16_nosignbit(<8 x i16> %a, <8 x i16> %b) {
; SSE2-LABEL: test_v8i16_nosignbit:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pmaxsw %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: test_v8i16_nosignbit:
; SSE41: # %bb.0:
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: psrlw $1, %xmm1
; SSE41-NEXT: pmaxuw %xmm1, %xmm0
; SSE41-NEXT: retq
;
; SSE42-LABEL: test_v8i16_nosignbit:
; SSE42: # %bb.0:
-; SSE42-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE42-NEXT: psrlw $1, %xmm1
; SSE42-NEXT: pmaxuw %xmm1, %xmm0
; SSE42-NEXT: retq
;
; AVX-LABEL: test_v8i16_nosignbit:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1
; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/combine-urem.ll b/llvm/test/CodeGen/X86/combine-urem.ll
index cd0b21d02969c..e0faa355f7914 100644
--- a/llvm/test/CodeGen/X86/combine-urem.ll
+++ b/llvm/test/CodeGen/X86/combine-urem.ll
@@ -72,12 +72,12 @@ define i32 @combine_urem_by_minsigned(i32 %x) {
define <4 x i32> @combine_vec_urem_by_minsigned(<4 x i32> %x) {
; SSE-LABEL: combine_vec_urem_by_minsigned:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: combine_vec_urem_by_minsigned:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_urem_by_minsigned:
@@ -141,12 +141,12 @@ define <4 x i32> @combine_vec_urem_dupe(<4 x i32> %x) {
define <4 x i32> @combine_vec_urem_by_pow2a(<4 x i32> %x) {
; SSE-LABEL: combine_vec_urem_by_pow2a:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: combine_vec_urem_by_pow2a:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_urem_by_pow2a:
@@ -161,12 +161,12 @@ define <4 x i32> @combine_vec_urem_by_pow2a(<4 x i32> %x) {
define <4 x i32> @combine_vec_urem_by_pow2b(<4 x i32> %x) {
; SSE-LABEL: combine_vec_urem_by_pow2b:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_urem_by_pow2b:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = urem <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
ret <4 x i32> %1
@@ -176,7 +176,7 @@ define <4 x i32> @combine_vec_urem_by_pow2c(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_urem_by_pow2c:
; SSE: # %bb.0:
; SSE-NEXT: pslld $23, %xmm1
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: cvttps2dq %xmm1, %xmm1
; SSE-NEXT: pcmpeqd %xmm2, %xmm2
; SSE-NEXT: paddd %xmm1, %xmm2
@@ -186,7 +186,7 @@ define <4 x i32> @combine_vec_urem_by_pow2c(<4 x i32> %x, <4 x i32> %y) {
; AVX1-LABEL: combine_vec_urem_by_pow2c:
; AVX1: # %bb.0:
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
-; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
@@ -268,7 +268,7 @@ define <4 x i32> @combine_vec_urem_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_urem_by_shl_pow2a:
; SSE: # %bb.0:
; SSE-NEXT: pslld $23, %xmm1
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: cvttps2dq %xmm1, %xmm1
; SSE-NEXT: pslld $2, %xmm1
; SSE-NEXT: pcmpeqd %xmm2, %xmm2
@@ -279,7 +279,7 @@ define <4 x i32> @combine_vec_urem_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
; AVX1-LABEL: combine_vec_urem_by_shl_pow2a:
; AVX1: # %bb.0:
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
-; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
; AVX1-NEXT: vpslld $2, %xmm1, %xmm1
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
@@ -304,9 +304,9 @@ define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_urem_by_shl_pow2b:
; SSE: # %bb.0:
; SSE-NEXT: pslld $23, %xmm1
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: cvttps2dq %xmm1, %xmm1
-; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: pcmpeqd %xmm2, %xmm2
; SSE-NEXT: paddd %xmm1, %xmm2
; SSE-NEXT: pand %xmm2, %xmm0
@@ -315,9 +315,9 @@ define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
; AVX1-LABEL: combine_vec_urem_by_shl_pow2b:
; AVX1: # %bb.0:
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
-; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll b/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
index a6d7d9fac36a4..88b18199606e6 100644
--- a/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
+++ b/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
@@ -16,7 +16,7 @@ define void @TestvMeth(i32 %0, i64 %1) gc "statepoint-example" !prof !1 {
; CHECK-NEXT: movl $10, %esi
; CHECK-NEXT: movl $10, %edx
; CHECK-NEXT: movl $400, %ecx # imm = 0x190
-; CHECK-NEXT: callq newarray
+; CHECK-NEXT: callq newarray at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: addss (%rax), %xmm0
diff --git a/llvm/test/CodeGen/X86/concat-cast.ll b/llvm/test/CodeGen/X86/concat-cast.ll
index 456c1867cba21..ccd61af7bef59 100644
--- a/llvm/test/CodeGen/X86/concat-cast.ll
+++ b/llvm/test/CodeGen/X86/concat-cast.ll
@@ -30,10 +30,10 @@ define <4 x float> @uitofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE2-NEXT: pand %xmm0, %xmm1
-; SSE2-NEXT: por {{.*}}(%rip), %xmm1
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrld $16, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
-; SSE2-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -44,7 +44,7 @@ define <4 x float> @uitofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
; SSE4-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
; SSE4-NEXT: psrld $16, %xmm0
; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; SSE4-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE4-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: addps %xmm1, %xmm0
; SSE4-NEXT: retq
;
@@ -54,7 +54,7 @@ define <4 x float> @uitofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; AVX1-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/consecutive-load-shuffle.ll b/llvm/test/CodeGen/X86/consecutive-load-shuffle.ll
index 69739b98d2240..743e39da1f31d 100644
--- a/llvm/test/CodeGen/X86/consecutive-load-shuffle.ll
+++ b/llvm/test/CodeGen/X86/consecutive-load-shuffle.ll
@@ -11,8 +11,8 @@
define void @foo2() {
; CHECK-LABEL: foo2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: movaps f(%rip), %xmm0
+; CHECK-NEXT: movaps %xmm0, ms(%rip)
; CHECK-NEXT: retq
entry:
%0 = load <2 x float>, <2 x float>* bitcast (float* getelementptr inbounds ([4 x float], [4 x float]* @f, i64 0, i64 2) to <2 x float>*), align 8
diff --git a/llvm/test/CodeGen/X86/copy-eflags.ll b/llvm/test/CodeGen/X86/copy-eflags.ll
index 5a232a92ada10..4d382b24a2a5b 100644
--- a/llvm/test/CodeGen/X86/copy-eflags.ll
+++ b/llvm/test/CodeGen/X86/copy-eflags.ll
@@ -44,16 +44,16 @@ define dso_local i32 @test1() nounwind {
; X64-LABEL: test1:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: movb {{.*}}(%rip), %cl
+; X64-NEXT: movb b(%rip), %cl
; X64-NEXT: leal 1(%rcx), %eax
-; X64-NEXT: movb %al, {{.*}}(%rip)
-; X64-NEXT: incl {{.*}}(%rip)
+; X64-NEXT: movb %al, b(%rip)
+; X64-NEXT: incl c(%rip)
; X64-NEXT: sete %dl
-; X64-NEXT: movb {{.*}}(%rip), %sil
+; X64-NEXT: movb a(%rip), %sil
; X64-NEXT: leal 1(%rsi), %edi
; X64-NEXT: cmpb %cl, %sil
-; X64-NEXT: sete {{.*}}(%rip)
-; X64-NEXT: movb %dil, {{.*}}(%rip)
+; X64-NEXT: sete d(%rip)
+; X64-NEXT: movb %dil, a(%rip)
; X64-NEXT: testb %dl, %dl
; X64-NEXT: jne .LBB0_2
; X64-NEXT: # %bb.1: # %if.then
@@ -167,8 +167,8 @@ define dso_local void @test_tail_call(i32* %ptr) nounwind optsize {
; X64: # %bb.0: # %entry
; X64-NEXT: incl (%rdi)
; X64-NEXT: setne %al
-; X64-NEXT: incb {{.*}}(%rip)
-; X64-NEXT: sete {{.*}}(%rip)
+; X64-NEXT: incb a(%rip)
+; X64-NEXT: sete d(%rip)
; X64-NEXT: testb %al, %al
; X64-NEXT: jne external_b # TAILCALL
; X64-NEXT: # %bb.1: # %then
diff --git a/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll b/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll
index dd7d4a84a18a0..0052359eedb50 100644
--- a/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll
+++ b/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll
@@ -13,7 +13,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
define double @mag_pos0_double(double %x) nounwind {
; CHECK-LABEL: mag_pos0_double:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call double @copysign(double 0.0, double %x)
ret double %y
@@ -25,7 +25,7 @@ define double @mag_pos0_double(double %x) nounwind {
define double @mag_neg0_double(double %x) nounwind {
; CHECK-LABEL: mag_neg0_double:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call double @copysign(double -0.0, double %x)
ret double %y
@@ -40,8 +40,8 @@ define double @mag_neg0_double(double %x) nounwind {
define double @mag_pos1_double(double %x) nounwind {
; CHECK-LABEL: mag_pos1_double:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call double @copysign(double 1.0, double %x)
ret double %y
@@ -57,8 +57,8 @@ define double @mag_pos1_double(double %x) nounwind {
define double @mag_neg1_double(double %x) nounwind {
; CHECK-LABEL: mag_neg1_double:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call double @copysign(double -1.0, double %x)
ret double %y
@@ -73,7 +73,7 @@ define double @mag_neg1_double(double %x) nounwind {
define float @mag_pos0_float(float %x) nounwind {
; CHECK-LABEL: mag_pos0_float:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call float @copysignf(float 0.0, float %x)
ret float %y
@@ -85,7 +85,7 @@ define float @mag_pos0_float(float %x) nounwind {
define float @mag_neg0_float(float %x) nounwind {
; CHECK-LABEL: mag_neg0_float:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call float @copysignf(float -0.0, float %x)
ret float %y
@@ -102,8 +102,8 @@ define float @mag_neg0_float(float %x) nounwind {
define float @mag_pos1_float(float %x) nounwind {
; CHECK-LABEL: mag_pos1_float:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call float @copysignf(float 1.0, float %x)
ret float %y
@@ -123,8 +123,8 @@ define float @mag_pos1_float(float %x) nounwind {
define float @mag_neg1_float(float %x) nounwind {
; CHECK-LABEL: mag_neg1_float:
; CHECK: ## %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = call float @copysignf(float -1.0, float %x)
ret float %y
diff --git a/llvm/test/CodeGen/X86/critical-anti-dep-breaker.ll b/llvm/test/CodeGen/X86/critical-anti-dep-breaker.ll
index 6daee0ce4f8d6..c91513dc11127 100644
--- a/llvm/test/CodeGen/X86/critical-anti-dep-breaker.ll
+++ b/llvm/test/CodeGen/X86/critical-anti-dep-breaker.ll
@@ -22,8 +22,8 @@ define i32 @Part_Create(i64* %Anchor, i32 %TypeNum, i32 %F, i32 %Z, i32* %Status
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %rbp, -16
-; CHECK-NEXT: movq NullToken@{{.*}}(%rip), %rax
-; CHECK-NEXT: movq PartClass@{{.*}}(%rip), %r10
+; CHECK-NEXT: movq NullToken at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movq PartClass at GOTPCREL(%rip), %r10
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movq %rdi, %rbx
diff --git a/llvm/test/CodeGen/X86/csr-split.ll b/llvm/test/CodeGen/X86/csr-split.ll
index ebea77e955d81..1da965fa9da2d 100644
--- a/llvm/test/CodeGen/X86/csr-split.ll
+++ b/llvm/test/CodeGen/X86/csr-split.ll
@@ -12,7 +12,7 @@ define dso_local signext i32 @test1(i32* %b) local_unnamed_addr {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: movslq {{.*}}(%rip), %rax
+; CHECK-NEXT: movslq a(%rip), %rax
; CHECK-NEXT: cmpq %rdi, %rax
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.end
@@ -76,7 +76,7 @@ define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
; CHECK-NEXT: je .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: movslq {{.*}}(%rip), %rax
+; CHECK-NEXT: movslq a(%rip), %rax
; CHECK-NEXT: cmpq %rdi, %rax
; CHECK-NEXT: je .LBB1_3
; CHECK-NEXT: .LBB1_2: # %return
diff --git a/llvm/test/CodeGen/X86/cvt16.ll b/llvm/test/CodeGen/X86/cvt16.ll
index 64be9aad49be5..035e3323478f2 100644
--- a/llvm/test/CodeGen/X86/cvt16.ll
+++ b/llvm/test/CodeGen/X86/cvt16.ll
@@ -28,7 +28,7 @@ define void @test1(float %src, i16* %dest) {
; LIBCALL-NEXT: .cfi_def_cfa_offset 16
; LIBCALL-NEXT: .cfi_offset %rbx, -16
; LIBCALL-NEXT: movq %rdi, %rbx
-; LIBCALL-NEXT: callq __gnu_f2h_ieee
+; LIBCALL-NEXT: callq __gnu_f2h_ieee at PLT
; LIBCALL-NEXT: movw %ax, (%rbx)
; LIBCALL-NEXT: popq %rbx
; LIBCALL-NEXT: .cfi_def_cfa_offset 8
@@ -46,7 +46,7 @@ define void @test1(float %src, i16* %dest) {
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 16
; SOFTFLOAT-NEXT: .cfi_offset %rbx, -16
; SOFTFLOAT-NEXT: movq %rsi, %rbx
-; SOFTFLOAT-NEXT: callq __gnu_f2h_ieee
+; SOFTFLOAT-NEXT: callq __gnu_f2h_ieee at PLT
; SOFTFLOAT-NEXT: movw %ax, (%rbx)
; SOFTFLOAT-NEXT: popq %rbx
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 8
@@ -74,7 +74,7 @@ define float @test2(i16* nocapture %src) {
; SOFTFLOAT-NEXT: pushq %rax
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 16
; SOFTFLOAT-NEXT: movzwl (%rdi), %edi
-; SOFTFLOAT-NEXT: callq __gnu_h2f_ieee
+; SOFTFLOAT-NEXT: callq __gnu_h2f_ieee at PLT
; SOFTFLOAT-NEXT: popq %rcx
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 8
; SOFTFLOAT-NEXT: retq
@@ -88,7 +88,7 @@ define float @test3(float %src) nounwind uwtable readnone {
; LIBCALL: # %bb.0:
; LIBCALL-NEXT: pushq %rax
; LIBCALL-NEXT: .cfi_def_cfa_offset 16
-; LIBCALL-NEXT: callq __gnu_f2h_ieee
+; LIBCALL-NEXT: callq __gnu_f2h_ieee at PLT
; LIBCALL-NEXT: movzwl %ax, %edi
; LIBCALL-NEXT: popq %rax
; LIBCALL-NEXT: .cfi_def_cfa_offset 8
@@ -104,9 +104,9 @@ define float @test3(float %src) nounwind uwtable readnone {
; SOFTFLOAT: # %bb.0:
; SOFTFLOAT-NEXT: pushq %rax
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 16
-; SOFTFLOAT-NEXT: callq __gnu_f2h_ieee
+; SOFTFLOAT-NEXT: callq __gnu_f2h_ieee at PLT
; SOFTFLOAT-NEXT: movzwl %ax, %edi
-; SOFTFLOAT-NEXT: callq __gnu_h2f_ieee
+; SOFTFLOAT-NEXT: callq __gnu_h2f_ieee at PLT
; SOFTFLOAT-NEXT: popq %rcx
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 8
; SOFTFLOAT-NEXT: retq
@@ -121,7 +121,7 @@ define double @test4(i16* nocapture %src) {
; LIBCALL-NEXT: pushq %rax
; LIBCALL-NEXT: .cfi_def_cfa_offset 16
; LIBCALL-NEXT: movzwl (%rdi), %edi
-; LIBCALL-NEXT: callq __gnu_h2f_ieee
+; LIBCALL-NEXT: callq __gnu_h2f_ieee at PLT
; LIBCALL-NEXT: cvtss2sd %xmm0, %xmm0
; LIBCALL-NEXT: popq %rax
; LIBCALL-NEXT: .cfi_def_cfa_offset 8
@@ -140,9 +140,9 @@ define double @test4(i16* nocapture %src) {
; SOFTFLOAT-NEXT: pushq %rax
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 16
; SOFTFLOAT-NEXT: movzwl (%rdi), %edi
-; SOFTFLOAT-NEXT: callq __gnu_h2f_ieee
+; SOFTFLOAT-NEXT: callq __gnu_h2f_ieee at PLT
; SOFTFLOAT-NEXT: movl %eax, %edi
-; SOFTFLOAT-NEXT: callq __extendsfdf2
+; SOFTFLOAT-NEXT: callq __extendsfdf2 at PLT
; SOFTFLOAT-NEXT: popq %rcx
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 8
; SOFTFLOAT-NEXT: retq
@@ -164,7 +164,7 @@ define i16 @test5(double %src) {
; SOFTFLOAT: # %bb.0:
; SOFTFLOAT-NEXT: pushq %rax
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 16
-; SOFTFLOAT-NEXT: callq __truncdfhf2
+; SOFTFLOAT-NEXT: callq __truncdfhf2 at PLT
; SOFTFLOAT-NEXT: popq %rcx
; SOFTFLOAT-NEXT: .cfi_def_cfa_offset 8
; SOFTFLOAT-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
index 45b6d020ce450..75439f8118607 100644
--- a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
+++ b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
@@ -22,6 +22,41 @@
; Test for PR30775
define void @_Z1nv() local_unnamed_addr {
; CHECK-LABEL: _Z1nv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq k at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movl 4(%rax), %r11d
+; CHECK-NEXT: movq c at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movswl (%rax), %r10d
+; CHECK-NEXT: movq b at GOTPCREL(%rip), %r8
+; CHECK-NEXT: movswl (%r8), %r9d
+; CHECK-NEXT: movq a at GOTPCREL(%rip), %rsi
+; CHECK-NEXT: movl (%rsi), %esi
+; CHECK-NEXT: movq l at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movl (%rax), %edi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shll $7, %eax
+; CHECK-NEXT: sarl $7, %eax
+; CHECK-NEXT: negl %eax
+; CHECK-NEXT: testl %esi, %esi
+; CHECK-NEXT: cmovel %esi, %eax
+; CHECK-NEXT: movzwl %r11w, %ecx
+; CHECK-NEXT: leal (%r10,%rcx,2), %ecx
+; CHECK-NEXT: addl %r9d, %ecx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: testl $33554431, %edi # imm = 0x1FFFFFF
+; CHECK-NEXT: sete %dl
+; CHECK-NEXT: orb %al, %dl
+; CHECK-NEXT: movzbl %dl, %eax
+; CHECK-NEXT: movq e at GOTPCREL(%rip), %rdx
+; CHECK-NEXT: movw %ax, (%rdx)
+; CHECK-NEXT: notl %ecx
+; CHECK-NEXT: shrl $31, %ecx
+; CHECK-NEXT: addl %r11d, %ecx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: sarl %cl, %esi
+; CHECK-NEXT: movw %si, (%r8)
+; CHECK-NEXT: retq
entry:
%bf.load = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.m, %struct.m* @k, i64 0, i32 0, i32 1) to i32*), align 4
%0 = load i16, i16* @c, align 2
@@ -60,6 +95,180 @@ entry:
; Test for PR31536
define void @_Z2x6v() local_unnamed_addr {
; CHECK-LABEL: _Z2x6v:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 56
+; CHECK-NEXT: .cfi_offset %rbx, -56
+; CHECK-NEXT: .cfi_offset %r12, -48
+; CHECK-NEXT: .cfi_offset %r13, -40
+; CHECK-NEXT: .cfi_offset %r14, -32
+; CHECK-NEXT: .cfi_offset %r15, -24
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq x1 at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movl (%rax), %ecx
+; CHECK-NEXT: andl $511, %ecx # imm = 0x1FF
+; CHECK-NEXT: leaq 1(%rcx), %r13
+; CHECK-NEXT: movq x4 at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movl %r13d, (%rax)
+; CHECK-NEXT: movq x3 at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movl (%rax), %edx
+; CHECK-NEXT: testl %edx, %edx
+; CHECK-NEXT: je .LBB1_18
+; CHECK-NEXT: # %bb.1: # %for.cond1thread-pre-split.lr.ph
+; CHECK-NEXT: movq x5 at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movq (%rax), %r12
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: notl %eax
+; CHECK-NEXT: leaq 8(,%rax,8), %r14
+; CHECK-NEXT: imulq %r13, %r14
+; CHECK-NEXT: addq %r12, %r14
+; CHECK-NEXT: movq x2 at GOTPCREL(%rip), %r15
+; CHECK-NEXT: movl (%r15), %eax
+; CHECK-NEXT: leal 8(,%rcx,8), %ecx
+; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: leaq 8(%r12), %rcx
+; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: leaq 32(%r12), %rbx
+; CHECK-NEXT: shlq $3, %r13
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: movq x0 at GOTPCREL(%rip), %rcx
+; CHECK-NEXT: movq %r12, %rdi
+; CHECK-NEXT: jmp .LBB1_2
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB1_15: # %for.cond1.for.inc3_crit_edge
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: movl %eax, (%r15)
+; CHECK-NEXT: .LBB1_16: # %for.inc3
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: addq %r13, %rdi
+; CHECK-NEXT: incq %rsi
+; CHECK-NEXT: addq %r13, %rbx
+; CHECK-NEXT: incl %edx
+; CHECK-NEXT: je .LBB1_17
+; CHECK-NEXT: .LBB1_2: # %for.cond1thread-pre-split
+; CHECK-NEXT: # =>This Loop Header: Depth=1
+; CHECK-NEXT: # Child Loop BB1_12 Depth 2
+; CHECK-NEXT: # Child Loop BB1_14 Depth 2
+; CHECK-NEXT: testl %eax, %eax
+; CHECK-NEXT: jns .LBB1_16
+; CHECK-NEXT: # %bb.3: # %for.body2.preheader
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: movslq %eax, %r9
+; CHECK-NEXT: testq %r9, %r9
+; CHECK-NEXT: movq $-1, %rbp
+; CHECK-NEXT: cmovnsq %r9, %rbp
+; CHECK-NEXT: subq %r9, %rbp
+; CHECK-NEXT: incq %rbp
+; CHECK-NEXT: cmpq $4, %rbp
+; CHECK-NEXT: jb .LBB1_14
+; CHECK-NEXT: # %bb.4: # %min.iters.checked
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: movq %rbp, %r8
+; CHECK-NEXT: andq $-4, %r8
+; CHECK-NEXT: je .LBB1_14
+; CHECK-NEXT: # %bb.5: # %vector.memcheck
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Reload
+; CHECK-NEXT: imulq %rsi, %r10
+; CHECK-NEXT: leaq (%r12,%r10), %rax
+; CHECK-NEXT: leaq (%rax,%r9,8), %rax
+; CHECK-NEXT: testq %r9, %r9
+; CHECK-NEXT: movq $-1, %r11
+; CHECK-NEXT: cmovnsq %r9, %r11
+; CHECK-NEXT: cmpq %rcx, %rax
+; CHECK-NEXT: jae .LBB1_7
+; CHECK-NEXT: # %bb.6: # %vector.memcheck
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Folded Reload
+; CHECK-NEXT: leaq (%r10,%r11,8), %rax
+; CHECK-NEXT: cmpq %rcx, %rax
+; CHECK-NEXT: ja .LBB1_14
+; CHECK-NEXT: .LBB1_7: # %vector.body.preheader
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: leaq -4(%r8), %rax
+; CHECK-NEXT: movq %rax, %r10
+; CHECK-NEXT: shrq $2, %r10
+; CHECK-NEXT: btl $2, %eax
+; CHECK-NEXT: jb .LBB1_8
+; CHECK-NEXT: # %bb.9: # %vector.body.prol.preheader
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; CHECK-NEXT: movdqu %xmm0, (%rdi,%r9,8)
+; CHECK-NEXT: movdqu %xmm0, 16(%rdi,%r9,8)
+; CHECK-NEXT: movl $4, %r11d
+; CHECK-NEXT: testq %r10, %r10
+; CHECK-NEXT: jne .LBB1_11
+; CHECK-NEXT: jmp .LBB1_13
+; CHECK-NEXT: .LBB1_8: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: testq %r10, %r10
+; CHECK-NEXT: je .LBB1_13
+; CHECK-NEXT: .LBB1_11: # %vector.body.preheader.new
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; CHECK-NEXT: movq %r11, %rax
+; CHECK-NEXT: subq %r8, %rax
+; CHECK-NEXT: addq %r9, %r11
+; CHECK-NEXT: leaq (%rbx,%r11,8), %r11
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB1_12: # %vector.body
+; CHECK-NEXT: # Parent Loop BB1_2 Depth=1
+; CHECK-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-NEXT: movdqu %xmm0, -32(%r11)
+; CHECK-NEXT: movdqu %xmm0, -16(%r11)
+; CHECK-NEXT: movdqu %xmm0, (%r11)
+; CHECK-NEXT: movdqu %xmm0, 16(%r11)
+; CHECK-NEXT: addq $64, %r11
+; CHECK-NEXT: addq $8, %rax
+; CHECK-NEXT: jne .LBB1_12
+; CHECK-NEXT: .LBB1_13: # %middle.block
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: addq %r8, %r9
+; CHECK-NEXT: cmpq %r8, %rbp
+; CHECK-NEXT: movq %r9, %rax
+; CHECK-NEXT: je .LBB1_15
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB1_14: # %for.body2
+; CHECK-NEXT: # Parent Loop BB1_2 Depth=1
+; CHECK-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-NEXT: movq (%rcx), %rax
+; CHECK-NEXT: movq %rax, (%rdi,%r9,8)
+; CHECK-NEXT: leaq 1(%r9), %rax
+; CHECK-NEXT: cmpq $-1, %r9
+; CHECK-NEXT: movq %rax, %r9
+; CHECK-NEXT: jl .LBB1_14
+; CHECK-NEXT: jmp .LBB1_15
+; CHECK-NEXT: .LBB1_17: # %for.cond.for.end5_crit_edge
+; CHECK-NEXT: movq x5 at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movq %r14, (%rax)
+; CHECK-NEXT: movq x3 at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movl $0, (%rax)
+; CHECK-NEXT: .LBB1_18: # %for.end5
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
entry:
%0 = load i32, i32* @x1, align 4
%and = and i32 %0, 511
diff --git a/llvm/test/CodeGen/X86/divmod128.ll b/llvm/test/CodeGen/X86/divmod128.ll
index 6004d99ddab49..00373be01ad2d 100644
--- a/llvm/test/CodeGen/X86/divmod128.ll
+++ b/llvm/test/CodeGen/X86/divmod128.ll
@@ -10,7 +10,7 @@ define i64 @mod128(i128 %x) nounwind {
; X86-64-NEXT: pushq %rax
; X86-64-NEXT: movl $3, %edx
; X86-64-NEXT: xorl %ecx, %ecx
-; X86-64-NEXT: callq __modti3
+; X86-64-NEXT: callq __modti3 at PLT
; X86-64-NEXT: popq %rcx
; X86-64-NEXT: retq
;
@@ -40,7 +40,7 @@ define i64 @div128(i128 %x) nounwind {
; X86-64-NEXT: pushq %rax
; X86-64-NEXT: movl $3, %edx
; X86-64-NEXT: xorl %ecx, %ecx
-; X86-64-NEXT: callq __divti3
+; X86-64-NEXT: callq __divti3 at PLT
; X86-64-NEXT: popq %rcx
; X86-64-NEXT: retq
;
@@ -70,7 +70,7 @@ define i64 @umod128(i128 %x) nounwind {
; X86-64-NEXT: pushq %rax
; X86-64-NEXT: movl $3, %edx
; X86-64-NEXT: xorl %ecx, %ecx
-; X86-64-NEXT: callq __umodti3
+; X86-64-NEXT: callq __umodti3 at PLT
; X86-64-NEXT: popq %rcx
; X86-64-NEXT: retq
;
@@ -100,7 +100,7 @@ define i64 @udiv128(i128 %x) nounwind {
; X86-64-NEXT: pushq %rax
; X86-64-NEXT: movl $3, %edx
; X86-64-NEXT: xorl %ecx, %ecx
-; X86-64-NEXT: callq __udivti3
+; X86-64-NEXT: callq __udivti3 at PLT
; X86-64-NEXT: popq %rcx
; X86-64-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/divrem8_ext.ll b/llvm/test/CodeGen/X86/divrem8_ext.ll
index a6644b389c984..3db71f8be606e 100644
--- a/llvm/test/CodeGen/X86/divrem8_ext.ll
+++ b/llvm/test/CodeGen/X86/divrem8_ext.ll
@@ -17,7 +17,7 @@ define zeroext i8 @test_udivrem_zext_ah(i8 %x, i8 %y) {
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %ecx
-; X64-NEXT: movb %al, {{.*}}(%rip)
+; X64-NEXT: movb %al, z(%rip)
; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%div = udiv i8 %x, %y
@@ -105,7 +105,7 @@ define signext i8 @test_sdivrem_sext_ah(i8 %x, i8 %y) {
; X64-NEXT: movsbl %dil, %eax
; X64-NEXT: idivb %sil
; X64-NEXT: movsbl %ah, %ecx
-; X64-NEXT: movb %al, {{.*}}(%rip)
+; X64-NEXT: movb %al, z(%rip)
; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%div = sdiv i8 %x, %y
diff --git a/llvm/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll b/llvm/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll
index 9244ab0f860cf..afffc980c61a5 100644
--- a/llvm/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll
@@ -9,7 +9,7 @@ define i8* @test_memcpy1_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -27,7 +27,7 @@ define i8* @test_memcpy2_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_2
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_2 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -45,7 +45,7 @@ define i8* @test_memcpy4_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -63,7 +63,7 @@ define i8* @test_memcpy8(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_8
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_8 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -81,7 +81,7 @@ define i8* @test_memcpy16_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_16
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_16 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -100,7 +100,7 @@ define void @test_memcpy_args(i8** %Storage) {
; CHECK-NEXT: movq 8(%rdi), %rsi
; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -123,7 +123,7 @@ define i8* @test_memmove1_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -141,7 +141,7 @@ define i8* @test_memmove2_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_2
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_2 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -159,7 +159,7 @@ define i8* @test_memmove4_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -177,7 +177,7 @@ define i8* @test_memmove8_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_8
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_8 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -195,7 +195,7 @@ define i8* @test_memmove16_generic(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_16
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_16 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -214,7 +214,7 @@ define void @test_memmove_args(i8** %Storage) {
; CHECK-NEXT: movq 8(%rdi), %rsi
; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -237,7 +237,7 @@ define i8* @test_memset1_generic(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -255,7 +255,7 @@ define i8* @test_memset2_generic(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_2
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_2 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -273,7 +273,7 @@ define i8* @test_memset4_generic(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -291,7 +291,7 @@ define i8* @test_memset8_generic(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_8
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_8 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -309,7 +309,7 @@ define i8* @test_memset16_generic(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -327,7 +327,7 @@ define void @test_memset_args(i8** %Storage, i8* %V) {
; CHECK-NEXT: movq (%rdi), %rdi
; CHECK-NEXT: movzbl (%rsi), %esi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -353,7 +353,7 @@ define i8* @test_memcpy1_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -371,7 +371,7 @@ define i8* @test_memcpy1_64_align4(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -388,7 +388,7 @@ define i8* @test_memcpy1_64_align8(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -406,7 +406,7 @@ define i8* @test_memcpy1_64_align16(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -425,7 +425,7 @@ define i8* @test_memcpy1_64_
diff _aligns(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -442,7 +442,7 @@ define i8* @test_memcpy2_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_2
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_2 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -459,7 +459,7 @@ define i8* @test_memcpy4_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -476,7 +476,7 @@ define i8* @test_memcpy8_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_8
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_8 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -493,7 +493,7 @@ define i8* @test_memcpy16_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_16
+; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_16 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -512,7 +512,7 @@ define i8* @test_memmove1_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -530,7 +530,7 @@ define i8* @test_memmove1_64_align16(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -548,7 +548,7 @@ define i8* @test_memmove1_64_
diff _aligns(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -565,7 +565,7 @@ define i8* @test_memmove2_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_2
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_2 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -582,7 +582,7 @@ define i8* @test_memmove4_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -599,7 +599,7 @@ define i8* @test_memmove8_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_8
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_8 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -616,7 +616,7 @@ define i8* @test_memmove16_64(i8* %P, i8* %Q) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_16
+; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_16 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -636,7 +636,7 @@ define i8* @test_memset1_64(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -653,7 +653,7 @@ define i8* @test_memset1_64_align16(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -670,7 +670,7 @@ define i8* @test_memset2_64(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_2
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_2 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -690,7 +690,7 @@ define i8* @test_memset4_64(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -707,7 +707,7 @@ define i8* @test_memset4_64_align8(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -724,7 +724,7 @@ define i8* @test_memset4_64_align16(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -741,7 +741,7 @@ define i8* @test_memset4_64_align64(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -758,7 +758,7 @@ define i8* @test_memset4_4(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $4, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -775,7 +775,7 @@ define i8* @test_memset4_8(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $8, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -792,7 +792,7 @@ define i8* @test_memset4_8_align8(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $8, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -809,7 +809,7 @@ define i8* @test_memset4_12(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $12, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -826,7 +826,7 @@ define i8* @test_memset4_16(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $16, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -843,7 +843,7 @@ define i8* @test_memset4_16_align16(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $16, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -860,7 +860,7 @@ define i8* @test_memset4_60(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $60, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -877,7 +877,7 @@ define i8* @test_memset8_64(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_8
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_8 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -894,7 +894,7 @@ define i8* @test_memset16_64(i8* %P, i8 %V) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -912,7 +912,7 @@ define i8* @test_memset16_64_zero(i8* %P) {
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: movl $64, %edx
-; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16
+; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16 at PLT
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
index e7fa68fee33a8..0dbcc7fa22c7c 100644
--- a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
@@ -4,51 +4,55 @@
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+enqcmd | FileCheck %s --check-prefix=X32
define i8 @test_enqcmd(i8* %dst, i8* %src) {
-entry:
; X64-LABEL: test_enqcmd:
; X64: # %bb.0: # %entry
; X64-NEXT: enqcmd (%rsi), %rdi
; X64-NEXT: sete %al
; X64-NEXT: retq
-
+;
; X86-LABEL: test_enqcmd:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl {{[0-9+]}}(%esp), %eax
-; X86-NEXT: movl {{[0-9+]}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: enqcmd (%eax), %ecx
; X86-NEXT: sete %al
; X86-NEXT: retl
-
+;
; X32-LABEL: test_enqcmd:
; X32: # %bb.0: # %entry
-; X32: enqcmd (%esi), %edi
+; X32-NEXT: enqcmd (%esi), %edi
; X32-NEXT: sete %al
; X32-NEXT: retq
+entry:
+
+
%0 = call i8 @llvm.x86.enqcmd(i8* %dst, i8* %src)
ret i8 %0
}
define i8 @test_enqcmds(i8* %dst, i8* %src) {
-entry:
; X64-LABEL: test_enqcmds:
; X64: # %bb.0: # %entry
; X64-NEXT: enqcmds (%rsi), %rdi
; X64-NEXT: sete %al
; X64-NEXT: retq
-
+;
; X86-LABEL: test_enqcmds:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl {{[0-9+]}}(%esp), %eax
-; X86-NEXT: movl {{[0-9+]}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: enqcmds (%eax), %ecx
; X86-NEXT: sete %al
; X86-NEXT: retl
-
+;
; X32-LABEL: test_enqcmds:
; X32: # %bb.0: # %entry
-; X32: enqcmds (%esi), %edi
+; X32-NEXT: enqcmds (%esi), %edi
; X32-NEXT: sete %al
; X32-NEXT: retq
+entry:
+
+
%0 = call i8 @llvm.x86.enqcmds(i8* %dst, i8* %src)
ret i8 %0
}
diff --git a/llvm/test/CodeGen/X86/exedepsfix-broadcast.ll b/llvm/test/CodeGen/X86/exedepsfix-broadcast.ll
index 83b1dbb7a8469..e57c95c2eddef 100644
--- a/llvm/test/CodeGen/X86/exedepsfix-broadcast.ll
+++ b/llvm/test/CodeGen/X86/exedepsfix-broadcast.ll
@@ -7,7 +7,7 @@
define <4 x float> @ExeDepsFix_broadcastss(<4 x float> %arg, <4 x float> %arg2) {
; CHECK-LABEL: ExeDepsFix_broadcastss:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %xmm2
+; CHECK-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
; CHECK-NEXT: vandps %xmm2, %xmm0, %xmm0
; CHECK-NEXT: vmaxps %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
@@ -22,7 +22,7 @@ define <4 x float> @ExeDepsFix_broadcastss(<4 x float> %arg, <4 x float> %arg2)
define <8 x float> @ExeDepsFix_broadcastss256(<8 x float> %arg, <8 x float> %arg2) {
; CHECK-LABEL: ExeDepsFix_broadcastss256:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %ymm2
+; CHECK-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
; CHECK-NEXT: vandps %ymm2, %ymm0, %ymm0
; CHECK-NEXT: vmaxps %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
@@ -74,7 +74,7 @@ define <8 x float> @ExeDepsFix_broadcastss256_inreg(<8 x float> %arg, <8 x float
define <2 x double> @ExeDepsFix_broadcastsd(<2 x double> %arg, <2 x double> %arg2) {
; CHECK-LABEL: ExeDepsFix_broadcastsd:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%bitcast = bitcast <2 x double> %arg to <2 x i64>
@@ -88,7 +88,7 @@ define <2 x double> @ExeDepsFix_broadcastsd(<2 x double> %arg, <2 x double> %arg
define <4 x double> @ExeDepsFix_broadcastsd256(<4 x double> %arg, <4 x double> %arg2) {
; CHECK-LABEL: ExeDepsFix_broadcastsd256:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastsd {{.*}}(%rip), %ymm2
+; CHECK-NEXT: vbroadcastsd {{.*#+}} ymm2 = [2147483647,2147483647,2147483647,2147483647]
; CHECK-NEXT: vandpd %ymm2, %ymm0, %ymm0
; CHECK-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/extract-fp.ll b/llvm/test/CodeGen/X86/extract-fp.ll
index 317f3188c2dfc..1ef32156a348b 100644
--- a/llvm/test/CodeGen/X86/extract-fp.ll
+++ b/llvm/test/CodeGen/X86/extract-fp.ll
@@ -5,7 +5,7 @@ define float @ext_fadd_v4f32(<4 x float> %x) {
; CHECK-LABEL: ext_fadd_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: addss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%bo = fadd <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 42.0>
%ext = extractelement <4 x float> %bo, i32 2
@@ -29,7 +29,7 @@ define float @ext_fmul_v4f32(<4 x float> %x) {
; CHECK-LABEL: ext_fmul_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%bo = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 42.0>
%ext = extractelement <4 x float> %bo, i32 3
@@ -87,7 +87,7 @@ define float @ext_maxnum_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: ext_maxnum_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: maxss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: maxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%v = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> <float 0.0, float 1.0, float 2.0, float 3.0>)
%r = extractelement <4 x float> %v, i32 2
@@ -98,7 +98,7 @@ define double @ext_minnum_v2f64(<2 x double> %x) nounwind {
; CHECK-LABEL: ext_minnum_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: minsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%v = call <2 x double> @llvm.minnum.v2f64(<2 x double> <double 0.0, double 1.0>, <2 x double> %x)
%r = extractelement <2 x double> %v, i32 1
diff --git a/llvm/test/CodeGen/X86/extractelement-fp.ll b/llvm/test/CodeGen/X86/extractelement-fp.ll
index 89b3f4f7c0ec8..8ff73d5a7ffa8 100644
--- a/llvm/test/CodeGen/X86/extractelement-fp.ll
+++ b/llvm/test/CodeGen/X86/extractelement-fp.ll
@@ -319,7 +319,7 @@ define void @extsetcc(<4 x float> %x) {
define <3 x double> @extvselectsetcc_crash(<2 x double> %x) {
; X64-LABEL: extvselectsetcc_crash:
; X64: # %bb.0:
-; X64-NEXT: vcmpeqpd {{.*}}(%rip), %xmm0, %xmm1
+; X64-NEXT: vcmpeqpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X64-NEXT: vandpd %xmm2, %xmm1, %xmm1
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -328,7 +328,7 @@ define <3 x double> @extvselectsetcc_crash(<2 x double> %x) {
;
; X86-LABEL: extvselectsetcc_crash:
; X86: # %bb.0:
-; X86-NEXT: vcmpeqpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
+; X86-NEXT: vcmpeqpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X86-NEXT: vandpd %xmm2, %xmm1, %xmm1
; X86-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -546,7 +546,7 @@ define float @fabs_v4f32(<4 x float> %x) nounwind {
define double @fabs_v4f64(<4 x double> %x) nounwind {
; X64-LABEL: fabs_v4f64:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
;
@@ -556,7 +556,7 @@ define double @fabs_v4f64(<4 x double> %x) nounwind {
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
-; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vmovlps %xmm0, (%esp)
; X86-NEXT: fldl (%esp)
; X86-NEXT: movl %ebp, %esp
@@ -818,8 +818,8 @@ define float @copysign_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
define double @copysign_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; X64-LABEL: copysign_v4f64:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
-; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vorps %xmm1, %xmm0, %xmm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
@@ -830,8 +830,8 @@ define double @copysign_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
-; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
-; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vorps %xmm1, %xmm0, %xmm0
; X86-NEXT: vmovlps %xmm0, (%esp)
; X86-NEXT: fldl (%esp)
@@ -1096,7 +1096,7 @@ define float @round_v4f32(<4 x float> %x) nounwind {
define double @round_v4f64(<4 x double> %x) nounwind {
; X64-LABEL: round_v4f64:
; X64: # %bb.0:
-; X64-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm1
+; X64-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-NEXT: vmovddup {{.*#+}} xmm2 = [4.9999999999999994E-1,4.9999999999999994E-1]
; X64-NEXT: # xmm2 = mem[0,0]
; X64-NEXT: vorpd %xmm1, %xmm2, %xmm1
@@ -1111,7 +1111,7 @@ define double @round_v4f64(<4 x double> %x) nounwind {
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
-; X86-NEXT: vandpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
+; X86-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-NEXT: vmovddup {{.*#+}} xmm2 = [4.9999999999999994E-1,4.9999999999999994E-1]
; X86-NEXT: # xmm2 = mem[0,0]
; X86-NEXT: vorpd %xmm1, %xmm2, %xmm1
diff --git a/llvm/test/CodeGen/X86/fabs.ll b/llvm/test/CodeGen/X86/fabs.ll
index 02e86e15bdc5f..82c82ac3e917e 100644
--- a/llvm/test/CodeGen/X86/fabs.ll
+++ b/llvm/test/CodeGen/X86/fabs.ll
@@ -21,7 +21,7 @@ define float @test1(float %X) {
;
; X64-LABEL: test1:
; X64: # %bb.0:
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%Y = call float @fabsf(float %X) readnone
ret float %Y
diff --git a/llvm/test/CodeGen/X86/fadd-combines.ll b/llvm/test/CodeGen/X86/fadd-combines.ll
index 048e5c5d325e2..15512e997d14d 100644
--- a/llvm/test/CodeGen/X86/fadd-combines.ll
+++ b/llvm/test/CodeGen/X86/fadd-combines.ll
@@ -29,7 +29,7 @@ define <4 x float> @fadd_zero_4f32_undef(<4 x float> %x) {
define float @fadd_2const_f32(float %x) #0 {
; CHECK-LABEL: fadd_2const_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd float %x, 1.0
%z = fadd float %y, 2.0
@@ -43,7 +43,7 @@ define float @fadd_2const_f32(float %x) #0 {
define <4 x float> @fadd_2const_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_2const_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
%z = fadd <4 x float> %y, <float 4.0, float 3.0, float 2.0, float 1.0>
@@ -54,7 +54,7 @@ define <4 x float> @fadd_2const_4f32(<4 x float> %x) #0 {
define float @fadd_x_fmul_x_c_f32(float %x) #0 {
; CHECK-LABEL: fadd_x_fmul_x_c_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul float %x, 2.0
%z = fadd float %x, %y
@@ -68,7 +68,7 @@ define float @fadd_x_fmul_x_c_f32(float %x) #0 {
define <4 x float> @fadd_x_fmul_x_c_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_x_fmul_x_c_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
%z = fadd <4 x float> %x, %y
@@ -79,7 +79,7 @@ define <4 x float> @fadd_x_fmul_x_c_4f32(<4 x float> %x) #0 {
define float @fadd_fmul_x_c_x_f32(float %x) #0 {
; CHECK-LABEL: fadd_fmul_x_c_x_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul float %x, 2.0
%z = fadd float %y, %x
@@ -93,7 +93,7 @@ define float @fadd_fmul_x_c_x_f32(float %x) #0 {
define <4 x float> @fadd_fmul_x_c_x_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_fmul_x_c_x_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
%z = fadd <4 x float> %y, %x
@@ -104,7 +104,7 @@ define <4 x float> @fadd_fmul_x_c_x_4f32(<4 x float> %x) #0 {
define float @fadd_fadd_x_x_fmul_x_c_f32(float %x) #0 {
; CHECK-LABEL: fadd_fadd_x_x_fmul_x_c_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd float %x, %x
%z = fmul float %x, 2.0
@@ -119,7 +119,7 @@ define float @fadd_fadd_x_x_fmul_x_c_f32(float %x) #0 {
define <4 x float> @fadd_fadd_x_x_fmul_x_c_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_fadd_x_x_fmul_x_c_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd <4 x float> %x, %x
%z = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
@@ -131,7 +131,7 @@ define <4 x float> @fadd_fadd_x_x_fmul_x_c_4f32(<4 x float> %x) #0 {
define float @fadd_fmul_x_c_fadd_x_x_f32(float %x) #0 {
; CHECK-LABEL: fadd_fmul_x_c_fadd_x_x_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd float %x, %x
%z = fmul float %x, 2.0
@@ -146,7 +146,7 @@ define float @fadd_fmul_x_c_fadd_x_x_f32(float %x) #0 {
define <4 x float> @fadd_fmul_x_c_fadd_x_x_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_fmul_x_c_fadd_x_x_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd <4 x float> %x, %x
%z = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
@@ -158,7 +158,7 @@ define <4 x float> @fadd_fmul_x_c_fadd_x_x_4f32(<4 x float> %x) #0 {
define float @fadd_x_fadd_x_x_f32(float %x) #0 {
; CHECK-LABEL: fadd_x_fadd_x_x_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd float %x, %x
%z = fadd float %x, %y
@@ -172,7 +172,7 @@ define float @fadd_x_fadd_x_x_f32(float %x) #0 {
define <4 x float> @fadd_x_fadd_x_x_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_x_fadd_x_x_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd <4 x float> %x, %x
%z = fadd <4 x float> %x, %y
@@ -183,7 +183,7 @@ define <4 x float> @fadd_x_fadd_x_x_4f32(<4 x float> %x) #0 {
define float @fadd_fadd_x_x_x_f32(float %x) #0 {
; CHECK-LABEL: fadd_fadd_x_x_x_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd float %x, %x
%z = fadd float %y, %x
@@ -197,7 +197,7 @@ define float @fadd_fadd_x_x_x_f32(float %x) #0 {
define <4 x float> @fadd_fadd_x_x_x_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_fadd_x_x_x_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd <4 x float> %x, %x
%z = fadd <4 x float> %y, %x
@@ -208,7 +208,7 @@ define <4 x float> @fadd_fadd_x_x_x_4f32(<4 x float> %x) #0 {
define float @fadd_fadd_x_x_fadd_x_x_f32(float %x) #0 {
; CHECK-LABEL: fadd_fadd_x_x_fadd_x_x_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd float %x, %x
%z = fadd float %y, %y
@@ -222,7 +222,7 @@ define float @fadd_fadd_x_x_fadd_x_x_f32(float %x) #0 {
define <4 x float> @fadd_fadd_x_x_fadd_x_x_4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fadd_fadd_x_x_fadd_x_x_4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd <4 x float> %x, %x
%z = fadd <4 x float> %y, %y
@@ -238,7 +238,7 @@ define float @fadd_const_multiuse_attr(float %x) #0 {
; CHECK: # %bb.0:
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: addss %xmm0, %xmm1
-; CHECK-NEXT: addss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: retq
%a1 = fadd float %x, 42.0
diff --git a/llvm/test/CodeGen/X86/fast-isel-bc.ll b/llvm/test/CodeGen/X86/fast-isel-bc.ll
index 3287f992cd06e..0fbc9fab05681 100644
--- a/llvm/test/CodeGen/X86/fast-isel-bc.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-bc.ll
@@ -12,7 +12,7 @@ define void @func1() nounwind {
; X86-LABEL: func1:
; X86: ## %bb.0:
; X86-NEXT: subl $12, %esp
-; X86-NEXT: movq LCPI0_0, %mm0 ## mm0 = 0x200000000
+; X86-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}, %mm0 ## mm0 = 0x200000000
; X86-NEXT: calll _func2
; X86-NEXT: addl $12, %esp
; X86-NEXT: retl
@@ -20,7 +20,7 @@ define void @func1() nounwind {
; X64-LABEL: func1:
; X64: ## %bb.0:
; X64-NEXT: pushq %rax
-; X64-NEXT: movq {{.*}}(%rip), %mm0 ## mm0 = 0x200000000
+; X64-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %mm0 ## mm0 = 0x200000000
; X64-NEXT: movq2dq %mm0, %xmm0
; X64-NEXT: callq _func2
; X64-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/fast-isel-constpool.ll b/llvm/test/CodeGen/X86/fast-isel-constpool.ll
index a2ce3d58e43b9..5b6311db024ca 100644
--- a/llvm/test/CodeGen/X86/fast-isel-constpool.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-constpool.ll
@@ -22,7 +22,7 @@ define float @constpool_float(float %x) {
;
; LARGE-LABEL: constpool_float:
; LARGE: ## %bb.0:
-; LARGE-NEXT: movabsq $LCPI0_0, %rax
+; LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE-NEXT: addss (%rax), %xmm0
; LARGE-NEXT: retq
;
@@ -32,7 +32,7 @@ define float @constpool_float(float %x) {
; LARGE_PIC-NEXT: leaq .L0$pb(%rip), %rax
; LARGE_PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L0$pb, %rcx
; LARGE_PIC-NEXT: addq %rax, %rcx
-; LARGE_PIC-NEXT: movabsq $.LCPI0_0 at GOTOFF, %rax
+; LARGE_PIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
; LARGE_PIC-NEXT: addss (%rax,%rcx), %xmm0
; LARGE_PIC-NEXT: retq
;
@@ -44,7 +44,7 @@ define float @constpool_float(float %x) {
;
; LARGE_AVX-LABEL: constpool_float:
; LARGE_AVX: ## %bb.0:
-; LARGE_AVX-NEXT: movabsq $LCPI0_0, %rax
+; LARGE_AVX-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE_AVX-NEXT: vaddss (%rax), %xmm0, %xmm0
; LARGE_AVX-NEXT: retq
;
@@ -54,8 +54,8 @@ define float @constpool_float(float %x) {
; X86-LARGE-NEXT: .cfi_def_cfa_offset 8
; X86-LARGE-NEXT: movss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xf3,0x0f,0x10,0x44,0x24,0x08]
; X86-LARGE-NEXT: ## xmm0 = mem[0],zero,zero,zero
-; X86-LARGE-NEXT: addss LCPI0_0, %xmm0 ## encoding: [0xf3,0x0f,0x58,0x05,A,A,A,A]
-; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI0_0, kind: FK_Data_4
+; X86-LARGE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## encoding: [0xf3,0x0f,0x58,0x05,A,A,A,A]
+; X86-LARGE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-LARGE-NEXT: movss %xmm0, (%esp) ## encoding: [0xf3,0x0f,0x11,0x04,0x24]
; X86-LARGE-NEXT: flds (%esp) ## encoding: [0xd9,0x04,0x24]
; X86-LARGE-NEXT: popl %eax ## encoding: [0x58]
@@ -74,10 +74,20 @@ define double @constpool_double(double %x) nounwind {
;
; LARGE-LABEL: constpool_double:
; LARGE: ## %bb.0:
-; LARGE-NEXT: movabsq $LCPI1_0, %rax
+; LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE-NEXT: addsd (%rax), %xmm0
; LARGE-NEXT: retq
;
+; LARGE_PIC-LABEL: constpool_double:
+; LARGE_PIC: # %bb.0:
+; LARGE_PIC-NEXT: .L1$pb:
+; LARGE_PIC-NEXT: leaq .L1$pb(%rip), %rax
+; LARGE_PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L1$pb, %rcx
+; LARGE_PIC-NEXT: addq %rax, %rcx
+; LARGE_PIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
+; LARGE_PIC-NEXT: addsd (%rax,%rcx), %xmm0
+; LARGE_PIC-NEXT: retq
+;
; AVX-LABEL: constpool_double:
; AVX: ## %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
@@ -86,7 +96,7 @@ define double @constpool_double(double %x) nounwind {
;
; LARGE_AVX-LABEL: constpool_double:
; LARGE_AVX: ## %bb.0:
-; LARGE_AVX-NEXT: movabsq $LCPI1_0, %rax
+; LARGE_AVX-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE_AVX-NEXT: vaddsd (%rax), %xmm0, %xmm0
; LARGE_AVX-NEXT: retq
;
@@ -95,8 +105,8 @@ define double @constpool_double(double %x) nounwind {
; X86-LARGE-NEXT: subl $12, %esp ## encoding: [0x83,0xec,0x0c]
; X86-LARGE-NEXT: movsd {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xf2,0x0f,0x10,0x44,0x24,0x10]
; X86-LARGE-NEXT: ## xmm0 = mem[0],zero
-; X86-LARGE-NEXT: addsd LCPI1_0, %xmm0 ## encoding: [0xf2,0x0f,0x58,0x05,A,A,A,A]
-; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
+; X86-LARGE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## encoding: [0xf2,0x0f,0x58,0x05,A,A,A,A]
+; X86-LARGE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-LARGE-NEXT: movsd %xmm0, (%esp) ## encoding: [0xf2,0x0f,0x11,0x04,0x24]
; X86-LARGE-NEXT: fldl (%esp) ## encoding: [0xdd,0x04,0x24]
; X86-LARGE-NEXT: addl $12, %esp ## encoding: [0x83,0xc4,0x0c]
@@ -116,12 +126,24 @@ define void @constpool_float_no_fp_args(float* %x) nounwind {
;
; LARGE-LABEL: constpool_float_no_fp_args:
; LARGE: ## %bb.0:
-; LARGE-NEXT: movabsq $LCPI2_0, %rax
+; LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; LARGE-NEXT: addss (%rdi), %xmm0
; LARGE-NEXT: movss %xmm0, (%rdi)
; LARGE-NEXT: retq
;
+; LARGE_PIC-LABEL: constpool_float_no_fp_args:
+; LARGE_PIC: # %bb.0:
+; LARGE_PIC-NEXT: .L2$pb:
+; LARGE_PIC-NEXT: leaq .L2$pb(%rip), %rax
+; LARGE_PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L2$pb, %rcx
+; LARGE_PIC-NEXT: addq %rax, %rcx
+; LARGE_PIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
+; LARGE_PIC-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; LARGE_PIC-NEXT: addss (%rdi), %xmm0
+; LARGE_PIC-NEXT: movss %xmm0, (%rdi)
+; LARGE_PIC-NEXT: retq
+;
; AVX-LABEL: constpool_float_no_fp_args:
; AVX: ## %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -131,7 +153,7 @@ define void @constpool_float_no_fp_args(float* %x) nounwind {
;
; LARGE_AVX-LABEL: constpool_float_no_fp_args:
; LARGE_AVX: ## %bb.0:
-; LARGE_AVX-NEXT: movabsq $LCPI2_0, %rax
+; LARGE_AVX-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE_AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; LARGE_AVX-NEXT: vaddss (%rdi), %xmm0, %xmm0
; LARGE_AVX-NEXT: vmovss %xmm0, (%rdi)
@@ -140,8 +162,8 @@ define void @constpool_float_no_fp_args(float* %x) nounwind {
; X86-LARGE-LABEL: constpool_float_no_fp_args:
; X86-LARGE: ## %bb.0:
; X86-LARGE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; X86-LARGE-NEXT: movss LCPI2_0, %xmm0 ## encoding: [0xf3,0x0f,0x10,0x05,A,A,A,A]
-; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI2_0, kind: FK_Data_4
+; X86-LARGE-NEXT: movss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## encoding: [0xf3,0x0f,0x10,0x05,A,A,A,A]
+; X86-LARGE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-LARGE-NEXT: ## xmm0 = mem[0],zero,zero,zero
; X86-LARGE-NEXT: addss (%eax), %xmm0 ## encoding: [0xf3,0x0f,0x58,0x00]
; X86-LARGE-NEXT: movss %xmm0, (%eax) ## encoding: [0xf3,0x0f,0x11,0x00]
@@ -162,12 +184,24 @@ define void @constpool_double_no_fp_args(double* %x) nounwind {
;
; LARGE-LABEL: constpool_double_no_fp_args:
; LARGE: ## %bb.0:
-; LARGE-NEXT: movabsq $LCPI3_0, %rax
+; LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; LARGE-NEXT: addsd (%rdi), %xmm0
; LARGE-NEXT: movsd %xmm0, (%rdi)
; LARGE-NEXT: retq
;
+; LARGE_PIC-LABEL: constpool_double_no_fp_args:
+; LARGE_PIC: # %bb.0:
+; LARGE_PIC-NEXT: .L3$pb:
+; LARGE_PIC-NEXT: leaq .L3$pb(%rip), %rax
+; LARGE_PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L3$pb, %rcx
+; LARGE_PIC-NEXT: addq %rax, %rcx
+; LARGE_PIC-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
+; LARGE_PIC-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; LARGE_PIC-NEXT: addsd (%rdi), %xmm0
+; LARGE_PIC-NEXT: movsd %xmm0, (%rdi)
+; LARGE_PIC-NEXT: retq
+;
; AVX-LABEL: constpool_double_no_fp_args:
; AVX: ## %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -177,7 +211,7 @@ define void @constpool_double_no_fp_args(double* %x) nounwind {
;
; LARGE_AVX-LABEL: constpool_double_no_fp_args:
; LARGE_AVX: ## %bb.0:
-; LARGE_AVX-NEXT: movabsq $LCPI3_0, %rax
+; LARGE_AVX-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; LARGE_AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; LARGE_AVX-NEXT: vaddsd (%rdi), %xmm0, %xmm0
; LARGE_AVX-NEXT: vmovsd %xmm0, (%rdi)
@@ -186,8 +220,8 @@ define void @constpool_double_no_fp_args(double* %x) nounwind {
; X86-LARGE-LABEL: constpool_double_no_fp_args:
; X86-LARGE: ## %bb.0:
; X86-LARGE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; X86-LARGE-NEXT: movsd LCPI3_0, %xmm0 ## encoding: [0xf2,0x0f,0x10,0x05,A,A,A,A]
-; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
+; X86-LARGE-NEXT: movsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## encoding: [0xf2,0x0f,0x10,0x05,A,A,A,A]
+; X86-LARGE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-LARGE-NEXT: ## xmm0 = mem[0],zero
; X86-LARGE-NEXT: addsd (%eax), %xmm0 ## encoding: [0xf2,0x0f,0x58,0x00]
; X86-LARGE-NEXT: movsd %xmm0, (%eax) ## encoding: [0xf2,0x0f,0x11,0x00]
diff --git a/llvm/test/CodeGen/X86/fast-isel-fneg.ll b/llvm/test/CodeGen/X86/fast-isel-fneg.ll
index 28aabc8fadf5e..a741cbee6cdc9 100644
--- a/llvm/test/CodeGen/X86/fast-isel-fneg.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-fneg.ll
@@ -18,7 +18,7 @@ define double @fneg_f64(double %x) nounwind {
; SSE2-NEXT: andl $-8, %esp
; SSE2-NEXT: subl $8, %esp
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2-NEXT: movlps %xmm0, (%esp)
; SSE2-NEXT: fldl (%esp)
; SSE2-NEXT: movl %ebp, %esp
@@ -40,7 +40,7 @@ define float @fneg_f32(float %x) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: pushl %eax
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2-NEXT: movss %xmm0, (%esp)
; SSE2-NEXT: flds (%esp)
; SSE2-NEXT: popl %eax
@@ -65,7 +65,7 @@ define void @fneg_f64_mem(double* %x, double* %y) nounwind {
; SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2-NEXT: movsd %xmm0, (%eax)
; SSE2-NEXT: retl
%a = load double, double* %x
diff --git a/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll b/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll
index c2ce7cb3fb3b0..362fe73073f02 100644
--- a/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll
+++ b/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll
@@ -15,7 +15,7 @@ define zeroext i16 @test1_fast(double %d) #0 {
; AVX: # %bb.0: # %entry
; AVX-NEXT: pushq %rax
; AVX-NEXT: .cfi_def_cfa_offset 16
-; AVX-NEXT: callq __truncdfhf2
+; AVX-NEXT: callq __truncdfhf2 at PLT
; AVX-NEXT: popq %rcx
; AVX-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq
@@ -41,7 +41,7 @@ define zeroext i16 @test2_fast(x86_fp80 %d) #0 {
; AVX-NEXT: .cfi_def_cfa_offset 32
; AVX-NEXT: fldt {{[0-9]+}}(%rsp)
; AVX-NEXT: fstpt (%rsp)
-; AVX-NEXT: callq __truncxfhf2
+; AVX-NEXT: callq __truncxfhf2 at PLT
; AVX-NEXT: addq $24, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq
@@ -55,7 +55,7 @@ define zeroext i16 @test1(double %d) #1 {
; ALL: # %bb.0: # %entry
; ALL-NEXT: pushq %rax
; ALL-NEXT: .cfi_def_cfa_offset 16
-; ALL-NEXT: callq __truncdfhf2
+; ALL-NEXT: callq __truncdfhf2 at PLT
; ALL-NEXT: popq %rcx
; ALL-NEXT: .cfi_def_cfa_offset 8
; ALL-NEXT: retq
@@ -71,7 +71,7 @@ define zeroext i16 @test2(x86_fp80 %d) #1 {
; ALL-NEXT: .cfi_def_cfa_offset 32
; ALL-NEXT: fldt {{[0-9]+}}(%rsp)
; ALL-NEXT: fstpt (%rsp)
-; ALL-NEXT: callq __truncxfhf2
+; ALL-NEXT: callq __truncxfhf2 at PLT
; ALL-NEXT: addq $24, %rsp
; ALL-NEXT: .cfi_def_cfa_offset 8
; ALL-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/fdiv-combine.ll b/llvm/test/CodeGen/X86/fdiv-combine.ll
index 0c102f1456b14..a97f0891e002b 100644
--- a/llvm/test/CodeGen/X86/fdiv-combine.ll
+++ b/llvm/test/CodeGen/X86/fdiv-combine.ll
@@ -131,7 +131,7 @@ define void @PR24141() {
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB8_1: # %while.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: callq g
+; CHECK-NEXT: callq g at PLT
; CHECK-NEXT: divsd %xmm1, %xmm0
; CHECK-NEXT: jmp .LBB8_1
entry:
diff --git a/llvm/test/CodeGen/X86/fdiv.ll b/llvm/test/CodeGen/X86/fdiv.ll
index c361ab0f5aed7..6d2db80a87bdf 100644
--- a/llvm/test/CodeGen/X86/fdiv.ll
+++ b/llvm/test/CodeGen/X86/fdiv.ll
@@ -5,7 +5,7 @@ define double @exact(double %x) {
; Exact division by a constant converted to multiplication.
; CHECK-LABEL: exact:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%div = fdiv double %x, 2.0
ret double %div
@@ -15,7 +15,7 @@ define double @inexact(double %x) {
; Inexact division by a constant converted to multiplication.
; CHECK-LABEL: inexact:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%div = fdiv double %x, 0x41DFFFFFFFC00000
ret double %div
@@ -36,7 +36,7 @@ define double @denormal1(double %x) {
; Don't generate multiplication by a denormal.
; CHECK-LABEL: denormal1:
; CHECK: # %bb.0:
-; CHECK-NEXT: divsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%div = fdiv double %x, 0x7FD0000000000001
ret double %div
@@ -46,7 +46,7 @@ define double @denormal2(double %x) {
; Don't generate multiplication by a denormal.
; CHECK-LABEL: denormal2:
; CHECK: # %bb.0:
-; CHECK-NEXT: divsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%div = fdiv double %x, 0x7FEFFFFFFFFFFFFF
ret double %div
diff --git a/llvm/test/CodeGen/X86/fildll.ll b/llvm/test/CodeGen/X86/fildll.ll
index 8499397fed2d0..43c5525f6068c 100644
--- a/llvm/test/CodeGen/X86/fildll.ll
+++ b/llvm/test/CodeGen/X86/fildll.ll
@@ -36,7 +36,7 @@ define fastcc double @uint64_to_fp(i64 %X) {
; CHECK-NEXT: movl %ecx, (%esp)
; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: fildll (%esp)
-; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%edx,4)
+; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%edx,4)
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ebp, %esp
diff --git a/llvm/test/CodeGen/X86/finite-libcalls.ll b/llvm/test/CodeGen/X86/finite-libcalls.ll
index 8a911505084fa..6b5b68e321c7c 100644
--- a/llvm/test/CodeGen/X86/finite-libcalls.ll
+++ b/llvm/test/CodeGen/X86/finite-libcalls.ll
@@ -44,7 +44,7 @@ define x86_fp80 @exp_f80(x86_fp80 %x) #0 {
; GNU-NEXT: subq $24, %rsp
; GNU-NEXT: fldt {{[0-9]+}}(%rsp)
; GNU-NEXT: fstpt (%rsp)
-; GNU-NEXT: callq expl
+; GNU-NEXT: callq expl at PLT
; GNU-NEXT: addq $24, %rsp
; GNU-NEXT: retq
;
@@ -115,7 +115,7 @@ define x86_fp80 @exp2_f80(x86_fp80 %x) #0 {
; GNU-NEXT: subq $24, %rsp
; GNU-NEXT: fldt {{[0-9]+}}(%rsp)
; GNU-NEXT: fstpt (%rsp)
-; GNU-NEXT: callq exp2l
+; GNU-NEXT: callq exp2l at PLT
; GNU-NEXT: addq $24, %rsp
; GNU-NEXT: retq
;
@@ -186,7 +186,7 @@ define x86_fp80 @log_f80(x86_fp80 %x) #0 {
; GNU-NEXT: subq $24, %rsp
; GNU-NEXT: fldt {{[0-9]+}}(%rsp)
; GNU-NEXT: fstpt (%rsp)
-; GNU-NEXT: callq logl
+; GNU-NEXT: callq logl at PLT
; GNU-NEXT: addq $24, %rsp
; GNU-NEXT: retq
;
@@ -257,7 +257,7 @@ define x86_fp80 @log2_f80(x86_fp80 %x) #0 {
; GNU-NEXT: subq $24, %rsp
; GNU-NEXT: fldt {{[0-9]+}}(%rsp)
; GNU-NEXT: fstpt (%rsp)
-; GNU-NEXT: callq log2l
+; GNU-NEXT: callq log2l at PLT
; GNU-NEXT: addq $24, %rsp
; GNU-NEXT: retq
;
@@ -328,7 +328,7 @@ define x86_fp80 @log10_f80(x86_fp80 %x) #0 {
; GNU-NEXT: subq $24, %rsp
; GNU-NEXT: fldt {{[0-9]+}}(%rsp)
; GNU-NEXT: fstpt (%rsp)
-; GNU-NEXT: callq log10l
+; GNU-NEXT: callq log10l at PLT
; GNU-NEXT: addq $24, %rsp
; GNU-NEXT: retq
;
@@ -407,7 +407,7 @@ define x86_fp80 @pow_f80(x86_fp80 %x) #0 {
; GNU-NEXT: fld %st(0)
; GNU-NEXT: fstpt {{[0-9]+}}(%rsp)
; GNU-NEXT: fstpt (%rsp)
-; GNU-NEXT: callq powl
+; GNU-NEXT: callq powl at PLT
; GNU-NEXT: addq $40, %rsp
; GNU-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll b/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
index c536ff33c578d..6c0179e36f82c 100644
--- a/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
+++ b/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
@@ -111,13 +111,13 @@ declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>)
define float @negated_constant(float %x) {
; FMA3-LABEL: negated_constant:
; FMA3: # %bb.0:
-; FMA3-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; FMA3-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; FMA3-NEXT: vfnmsub132ss {{.*#+}} xmm0 = -(xmm0 * mem) - xmm1
; FMA3-NEXT: retq
;
; FMA4-LABEL: negated_constant:
; FMA4: # %bb.0:
-; FMA4-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; FMA4-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; FMA4-NEXT: vfnmsubss {{.*#+}} xmm0 = -(xmm0 * mem) - xmm1
; FMA4-NEXT: retq
%m = fmul float %x, 42.0
diff --git a/llvm/test/CodeGen/X86/fma-fneg-combine.ll b/llvm/test/CodeGen/X86/fma-fneg-combine.ll
index f906c2887d0ab..47a70e5397156 100644
--- a/llvm/test/CodeGen/X86/fma-fneg-combine.ll
+++ b/llvm/test/CodeGen/X86/fma-fneg-combine.ll
@@ -32,13 +32,13 @@ define <16 x float> @test2(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
; SKX-LABEL: test2:
; SKX: # %bb.0:
; SKX-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
-; SKX-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test2:
; KNL: # %bb.0:
; KNL-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
-; KNL-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; KNL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; KNL-NEXT: retq
%fma = call <16 x float> @llvm.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c)
%neg = fneg <16 x float> %fma
@@ -59,13 +59,13 @@ define <16 x float> @test3(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
; SKX-LABEL: test3:
; SKX: # %bb.0:
; SKX-NEXT: vfnmadd213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm2
-; SKX-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test3:
; KNL: # %bb.0:
; KNL-NEXT: vfnmadd213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm2
-; KNL-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; KNL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; KNL-NEXT: retq
%t0 = fneg <16 x float> %b
%t1 = call <16 x float> @llvm.fma.v16f32(<16 x float> %a, <16 x float> %t0, <16 x float> %c)
@@ -88,13 +88,13 @@ define <16 x float> @test4(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
; SKX-LABEL: test4:
; SKX: # %bb.0:
; SKX-NEXT: vfnmsub213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
-; SKX-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test4:
; KNL: # %bb.0:
; KNL-NEXT: vfnmsub213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
-; KNL-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; KNL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; KNL-NEXT: retq
%t0 = fneg <16 x float> %b
%t1 = fneg <16 x float> %c
@@ -130,13 +130,13 @@ define <16 x float> @test6(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
; SKX-LABEL: test6:
; SKX: # %bb.0:
; SKX-NEXT: vfnmsub213ps {ru-sae}, %zmm2, %zmm1, %zmm0
-; SKX-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test6:
; KNL: # %bb.0:
; KNL-NEXT: vfnmsub213ps {ru-sae}, %zmm2, %zmm1, %zmm0
-; KNL-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; KNL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; KNL-NEXT: retq
%t0 = fneg <16 x float> %b
%t1 = fneg <16 x float> %c
@@ -161,7 +161,7 @@ define <8 x float> @test7(<8 x float> %a, <8 x float> %b, <8 x float> %c) {
; SKX-LABEL: test7:
; SKX: # %bb.0:
; SKX-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) - ymm2
-; SKX-NEXT: vxorps {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; SKX-NEXT: retq
;
; KNL-LABEL: test7:
@@ -202,13 +202,13 @@ define <8 x double> @test9(<8 x double> %a, <8 x double> %b, <8 x double> %c) {
; SKX-LABEL: test9:
; SKX: # %bb.0:
; SKX-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
-; SKX-NEXT: vxorpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test9:
; KNL: # %bb.0:
; KNL-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
-; KNL-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; KNL-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; KNL-NEXT: retq
%t0 = tail call <8 x double> @llvm.x86.avx512.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i32 4)
%sub.i = fneg <8 x double> %t0
@@ -229,7 +229,7 @@ define <2 x double> @test10(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: test10:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
%0 = tail call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 -1, i32 4) #2
@@ -240,7 +240,7 @@ entry:
define <4 x float> @test11(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 zeroext %mask) local_unnamed_addr #0 {
; SKX-LABEL: test11:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vxorps {{.*}}(%rip){1to4}, %xmm2, %xmm3
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm3
; SKX-NEXT: vfmsub213ss {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k1}
@@ -285,14 +285,14 @@ define <8 x double> @test12(<8 x double> %a, <8 x double> %b, <8 x double> %c, i
; SKX: # %bb.0: # %entry
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vfmadd132pd {{.*#+}} zmm0 {%k1} = (zmm0 * zmm1) + zmm2
-; SKX-NEXT: vxorpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test12:
; KNL: # %bb.0: # %entry
; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: vfmadd132pd {{.*#+}} zmm0 {%k1} = (zmm0 * zmm1) + zmm2
-; KNL-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; KNL-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; KNL-NEXT: retq
entry:
%0 = tail call <8 x double> @llvm.x86.avx512.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i32 4) #2
@@ -305,7 +305,7 @@ entry:
define <2 x double> @test13(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
; SKX-LABEL: test13:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm3
+; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; SKX-NEXT: vfnmadd213sd {{.*#+}} xmm1 = -(xmm0 * xmm1) + xmm2
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vmovsd %xmm1, %xmm3, %xmm3 {%k1}
@@ -314,7 +314,7 @@ define <2 x double> @test13(<2 x double> %a, <2 x double> %b, <2 x double> %c, i
;
; KNL-LABEL: test13:
; KNL: # %bb.0: # %entry
-; KNL-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm3
+; KNL-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; KNL-NEXT: vfnmadd213sd {{.*#+}} xmm1 = -(xmm0 * xmm1) + xmm2
; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: vmovsd %xmm1, %xmm3, %xmm3 {%k1}
@@ -331,14 +331,14 @@ define <16 x float> @test14(<16 x float> %a, <16 x float> %b, <16 x float> %c, i
; SKX: # %bb.0: # %entry
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vfnmsub132ps {ru-sae}, %zmm1, %zmm2, %zmm0 {%k1}
-; SKX-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test14:
; KNL: # %bb.0: # %entry
; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: vfnmsub132ps {ru-sae}, %zmm1, %zmm2, %zmm0 {%k1}
-; KNL-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; KNL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; KNL-NEXT: retq
entry:
%0 = tail call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask, i32 10) #2
@@ -350,7 +350,7 @@ define <16 x float> @test15(<16 x float> %a, <16 x float> %b, <16 x float> %c, i
; SKX-LABEL: test15:
; SKX: # %bb.0: # %entry
; SKX-NEXT: kmovd %edi, %k1
-; SKX-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm3
+; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm3
; SKX-NEXT: vfnmadd213ps {ru-sae}, %zmm2, %zmm0, %zmm1
; SKX-NEXT: vmovaps %zmm1, %zmm3 {%k1}
; SKX-NEXT: vfnmadd132ps {rd-sae}, %zmm0, %zmm2, %zmm3 {%k1}
@@ -360,7 +360,7 @@ define <16 x float> @test15(<16 x float> %a, <16 x float> %b, <16 x float> %c, i
; KNL-LABEL: test15:
; KNL: # %bb.0: # %entry
; KNL-NEXT: kmovw %edi, %k1
-; KNL-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm3
+; KNL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm3
; KNL-NEXT: vfnmadd213ps {ru-sae}, %zmm2, %zmm0, %zmm1
; KNL-NEXT: vmovaps %zmm1, %zmm3 {%k1}
; KNL-NEXT: vfnmadd132ps {rd-sae}, %zmm0, %zmm2, %zmm3 {%k1}
diff --git a/llvm/test/CodeGen/X86/fma-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/fma-intrinsics-fast-isel.ll
index d82fe58ec40f7..e4cc8f23fd38e 100644
--- a/llvm/test/CodeGen/X86/fma-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/fma-intrinsics-fast-isel.ll
@@ -52,7 +52,7 @@ entry:
define <4 x float> @test_mm_fmsub_ps(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test_mm_fmsub_ps:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2
+; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; CHECK-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; CHECK-NEXT: retq
entry:
@@ -64,7 +64,7 @@ entry:
define <2 x double> @test_mm_fmsub_pd(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: test_mm_fmsub_pd:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %xmm2, %xmm2
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; CHECK-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; CHECK-NEXT: retq
entry:
@@ -106,7 +106,7 @@ entry:
define <4 x float> @test_mm_fnmadd_ps(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test_mm_fnmadd_ps:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; CHECK-NEXT: retq
entry:
@@ -118,7 +118,7 @@ entry:
define <2 x double> @test_mm_fnmadd_pd(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: test_mm_fnmadd_pd:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; CHECK-NEXT: retq
entry:
@@ -294,7 +294,7 @@ entry:
define <8 x float> @test_mm256_fmsub_ps(<8 x float> %a, <8 x float> %b, <8 x float> %c) {
; CHECK-LABEL: test_mm256_fmsub_ps:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorps {{.*}}(%rip), %ymm2, %ymm2
+; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; CHECK-NEXT: vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
; CHECK-NEXT: retq
entry:
@@ -306,7 +306,7 @@ entry:
define <4 x double> @test_mm256_fmsub_pd(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
; CHECK-LABEL: test_mm256_fmsub_pd:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %ymm2, %ymm2
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; CHECK-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
; CHECK-NEXT: retq
entry:
@@ -318,7 +318,7 @@ entry:
define <8 x float> @test_mm256_fnmadd_ps(<8 x float> %a, <8 x float> %b, <8 x float> %c) {
; CHECK-LABEL: test_mm256_fnmadd_ps:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
; CHECK-NEXT: retq
entry:
@@ -330,7 +330,7 @@ entry:
define <4 x double> @test_mm256_fnmadd_pd(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
; CHECK-LABEL: test_mm256_fnmadd_pd:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/fma-scalar-combine.ll b/llvm/test/CodeGen/X86/fma-scalar-combine.ll
index 02e96ea73cebc..08ae3430ea20b 100644
--- a/llvm/test/CodeGen/X86/fma-scalar-combine.ll
+++ b/llvm/test/CodeGen/X86/fma-scalar-combine.ll
@@ -547,10 +547,10 @@ entry:
define float @fma_const_fmul(float %x) {
; CHECK-LABEL: fma_const_fmul:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x59,0x0d,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; CHECK-NEXT: vfmadd132ss {{.*}}(%rip), %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x99,0x05,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x59,0x0d,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: vfmadd132ss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x99,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: # xmm0 = (xmm0 * mem) + xmm1
; CHECK-NEXT: retq # encoding: [0xc3]
%mul1 = fmul contract float %x, 10.0
diff --git a/llvm/test/CodeGen/X86/fma-signed-zero.ll b/llvm/test/CodeGen/X86/fma-signed-zero.ll
index 6f7d29b9d87f7..f9e4e9929c6c4 100644
--- a/llvm/test/CodeGen/X86/fma-signed-zero.ll
+++ b/llvm/test/CodeGen/X86/fma-signed-zero.ll
@@ -10,7 +10,7 @@ define float @fneg_fma32(float %x, float %y, float %z) {
; CHECK-LABEL: fneg_fma32:
; CHECK: # %bb.0:
; CHECK-NEXT: vfnmsub213ss {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
-; CHECK-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%negx = fneg float %x
%negz = fneg float %z
@@ -37,7 +37,7 @@ define double @fneg_fma64(double %x, double %y, double %z) {
; CHECK-LABEL: fneg_fma64:
; CHECK: # %bb.0:
; CHECK-NEXT: vfnmsub213sd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%negx = fneg double %x
%negz = fneg double %z
diff --git a/llvm/test/CodeGen/X86/fma4-fneg-combine.ll b/llvm/test/CodeGen/X86/fma4-fneg-combine.ll
index af86a2c917a25..9949c79ed2a42 100644
--- a/llvm/test/CodeGen/X86/fma4-fneg-combine.ll
+++ b/llvm/test/CodeGen/X86/fma4-fneg-combine.ll
@@ -10,7 +10,7 @@ define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: vfmaddss {{.*#+}} xmm0 = (xmm0 * xmm1) + xmm2
-; CHECK-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%res = tail call <4 x float> @llvm.x86.fma4.vfmadd.ss(<4 x float> %a, <4 x float> %b, <4 x float> %c)
%sub.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %res
@@ -62,7 +62,7 @@ define <2 x double> @test6(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: test6:
; CHECK: # %bb.0:
; CHECK-NEXT: vfmaddsd {{.*#+}} xmm0 = (xmm0 * xmm1) + xmm2
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%res = tail call <2 x double> @llvm.x86.fma4.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c)
%sub.i = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %res
diff --git a/llvm/test/CodeGen/X86/fma_patterns.ll b/llvm/test/CodeGen/X86/fma_patterns.ll
index f2bf812d9fef7..ee1e7cb4ed162 100644
--- a/llvm/test/CodeGen/X86/fma_patterns.ll
+++ b/llvm/test/CodeGen/X86/fma_patterns.ll
@@ -563,19 +563,19 @@ define <2 x double> @test_2f64_fmsub_load(<2 x double>* %a0, <2 x double> %a1, <
define <4 x float> @test_v4f32_mul_add_x_one_y(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_add_x_one_y:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_add_x_one_y:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_add_x_one_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -601,19 +601,19 @@ define <4 x float> @test_v4f32_mul_add_x_one_y(<4 x float> %x, <4 x float> %y) {
define <4 x float> @test_v4f32_mul_y_add_x_one(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_add_x_one:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_add_x_one:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_add_x_one:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -639,19 +639,19 @@ define <4 x float> @test_v4f32_mul_y_add_x_one(<4 x float> %x, <4 x float> %y) {
define <4 x float> @test_v4f32_mul_y_add_x_one_undefs(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_add_x_one_undefs:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_add_x_one_undefs:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_add_x_one_undefs:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -677,19 +677,19 @@ define <4 x float> @test_v4f32_mul_y_add_x_one_undefs(<4 x float> %x, <4 x float
define <4 x float> @test_v4f32_mul_add_x_negone_y(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_add_x_negone_y:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_add_x_negone_y:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_add_x_negone_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -715,19 +715,19 @@ define <4 x float> @test_v4f32_mul_add_x_negone_y(<4 x float> %x, <4 x float> %y
define <4 x float> @test_v4f32_mul_y_add_x_negone(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_add_x_negone:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_add_x_negone:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_add_x_negone:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -753,19 +753,19 @@ define <4 x float> @test_v4f32_mul_y_add_x_negone(<4 x float> %x, <4 x float> %y
define <4 x float> @test_v4f32_mul_y_add_x_negone_undefs(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_add_x_negone_undefs:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_add_x_negone_undefs:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_add_x_negone_undefs:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -1037,19 +1037,19 @@ define <4 x float> @test_v4f32_mul_y_sub_negone_x_undefs(<4 x float> %x, <4 x fl
define <4 x float> @test_v4f32_mul_sub_x_one_y(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_sub_x_one_y:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_sub_x_one_y:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_sub_x_one_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -1075,19 +1075,19 @@ define <4 x float> @test_v4f32_mul_sub_x_one_y(<4 x float> %x, <4 x float> %y) {
define <4 x float> @test_v4f32_mul_y_sub_x_one(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_sub_x_one:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_sub_x_one:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_sub_x_one:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -1113,19 +1113,19 @@ define <4 x float> @test_v4f32_mul_y_sub_x_one(<4 x float> %x, <4 x float> %y) {
define <4 x float> @test_v4f32_mul_y_sub_x_one_undefs(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_sub_x_one_undefs:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_sub_x_one_undefs:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_sub_x_one_undefs:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -1151,19 +1151,19 @@ define <4 x float> @test_v4f32_mul_y_sub_x_one_undefs(<4 x float> %x, <4 x float
define <4 x float> @test_v4f32_mul_sub_x_negone_y(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_sub_x_negone_y:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_sub_x_negone_y:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_sub_x_negone_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -1189,19 +1189,19 @@ define <4 x float> @test_v4f32_mul_sub_x_negone_y(<4 x float> %x, <4 x float> %y
define <4 x float> @test_v4f32_mul_y_sub_x_negone(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_sub_x_negone:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_sub_x_negone:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_sub_x_negone:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -1227,19 +1227,19 @@ define <4 x float> @test_v4f32_mul_y_sub_x_negone(<4 x float> %x, <4 x float> %y
define <4 x float> @test_v4f32_mul_y_sub_x_negone_undefs(<4 x float> %x, <4 x float> %y) {
; FMA-INFS-LABEL: test_v4f32_mul_y_sub_x_negone_undefs:
; FMA-INFS: # %bb.0:
-; FMA-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-INFS-NEXT: retq
;
; FMA4-INFS-LABEL: test_v4f32_mul_y_sub_x_negone_undefs:
; FMA4-INFS: # %bb.0:
-; FMA4-INFS-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA4-INFS-NEXT: retq
;
; AVX512-INFS-LABEL: test_v4f32_mul_y_sub_x_negone_undefs:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-INFS-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-INFS-NEXT: retq
;
@@ -1657,17 +1657,17 @@ define <4 x double> @test_v4f64_fneg_fnmsub(<4 x double> %a0, <4 x double> %a1,
define <4 x float> @test_v4f32_fma_x_c1_fmul_x_c2(<4 x float> %x) #0 {
; FMA-LABEL: test_v4f32_fma_x_c1_fmul_x_c2:
; FMA: # %bb.0:
-; FMA-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-NEXT: retq
;
; FMA4-LABEL: test_v4f32_fma_x_c1_fmul_x_c2:
; FMA4: # %bb.0:
-; FMA4-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
;
; AVX512-LABEL: test_v4f32_fma_x_c1_fmul_x_c2:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmulps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-NEXT: retq
%m0 = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
%m1 = fmul <4 x float> %x, <float 4.0, float 3.0, float 2.0, float 1.0>
@@ -1775,19 +1775,19 @@ define <4 x double> @test_v4f64_fneg_fmul_no_nsz(<4 x double> %x, <4 x double> %
; FMA-LABEL: test_v4f64_fneg_fmul_no_nsz:
; FMA: # %bb.0:
; FMA-NEXT: vmulpd %ymm1, %ymm0, %ymm0
-; FMA-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0
+; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; FMA-NEXT: retq
;
; FMA4-LABEL: test_v4f64_fneg_fmul_no_nsz:
; FMA4: # %bb.0:
; FMA4-NEXT: vmulpd %ymm1, %ymm0, %ymm0
-; FMA4-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0
+; FMA4-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; FMA4-NEXT: retq
;
; AVX512-LABEL: test_v4f64_fneg_fmul_no_nsz:
; AVX512: # %bb.0:
; AVX512-NEXT: vmulpd %ymm1, %ymm0, %ymm0
-; AVX512-NEXT: vxorpd {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512-NEXT: retq
%m = fmul <4 x double> %x, %y
%n = fsub <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %m
diff --git a/llvm/test/CodeGen/X86/fma_patterns_wide.ll b/llvm/test/CodeGen/X86/fma_patterns_wide.ll
index a96435562bb75..6a732c0c0c31c 100644
--- a/llvm/test/CodeGen/X86/fma_patterns_wide.ll
+++ b/llvm/test/CodeGen/X86/fma_patterns_wide.ll
@@ -277,7 +277,7 @@ define <16 x float> @test_v16f32_mul_add_x_one_y(<16 x float> %x, <16 x float> %
;
; AVX512-INFS-LABEL: test_v16f32_mul_add_x_one_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulps %zmm1, %zmm0, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -323,7 +323,7 @@ define <8 x double> @test_v8f64_mul_y_add_x_one(<8 x double> %x, <8 x double> %y
;
; AVX512-INFS-LABEL: test_v8f64_mul_y_add_x_one:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulpd %zmm0, %zmm1, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -369,7 +369,7 @@ define <16 x float> @test_v16f32_mul_add_x_negone_y(<16 x float> %x, <16 x float
;
; AVX512-INFS-LABEL: test_v16f32_mul_add_x_negone_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulps %zmm1, %zmm0, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -415,7 +415,7 @@ define <8 x double> @test_v8f64_mul_y_add_x_negone(<8 x double> %x, <8 x double>
;
; AVX512-INFS-LABEL: test_v8f64_mul_y_add_x_negone:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulpd %zmm0, %zmm1, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -649,7 +649,7 @@ define <16 x float> @test_v16f32_mul_sub_x_one_y(<16 x float> %x, <16 x float> %
;
; AVX512-INFS-LABEL: test_v16f32_mul_sub_x_one_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulps %zmm1, %zmm0, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -695,7 +695,7 @@ define <8 x double> @test_v8f64_mul_y_sub_x_one(<8 x double> %x, <8 x double> %y
;
; AVX512-INFS-LABEL: test_v8f64_mul_y_sub_x_one:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulpd %zmm0, %zmm1, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -741,7 +741,7 @@ define <16 x float> @test_v16f32_mul_sub_x_negone_y(<16 x float> %x, <16 x float
;
; AVX512-INFS-LABEL: test_v16f32_mul_sub_x_negone_y:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulps %zmm1, %zmm0, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -787,7 +787,7 @@ define <8 x double> @test_v8f64_mul_y_sub_x_negone(<8 x double> %x, <8 x double>
;
; AVX512-INFS-LABEL: test_v8f64_mul_y_sub_x_negone:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vaddpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512-INFS-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512-INFS-NEXT: vmulpd %zmm0, %zmm1, %zmm0
; AVX512-INFS-NEXT: retq
;
@@ -1039,19 +1039,19 @@ define <8 x double> @test_v8f64_fneg_fnmsub(<8 x double> %a0, <8 x double> %a1,
define <16 x float> @test_v16f32_fma_x_c1_fmul_x_c2(<16 x float> %x) #0 {
; FMA-LABEL: test_v16f32_fma_x_c1_fmul_x_c2:
; FMA: # %bb.0:
-; FMA-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
-; FMA-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; FMA-NEXT: retq
;
; FMA4-LABEL: test_v16f32_fma_x_c1_fmul_x_c2:
; FMA4: # %bb.0:
-; FMA4-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
-; FMA4-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; FMA4-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; FMA4-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; FMA4-NEXT: retq
;
; AVX512-LABEL: test_v16f32_fma_x_c1_fmul_x_c2:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmulps {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%m0 = fmul <16 x float> %x, <float 17.0, float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0>
%m1 = fmul <16 x float> %x, <float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0, float 1.0>
@@ -1160,7 +1160,7 @@ define <8 x double> @test_v8f64_fneg_fmul_no_nsz(<8 x double> %x, <8 x double> %
; AVX512-LABEL: test_v8f64_fneg_fmul_no_nsz:
; AVX512: # %bb.0:
; AVX512-NEXT: vmulpd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT: vxorpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512-NEXT: retq
%m = fmul <8 x double> %x, %y
%n = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %m
diff --git a/llvm/test/CodeGen/X86/fmaxnum.ll b/llvm/test/CodeGen/X86/fmaxnum.ll
index 95a5cfe4ca310..2160624d5de33 100644
--- a/llvm/test/CodeGen/X86/fmaxnum.ll
+++ b/llvm/test/CodeGen/X86/fmaxnum.ll
@@ -102,7 +102,7 @@ define x86_fp80 @test_fmaxl(x86_fp80 %x, x86_fp80 %y) {
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq fmaxl
+; CHECK-NEXT: callq fmaxl at PLT
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -181,7 +181,7 @@ define x86_fp80 @test_intrinsic_fmaxl(x86_fp80 %x, x86_fp80 %y) {
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq fmaxl
+; CHECK-NEXT: callq fmaxl at PLT
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -584,12 +584,12 @@ define <2 x double> @maxnum_intrinsic_nnan_attr_f64(<2 x double> %a, <2 x double
define float @test_maxnum_const_op1(float %x) {
; SSE-LABEL: test_maxnum_const_op1:
; SSE: # %bb.0:
-; SSE-NEXT: maxss {{.*}}(%rip), %xmm0
+; SSE-NEXT: maxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_maxnum_const_op1:
; AVX: # %bb.0:
-; AVX-NEXT: vmaxss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%r = call float @llvm.maxnum.f32(float 1.0, float %x)
ret float %r
@@ -598,12 +598,12 @@ define float @test_maxnum_const_op1(float %x) {
define float @test_maxnum_const_op2(float %x) {
; SSE-LABEL: test_maxnum_const_op2:
; SSE: # %bb.0:
-; SSE-NEXT: maxss {{.*}}(%rip), %xmm0
+; SSE-NEXT: maxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_maxnum_const_op2:
; AVX: # %bb.0:
-; AVX-NEXT: vmaxss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%r = call float @llvm.maxnum.f32(float %x, float 1.0)
ret float %r
diff --git a/llvm/test/CodeGen/X86/fmf-flags.ll b/llvm/test/CodeGen/X86/fmf-flags.ll
index a4285ebc888be..102a162b44824 100644
--- a/llvm/test/CodeGen/X86/fmf-flags.ll
+++ b/llvm/test/CodeGen/X86/fmf-flags.ll
@@ -10,8 +10,8 @@ define dso_local float @fast_recip_sqrt(float %x) {
; X64-NEXT: rsqrtss %xmm0, %xmm1
; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: mulss %xmm1, %xmm0
-; X64-NEXT: addss {{.*}}(%rip), %xmm0
-; X64-NEXT: mulss {{.*}}(%rip), %xmm1
+; X64-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: retq
;
@@ -32,13 +32,13 @@ declare float @llvm.fmuladd.f32(float %a, float %b, float %c);
define dso_local float @fast_fmuladd_opts(float %a , float %b , float %c) {
; X64-LABEL: fast_fmuladd_opts:
; X64: # %bb.0:
-; X64-NEXT: mulss {{.*}}(%rip), %xmm0
+; X64-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
;
; X86-LABEL: fast_fmuladd_opts:
; X86: # %bb.0:
; X86-NEXT: flds {{[0-9]+}}(%esp)
-; X86-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; X86-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; X86-NEXT: retl
%res = call fast float @llvm.fmuladd.f32(float %a, float 2.0, float %a)
ret float %res
@@ -53,17 +53,17 @@ define dso_local double @not_so_fast_mul_add(double %x) {
; X64: # %bb.0:
; X64-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; X64-NEXT: mulsd %xmm0, %xmm1
-; X64-NEXT: mulsd {{.*}}(%rip), %xmm0
-; X64-NEXT: movsd %xmm1, {{.*}}(%rip)
+; X64-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: movsd %xmm1, mul1(%rip)
; X64-NEXT: retq
;
; X86-LABEL: not_so_fast_mul_add:
; X86: # %bb.0:
; X86-NEXT: fldl {{[0-9]+}}(%esp)
; X86-NEXT: fld %st(0)
-; X86-NEXT: fmull {{\.LCPI[0-9]+_[0-9]+}}
+; X86-NEXT: fmull {{\.?LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fxch %st(1)
-; X86-NEXT: fmull {{\.LCPI[0-9]+_[0-9]+}}
+; X86-NEXT: fmull {{\.?LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fxch %st(1)
; X86-NEXT: fstpl mul1
; X86-NEXT: retl
@@ -84,10 +84,10 @@ define dso_local float @not_so_fast_recip_sqrt(float %x) {
; X64-NEXT: sqrtss %xmm0, %xmm2
; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: mulss %xmm1, %xmm0
-; X64-NEXT: addss {{.*}}(%rip), %xmm0
-; X64-NEXT: mulss {{.*}}(%rip), %xmm1
+; X64-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: mulss %xmm1, %xmm0
-; X64-NEXT: movss %xmm2, {{.*}}(%rip)
+; X64-NEXT: movss %xmm2, sqrt1(%rip)
; X64-NEXT: retq
;
; X86-LABEL: not_so_fast_recip_sqrt:
@@ -113,7 +113,7 @@ define dso_local float @div_arcp_by_const(half %x) {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movzwl %di, %edi
; X64-NEXT: callq __gnu_h2f_ieee at PLT
-; X64-NEXT: mulss {{.*}}(%rip), %xmm0
+; X64-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: callq __gnu_f2h_ieee at PLT
; X64-NEXT: movzwl %ax, %edi
; X64-NEXT: popq %rax
@@ -127,7 +127,7 @@ define dso_local float @div_arcp_by_const(half %x) {
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll __gnu_h2f_ieee
-; X86-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; X86-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fstps (%esp)
; X86-NEXT: calll __gnu_f2h_ieee
; X86-NEXT: movzwl %ax, %eax
diff --git a/llvm/test/CodeGen/X86/fminnum.ll b/llvm/test/CodeGen/X86/fminnum.ll
index 1bb9329c89588..6025a4f3adfdc 100644
--- a/llvm/test/CodeGen/X86/fminnum.ll
+++ b/llvm/test/CodeGen/X86/fminnum.ll
@@ -102,7 +102,7 @@ define x86_fp80 @test_fminl(x86_fp80 %x, x86_fp80 %y) {
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq fminl
+; CHECK-NEXT: callq fminl at PLT
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -181,7 +181,7 @@ define x86_fp80 @test_intrinsic_fminl(x86_fp80 %x, x86_fp80 %y) {
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq fminl
+; CHECK-NEXT: callq fminl at PLT
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -584,12 +584,12 @@ define <4 x float> @minnum_intrinsic_nnan_attr_v4f32(<4 x float> %a, <4 x float>
define float @test_minnum_const_op1(float %x) {
; SSE-LABEL: test_minnum_const_op1:
; SSE: # %bb.0:
-; SSE-NEXT: minss {{.*}}(%rip), %xmm0
+; SSE-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_minnum_const_op1:
; AVX: # %bb.0:
-; AVX-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%r = call float @llvm.minnum.f32(float 1.0, float %x)
ret float %r
@@ -598,12 +598,12 @@ define float @test_minnum_const_op1(float %x) {
define float @test_minnum_const_op2(float %x) {
; SSE-LABEL: test_minnum_const_op2:
; SSE: # %bb.0:
-; SSE-NEXT: minss {{.*}}(%rip), %xmm0
+; SSE-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_minnum_const_op2:
; AVX: # %bb.0:
-; AVX-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%r = call float @llvm.minnum.f32(float %x, float 1.0)
ret float %r
diff --git a/llvm/test/CodeGen/X86/fmsubadd-combine.ll b/llvm/test/CodeGen/X86/fmsubadd-combine.ll
index 912445ae07400..76262561c987a 100644
--- a/llvm/test/CodeGen/X86/fmsubadd-combine.ll
+++ b/llvm/test/CodeGen/X86/fmsubadd-combine.ll
@@ -6,19 +6,14 @@
; This test checks the fusing of MUL + SUB/ADD to FMSUBADD.
define <2 x double> @mul_subadd_pd128(<2 x double> %A, <2 x double> %B, <2 x double> %C) #0 {
-; FMA3_256-LABEL: mul_subadd_pd128:
-; FMA3_256: # %bb.0: # %entry
-; FMA3_256-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0
-; FMA3_256-NEXT: retq
-;
-; FMA3_512-LABEL: mul_subadd_pd128:
-; FMA3_512: # %bb.0: # %entry
-; FMA3_512-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0
-; FMA3_512-NEXT: retq
+; FMA3-LABEL: mul_subadd_pd128:
+; FMA3: # %bb.0: # %entry
+; FMA3-NEXT: vfmsubadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm2
+; FMA3-NEXT: retq
;
; FMA4-LABEL: mul_subadd_pd128:
; FMA4: # %bb.0: # %entry
-; FMA4-NEXT: vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0
+; FMA4-NEXT: vfmsubaddpd {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm2
; FMA4-NEXT: retq
entry:
%AB = fmul <2 x double> %A, %B
@@ -31,12 +26,12 @@ entry:
define <4 x float> @mul_subadd_ps128(<4 x float> %A, <4 x float> %B, <4 x float> %C) #0 {
; FMA3-LABEL: mul_subadd_ps128:
; FMA3: # %bb.0: # %entry
-; FMA3-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0
+; FMA3-NEXT: vfmsubadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm2
; FMA3-NEXT: retq
;
; FMA4-LABEL: mul_subadd_ps128:
; FMA4: # %bb.0: # %entry
-; FMA4-NEXT: vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0
+; FMA4-NEXT: vfmsubaddps {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm2
; FMA4-NEXT: retq
entry:
%AB = fmul <4 x float> %A, %B
@@ -49,12 +44,12 @@ entry:
define <4 x double> @mul_subadd_pd256(<4 x double> %A, <4 x double> %B, <4 x double> %C) #0 {
; FMA3-LABEL: mul_subadd_pd256:
; FMA3: # %bb.0: # %entry
-; FMA3-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0
+; FMA3-NEXT: vfmsubadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2
; FMA3-NEXT: retq
;
; FMA4-LABEL: mul_subadd_pd256:
; FMA4: # %bb.0: # %entry
-; FMA4-NEXT: vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0
+; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm2
; FMA4-NEXT: retq
entry:
%AB = fmul <4 x double> %A, %B
@@ -67,12 +62,12 @@ entry:
define <8 x float> @mul_subadd_ps256(<8 x float> %A, <8 x float> %B, <8 x float> %C) #0 {
; FMA3-LABEL: mul_subadd_ps256:
; FMA3: # %bb.0: # %entry
-; FMA3-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0
+; FMA3-NEXT: vfmsubadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2
; FMA3-NEXT: retq
;
; FMA4-LABEL: mul_subadd_ps256:
; FMA4: # %bb.0: # %entry
-; FMA4-NEXT: vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0
+; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm2
; FMA4-NEXT: retq
entry:
%AB = fmul <8 x float> %A, %B
@@ -85,19 +80,19 @@ entry:
define <8 x double> @mul_subadd_pd512(<8 x double> %A, <8 x double> %B, <8 x double> %C) #0 {
; FMA3_256-LABEL: mul_subadd_pd512:
; FMA3_256: # %bb.0: # %entry
-; FMA3_256-NEXT: vfmsubadd213pd %ymm4, %ymm2, %ymm0
-; FMA3_256-NEXT: vfmsubadd213pd %ymm5, %ymm3, %ymm1
+; FMA3_256-NEXT: vfmsubadd213pd {{.*#+}} ymm0 = (ymm2 * ymm0) -/+ ymm4
+; FMA3_256-NEXT: vfmsubadd213pd {{.*#+}} ymm1 = (ymm3 * ymm1) -/+ ymm5
; FMA3_256-NEXT: retq
;
; FMA3_512-LABEL: mul_subadd_pd512:
; FMA3_512: # %bb.0: # %entry
-; FMA3_512-NEXT: vfmsubadd213pd %zmm2, %zmm1, %zmm0
+; FMA3_512-NEXT: vfmsubadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) -/+ zmm2
; FMA3_512-NEXT: retq
;
; FMA4-LABEL: mul_subadd_pd512:
; FMA4: # %bb.0: # %entry
-; FMA4-NEXT: vfmsubaddpd %ymm4, %ymm2, %ymm0, %ymm0
-; FMA4-NEXT: vfmsubaddpd %ymm5, %ymm3, %ymm1, %ymm1
+; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm4
+; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm1 = (ymm1 * ymm3) -/+ ymm5
; FMA4-NEXT: retq
entry:
%AB = fmul <8 x double> %A, %B
@@ -110,19 +105,19 @@ entry:
define <16 x float> @mul_subadd_ps512(<16 x float> %A, <16 x float> %B, <16 x float> %C) #0 {
; FMA3_256-LABEL: mul_subadd_ps512:
; FMA3_256: # %bb.0: # %entry
-; FMA3_256-NEXT: vfmsubadd213ps %ymm4, %ymm2, %ymm0
-; FMA3_256-NEXT: vfmsubadd213ps %ymm5, %ymm3, %ymm1
+; FMA3_256-NEXT: vfmsubadd213ps {{.*#+}} ymm0 = (ymm2 * ymm0) -/+ ymm4
+; FMA3_256-NEXT: vfmsubadd213ps {{.*#+}} ymm1 = (ymm3 * ymm1) -/+ ymm5
; FMA3_256-NEXT: retq
;
; FMA3_512-LABEL: mul_subadd_ps512:
; FMA3_512: # %bb.0: # %entry
-; FMA3_512-NEXT: vfmsubadd213ps %zmm2, %zmm1, %zmm0
+; FMA3_512-NEXT: vfmsubadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) -/+ zmm2
; FMA3_512-NEXT: retq
;
; FMA4-LABEL: mul_subadd_ps512:
; FMA4: # %bb.0: # %entry
-; FMA4-NEXT: vfmsubaddps %ymm4, %ymm2, %ymm0, %ymm0
-; FMA4-NEXT: vfmsubaddps %ymm5, %ymm3, %ymm1, %ymm1
+; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm4
+; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm1 = (ymm1 * ymm3) -/+ ymm5
; FMA4-NEXT: retq
entry:
%AB = fmul <16 x float> %A, %B
diff --git a/llvm/test/CodeGen/X86/fmul-combines.ll b/llvm/test/CodeGen/X86/fmul-combines.ll
index f9a3e75c3d783..6bb9f2dfe2dcb 100644
--- a/llvm/test/CodeGen/X86/fmul-combines.ll
+++ b/llvm/test/CodeGen/X86/fmul-combines.ll
@@ -97,7 +97,7 @@ define <4 x float> @fmul0_v4f32_undef(<4 x float> %x) {
define <4 x float> @fmul_c2_c4_v4f32(<4 x float> %x) {
; CHECK-LABEL: fmul_c2_c4_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul fast <4 x float> %x, <float 2.0, float 2.0, float 2.0, float 2.0>
%z = fmul fast <4 x float> %y, <float 4.0, float 4.0, float 4.0, float 4.0>
@@ -107,7 +107,7 @@ define <4 x float> @fmul_c2_c4_v4f32(<4 x float> %x) {
define <4 x float> @fmul_c3_c4_v4f32(<4 x float> %x) {
; CHECK-LABEL: fmul_c3_c4_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul fast <4 x float> %x, <float 3.0, float 3.0, float 3.0, float 3.0>
%z = fmul fast <4 x float> %y, <float 4.0, float 4.0, float 4.0, float 4.0>
@@ -123,7 +123,7 @@ define <4 x float> @fmul_c3_c4_v4f32(<4 x float> %x) {
define <4 x float> @fmul_v4f32_two_consts_no_splat(<4 x float> %x) {
; CHECK-LABEL: fmul_v4f32_two_consts_no_splat:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul fast <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
%z = fmul fast <4 x float> %y, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -134,7 +134,7 @@ define <4 x float> @fmul_v4f32_two_consts_no_splat(<4 x float> %x) {
define <4 x float> @fmul_v4f32_two_consts_no_splat_non_canonical(<4 x float> %x) {
; CHECK-LABEL: fmul_v4f32_two_consts_no_splat_non_canonical:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul fast <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, %x
%z = fmul fast <4 x float> <float 5.0, float 6.0, float 7.0, float 8.0>, %y
@@ -146,7 +146,7 @@ define <4 x float> @fmul_v4f32_two_consts_no_splat_non_canonical(<4 x float> %x)
define <4 x float> @fmul_v4f32_two_consts_no_splat_reassoc(<4 x float> %x) {
; CHECK-LABEL: fmul_v4f32_two_consts_no_splat_reassoc:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
%z = fmul reassoc <4 x float> %y, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -158,7 +158,7 @@ define <4 x float> @fmul_v4f32_two_consts_no_splat_reassoc(<4 x float> %x) {
define <4 x float> @fmul_v4f32_two_consts_no_splat_reassoc_2(<4 x float> %x) {
; CHECK-LABEL: fmul_v4f32_two_consts_no_splat_reassoc_2:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fadd <4 x float> %x, %x
%z = fmul reassoc <4 x float> %y, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -175,7 +175,7 @@ define <4 x float> @fmul_v4f32_two_consts_no_splat_reassoc_2(<4 x float> %x) {
define <4 x float> @fmul_v4f32_two_consts_no_splat_multiple_use(<4 x float> %x) {
; CHECK-LABEL: fmul_v4f32_two_consts_no_splat_multiple_use:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul fast <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
%z = fmul fast <4 x float> %y, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -194,7 +194,7 @@ define <4 x float> @fmul_v4f32_two_consts_no_splat_multiple_use(<4 x float> %x)
define <4 x float> @PR22698_splats(<4 x float> %a) {
; CHECK-LABEL: PR22698_splats:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%mul1 = fmul fast <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, <float 3.0, float 3.0, float 3.0, float 3.0>
%mul2 = fmul fast <4 x float> <float 4.0, float 4.0, float 4.0, float 4.0>, %mul1
@@ -212,7 +212,7 @@ define <4 x float> @PR22698_splats(<4 x float> %a) {
define <4 x float> @PR22698_no_splats(<4 x float> %a) {
; CHECK-LABEL: PR22698_no_splats:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%mul1 = fmul fast <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <float 5.0, float 6.0, float 7.0, float 8.0>
%mul2 = fmul fast <4 x float> <float 9.0, float 10.0, float 11.0, float 12.0>, %mul1
@@ -223,7 +223,7 @@ define <4 x float> @PR22698_no_splats(<4 x float> %a) {
define float @fmul_c2_c4_f32(float %x) {
; CHECK-LABEL: fmul_c2_c4_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul fast float %x, 2.0
%z = fmul fast float %y, 4.0
@@ -233,7 +233,7 @@ define float @fmul_c2_c4_f32(float %x) {
define float @fmul_c3_c4_f32(float %x) {
; CHECK-LABEL: fmul_c3_c4_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulss {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul fast float %x, 3.0
%z = fmul fast float %y, 4.0
diff --git a/llvm/test/CodeGen/X86/fold-call-3.ll b/llvm/test/CodeGen/X86/fold-call-3.ll
index d0f311d39f38d..81a86bada325a 100644
--- a/llvm/test/CodeGen/X86/fold-call-3.ll
+++ b/llvm/test/CodeGen/X86/fold-call-3.ll
@@ -16,7 +16,7 @@ define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: cmpl $0, {{.*}}(%rip)
+; CHECK-NEXT: cmpl $0, _NumTrials(%rip)
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: ## %bb.1: ## %bb.nph
; CHECK-NEXT: movq %rsi, %rbx
@@ -32,7 +32,7 @@ define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: incl %ebp
-; CHECK-NEXT: cmpl {{.*}}(%rip), %ebp
+; CHECK-NEXT: cmpl _NumTrials(%rip), %ebp
; CHECK-NEXT: jb LBB0_2
; CHECK-NEXT: LBB0_3: ## %return
; CHECK-NEXT: addq $24, %rsp
@@ -45,7 +45,7 @@ define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.
; pre-RA-NEXT: pushq %rbp
; pre-RA-NEXT: pushq %rbx
; pre-RA-NEXT: subq $24, %rsp
-; pre-RA-NEXT: cmpl $0, {{.*}}(%rip)
+; pre-RA-NEXT: cmpl $0, _NumTrials(%rip)
; pre-RA-NEXT: je LBB0_3
; pre-RA-NEXT: ## %bb.1: ## %bb.nph
; pre-RA-NEXT: movq %rsi, %rbx
@@ -61,7 +61,7 @@ define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.
; pre-RA-NEXT: incl %ebp
; pre-RA-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; pre-RA-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
-; pre-RA-NEXT: cmpl {{.*}}(%rip), %ebp
+; pre-RA-NEXT: cmpl _NumTrials(%rip), %ebp
; pre-RA-NEXT: jb LBB0_2
; pre-RA-NEXT: LBB0_3: ## %return
; pre-RA-NEXT: addq $24, %rsp
diff --git a/llvm/test/CodeGen/X86/fold-load-vec.ll b/llvm/test/CodeGen/X86/fold-load-vec.ll
index e8dc8f26ffa20..b41449641bac5 100644
--- a/llvm/test/CodeGen/X86/fold-load-vec.ll
+++ b/llvm/test/CodeGen/X86/fold-load-vec.ll
@@ -18,7 +18,7 @@ define void @sample_test(<4 x float>* %source, <2 x float>* %dest) nounwind {
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-NEXT: callq ext
+; CHECK-NEXT: callq ext at PLT
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
index 9708300b1fc31..667c9dbd20106 100644
--- a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
+++ b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
@@ -30,28 +30,28 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X32-NEXT: retl
; X32-NEXT: LBB0_3: ## %forbody
; X32-NEXT: movaps {{.*#+}} xmm1 = [1.28E+2,1.28E+2,1.28E+2,1.28E+2]
-; X32-NEXT: minps LCPI0_3, %xmm1
+; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: cvttps2dq %xmm1, %xmm0
; X32-NEXT: cvtdq2ps %xmm0, %xmm0
; X32-NEXT: subps %xmm0, %xmm1
; X32-NEXT: movaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: mulps LCPI0_3, %xmm0
+; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: addps LCPI0_1, %xmm0
+; X32-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: mulps %xmm1, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: addps LCPI0_2, %xmm0
+; X32-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: psubd LCPI0_4, %xmm0
+; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: mulps LCPI0_3, %xmm0
+; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
@@ -59,7 +59,7 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X32-NEXT: mulps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: mulps LCPI0_3, %xmm0
+; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
@@ -67,7 +67,7 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X32-NEXT: cmpunordps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: minps LCPI0_3, %xmm0
+; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
@@ -79,12 +79,12 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; X32-NEXT: calll *%esi
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: minps LCPI0_3, %xmm0
+; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: pxor %xmm1, %xmm1
; X32-NEXT: psubd {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X32-NEXT: psubd LCPI0_4, %xmm0
+; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: por %xmm1, %xmm0
@@ -116,28 +116,28 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; X64-NEXT: movaps {{.*#+}} xmm1 = [1.28E+2,1.28E+2,1.28E+2,1.28E+2]
-; X64-NEXT: minps {{.*}}(%rip), %xmm1
+; X64-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: cvttps2dq %xmm1, %xmm0
; X64-NEXT: cvtdq2ps %xmm0, %xmm0
; X64-NEXT: subps %xmm0, %xmm1
; X64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
-; X64-NEXT: mulps {{.*}}(%rip), %xmm0
+; X64-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
-; X64-NEXT: addps {{.*}}(%rip), %xmm0
+; X64-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; X64-NEXT: mulps %xmm1, %xmm0
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
-; X64-NEXT: addps {{.*}}(%rip), %xmm0
+; X64-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: movdqa (%rsp), %xmm0 ## 16-byte Reload
-; X64-NEXT: psubd {{.*}}(%rip), %xmm0
+; X64-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movdqa %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
-; X64-NEXT: mulps {{.*}}(%rip), %xmm0
+; X64-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
@@ -145,7 +145,7 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X64-NEXT: mulps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
-; X64-NEXT: mulps {{.*}}(%rip), %xmm0
+; X64-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
@@ -153,7 +153,7 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X64-NEXT: cmpunordps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X64-NEXT: minps {{.*}}(%rip), %xmm0
+; X64-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; X64-NEXT: xorl %ebx, %ebx
; X64-NEXT: xorps %xmm3, %xmm3
@@ -164,13 +164,13 @@ define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x
; X64-NEXT: xorl %edi, %edi
; X64-NEXT: callq *%rbx
; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
-; X64-NEXT: minps {{.*}}(%rip), %xmm0
+; X64-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; X64-NEXT: psubd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
-; X64-NEXT: psubd {{.*}}(%rip), %xmm0
+; X64-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; X64-NEXT: orps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/X86/fold-rmw-ops.ll b/llvm/test/CodeGen/X86/fold-rmw-ops.ll
index 04d73c7ac78de..1fc813346c67b 100644
--- a/llvm/test/CodeGen/X86/fold-rmw-ops.ll
+++ b/llvm/test/CodeGen/X86/fold-rmw-ops.ll
@@ -14,7 +14,7 @@ declare dso_local void @b()
define void @add64_imm32_br() nounwind {
; CHECK-LABEL: add64_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq $16777214, {{.*}}(%rip) # encoding: [0x48,0x81,0x05,A,A,A,A,0xfe,0xff,0xff,0x00]
+; CHECK-NEXT: addq $16777214, g64(%rip) # encoding: [0x48,0x81,0x05,A,A,A,A,0xfe,0xff,0xff,0x00]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0xFFFFFE
; CHECK-NEXT: js .LBB0_1 # encoding: [0x78,A]
@@ -47,7 +47,7 @@ b:
define void @add64_sext_imm32_br() nounwind {
; CHECK-LABEL: add64_sext_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq $-2147483648, {{.*}}(%rip) # encoding: [0x48,0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: addq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: js .LBB1_1 # encoding: [0x78,A]
@@ -80,7 +80,7 @@ b:
define void @add64_imm32_via_sub_br() nounwind {
; CHECK-LABEL: add64_imm32_via_sub_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $-2147483648, {{.*}}(%rip) # encoding: [0x48,0x81,0x2d,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: subq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x2d,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: js .LBB2_1 # encoding: [0x78,A]
@@ -116,7 +116,7 @@ define void @add64_no_imm32_via_sub_due_to_cf_br() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $2147483648, %eax # encoding: [0xb8,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # imm = 0x80000000
-; CHECK-NEXT: addq %rax, {{.*}}(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
+; CHECK-NEXT: addq %rax, g64(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: jae .LBB3_2 # encoding: [0x73,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB3_2-1, kind: FK_PCRel_1
@@ -152,7 +152,7 @@ define void @add64_too_large_imm32_br() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $2147483649, %eax # encoding: [0xb8,0x01,0x00,0x00,0x80]
; CHECK-NEXT: # imm = 0x80000001
-; CHECK-NEXT: addq %rax, {{.*}}(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
+; CHECK-NEXT: addq %rax, g64(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB4_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB4_1-1, kind: FK_PCRel_1
@@ -185,7 +185,7 @@ b:
define void @add64_imm8_via_sub_br() nounwind {
; CHECK-LABEL: add64_imm8_via_sub_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $-128, {{.*}}(%rip) # encoding: [0x48,0x83,0x2d,A,A,A,A,0x80]
+; CHECK-NEXT: subq $-128, g64(%rip) # encoding: [0x48,0x83,0x2d,A,A,A,A,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB5_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_1-1, kind: FK_PCRel_1
@@ -218,7 +218,7 @@ b:
define void @add64_imm8_br() nounwind {
; CHECK-LABEL: add64_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq $42, {{.*}}(%rip) # encoding: [0x48,0x83,0x05,A,A,A,A,0x2a]
+; CHECK-NEXT: addq $42, g64(%rip) # encoding: [0x48,0x83,0x05,A,A,A,A,0x2a]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB6_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
@@ -249,7 +249,7 @@ b:
define void @add64_imm8_neg_br() nounwind {
; CHECK-LABEL: add64_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq $-42, {{.*}}(%rip) # encoding: [0x48,0x83,0x05,A,A,A,A,0xd6]
+; CHECK-NEXT: addq $-42, g64(%rip) # encoding: [0x48,0x83,0x05,A,A,A,A,0xd6]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB7_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB7_1-1, kind: FK_PCRel_1
@@ -280,7 +280,7 @@ b:
define void @add32_imm_br() nounwind {
; CHECK-LABEL: add32_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $-2147483648, {{.*}}(%rip) # encoding: [0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: addl $-2147483648, g32(%rip) # encoding: [0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: js .LBB8_1 # encoding: [0x78,A]
@@ -313,7 +313,7 @@ b:
define void @add32_imm8_br() nounwind {
; CHECK-LABEL: add32_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $42, {{.*}}(%rip) # encoding: [0x83,0x05,A,A,A,A,0x2a]
+; CHECK-NEXT: addl $42, g32(%rip) # encoding: [0x83,0x05,A,A,A,A,0x2a]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB9_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB9_1-1, kind: FK_PCRel_1
@@ -344,7 +344,7 @@ b:
define void @add32_imm8_neg_br() nounwind {
; CHECK-LABEL: add32_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $-42, {{.*}}(%rip) # encoding: [0x83,0x05,A,A,A,A,0xd6]
+; CHECK-NEXT: addl $-42, g32(%rip) # encoding: [0x83,0x05,A,A,A,A,0xd6]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB10_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB10_1-1, kind: FK_PCRel_1
@@ -375,7 +375,7 @@ b:
define void @add16_imm_br() nounwind {
; CHECK-LABEL: add16_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addw $-32768, {{.*}}(%rip) # encoding: [0x66,0x81,0x05,A,A,A,A,0x00,0x80]
+; CHECK-NEXT: addw $-32768, g16(%rip) # encoding: [0x66,0x81,0x05,A,A,A,A,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x8000
; CHECK-NEXT: js .LBB11_1 # encoding: [0x78,A]
@@ -408,7 +408,7 @@ b:
define void @add16_imm8_br() nounwind {
; CHECK-LABEL: add16_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addw $42, {{.*}}(%rip) # encoding: [0x66,0x83,0x05,A,A,A,A,0x2a]
+; CHECK-NEXT: addw $42, g16(%rip) # encoding: [0x66,0x83,0x05,A,A,A,A,0x2a]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB12_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB12_1-1, kind: FK_PCRel_1
@@ -439,7 +439,7 @@ b:
define void @add16_imm8_neg_br() nounwind {
; CHECK-LABEL: add16_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addw $-42, {{.*}}(%rip) # encoding: [0x66,0x83,0x05,A,A,A,A,0xd6]
+; CHECK-NEXT: addw $-42, g16(%rip) # encoding: [0x66,0x83,0x05,A,A,A,A,0xd6]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB13_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB13_1-1, kind: FK_PCRel_1
@@ -470,7 +470,7 @@ b:
define void @add8_imm_br() nounwind {
; CHECK-LABEL: add8_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addb $-2, {{.*}}(%rip) # encoding: [0x80,0x05,A,A,A,A,0xfe]
+; CHECK-NEXT: addb $-2, g8(%rip) # encoding: [0x80,0x05,A,A,A,A,0xfe]
; CHECK-NEXT: # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB14_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB14_1-1, kind: FK_PCRel_1
@@ -501,7 +501,7 @@ b:
define void @add64_reg_br(i64 %arg) nounwind {
; CHECK-LABEL: add64_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq %rdi, {{.*}}(%rip) # encoding: [0x48,0x01,0x3d,A,A,A,A]
+; CHECK-NEXT: addq %rdi, g64(%rip) # encoding: [0x48,0x01,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB15_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB15_1-1, kind: FK_PCRel_1
@@ -532,7 +532,7 @@ b:
define void @add32_reg_br(i32 %arg) nounwind {
; CHECK-LABEL: add32_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl %edi, {{.*}}(%rip) # encoding: [0x01,0x3d,A,A,A,A]
+; CHECK-NEXT: addl %edi, g32(%rip) # encoding: [0x01,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB16_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB16_1-1, kind: FK_PCRel_1
@@ -563,7 +563,7 @@ b:
define void @add16_reg_br(i16 %arg) nounwind {
; CHECK-LABEL: add16_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addw %di, {{.*}}(%rip) # encoding: [0x66,0x01,0x3d,A,A,A,A]
+; CHECK-NEXT: addw %di, g16(%rip) # encoding: [0x66,0x01,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB17_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB17_1-1, kind: FK_PCRel_1
@@ -594,7 +594,7 @@ b:
define void @add8_reg_br(i8 %arg) nounwind {
; CHECK-LABEL: add8_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addb %dil, {{.*}}(%rip) # encoding: [0x40,0x00,0x3d,A,A,A,A]
+; CHECK-NEXT: addb %dil, g8(%rip) # encoding: [0x40,0x00,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB18_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB18_1-1, kind: FK_PCRel_1
@@ -625,7 +625,7 @@ b:
define void @sub64_imm32_br() nounwind {
; CHECK-LABEL: sub64_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $-2147483648, {{.*}}(%rip) # encoding: [0x48,0x81,0x2d,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: subq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x2d,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: js .LBB19_1 # encoding: [0x78,A]
@@ -661,7 +661,7 @@ define void @sub64_too_large_imm32_br() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movabsq $-4294967295, %rax # encoding: [0x48,0xb8,0x01,0x00,0x00,0x00,0xff,0xff,0xff,0xff]
; CHECK-NEXT: # imm = 0xFFFFFFFF00000001
-; CHECK-NEXT: addq %rax, {{.*}}(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
+; CHECK-NEXT: addq %rax, g64(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB20_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB20_1-1, kind: FK_PCRel_1
@@ -694,7 +694,7 @@ b:
define void @sub64_imm8_br() nounwind {
; CHECK-LABEL: sub64_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $-128, {{.*}}(%rip) # encoding: [0x48,0x83,0x2d,A,A,A,A,0x80]
+; CHECK-NEXT: subq $-128, g64(%rip) # encoding: [0x48,0x83,0x2d,A,A,A,A,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB21_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB21_1-1, kind: FK_PCRel_1
@@ -727,7 +727,7 @@ b:
define void @sub32_imm_br() nounwind {
; CHECK-LABEL: sub32_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $-2147483648, {{.*}}(%rip) # encoding: [0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: addl $-2147483648, g32(%rip) # encoding: [0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: js .LBB22_1 # encoding: [0x78,A]
@@ -761,7 +761,7 @@ b:
define void @sub32_imm8_br() nounwind {
; CHECK-LABEL: sub32_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subl $-128, {{.*}}(%rip) # encoding: [0x83,0x2d,A,A,A,A,0x80]
+; CHECK-NEXT: subl $-128, g32(%rip) # encoding: [0x83,0x2d,A,A,A,A,0x80]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB23_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB23_1-1, kind: FK_PCRel_1
@@ -794,7 +794,7 @@ b:
define void @sub16_imm_br() nounwind {
; CHECK-LABEL: sub16_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addw $-32768, {{.*}}(%rip) # encoding: [0x66,0x81,0x05,A,A,A,A,0x00,0x80]
+; CHECK-NEXT: addw $-32768, g16(%rip) # encoding: [0x66,0x81,0x05,A,A,A,A,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x8000
; CHECK-NEXT: js .LBB24_1 # encoding: [0x78,A]
@@ -828,7 +828,7 @@ b:
define void @sub16_imm8_br() nounwind {
; CHECK-LABEL: sub16_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subw $-128, {{.*}}(%rip) # encoding: [0x66,0x83,0x2d,A,A,A,A,0x80]
+; CHECK-NEXT: subw $-128, g16(%rip) # encoding: [0x66,0x83,0x2d,A,A,A,A,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB25_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB25_1-1, kind: FK_PCRel_1
@@ -861,7 +861,7 @@ b:
define void @sub8_imm_br() nounwind {
; CHECK-LABEL: sub8_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addb $-128, {{.*}}(%rip) # encoding: [0x80,0x05,A,A,A,A,0x80]
+; CHECK-NEXT: addb $-128, g8(%rip) # encoding: [0x80,0x05,A,A,A,A,0x80]
; CHECK-NEXT: # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB26_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB26_1-1, kind: FK_PCRel_1
@@ -894,7 +894,7 @@ b:
define void @sub64_reg_br(i64 %arg) nounwind {
; CHECK-LABEL: sub64_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq %rdi, {{.*}}(%rip) # encoding: [0x48,0x29,0x3d,A,A,A,A]
+; CHECK-NEXT: subq %rdi, g64(%rip) # encoding: [0x48,0x29,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB27_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB27_1-1, kind: FK_PCRel_1
@@ -925,7 +925,7 @@ b:
define void @sub32_reg_br(i32 %arg) nounwind {
; CHECK-LABEL: sub32_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subl %edi, {{.*}}(%rip) # encoding: [0x29,0x3d,A,A,A,A]
+; CHECK-NEXT: subl %edi, g32(%rip) # encoding: [0x29,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB28_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB28_1-1, kind: FK_PCRel_1
@@ -956,7 +956,7 @@ b:
define void @sub16_reg_br(i16 %arg) nounwind {
; CHECK-LABEL: sub16_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subw %di, {{.*}}(%rip) # encoding: [0x66,0x29,0x3d,A,A,A,A]
+; CHECK-NEXT: subw %di, g16(%rip) # encoding: [0x66,0x29,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB29_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB29_1-1, kind: FK_PCRel_1
@@ -987,7 +987,7 @@ b:
define void @sub8_reg_br(i8 %arg) nounwind {
; CHECK-LABEL: sub8_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subb %dil, {{.*}}(%rip) # encoding: [0x40,0x28,0x3d,A,A,A,A]
+; CHECK-NEXT: subb %dil, g8(%rip) # encoding: [0x40,0x28,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB30_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB30_1-1, kind: FK_PCRel_1
@@ -1018,7 +1018,7 @@ b:
define void @and64_imm32_br() nounwind {
; CHECK-LABEL: and64_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq $16777215, {{.*}}(%rip) # encoding: [0x48,0x81,0x25,A,A,A,A,0xff,0xff,0xff,0x00]
+; CHECK-NEXT: andq $16777215, g64(%rip) # encoding: [0x48,0x81,0x25,A,A,A,A,0xff,0xff,0xff,0x00]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0xFFFFFF
; CHECK-NEXT: je .LBB31_1 # encoding: [0x74,A]
@@ -1051,7 +1051,7 @@ b:
define void @and64_sext_imm32_br() nounwind {
; CHECK-LABEL: and64_sext_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq $-2147483648, {{.*}}(%rip) # encoding: [0x48,0x81,0x25,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: andq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x25,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: je .LBB32_1 # encoding: [0x74,A]
@@ -1084,7 +1084,7 @@ b:
define void @and64_imm8_br() nounwind {
; CHECK-LABEL: and64_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq $15, {{.*}}(%rip) # encoding: [0x48,0x83,0x25,A,A,A,A,0x0f]
+; CHECK-NEXT: andq $15, g64(%rip) # encoding: [0x48,0x83,0x25,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB33_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB33_1-1, kind: FK_PCRel_1
@@ -1115,7 +1115,7 @@ b:
define void @and64_imm8_neg_br() nounwind {
; CHECK-LABEL: and64_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq $-4, {{.*}}(%rip) # encoding: [0x48,0x83,0x25,A,A,A,A,0xfc]
+; CHECK-NEXT: andq $-4, g64(%rip) # encoding: [0x48,0x83,0x25,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB34_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB34_1-1, kind: FK_PCRel_1
@@ -1146,7 +1146,7 @@ b:
define void @and32_imm_br() nounwind {
; CHECK-LABEL: and32_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $-2147483648, {{.*}}(%rip) # encoding: [0x81,0x25,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: andl $-2147483648, g32(%rip) # encoding: [0x81,0x25,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: jne .LBB35_2 # encoding: [0x75,A]
@@ -1179,7 +1179,7 @@ b:
define void @and32_imm8_br() nounwind {
; CHECK-LABEL: and32_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $15, {{.*}}(%rip) # encoding: [0x83,0x25,A,A,A,A,0x0f]
+; CHECK-NEXT: andl $15, g32(%rip) # encoding: [0x83,0x25,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB36_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB36_1-1, kind: FK_PCRel_1
@@ -1210,7 +1210,7 @@ b:
define void @and32_imm8_neg_br() nounwind {
; CHECK-LABEL: and32_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $-4, {{.*}}(%rip) # encoding: [0x83,0x25,A,A,A,A,0xfc]
+; CHECK-NEXT: andl $-4, g32(%rip) # encoding: [0x83,0x25,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB37_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB37_1-1, kind: FK_PCRel_1
@@ -1241,7 +1241,7 @@ b:
define void @and16_imm_br() nounwind {
; CHECK-LABEL: and16_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw $-32768, {{.*}}(%rip) # encoding: [0x66,0x81,0x25,A,A,A,A,0x00,0x80]
+; CHECK-NEXT: andw $-32768, g16(%rip) # encoding: [0x66,0x81,0x25,A,A,A,A,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x8000
; CHECK-NEXT: jne .LBB38_2 # encoding: [0x75,A]
@@ -1273,7 +1273,7 @@ b:
define void @and16_imm8_br() nounwind {
; CHECK-LABEL: and16_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw $15, {{.*}}(%rip) # encoding: [0x66,0x83,0x25,A,A,A,A,0x0f]
+; CHECK-NEXT: andw $15, g16(%rip) # encoding: [0x66,0x83,0x25,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB39_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB39_1-1, kind: FK_PCRel_1
@@ -1304,7 +1304,7 @@ b:
define void @and16_imm8_neg_br() nounwind {
; CHECK-LABEL: and16_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw $-4, {{.*}}(%rip) # encoding: [0x66,0x83,0x25,A,A,A,A,0xfc]
+; CHECK-NEXT: andw $-4, g16(%rip) # encoding: [0x66,0x83,0x25,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB40_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB40_1-1, kind: FK_PCRel_1
@@ -1335,7 +1335,7 @@ b:
define void @and8_imm_br() nounwind {
; CHECK-LABEL: and8_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb $-4, {{.*}}(%rip) # encoding: [0x80,0x25,A,A,A,A,0xfc]
+; CHECK-NEXT: andb $-4, g8(%rip) # encoding: [0x80,0x25,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB41_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB41_1-1, kind: FK_PCRel_1
@@ -1366,7 +1366,7 @@ b:
define void @and64_reg_br(i64 %arg) nounwind {
; CHECK-LABEL: and64_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq %rdi, {{.*}}(%rip) # encoding: [0x48,0x21,0x3d,A,A,A,A]
+; CHECK-NEXT: andq %rdi, g64(%rip) # encoding: [0x48,0x21,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB42_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB42_1-1, kind: FK_PCRel_1
@@ -1397,7 +1397,7 @@ b:
define void @and32_reg_br(i32 %arg) nounwind {
; CHECK-LABEL: and32_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl %edi, {{.*}}(%rip) # encoding: [0x21,0x3d,A,A,A,A]
+; CHECK-NEXT: andl %edi, g32(%rip) # encoding: [0x21,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB43_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB43_1-1, kind: FK_PCRel_1
@@ -1428,7 +1428,7 @@ b:
define void @and16_reg_br(i16 %arg) nounwind {
; CHECK-LABEL: and16_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw %di, {{.*}}(%rip) # encoding: [0x66,0x21,0x3d,A,A,A,A]
+; CHECK-NEXT: andw %di, g16(%rip) # encoding: [0x66,0x21,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB44_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB44_1-1, kind: FK_PCRel_1
@@ -1459,7 +1459,7 @@ b:
define void @and8_reg_br(i8 %arg) nounwind {
; CHECK-LABEL: and8_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb %dil, {{.*}}(%rip) # encoding: [0x40,0x20,0x3d,A,A,A,A]
+; CHECK-NEXT: andb %dil, g8(%rip) # encoding: [0x40,0x20,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB45_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB45_1-1, kind: FK_PCRel_1
@@ -1490,7 +1490,7 @@ b:
define void @or64_imm32_br() nounwind {
; CHECK-LABEL: or64_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orq $16777215, {{.*}}(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
+; CHECK-NEXT: orq $16777215, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0xFFFFFF
; CHECK-NEXT: je .LBB46_1 # encoding: [0x74,A]
@@ -1523,7 +1523,7 @@ b:
define void @or64_sext_imm32_br() nounwind {
; CHECK-LABEL: or64_sext_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orq $-2147483648, {{.*}}(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: orq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: je .LBB47_1 # encoding: [0x74,A]
@@ -1556,7 +1556,7 @@ b:
define void @or64_imm8_br() nounwind {
; CHECK-LABEL: or64_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orq $15, {{.*}}(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT: orq $15, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB48_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB48_1-1, kind: FK_PCRel_1
@@ -1587,7 +1587,7 @@ b:
define void @or64_imm8_neg_br() nounwind {
; CHECK-LABEL: or64_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orq $-4, {{.*}}(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0xfc]
+; CHECK-NEXT: orq $-4, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB49_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB49_1-1, kind: FK_PCRel_1
@@ -1618,7 +1618,7 @@ b:
define void @or32_imm_br() nounwind {
; CHECK-LABEL: or32_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl $-2147483648, {{.*}}(%rip) # encoding: [0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: orl $-2147483648, g32(%rip) # encoding: [0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: je .LBB50_1 # encoding: [0x74,A]
@@ -1651,7 +1651,7 @@ b:
define void @or32_imm8_br() nounwind {
; CHECK-LABEL: or32_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl $15, {{.*}}(%rip) # encoding: [0x83,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT: orl $15, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB51_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB51_1-1, kind: FK_PCRel_1
@@ -1682,7 +1682,7 @@ b:
define void @or32_imm8_neg_br() nounwind {
; CHECK-LABEL: or32_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl $-4, {{.*}}(%rip) # encoding: [0x83,0x0d,A,A,A,A,0xfc]
+; CHECK-NEXT: orl $-4, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB52_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB52_1-1, kind: FK_PCRel_1
@@ -1713,7 +1713,7 @@ b:
define void @or16_imm_br() nounwind {
; CHECK-LABEL: or16_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orw $-32768, {{.*}}(%rip) # encoding: [0x66,0x81,0x0d,A,A,A,A,0x00,0x80]
+; CHECK-NEXT: orw $-32768, g16(%rip) # encoding: [0x66,0x81,0x0d,A,A,A,A,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x8000
; CHECK-NEXT: je .LBB53_1 # encoding: [0x74,A]
@@ -1745,7 +1745,7 @@ b:
define void @or16_imm8_br() nounwind {
; CHECK-LABEL: or16_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orw $15, {{.*}}(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT: orw $15, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB54_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB54_1-1, kind: FK_PCRel_1
@@ -1776,7 +1776,7 @@ b:
define void @or16_imm8_neg_br() nounwind {
; CHECK-LABEL: or16_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orw $-4, {{.*}}(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0xfc]
+; CHECK-NEXT: orw $-4, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB55_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB55_1-1, kind: FK_PCRel_1
@@ -1807,7 +1807,7 @@ b:
define void @or8_imm_br() nounwind {
; CHECK-LABEL: or8_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orb $-4, {{.*}}(%rip) # encoding: [0x80,0x0d,A,A,A,A,0xfc]
+; CHECK-NEXT: orb $-4, g8(%rip) # encoding: [0x80,0x0d,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB56_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB56_1-1, kind: FK_PCRel_1
@@ -1838,7 +1838,7 @@ b:
define void @or64_reg_br(i64 %arg) nounwind {
; CHECK-LABEL: or64_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orq %rdi, {{.*}}(%rip) # encoding: [0x48,0x09,0x3d,A,A,A,A]
+; CHECK-NEXT: orq %rdi, g64(%rip) # encoding: [0x48,0x09,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB57_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB57_1-1, kind: FK_PCRel_1
@@ -1869,7 +1869,7 @@ b:
define void @or32_reg_br(i32 %arg) nounwind {
; CHECK-LABEL: or32_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl %edi, {{.*}}(%rip) # encoding: [0x09,0x3d,A,A,A,A]
+; CHECK-NEXT: orl %edi, g32(%rip) # encoding: [0x09,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB58_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB58_1-1, kind: FK_PCRel_1
@@ -1900,7 +1900,7 @@ b:
define void @or16_reg_br(i16 %arg) nounwind {
; CHECK-LABEL: or16_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orw %di, {{.*}}(%rip) # encoding: [0x66,0x09,0x3d,A,A,A,A]
+; CHECK-NEXT: orw %di, g16(%rip) # encoding: [0x66,0x09,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB59_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB59_1-1, kind: FK_PCRel_1
@@ -1931,7 +1931,7 @@ b:
define void @or8_reg_br(i8 %arg) nounwind {
; CHECK-LABEL: or8_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orb %dil, {{.*}}(%rip) # encoding: [0x40,0x08,0x3d,A,A,A,A]
+; CHECK-NEXT: orb %dil, g8(%rip) # encoding: [0x40,0x08,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB60_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB60_1-1, kind: FK_PCRel_1
@@ -1962,7 +1962,7 @@ b:
define void @xor64_imm32_br() nounwind {
; CHECK-LABEL: xor64_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorq $16777215, {{.*}}(%rip) # encoding: [0x48,0x81,0x35,A,A,A,A,0xff,0xff,0xff,0x00]
+; CHECK-NEXT: xorq $16777215, g64(%rip) # encoding: [0x48,0x81,0x35,A,A,A,A,0xff,0xff,0xff,0x00]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0xFFFFFF
; CHECK-NEXT: je .LBB61_1 # encoding: [0x74,A]
@@ -1995,7 +1995,7 @@ b:
define void @xor64_sext_imm32_br() nounwind {
; CHECK-LABEL: xor64_sext_imm32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorq $-2147483648, {{.*}}(%rip) # encoding: [0x48,0x81,0x35,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: xorq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x35,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: je .LBB62_1 # encoding: [0x74,A]
@@ -2028,7 +2028,7 @@ b:
define void @xor64_imm8_br() nounwind {
; CHECK-LABEL: xor64_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorq $15, {{.*}}(%rip) # encoding: [0x48,0x83,0x35,A,A,A,A,0x0f]
+; CHECK-NEXT: xorq $15, g64(%rip) # encoding: [0x48,0x83,0x35,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB63_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB63_1-1, kind: FK_PCRel_1
@@ -2059,7 +2059,7 @@ b:
define void @xor64_imm8_neg_br() nounwind {
; CHECK-LABEL: xor64_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorq $-4, {{.*}}(%rip) # encoding: [0x48,0x83,0x35,A,A,A,A,0xfc]
+; CHECK-NEXT: xorq $-4, g64(%rip) # encoding: [0x48,0x83,0x35,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB64_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB64_1-1, kind: FK_PCRel_1
@@ -2090,7 +2090,7 @@ b:
define void @xor32_imm_br() nounwind {
; CHECK-LABEL: xor32_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorl $-2147483648, {{.*}}(%rip) # encoding: [0x81,0x35,A,A,A,A,0x00,0x00,0x00,0x80]
+; CHECK-NEXT: xorl $-2147483648, g32(%rip) # encoding: [0x81,0x35,A,A,A,A,0x00,0x00,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x80000000
; CHECK-NEXT: je .LBB65_1 # encoding: [0x74,A]
@@ -2123,7 +2123,7 @@ b:
define void @xor32_imm8_br() nounwind {
; CHECK-LABEL: xor32_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorl $15, {{.*}}(%rip) # encoding: [0x83,0x35,A,A,A,A,0x0f]
+; CHECK-NEXT: xorl $15, g32(%rip) # encoding: [0x83,0x35,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB66_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB66_1-1, kind: FK_PCRel_1
@@ -2154,7 +2154,7 @@ b:
define void @xor32_imm8_neg_br() nounwind {
; CHECK-LABEL: xor32_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorl $-4, {{.*}}(%rip) # encoding: [0x83,0x35,A,A,A,A,0xfc]
+; CHECK-NEXT: xorl $-4, g32(%rip) # encoding: [0x83,0x35,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB67_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB67_1-1, kind: FK_PCRel_1
@@ -2185,7 +2185,7 @@ b:
define void @xor16_imm_br() nounwind {
; CHECK-LABEL: xor16_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorw $-32768, {{.*}}(%rip) # encoding: [0x66,0x81,0x35,A,A,A,A,0x00,0x80]
+; CHECK-NEXT: xorw $-32768, g16(%rip) # encoding: [0x66,0x81,0x35,A,A,A,A,0x00,0x80]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
; CHECK-NEXT: # imm = 0x8000
; CHECK-NEXT: je .LBB68_1 # encoding: [0x74,A]
@@ -2217,7 +2217,7 @@ b:
define void @xor16_imm8_br() nounwind {
; CHECK-LABEL: xor16_imm8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorw $15, {{.*}}(%rip) # encoding: [0x66,0x83,0x35,A,A,A,A,0x0f]
+; CHECK-NEXT: xorw $15, g16(%rip) # encoding: [0x66,0x83,0x35,A,A,A,A,0x0f]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB69_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB69_1-1, kind: FK_PCRel_1
@@ -2248,7 +2248,7 @@ b:
define void @xor16_imm8_neg_br() nounwind {
; CHECK-LABEL: xor16_imm8_neg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorw $-4, {{.*}}(%rip) # encoding: [0x66,0x83,0x35,A,A,A,A,0xfc]
+; CHECK-NEXT: xorw $-4, g16(%rip) # encoding: [0x66,0x83,0x35,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB70_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB70_1-1, kind: FK_PCRel_1
@@ -2279,7 +2279,7 @@ b:
define void @xor8_imm_br() nounwind {
; CHECK-LABEL: xor8_imm_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorb $-4, {{.*}}(%rip) # encoding: [0x80,0x35,A,A,A,A,0xfc]
+; CHECK-NEXT: xorb $-4, g8(%rip) # encoding: [0x80,0x35,A,A,A,A,0xfc]
; CHECK-NEXT: # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB71_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB71_1-1, kind: FK_PCRel_1
@@ -2310,7 +2310,7 @@ b:
define void @xor64_reg_br(i64 %arg) nounwind {
; CHECK-LABEL: xor64_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorq %rdi, {{.*}}(%rip) # encoding: [0x48,0x31,0x3d,A,A,A,A]
+; CHECK-NEXT: xorq %rdi, g64(%rip) # encoding: [0x48,0x31,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB72_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB72_1-1, kind: FK_PCRel_1
@@ -2341,7 +2341,7 @@ b:
define void @xor32_reg_br(i32 %arg) nounwind {
; CHECK-LABEL: xor32_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorl %edi, {{.*}}(%rip) # encoding: [0x31,0x3d,A,A,A,A]
+; CHECK-NEXT: xorl %edi, g32(%rip) # encoding: [0x31,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB73_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB73_1-1, kind: FK_PCRel_1
@@ -2372,7 +2372,7 @@ b:
define void @xor16_reg_br(i16 %arg) nounwind {
; CHECK-LABEL: xor16_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorw %di, {{.*}}(%rip) # encoding: [0x66,0x31,0x3d,A,A,A,A]
+; CHECK-NEXT: xorw %di, g16(%rip) # encoding: [0x66,0x31,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB74_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB74_1-1, kind: FK_PCRel_1
@@ -2403,7 +2403,7 @@ b:
define void @xor8_reg_br(i8 %arg) nounwind {
; CHECK-LABEL: xor8_reg_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorb %dil, {{.*}}(%rip) # encoding: [0x40,0x30,0x3d,A,A,A,A]
+; CHECK-NEXT: xorb %dil, g8(%rip) # encoding: [0x40,0x30,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
; CHECK-NEXT: je .LBB75_1 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB75_1-1, kind: FK_PCRel_1
@@ -2434,7 +2434,7 @@ b:
define void @neg64_br() nounwind {
; CHECK-LABEL: neg64_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negq {{.*}}(%rip) # encoding: [0x48,0xf7,0x1d,A,A,A,A]
+; CHECK-NEXT: negq g64(%rip) # encoding: [0x48,0xf7,0x1d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB76_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB76_1-1, kind: FK_PCRel_1
@@ -2465,7 +2465,7 @@ b:
define void @neg32_br() nounwind {
; CHECK-LABEL: neg32_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negl {{.*}}(%rip) # encoding: [0xf7,0x1d,A,A,A,A]
+; CHECK-NEXT: negl g32(%rip) # encoding: [0xf7,0x1d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB77_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB77_1-1, kind: FK_PCRel_1
@@ -2496,7 +2496,7 @@ b:
define void @neg16_br() nounwind {
; CHECK-LABEL: neg16_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negw {{.*}}(%rip) # encoding: [0x66,0xf7,0x1d,A,A,A,A]
+; CHECK-NEXT: negw g16(%rip) # encoding: [0x66,0xf7,0x1d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB78_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB78_1-1, kind: FK_PCRel_1
@@ -2527,7 +2527,7 @@ b:
define void @neg8_br() nounwind {
; CHECK-LABEL: neg8_br:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negb {{.*}}(%rip) # encoding: [0xf6,0x1d,A,A,A,A]
+; CHECK-NEXT: negb g8(%rip) # encoding: [0xf6,0x1d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: g8-4, kind: reloc_riprel_4byte
; CHECK-NEXT: js .LBB79_1 # encoding: [0x78,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB79_1-1, kind: FK_PCRel_1
diff --git a/llvm/test/CodeGen/X86/fp-cvt.ll b/llvm/test/CodeGen/X86/fp-cvt.ll
index facb84d6f104c..a5247851a6231 100644
--- a/llvm/test/CodeGen/X86/fp-cvt.ll
+++ b/llvm/test/CodeGen/X86/fp-cvt.ll
@@ -443,7 +443,7 @@ define i64 @fptoui_i64_fp80(x86_fp80 %a0) nounwind {
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp
; X86-NEXT: fldt 8(%ebp)
-; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fucom %st(1)
; X86-NEXT: fnstsw %ax
; X86-NEXT: xorl %edx, %edx
@@ -476,7 +476,7 @@ define i64 @fptoui_i64_fp80(x86_fp80 %a0) nounwind {
; X64-X87-LABEL: fptoui_i64_fp80:
; X64-X87: # %bb.0:
; X64-X87-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-X87-NEXT: flds {{.*}}(%rip)
+; X64-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-X87-NEXT: xorl %eax, %eax
; X64-X87-NEXT: fucomi %st(1), %st
; X64-X87-NEXT: setbe %al
@@ -498,7 +498,7 @@ define i64 @fptoui_i64_fp80(x86_fp80 %a0) nounwind {
; X64-SSSE3-LABEL: fptoui_i64_fp80:
; X64-SSSE3: # %bb.0:
; X64-SSSE3-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-SSSE3-NEXT: flds {{.*}}(%rip)
+; X64-SSSE3-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-SSSE3-NEXT: xorl %eax, %eax
; X64-SSSE3-NEXT: fucomi %st(1), %st
; X64-SSSE3-NEXT: fldz
@@ -523,7 +523,7 @@ define i64 @fptoui_i64_fp80_ld(x86_fp80 *%a0) nounwind {
; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: fldt (%eax)
-; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fucom %st(1)
; X86-NEXT: fnstsw %ax
; X86-NEXT: xorl %edx, %edx
@@ -556,7 +556,7 @@ define i64 @fptoui_i64_fp80_ld(x86_fp80 *%a0) nounwind {
; X64-X87-LABEL: fptoui_i64_fp80_ld:
; X64-X87: # %bb.0:
; X64-X87-NEXT: fldt (%rdi)
-; X64-X87-NEXT: flds {{.*}}(%rip)
+; X64-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-X87-NEXT: xorl %eax, %eax
; X64-X87-NEXT: fucomi %st(1), %st
; X64-X87-NEXT: setbe %al
@@ -578,7 +578,7 @@ define i64 @fptoui_i64_fp80_ld(x86_fp80 *%a0) nounwind {
; X64-SSSE3-LABEL: fptoui_i64_fp80_ld:
; X64-SSSE3: # %bb.0:
; X64-SSSE3-NEXT: fldt (%rdi)
-; X64-SSSE3-NEXT: flds {{.*}}(%rip)
+; X64-SSSE3-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-SSSE3-NEXT: xorl %eax, %eax
; X64-SSSE3-NEXT: fucomi %st(1), %st
; X64-SSSE3-NEXT: fldz
@@ -825,7 +825,7 @@ define x86_fp80 @uitofp_fp80_i64(i64 %a0) nounwind {
; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: shrl $31, %ecx
; X86-NEXT: fildll (%esp)
-; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
@@ -837,7 +837,7 @@ define x86_fp80 @uitofp_fp80_i64(i64 %a0) nounwind {
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: sets %al
; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
-; X64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rax,4)
+; X64-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%rax,4)
; X64-NEXT: retq
%1 = uitofp i64 %a0 to x86_fp80
ret x86_fp80 %1
@@ -857,7 +857,7 @@ define x86_fp80 @uitofp_fp80_i64_ld(i64 *%a0) nounwind {
; X86-NEXT: movl %ecx, (%esp)
; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll (%esp)
-; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
@@ -870,7 +870,7 @@ define x86_fp80 @uitofp_fp80_i64_ld(i64 *%a0) nounwind {
; X64-NEXT: testq %rax, %rax
; X64-NEXT: sets %cl
; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
-; X64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rcx,4)
+; X64-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%rcx,4)
; X64-NEXT: retq
%1 = load i64, i64 *%a0
%2 = uitofp i64 %1 to x86_fp80
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics-fma.ll b/llvm/test/CodeGen/X86/fp-intrinsics-fma.ll
index bc16cd768dcb9..2253d7cbaf8b6 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics-fma.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics-fma.ll
@@ -9,8 +9,8 @@ define float @f1(float %0, float %1, float %2) #0 {
; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: pushq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 16
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm0
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -37,8 +37,8 @@ define double @f2(double %0, double %1, double %2) #0 {
; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: pushq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 16
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm0
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -65,8 +65,8 @@ define float @f3(float %0, float %1, float %2) #0 {
; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: pushq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 16
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm2
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -93,8 +93,8 @@ define double @f4(double %0, double %1, double %2) #0 {
; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: pushq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 16
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm2
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -124,7 +124,7 @@ define float @f5(float %0, float %1, float %2) #0 {
; NOFMA-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; NOFMA-NEXT: xorps %xmm3, %xmm0
; NOFMA-NEXT: xorps %xmm3, %xmm2
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -155,7 +155,7 @@ define double @f6(double %0, double %1, double %2) #0 {
; NOFMA-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0]
; NOFMA-NEXT: xorps %xmm3, %xmm0
; NOFMA-NEXT: xorps %xmm3, %xmm2
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -183,8 +183,8 @@ define float @f7(float %0, float %1, float %2) #0 {
; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: pushq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 16
-; NOFMA-NEXT: callq fmaf
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm0
+; NOFMA-NEXT: callq fmaf at PLT
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -192,13 +192,13 @@ define float @f7(float %0, float %1, float %2) #0 {
; FMA-AVX1-LABEL: f7:
; FMA-AVX1: # %bb.0: # %entry
; FMA-AVX1-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
-; FMA-AVX1-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-AVX1-NEXT: retq
;
; FMA4-LABEL: f7:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfmaddss {{.*#+}} xmm0 = (xmm0 * xmm1) + xmm2
-; FMA4-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
;
; FMA-AVX512-LABEL: f7:
@@ -220,8 +220,8 @@ define double @f8(double %0, double %1, double %2) #0 {
; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: pushq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 16
-; NOFMA-NEXT: callq fma
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm0
+; NOFMA-NEXT: callq fma at PLT
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -229,13 +229,13 @@ define double @f8(double %0, double %1, double %2) #0 {
; FMA-LABEL: f8:
; FMA: # %bb.0: # %entry
; FMA-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
-; FMA-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-NEXT: retq
;
; FMA4-LABEL: f8:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfmaddsd {{.*#+}} xmm0 = (xmm0 * xmm1) + xmm2
-; FMA4-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
entry:
%3 = call double @llvm.experimental.constrained.fma.f64(double %0, double %1, double %2,
@@ -253,8 +253,8 @@ define float @f9(float %0, float %1, float %2) #0 {
; NOFMA-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; NOFMA-NEXT: xorps %xmm3, %xmm0
; NOFMA-NEXT: xorps %xmm3, %xmm2
-; NOFMA-NEXT: callq fmaf
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm0
+; NOFMA-NEXT: callq fmaf at PLT
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -262,13 +262,13 @@ define float @f9(float %0, float %1, float %2) #0 {
; FMA-AVX1-LABEL: f9:
; FMA-AVX1: # %bb.0: # %entry
; FMA-AVX1-NEXT: vfnmsub213ss {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
-; FMA-AVX1-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-AVX1-NEXT: retq
;
; FMA4-LABEL: f9:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfnmsubss {{.*#+}} xmm0 = -(xmm0 * xmm1) - xmm2
-; FMA4-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
;
; FMA-AVX512-LABEL: f9:
@@ -295,8 +295,8 @@ define double @f10(double %0, double %1, double %2) #0 {
; NOFMA-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0]
; NOFMA-NEXT: xorps %xmm3, %xmm0
; NOFMA-NEXT: xorps %xmm3, %xmm2
-; NOFMA-NEXT: callq fma
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm0
+; NOFMA-NEXT: callq fma at PLT
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -304,13 +304,13 @@ define double @f10(double %0, double %1, double %2) #0 {
; FMA-LABEL: f10:
; FMA: # %bb.0: # %entry
; FMA-NEXT: vfnmsub213sd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
-; FMA-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-NEXT: retq
;
; FMA4-LABEL: f10:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfnmsubsd {{.*#+}} xmm0 = -(xmm0 * xmm1) - xmm2
-; FMA4-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
entry:
%3 = fneg double %0
@@ -454,7 +454,7 @@ define float @f17() #0 {
; NOFMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NOFMA-NEXT: movaps %xmm0, %xmm1
; NOFMA-NEXT: movaps %xmm0, %xmm2
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -490,7 +490,7 @@ define double @f18() #0 {
; NOFMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NOFMA-NEXT: movaps %xmm0, %xmm1
; NOFMA-NEXT: movaps %xmm0, %xmm2
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: popq %rax
; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq
@@ -523,12 +523,12 @@ define <4 x float> @f19(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: .cfi_def_cfa_offset 96
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; NOFMA-NEXT: pxor {{.*}}(%rip), %xmm0
+; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
@@ -536,14 +536,14 @@ define <4 x float> @f19(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: punpckldq (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
@@ -551,7 +551,7 @@ define <4 x float> @f19(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[1,1,1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: punpcklqdq (%rsp), %xmm1 # 16-byte Folded Reload
@@ -585,9 +585,9 @@ define <2 x double> @f20(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: .cfi_def_cfa_offset 80
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm0
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
@@ -595,7 +595,7 @@ define <2 x double> @f20(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; NOFMA-NEXT: movdqa %xmm1, %xmm0
@@ -627,12 +627,12 @@ define <4 x float> @f21(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: .cfi_def_cfa_offset 96
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; NOFMA-NEXT: pxor {{.*}}(%rip), %xmm2
+; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; NOFMA-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[3,3,3,3]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
@@ -640,14 +640,14 @@ define <4 x float> @f21(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
@@ -655,7 +655,7 @@ define <4 x float> @f21(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[1,1,1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
@@ -689,9 +689,9 @@ define <2 x double> @f22(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: .cfi_def_cfa_offset 80
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm2
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
@@ -699,7 +699,7 @@ define <2 x double> @f22(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; NOFMA-NEXT: movaps %xmm1, %xmm0
@@ -738,7 +738,7 @@ define <4 x float> @f23(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[3,3,3,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
@@ -746,14 +746,14 @@ define <4 x float> @f23(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: punpckldq (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[1,1,1,1]
@@ -761,7 +761,7 @@ define <4 x float> @f23(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: # xmm2 = mem[1,1,1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: punpcklqdq (%rsp), %xmm1 # 16-byte Folded Reload
@@ -800,7 +800,7 @@ define <2 x double> @f24(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: xorps %xmm3, %xmm2
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
@@ -808,7 +808,7 @@ define <2 x double> @f24(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; NOFMA-NEXT: movdqa %xmm1, %xmm0
@@ -845,7 +845,7 @@ define <4 x float> @f25(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
@@ -853,14 +853,14 @@ define <4 x float> @f25(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
@@ -868,12 +868,12 @@ define <4 x float> @f25(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0]
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm1
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; NOFMA-NEXT: movaps %xmm1, %xmm0
; NOFMA-NEXT: addq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8
@@ -882,13 +882,13 @@ define <4 x float> @f25(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; FMA-AVX1-LABEL: f25:
; FMA-AVX1: # %bb.0: # %entry
; FMA-AVX1-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
-; FMA-AVX1-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-AVX1-NEXT: retq
;
; FMA4-LABEL: f25:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfmaddps {{.*#+}} xmm0 = (xmm0 * xmm1) + xmm2
-; FMA4-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
;
; FMA-AVX512-LABEL: f25:
@@ -913,7 +913,7 @@ define <2 x double> @f26(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
@@ -921,10 +921,10 @@ define <2 x double> @f26(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; NOFMA-NEXT: xorps {{.*}}(%rip), %xmm1
+; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; NOFMA-NEXT: movaps %xmm1, %xmm0
; NOFMA-NEXT: addq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8
@@ -933,13 +933,13 @@ define <2 x double> @f26(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; FMA-LABEL: f26:
; FMA: # %bb.0: # %entry
; FMA-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
-; FMA-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-NEXT: retq
;
; FMA4-LABEL: f26:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfmaddpd {{.*#+}} xmm0 = (xmm0 * xmm1) + xmm2
-; FMA4-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
entry:
%3 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %0, <2 x double> %1, <2 x double> %2,
@@ -963,7 +963,7 @@ define <4 x float> @f27(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[3,3,3,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
@@ -971,14 +971,14 @@ define <4 x float> @f27(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: punpckldq (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[1,1,1,1]
@@ -986,12 +986,12 @@ define <4 x float> @f27(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-NEXT: # xmm2 = mem[1,1,1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; NOFMA-NEXT: callq fmaf
+; NOFMA-NEXT: callq fmaf at PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: punpcklqdq (%rsp), %xmm1 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0]
-; NOFMA-NEXT: pxor {{.*}}(%rip), %xmm1
+; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; NOFMA-NEXT: movdqa %xmm1, %xmm0
; NOFMA-NEXT: addq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8
@@ -1000,13 +1000,13 @@ define <4 x float> @f27(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; FMA-AVX1-LABEL: f27:
; FMA-AVX1: # %bb.0: # %entry
; FMA-AVX1-NEXT: vfnmsub213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
-; FMA-AVX1-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-AVX1-NEXT: retq
;
; FMA4-LABEL: f27:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfnmsubps {{.*#+}} xmm0 = -(xmm0 * xmm1) - xmm2
-; FMA4-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
;
; FMA-AVX512-LABEL: f27:
@@ -1036,7 +1036,7 @@ define <2 x double> @f28(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: xorps %xmm3, %xmm2
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
@@ -1044,10 +1044,10 @@ define <2 x double> @f28(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; NOFMA-NEXT: callq fma
+; NOFMA-NEXT: callq fma at PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; NOFMA-NEXT: pxor {{.*}}(%rip), %xmm1
+; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; NOFMA-NEXT: movdqa %xmm1, %xmm0
; NOFMA-NEXT: addq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8
@@ -1056,13 +1056,13 @@ define <2 x double> @f28(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; FMA-LABEL: f28:
; FMA: # %bb.0: # %entry
; FMA-NEXT: vfnmsub213pd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
-; FMA-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA-NEXT: retq
;
; FMA4-LABEL: f28:
; FMA4: # %bb.0: # %entry
; FMA4-NEXT: vfnmsubpd {{.*#+}} xmm0 = -(xmm0 * xmm1) - xmm2
-; FMA4-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; FMA4-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; FMA4-NEXT: retq
entry:
%3 = fneg <2 x double> %0
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics.ll b/llvm/test/CodeGen/X86/fp-intrinsics.ll
index e2fdb904dabcb..af9a640fd1cd7 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics.ll
@@ -18,7 +18,7 @@ define double @f1() #0 {
; X87-LABEL: f1:
; X87: # %bb.0: # %entry
; X87-NEXT: fld1
-; X87-NEXT: fdivs {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: fdivs {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: wait
; X87-NEXT: retl
;
@@ -27,7 +27,7 @@ define double @f1() #0 {
; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT: divsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp)
; X86-SSE-NEXT: wait
@@ -38,13 +38,13 @@ define double @f1() #0 {
; SSE-LABEL: f1:
; SSE: # %bb.0: # %entry
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: divsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: f1:
; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vdivsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
entry:
%div = call double @llvm.experimental.constrained.fdiv.f64(
@@ -209,7 +209,7 @@ define double @f4(i32 %n, double %a) #0 {
; X86-SSE-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: jle .LBB3_2
; X86-SSE-NEXT: # %bb.1: # %if.then
-; X86-SSE-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: .LBB3_2: # %if.end
; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp)
@@ -223,7 +223,7 @@ define double @f4(i32 %n, double %a) #0 {
; SSE-NEXT: testl %edi, %edi
; SSE-NEXT: jle .LBB3_2
; SSE-NEXT: # %bb.1: # %if.then
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: .LBB3_2: # %if.end
; SSE-NEXT: retq
;
@@ -232,7 +232,7 @@ define double @f4(i32 %n, double %a) #0 {
; AVX-NEXT: testl %edi, %edi
; AVX-NEXT: jle .LBB3_2
; AVX-NEXT: # %bb.1: # %if.then
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: .LBB3_2: # %if.end
; AVX-NEXT: retq
entry:
@@ -255,7 +255,7 @@ if.end:
define double @f5() #0 {
; X87-LABEL: f5:
; X87: # %bb.0: # %entry
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fsqrt
; X87-NEXT: wait
; X87-NEXT: retl
@@ -297,9 +297,9 @@ define double @f6() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $28, %esp
; X87-NEXT: .cfi_def_cfa_offset 32
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
-; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll pow
@@ -355,7 +355,7 @@ define double @f7() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: movl $3, {{[0-9]+}}(%esp)
@@ -411,7 +411,7 @@ define double @f8() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll sin
@@ -462,7 +462,7 @@ define double @f9() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll cos
@@ -513,7 +513,7 @@ define double @f10() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll exp
@@ -564,7 +564,7 @@ define double @f11() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll exp2
@@ -615,7 +615,7 @@ define double @f12() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll log
@@ -666,7 +666,7 @@ define double @f13() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll log10
@@ -717,7 +717,7 @@ define double @f14() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll log2
@@ -768,7 +768,7 @@ define double @f15() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll rint
@@ -816,7 +816,7 @@ define double @f16() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait
; X87-NEXT: calll nearbyint
@@ -863,7 +863,7 @@ define double @f19() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $28, %esp
; X87-NEXT: .cfi_def_cfa_offset 32
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: movl $1072693248, {{[0-9]+}}(%esp) # imm = 0x3FF00000
@@ -1356,7 +1356,7 @@ define i64 @f20u64(double %x) #0 {
; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24
; X87-NEXT: fldl {{[0-9]+}}(%esp)
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: wait
; X87-NEXT: xorl %edx, %edx
; X87-NEXT: fcomi %st(1), %st
@@ -1541,7 +1541,7 @@ define float @f21() #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8
-; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstps (%esp)
; X87-NEXT: flds (%esp)
; X87-NEXT: wait
@@ -2437,8 +2437,8 @@ define double @uifdi(i32 %x) #0 {
; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp)
; X86-SSE-NEXT: wait
@@ -2480,7 +2480,7 @@ define double @uifdl(i64 %x) #0 {
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
-; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: wait
@@ -2497,7 +2497,7 @@ define double @uifdl(i64 %x) #0 {
; X86-SSE-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: shrl $31, %eax
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-SSE-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
@@ -2658,8 +2658,8 @@ define float @uiffi(i32 %x) #0 {
; X86-SSE-NEXT: pushl %eax
; X86-SSE-NEXT: .cfi_def_cfa_offset 8
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtsd2ss %xmm0, %xmm0
; X86-SSE-NEXT: movss %xmm0, (%esp)
; X86-SSE-NEXT: flds (%esp)
@@ -2702,7 +2702,7 @@ define float @uiffl(i64 %x) #0 {
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
-; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: wait
@@ -2719,7 +2719,7 @@ define float @uiffl(i64 %x) #0 {
; X86-SSE-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: shrl $31, %eax
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-SSE-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
diff --git a/llvm/test/CodeGen/X86/fp-logic.ll b/llvm/test/CodeGen/X86/fp-logic.ll
index 59a77a614783e..7fef4269f6565 100644
--- a/llvm/test/CodeGen/X86/fp-logic.ll
+++ b/llvm/test/CodeGen/X86/fp-logic.ll
@@ -243,7 +243,7 @@ define float @movmsk(float %x) {
define double @bitcast_fabs(double %x) {
; CHECK-LABEL: bitcast_fabs:
; CHECK: # %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast double %x to i64
%and = and i64 %bc1, 9223372036854775807
@@ -254,7 +254,7 @@ define double @bitcast_fabs(double %x) {
define float @bitcast_fneg(float %x) {
; CHECK-LABEL: bitcast_fneg:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast float %x to i32
%xor = xor i32 %bc1, 2147483648
@@ -265,7 +265,7 @@ define float @bitcast_fneg(float %x) {
define <2 x double> @bitcast_fabs_vec(<2 x double> %x) {
; CHECK-LABEL: bitcast_fabs_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <2 x double> %x to <2 x i64>
%and = and <2 x i64> %bc1, <i64 9223372036854775807, i64 9223372036854775807>
@@ -276,7 +276,7 @@ define <2 x double> @bitcast_fabs_vec(<2 x double> %x) {
define <4 x float> @bitcast_fneg_vec(<4 x float> %x) {
; CHECK-LABEL: bitcast_fneg_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %x to <4 x i32>
%xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
@@ -311,7 +311,7 @@ define float @fsub_bitcast_fneg(float %x, float %y) {
define float @nabsf(float %a) {
; CHECK-LABEL: nabsf:
; CHECK: # %bb.0:
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%conv = bitcast float %a to i32
%and = or i32 %conv, -2147483648
@@ -322,7 +322,7 @@ define float @nabsf(float %a) {
define double @nabsd(double %a) {
; CHECK-LABEL: nabsd:
; CHECK: # %bb.0:
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%conv = bitcast double %a to i64
%and = or i64 %conv, -9223372036854775808
@@ -333,7 +333,7 @@ define double @nabsd(double %a) {
define <4 x float> @nabsv4f32(<4 x float> %a) {
; CHECK-LABEL: nabsv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%conv = bitcast <4 x float> %a to <4 x i32>
%and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
@@ -344,7 +344,7 @@ define <4 x float> @nabsv4f32(<4 x float> %a) {
define <2 x double> @nabsv2d64(<2 x double> %a) {
; CHECK-LABEL: nabsv2d64:
; CHECK: # %bb.0:
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%conv = bitcast <2 x double> %a to <2 x i64>
%and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
@@ -403,7 +403,7 @@ define <4 x float> @fsub_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float>
define <4 x float> @fadd_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: fadd_bitcast_fneg_vec_width:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: addps %xmm1, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %y to <2 x i64>
@@ -416,7 +416,7 @@ define <4 x float> @fadd_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y)
define <4 x float> @fsub_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: fsub_bitcast_fneg_vec_width:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: subps %xmm1, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %y to <2 x i64>
diff --git a/llvm/test/CodeGen/X86/fp-round.ll b/llvm/test/CodeGen/X86/fp-round.ll
index 255ad732f9d62..2da2bdf439d0c 100644
--- a/llvm/test/CodeGen/X86/fp-round.ll
+++ b/llvm/test/CodeGen/X86/fp-round.ll
@@ -13,7 +13,7 @@ define float @round_f32(float %x) {
; SSE41: ## %bb.0:
; SSE41-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; SSE41-NEXT: andps %xmm0, %xmm1
-; SSE41-NEXT: orps {{.*}}(%rip), %xmm1
+; SSE41-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: addss %xmm0, %xmm1
; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: roundss $11, %xmm1, %xmm0
@@ -21,7 +21,7 @@ define float @round_f32(float %x) {
;
; AVX1-LABEL: round_f32:
; AVX1: ## %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1]
; AVX1-NEXT: vorps %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm0
@@ -50,7 +50,7 @@ define double @round_f64(double %x) {
; SSE41: ## %bb.0:
; SSE41-NEXT: movapd {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0]
; SSE41-NEXT: andpd %xmm0, %xmm1
-; SSE41-NEXT: orpd {{.*}}(%rip), %xmm1
+; SSE41-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: addsd %xmm0, %xmm1
; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: roundsd $11, %xmm1, %xmm0
@@ -58,7 +58,7 @@ define double @round_f64(double %x) {
;
; AVX-LABEL: round_f64:
; AVX: ## %bb.0:
-; AVX-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [4.9999999999999994E-1,4.9999999999999994E-1]
; AVX-NEXT: ## xmm2 = mem[0,0]
; AVX-NEXT: vorpd %xmm1, %xmm2, %xmm1
@@ -102,15 +102,15 @@ define <4 x float> @round_v4f32(<4 x float> %x) {
; SSE41: ## %bb.0:
; SSE41-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; SSE41-NEXT: andps %xmm0, %xmm1
-; SSE41-NEXT: orps {{.*}}(%rip), %xmm1
+; SSE41-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: addps %xmm0, %xmm1
; SSE41-NEXT: roundps $11, %xmm1, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: round_v4f32:
; AVX1: ## %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm1
-; AVX1-NEXT: vorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vroundps $11, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -149,15 +149,15 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; SSE41: ## %bb.0:
; SSE41-NEXT: movapd {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0]
; SSE41-NEXT: andpd %xmm0, %xmm1
-; SSE41-NEXT: orpd {{.*}}(%rip), %xmm1
+; SSE41-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: addpd %xmm0, %xmm1
; SSE41-NEXT: roundpd $11, %xmm1, %xmm0
; SSE41-NEXT: retq
;
; AVX-LABEL: round_v2f64:
; AVX: ## %bb.0:
-; AVX-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm1
-; AVX-NEXT: vorpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX-NEXT: retq
@@ -233,8 +233,8 @@ define <8 x float> @round_v8f32(<8 x float> %x) {
;
; AVX1-LABEL: round_v8f32:
; AVX1: ## %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm1
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vroundps $11, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -296,8 +296,8 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
;
; AVX1-LABEL: round_v4f64:
; AVX1: ## %bb.0:
-; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm1
-; AVX1-NEXT: vorpd {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX1-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vroundpd $11, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -454,7 +454,7 @@ define <16 x float> @round_v16f32(<16 x float> %x) {
; AVX512-LABEL: round_v16f32:
; AVX512: ## %bb.0:
; AVX512-NEXT: vpbroadcastd {{.*#+}} zmm1 = [4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1]
-; AVX512-NEXT: vpternlogd $248, {{.*}}(%rip){1to16}, %zmm0, %zmm1
+; AVX512-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm1
; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vrndscaleps $11, %zmm0, %zmm0
; AVX512-NEXT: retq
@@ -553,7 +553,7 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; AVX512-LABEL: round_v8f64:
; AVX512: ## %bb.0:
; AVX512-NEXT: vpbroadcastq {{.*#+}} zmm1 = [4.9999999999999994E-1,4.9999999999999994E-1,4.9999999999999994E-1,4.9999999999999994E-1,4.9999999999999994E-1,4.9999999999999994E-1,4.9999999999999994E-1,4.9999999999999994E-1]
-; AVX512-NEXT: vpternlogq $248, {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vrndscalepd $11, %zmm0, %zmm0
; AVX512-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/fp-stack-2results.ll b/llvm/test/CodeGen/X86/fp-stack-2results.ll
index 05a29a77d0339..8063b5fa66a42 100644
--- a/llvm/test/CodeGen/X86/fp-stack-2results.ll
+++ b/llvm/test/CodeGen/X86/fp-stack-2results.ll
@@ -49,7 +49,7 @@ define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-NEXT: .cfi_offset %edi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
-; i686-NEXT: calll test
+; i686-NEXT: calll test at PLT
; i686-NEXT: fstpt (%edi)
; i686-NEXT: fstpt (%esi)
; i686-NEXT: popl %esi
@@ -70,7 +70,7 @@ define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) {
; x86_64-NEXT: .cfi_offset %r14, -16
; x86_64-NEXT: movq %rsi, %r14
; x86_64-NEXT: movq %rdi, %rbx
-; x86_64-NEXT: callq test
+; x86_64-NEXT: callq test at PLT
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: fstpt (%r14)
; x86_64-NEXT: addq $8, %rsp
@@ -101,7 +101,7 @@ define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-NEXT: .cfi_offset %edi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
-; i686-NEXT: calll test
+; i686-NEXT: calll test at PLT
; i686-NEXT: fxch %st(1)
; i686-NEXT: fstpt (%edi)
; i686-NEXT: fstpt (%esi)
@@ -123,7 +123,7 @@ define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) {
; x86_64-NEXT: .cfi_offset %r14, -16
; x86_64-NEXT: movq %rsi, %r14
; x86_64-NEXT: movq %rdi, %rbx
-; x86_64-NEXT: callq test
+; x86_64-NEXT: callq test at PLT
; x86_64-NEXT: fxch %st(1)
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: fstpt (%r14)
@@ -151,7 +151,7 @@ define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: .cfi_offset %esi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
-; i686-NEXT: calll test
+; i686-NEXT: calll test at PLT
; i686-NEXT: fstp %st(1)
; i686-NEXT: fstpt (%esi)
; i686-NEXT: popl %esi
@@ -164,7 +164,7 @@ define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) {
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: .cfi_offset %rbx, -16
; x86_64-NEXT: movq %rdi, %rbx
-; x86_64-NEXT: callq test
+; x86_64-NEXT: callq test at PLT
; x86_64-NEXT: fstp %st(1)
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: popq %rbx
@@ -184,7 +184,7 @@ define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: .cfi_offset %esi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
-; i686-NEXT: calll test
+; i686-NEXT: calll test at PLT
; i686-NEXT: fstp %st(0)
; i686-NEXT: fstpt (%esi)
; i686-NEXT: popl %esi
@@ -197,7 +197,7 @@ define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) {
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: .cfi_offset %rbx, -16
; x86_64-NEXT: movq %rsi, %rbx
-; x86_64-NEXT: callq test
+; x86_64-NEXT: callq test at PLT
; x86_64-NEXT: fstp %st(0)
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: popq %rbx
diff --git a/llvm/test/CodeGen/X86/fp-stack-set-st1.ll b/llvm/test/CodeGen/X86/fp-stack-set-st1.ll
index 1e41c869332b5..097c601e4286f 100644
--- a/llvm/test/CodeGen/X86/fp-stack-set-st1.ll
+++ b/llvm/test/CodeGen/X86/fp-stack-set-st1.ll
@@ -4,8 +4,8 @@
define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: #APP
; CHECK-NEXT: fmul %st(1), %st
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
index 478f2796c5a98..9646e7db840c0 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
@@ -679,7 +679,7 @@ define i64 @fptoui_f32toi64(float %x) #0 {
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
; X87-NEXT: flds 8(%ebp)
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fcom %st(1)
; X87-NEXT: wait
; X87-NEXT: fnstsw %ax
@@ -1319,7 +1319,7 @@ define i64 @fptoui_f64toi64(double %x) #0 {
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
; X87-NEXT: fldl 8(%ebp)
-; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fcom %st(1)
; X87-NEXT: wait
; X87-NEXT: fnstsw %ax
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
index b060f3cc80674..51032e1299f71 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
@@ -488,8 +488,8 @@ define float @uitofp_i32tof32(i32 %x) #0 {
; SSE-X86-NEXT: pushl %eax
; SSE-X86-NEXT: .cfi_def_cfa_offset 8
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-X86-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE-X86-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-X86-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-X86-NEXT: cvtsd2ss %xmm0, %xmm0
; SSE-X86-NEXT: movss %xmm0, (%esp)
; SSE-X86-NEXT: flds (%esp)
@@ -509,8 +509,8 @@ define float @uitofp_i32tof32(i32 %x) #0 {
; AVX1-X86-NEXT: pushl %eax
; AVX1-X86-NEXT: .cfi_def_cfa_offset 8
; AVX1-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX1-X86-NEXT: vorpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; AVX1-X86-NEXT: vsubsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-X86-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-X86-NEXT: vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-X86-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0
; AVX1-X86-NEXT: vmovss %xmm0, (%esp)
; AVX1-X86-NEXT: flds (%esp)
@@ -581,7 +581,7 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; SSE-X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: shrl $31, %eax
; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-X86-NEXT: fstps {{[0-9]+}}(%esp)
; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -623,7 +623,7 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; AVX-X86-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-X86-NEXT: shrl $31, %eax
; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-X86-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-X86-NEXT: wait
; AVX-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -671,7 +671,7 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
-; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: wait
@@ -1164,8 +1164,8 @@ define double @uitofp_i32tof64(i32 %x) #0 {
; SSE-X86-NEXT: andl $-8, %esp
; SSE-X86-NEXT: subl $8, %esp
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-X86-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE-X86-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-X86-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-X86-NEXT: movsd %xmm0, (%esp)
; SSE-X86-NEXT: fldl (%esp)
; SSE-X86-NEXT: wait
@@ -1190,8 +1190,8 @@ define double @uitofp_i32tof64(i32 %x) #0 {
; AVX1-X86-NEXT: andl $-8, %esp
; AVX1-X86-NEXT: subl $8, %esp
; AVX1-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX1-X86-NEXT: vorpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; AVX1-X86-NEXT: vsubsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-X86-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-X86-NEXT: vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-X86-NEXT: vmovsd %xmm0, (%esp)
; AVX1-X86-NEXT: fldl (%esp)
; AVX1-X86-NEXT: wait
@@ -1268,7 +1268,7 @@ define double @uitofp_i64tof64(i64 %x) #0 {
; SSE-X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: shrl $31, %eax
; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-X86-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
@@ -1310,7 +1310,7 @@ define double @uitofp_i64tof64(i64 %x) #0 {
; AVX-X86-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-X86-NEXT: shrl $31, %eax
; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-X86-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-X86-NEXT: wait
; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -1358,7 +1358,7 @@ define double @uitofp_i64tof64(i64 %x) #0 {
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
-; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: wait
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-round.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-round.ll
index 973e837cd6b30..13f890ae6e191 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-round.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-round.ll
@@ -511,7 +511,7 @@ define float @fround32(float %f) #0 {
; SSE41-X64: # %bb.0:
; SSE41-X64-NEXT: pushq %rax
; SSE41-X64-NEXT: .cfi_def_cfa_offset 16
-; SSE41-X64-NEXT: callq roundf
+; SSE41-X64-NEXT: callq roundf at PLT
; SSE41-X64-NEXT: popq %rax
; SSE41-X64-NEXT: .cfi_def_cfa_offset 8
; SSE41-X64-NEXT: retq
@@ -531,7 +531,7 @@ define float @fround32(float %f) #0 {
; AVX-X64: # %bb.0:
; AVX-X64-NEXT: pushq %rax
; AVX-X64-NEXT: .cfi_def_cfa_offset 16
-; AVX-X64-NEXT: callq roundf
+; AVX-X64-NEXT: callq roundf at PLT
; AVX-X64-NEXT: popq %rax
; AVX-X64-NEXT: .cfi_def_cfa_offset 8
; AVX-X64-NEXT: retq
@@ -556,7 +556,7 @@ define double @froundf64(double %f) #0 {
; SSE41-X64: # %bb.0:
; SSE41-X64-NEXT: pushq %rax
; SSE41-X64-NEXT: .cfi_def_cfa_offset 16
-; SSE41-X64-NEXT: callq round
+; SSE41-X64-NEXT: callq round at PLT
; SSE41-X64-NEXT: popq %rax
; SSE41-X64-NEXT: .cfi_def_cfa_offset 8
; SSE41-X64-NEXT: retq
@@ -576,7 +576,7 @@ define double @froundf64(double %f) #0 {
; AVX-X64: # %bb.0:
; AVX-X64-NEXT: pushq %rax
; AVX-X64-NEXT: .cfi_def_cfa_offset 16
-; AVX-X64-NEXT: callq round
+; AVX-X64-NEXT: callq round at PLT
; AVX-X64-NEXT: popq %rax
; AVX-X64-NEXT: .cfi_def_cfa_offset 8
; AVX-X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar.ll b/llvm/test/CodeGen/X86/fp-strict-scalar.ll
index fbcde4aa4cd2e..bccae30bf7e30 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar.ll
@@ -626,7 +626,7 @@ define double @fma_f64(double %a, double %b, double %c) nounwind strictfp {
; SSE-X64-LABEL: fma_f64:
; SSE-X64: # %bb.0:
; SSE-X64-NEXT: pushq %rax
-; SSE-X64-NEXT: callq fma
+; SSE-X64-NEXT: callq fma at PLT
; SSE-X64-NEXT: popq %rax
; SSE-X64-NEXT: retq
;
@@ -687,7 +687,7 @@ define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
; SSE-X64-LABEL: fma_f32:
; SSE-X64: # %bb.0:
; SSE-X64-NEXT: pushq %rax
-; SSE-X64-NEXT: callq fmaf
+; SSE-X64-NEXT: callq fmaf at PLT
; SSE-X64-NEXT: popq %rax
; SSE-X64-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/fp-une-cmp.ll b/llvm/test/CodeGen/X86/fp-une-cmp.ll
index bd82ca8719fa1..9d6ae805757b3 100644
--- a/llvm/test/CodeGen/X86/fp-une-cmp.ll
+++ b/llvm/test/CodeGen/X86/fp-une-cmp.ll
@@ -30,7 +30,7 @@ define double @rdar_7859988(double %x, double %y) nounwind readnone optsize ssp
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: jp .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1
-; CHECK-NEXT: addsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: .LBB0_2: # %bb2
; CHECK-NEXT: retq
@@ -56,10 +56,10 @@ define double @profile_metadata(double %x, double %y) {
; CHECK-NEXT: ucomisd %xmm1, %xmm0
; CHECK-NEXT: jne .LBB1_1
; CHECK-NEXT: jp .LBB1_1
-; CHECK-NEXT: # %bb2
+; CHECK-NEXT: # %bb.2: # %bb2
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB1_1: # %bb1
-; CHECK-NEXT: addsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
entry:
@@ -104,12 +104,25 @@ if.end:
; Test that an FP oeq/une conditional branch can be inverted successfully even
; when the true and false targets are the same (PR27750).
-;
-; CHECK-LABEL: pr27750
-; CHECK: ucomiss
-; CHECK-NEXT: jne [[TARGET:.*]]
-; CHECK-NEXT: jp [[TARGET]]
define void @pr27750(i32* %b, float %x, i1 %y) {
+; CHECK-LABEL: pr27750:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: jmp .LBB3_1
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB3_3: # %for.end
+; CHECK-NEXT: # in Loop: Header=BB3_1 Depth=1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: jne .LBB3_1
+; CHECK-NEXT: jp .LBB3_1
+; CHECK-NEXT: .LBB3_1: # %for.cond1
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: testb $1, %sil
+; CHECK-NEXT: je .LBB3_3
+; CHECK-NEXT: # %bb.2: # %for.body3.lr.ph
+; CHECK-NEXT: # in Loop: Header=BB3_1 Depth=1
+; CHECK-NEXT: movl $0, (%rdi)
+; CHECK-NEXT: jmp .LBB3_3
entry:
br label %for.cond
diff --git a/llvm/test/CodeGen/X86/fp128-cast-strict.ll b/llvm/test/CodeGen/X86/fp128-cast-strict.ll
index b2458cd09d771..341e62b844edd 100644
--- a/llvm/test/CodeGen/X86/fp128-cast-strict.ll
+++ b/llvm/test/CodeGen/X86/fp128-cast-strict.ll
@@ -19,8 +19,8 @@ define dso_local void @TestFPExtF32_F128() nounwind strictfp {
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-SSE-NEXT: callq __extendsftf2
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: callq __extendsftf2 at PLT
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -28,8 +28,8 @@ define dso_local void @TestFPExtF32_F128() nounwind strictfp {
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
; X64-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-AVX-NEXT: callq __extendsftf2
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: callq __extendsftf2 at PLT
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
;
@@ -67,8 +67,8 @@ define dso_local void @TestFPExtF64_F128() nounwind strictfp {
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X64-SSE-NEXT: callq __extenddftf2
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: callq __extenddftf2 at PLT
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -76,8 +76,8 @@ define dso_local void @TestFPExtF64_F128() nounwind strictfp {
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
; X64-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X64-AVX-NEXT: callq __extenddftf2
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: callq __extenddftf2 at PLT
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
;
@@ -114,22 +114,22 @@ define dso_local void @TestFPExtF80_F128() nounwind strictfp {
; X64-SSE-LABEL: TestFPExtF80_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: subq $24, %rsp
-; X64-SSE-NEXT: fldt {{.*}}(%rip)
+; X64-SSE-NEXT: fldt vf80(%rip)
; X64-SSE-NEXT: fstpt (%rsp)
; X64-SSE-NEXT: wait
-; X64-SSE-NEXT: callq __extendxftf2
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: callq __extendxftf2 at PLT
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: addq $24, %rsp
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: TestFPExtF80_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: subq $24, %rsp
-; X64-AVX-NEXT: fldt {{.*}}(%rip)
+; X64-AVX-NEXT: fldt vf80(%rip)
; X64-AVX-NEXT: fstpt (%rsp)
; X64-AVX-NEXT: wait
-; X64-AVX-NEXT: callq __extendxftf2
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: callq __extendxftf2 at PLT
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: addq $24, %rsp
; X64-AVX-NEXT: retq
;
@@ -166,18 +166,18 @@ define dso_local void @TestFPTruncF128_F32() nounwind strictfp {
; X64-SSE-LABEL: TestFPTruncF128_F32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT: callq __trunctfsf2
-; X64-SSE-NEXT: movss %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
+; X64-SSE-NEXT: callq __trunctfsf2 at PLT
+; X64-SSE-NEXT: movss %xmm0, vf32(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: TestFPTruncF128_F32:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
-; X64-AVX-NEXT: callq __trunctfsf2
-; X64-AVX-NEXT: vmovss %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
+; X64-AVX-NEXT: callq __trunctfsf2 at PLT
+; X64-AVX-NEXT: vmovss %xmm0, vf32(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
;
@@ -205,18 +205,18 @@ define dso_local void @TestFPTruncF128_F64() nounwind strictfp {
; X64-SSE-LABEL: TestFPTruncF128_F64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT: callq __trunctfdf2
-; X64-SSE-NEXT: movsd %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
+; X64-SSE-NEXT: callq __trunctfdf2 at PLT
+; X64-SSE-NEXT: movsd %xmm0, vf64(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: TestFPTruncF128_F64:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
-; X64-AVX-NEXT: callq __trunctfdf2
-; X64-AVX-NEXT: vmovsd %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
+; X64-AVX-NEXT: callq __trunctfdf2 at PLT
+; X64-AVX-NEXT: vmovsd %xmm0, vf64(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
;
@@ -244,9 +244,9 @@ define dso_local void @TestFPTruncF128_F80() nounwind strictfp {
; X64-SSE-LABEL: TestFPTruncF128_F80:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT: callq __trunctfxf2
-; X64-SSE-NEXT: fstpt {{.*}}(%rip)
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
+; X64-SSE-NEXT: callq __trunctfxf2 at PLT
+; X64-SSE-NEXT: fstpt vf80(%rip)
; X64-SSE-NEXT: wait
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
@@ -254,9 +254,9 @@ define dso_local void @TestFPTruncF128_F80() nounwind strictfp {
; X64-AVX-LABEL: TestFPTruncF128_F80:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
-; X64-AVX-NEXT: callq __trunctfxf2
-; X64-AVX-NEXT: fstpt {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
+; X64-AVX-NEXT: callq __trunctfxf2 at PLT
+; X64-AVX-NEXT: fstpt vf80(%rip)
; X64-AVX-NEXT: wait
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
@@ -285,7 +285,7 @@ define dso_local i8 @fptosi_i8(fp128 %x) nounwind strictfp {
; X64-LABEL: fptosi_i8:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixtfsi
+; X64-NEXT: callq __fixtfsi at PLT
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: popq %rcx
; X64-NEXT: retq
@@ -311,7 +311,7 @@ define i16 @fptosi_i16(fp128 %x) nounwind strictfp {
; X64-LABEL: fptosi_i16:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixtfsi
+; X64-NEXT: callq __fixtfsi at PLT
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: popq %rcx
; X64-NEXT: retq
@@ -337,7 +337,7 @@ define dso_local i32 @fptosi_i32(fp128 %x) nounwind strictfp {
; X64-LABEL: fptosi_i32:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixtfsi
+; X64-NEXT: callq __fixtfsi at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
;
@@ -360,7 +360,7 @@ define i64 @fptosi_i64(fp128 %x) nounwind strictfp {
; X64-LABEL: fptosi_i64:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixtfdi
+; X64-NEXT: callq __fixtfdi at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
;
@@ -383,7 +383,7 @@ define i128 @fptosi_i128(fp128 %x) nounwind strictfp {
; X64-LABEL: fptosi_i128:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixtfti
+; X64-NEXT: callq __fixtfti at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
;
@@ -424,7 +424,7 @@ define dso_local i8 @fptoui_i8(fp128 %x) nounwind strictfp {
; X64-LABEL: fptoui_i8:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixtfsi
+; X64-NEXT: callq __fixtfsi at PLT
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: popq %rcx
; X64-NEXT: retq
@@ -450,7 +450,7 @@ define i16 @fptoui_i16(fp128 %x) nounwind strictfp {
; X64-LABEL: fptoui_i16:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixtfsi
+; X64-NEXT: callq __fixtfsi at PLT
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: popq %rcx
; X64-NEXT: retq
@@ -476,7 +476,7 @@ define dso_local i32 @fptoui_i32(fp128 %x) nounwind strictfp {
; X64-LABEL: fptoui_i32:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixunstfsi
+; X64-NEXT: callq __fixunstfsi at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
;
@@ -499,7 +499,7 @@ define i64 @fptoui_i64(fp128 %x) nounwind strictfp {
; X64-LABEL: fptoui_i64:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixunstfdi
+; X64-NEXT: callq __fixunstfdi at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
;
@@ -522,7 +522,7 @@ define i128 @fptoui_i128(fp128 %x) nounwind strictfp {
; X64-LABEL: fptoui_i128:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __fixunstfti
+; X64-NEXT: callq __fixunstfti at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
;
@@ -564,7 +564,7 @@ define fp128 @sitofp_i8(i8 %x) nounwind strictfp {
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
; X64-NEXT: movsbl %dil, %edi
-; X64-NEXT: callq __floatsitf
+; X64-NEXT: callq __floatsitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -604,7 +604,7 @@ define fp128 @sitofp_i16(i16 %x) nounwind strictfp {
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
; X64-NEXT: movswl %di, %edi
-; X64-NEXT: callq __floatsitf
+; X64-NEXT: callq __floatsitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -643,7 +643,7 @@ define fp128 @sitofp_i32(i32 %x) nounwind strictfp {
; X64-LABEL: sitofp_i32:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __floatsitf
+; X64-NEXT: callq __floatsitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -681,7 +681,7 @@ define fp128 @sitofp_i64(i64 %x) nounwind strictfp {
; X64-LABEL: sitofp_i64:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __floatditf
+; X64-NEXT: callq __floatditf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -720,7 +720,7 @@ define fp128 @sitofp_i128(i128 %x) nounwind strictfp {
; X64-LABEL: sitofp_i128:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __floattitf
+; X64-NEXT: callq __floattitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -762,7 +762,7 @@ define fp128 @uitofp_i8(i8 %x) nounwind strictfp {
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
; X64-NEXT: movzbl %dil, %edi
-; X64-NEXT: callq __floatsitf
+; X64-NEXT: callq __floatsitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -802,7 +802,7 @@ define fp128 @uitofp_i16(i16 %x) nounwind strictfp {
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
; X64-NEXT: movzwl %di, %edi
-; X64-NEXT: callq __floatsitf
+; X64-NEXT: callq __floatsitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -841,7 +841,7 @@ define fp128 @uitofp_i32(i32 %x) nounwind strictfp {
; X64-LABEL: uitofp_i32:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __floatunsitf
+; X64-NEXT: callq __floatunsitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -879,7 +879,7 @@ define fp128 @uitofp_i64(i64 %x) nounwind strictfp {
; X64-LABEL: uitofp_i64:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __floatunditf
+; X64-NEXT: callq __floatunditf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
@@ -918,7 +918,7 @@ define fp128 @uitofp_i128(i128 %x) nounwind strictfp {
; X64-LABEL: uitofp_i128:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
-; X64-NEXT: callq __floatuntitf
+; X64-NEXT: callq __floatuntitf at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/fp128-cast.ll b/llvm/test/CodeGen/X86/fp128-cast.ll
index ef5c7711aaca8..2ad7a0210f87c 100644
--- a/llvm/test/CodeGen/X86/fp128-cast.ll
+++ b/llvm/test/CodeGen/X86/fp128-cast.ll
@@ -27,7 +27,7 @@ define dso_local void @TestFPExtF32_F128() nounwind {
; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: callq __extendsftf2 at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -58,7 +58,7 @@ define dso_local void @TestFPExtF32_F128() nounwind {
; X64-AVX-NEXT: pushq %rax
; X64-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: callq __extendsftf2 at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -74,7 +74,7 @@ define dso_local void @TestFPExtF64_F128() nounwind {
; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X64-SSE-NEXT: callq __extenddftf2 at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -105,7 +105,7 @@ define dso_local void @TestFPExtF64_F128() nounwind {
; X64-AVX-NEXT: pushq %rax
; X64-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X64-AVX-NEXT: callq __extenddftf2 at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -119,10 +119,10 @@ define dso_local void @TestFPExtF80_F128() nounwind {
; X64-SSE-LABEL: TestFPExtF80_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: subq $24, %rsp
-; X64-SSE-NEXT: fldt {{.*}}(%rip)
+; X64-SSE-NEXT: fldt vf80(%rip)
; X64-SSE-NEXT: fstpt (%rsp)
; X64-SSE-NEXT: callq __extendxftf2 at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: addq $24, %rsp
; X64-SSE-NEXT: retq
;
@@ -151,10 +151,10 @@ define dso_local void @TestFPExtF80_F128() nounwind {
; X64-AVX-LABEL: TestFPExtF80_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: subq $24, %rsp
-; X64-AVX-NEXT: fldt {{.*}}(%rip)
+; X64-AVX-NEXT: fldt vf80(%rip)
; X64-AVX-NEXT: fstpt (%rsp)
; X64-AVX-NEXT: callq __extendxftf2 at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: addq $24, %rsp
; X64-AVX-NEXT: retq
entry:
@@ -168,9 +168,9 @@ define dso_local void @TestFPToSIF128_I16() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I16:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixtfsi at PLT
-; X64-SSE-NEXT: movw %ax, {{.*}}(%rip)
+; X64-SSE-NEXT: movw %ax, vi16(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -190,9 +190,9 @@ define dso_local void @TestFPToSIF128_I16() nounwind {
; X64-AVX-LABEL: TestFPToSIF128_I16:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixtfsi at PLT
-; X64-AVX-NEXT: movw %ax, {{.*}}(%rip)
+; X64-AVX-NEXT: movw %ax, vi16(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -206,9 +206,9 @@ define dso_local void @TestFPToUIF128_I16() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_I16:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixtfsi at PLT
-; X64-SSE-NEXT: movw %ax, {{.*}}(%rip)
+; X64-SSE-NEXT: movw %ax, vi16(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -228,9 +228,9 @@ define dso_local void @TestFPToUIF128_I16() nounwind {
; X64-AVX-LABEL: TestFPToUIF128_I16:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixtfsi at PLT
-; X64-AVX-NEXT: movw %ax, {{.*}}(%rip)
+; X64-AVX-NEXT: movw %ax, vi16(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -244,9 +244,9 @@ define dso_local void @TestFPToSIF128_I32() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixtfsi at PLT
-; X64-SSE-NEXT: movl %eax, {{.*}}(%rip)
+; X64-SSE-NEXT: movl %eax, vi32(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -266,9 +266,9 @@ define dso_local void @TestFPToSIF128_I32() nounwind {
; X64-AVX-LABEL: TestFPToSIF128_I32:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixtfsi at PLT
-; X64-AVX-NEXT: movl %eax, {{.*}}(%rip)
+; X64-AVX-NEXT: movl %eax, vi32(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -282,9 +282,9 @@ define dso_local void @TestFPToUIF128_U32() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_U32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixunstfsi at PLT
-; X64-SSE-NEXT: movl %eax, {{.*}}(%rip)
+; X64-SSE-NEXT: movl %eax, vu32(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -304,9 +304,9 @@ define dso_local void @TestFPToUIF128_U32() nounwind {
; X64-AVX-LABEL: TestFPToUIF128_U32:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixunstfsi at PLT
-; X64-AVX-NEXT: movl %eax, {{.*}}(%rip)
+; X64-AVX-NEXT: movl %eax, vu32(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -320,10 +320,10 @@ define dso_local void @TestFPToSIF128_I64() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixtfsi at PLT
; X64-SSE-NEXT: cltq
-; X64-SSE-NEXT: movq %rax, {{.*}}(%rip)
+; X64-SSE-NEXT: movq %rax, vi64(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -345,10 +345,10 @@ define dso_local void @TestFPToSIF128_I64() nounwind {
; X64-AVX-LABEL: TestFPToSIF128_I64:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixtfsi at PLT
; X64-AVX-NEXT: cltq
-; X64-AVX-NEXT: movq %rax, {{.*}}(%rip)
+; X64-AVX-NEXT: movq %rax, vi64(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -363,10 +363,10 @@ define dso_local void @TestFPToUIF128_U64() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_U64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixunstfsi at PLT
; X64-SSE-NEXT: movl %eax, %eax
-; X64-SSE-NEXT: movq %rax, {{.*}}(%rip)
+; X64-SSE-NEXT: movq %rax, vu64(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -387,10 +387,10 @@ define dso_local void @TestFPToUIF128_U64() nounwind {
; X64-AVX-LABEL: TestFPToUIF128_U64:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixunstfsi at PLT
; X64-AVX-NEXT: movl %eax, %eax
-; X64-AVX-NEXT: movq %rax, {{.*}}(%rip)
+; X64-AVX-NEXT: movq %rax, vu64(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -405,10 +405,10 @@ define dso_local void @TestFPToSIF128_I128() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixtfti at PLT
-; X64-SSE-NEXT: movq %rdx, vi128+{{.*}}(%rip)
-; X64-SSE-NEXT: movq %rax, {{.*}}(%rip)
+; X64-SSE-NEXT: movq %rdx, vi128+8(%rip)
+; X64-SSE-NEXT: movq %rax, vi128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -439,10 +439,10 @@ define dso_local void @TestFPToSIF128_I128() nounwind {
; X64-AVX-LABEL: TestFPToSIF128_I128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixtfti at PLT
-; X64-AVX-NEXT: movq %rdx, vi128+{{.*}}(%rip)
-; X64-AVX-NEXT: movq %rax, {{.*}}(%rip)
+; X64-AVX-NEXT: movq %rdx, vi128+8(%rip)
+; X64-AVX-NEXT: movq %rax, vi128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -456,10 +456,10 @@ define dso_local void @TestFPToUIF128_U128() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_U128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __fixunstfti at PLT
-; X64-SSE-NEXT: movq %rdx, vu128+{{.*}}(%rip)
-; X64-SSE-NEXT: movq %rax, {{.*}}(%rip)
+; X64-SSE-NEXT: movq %rdx, vu128+8(%rip)
+; X64-SSE-NEXT: movq %rax, vu128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -490,10 +490,10 @@ define dso_local void @TestFPToUIF128_U128() nounwind {
; X64-AVX-LABEL: TestFPToUIF128_U128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __fixunstfti at PLT
-; X64-AVX-NEXT: movq %rdx, vu128+{{.*}}(%rip)
-; X64-AVX-NEXT: movq %rax, {{.*}}(%rip)
+; X64-AVX-NEXT: movq %rdx, vu128+8(%rip)
+; X64-AVX-NEXT: movq %rax, vu128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -507,9 +507,9 @@ define dso_local void @TestFPTruncF128_F32() nounwind {
; X64-SSE-LABEL: TestFPTruncF128_F32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __trunctfsf2 at PLT
-; X64-SSE-NEXT: movss %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movss %xmm0, vf32(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -529,9 +529,9 @@ define dso_local void @TestFPTruncF128_F32() nounwind {
; X64-AVX-LABEL: TestFPTruncF128_F32:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __trunctfsf2 at PLT
-; X64-AVX-NEXT: vmovss %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovss %xmm0, vf32(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -545,9 +545,9 @@ define dso_local void @TestFPTruncF128_F64() nounwind {
; X64-SSE-LABEL: TestFPTruncF128_F64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __trunctfdf2 at PLT
-; X64-SSE-NEXT: movsd %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movsd %xmm0, vf64(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -567,9 +567,9 @@ define dso_local void @TestFPTruncF128_F64() nounwind {
; X64-AVX-LABEL: TestFPTruncF128_F64:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __trunctfdf2 at PLT
-; X64-AVX-NEXT: vmovsd %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovsd %xmm0, vf64(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -583,9 +583,9 @@ define dso_local void @TestFPTruncF128_F80() nounwind {
; X64-SSE-LABEL: TestFPTruncF128_F80:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movaps vf128(%rip), %xmm0
; X64-SSE-NEXT: callq __trunctfxf2 at PLT
-; X64-SSE-NEXT: fstpt {{.*}}(%rip)
+; X64-SSE-NEXT: fstpt vf80(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -605,9 +605,9 @@ define dso_local void @TestFPTruncF128_F80() nounwind {
; X64-AVX-LABEL: TestFPTruncF128_F80:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovaps vf128(%rip), %xmm0
; X64-AVX-NEXT: callq __trunctfxf2 at PLT
-; X64-AVX-NEXT: fstpt {{.*}}(%rip)
+; X64-AVX-NEXT: fstpt vf80(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -621,9 +621,9 @@ define dso_local void @TestSIToFPI16_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI16_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movswl {{.*}}(%rip), %edi
+; X64-SSE-NEXT: movswl vi16(%rip), %edi
; X64-SSE-NEXT: callq __floatsitf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -653,9 +653,9 @@ define dso_local void @TestSIToFPI16_F128() nounwind {
; X64-AVX-LABEL: TestSIToFPI16_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movswl {{.*}}(%rip), %edi
+; X64-AVX-NEXT: movswl vi16(%rip), %edi
; X64-AVX-NEXT: callq __floatsitf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -669,9 +669,9 @@ define dso_local void @TestSIToFPU16_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPU16_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movzwl {{.*}}(%rip), %edi
+; X64-SSE-NEXT: movzwl vi16(%rip), %edi
; X64-SSE-NEXT: callq __floatsitf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -701,9 +701,9 @@ define dso_local void @TestSIToFPU16_F128() nounwind {
; X64-AVX-LABEL: TestSIToFPU16_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movzwl {{.*}}(%rip), %edi
+; X64-AVX-NEXT: movzwl vi16(%rip), %edi
; X64-AVX-NEXT: callq __floatsitf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -717,9 +717,9 @@ define dso_local void @TestSIToFPI32_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI32_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movl {{.*}}(%rip), %edi
+; X64-SSE-NEXT: movl vi32(%rip), %edi
; X64-SSE-NEXT: callq __floatsitf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -747,9 +747,9 @@ define dso_local void @TestSIToFPI32_F128() nounwind {
; X64-AVX-LABEL: TestSIToFPI32_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movl {{.*}}(%rip), %edi
+; X64-AVX-NEXT: movl vi32(%rip), %edi
; X64-AVX-NEXT: callq __floatsitf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -763,9 +763,9 @@ define dso_local void @TestUIToFPU32_F128() #2 {
; X64-SSE-LABEL: TestUIToFPU32_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movl {{.*}}(%rip), %edi
+; X64-SSE-NEXT: movl vu32(%rip), %edi
; X64-SSE-NEXT: callq __floatunsitf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -793,9 +793,9 @@ define dso_local void @TestUIToFPU32_F128() #2 {
; X64-AVX-LABEL: TestUIToFPU32_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movl {{.*}}(%rip), %edi
+; X64-AVX-NEXT: movl vu32(%rip), %edi
; X64-AVX-NEXT: callq __floatunsitf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -809,9 +809,9 @@ define dso_local void @TestSIToFPI64_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI64_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rdi
+; X64-SSE-NEXT: movq vi64(%rip), %rdi
; X64-SSE-NEXT: callq __floatditf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -840,9 +840,9 @@ define dso_local void @TestSIToFPI64_F128() nounwind {
; X64-AVX-LABEL: TestSIToFPI64_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rdi
+; X64-AVX-NEXT: movq vi64(%rip), %rdi
; X64-AVX-NEXT: callq __floatditf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -856,9 +856,9 @@ define dso_local void @TestUIToFPU64_F128() #2 {
; X64-SSE-LABEL: TestUIToFPU64_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rdi
+; X64-SSE-NEXT: movq vu64(%rip), %rdi
; X64-SSE-NEXT: callq __floatunditf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -887,9 +887,9 @@ define dso_local void @TestUIToFPU64_F128() #2 {
; X64-AVX-LABEL: TestUIToFPU64_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rdi
+; X64-AVX-NEXT: movq vu64(%rip), %rdi
; X64-AVX-NEXT: callq __floatunditf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -903,10 +903,10 @@ define dso_local void @TestSIToFPI128_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI128_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rdi
-; X64-SSE-NEXT: movq vi128+{{.*}}(%rip), %rsi
+; X64-SSE-NEXT: movq vi128(%rip), %rdi
+; X64-SSE-NEXT: movq vi128+8(%rip), %rsi
; X64-SSE-NEXT: callq __floattitf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -937,10 +937,10 @@ define dso_local void @TestSIToFPI128_F128() nounwind {
; X64-AVX-LABEL: TestSIToFPI128_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rdi
-; X64-AVX-NEXT: movq vi128+{{.*}}(%rip), %rsi
+; X64-AVX-NEXT: movq vi128(%rip), %rdi
+; X64-AVX-NEXT: movq vi128+8(%rip), %rsi
; X64-AVX-NEXT: callq __floattitf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -954,10 +954,10 @@ define dso_local void @TestUIToFPU128_F128() #2 {
; X64-SSE-LABEL: TestUIToFPU128_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rdi
-; X64-SSE-NEXT: movq vu128+{{.*}}(%rip), %rsi
+; X64-SSE-NEXT: movq vu128(%rip), %rdi
+; X64-SSE-NEXT: movq vu128+8(%rip), %rsi
; X64-SSE-NEXT: callq __floatuntitf at PLT
-; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-SSE-NEXT: movaps %xmm0, vf128(%rip)
; X64-SSE-NEXT: popq %rax
; X64-SSE-NEXT: retq
;
@@ -988,10 +988,10 @@ define dso_local void @TestUIToFPU128_F128() #2 {
; X64-AVX-LABEL: TestUIToFPU128_F128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rdi
-; X64-AVX-NEXT: movq vu128+{{.*}}(%rip), %rsi
+; X64-AVX-NEXT: movq vu128(%rip), %rdi
+; X64-AVX-NEXT: movq vu128+8(%rip), %rsi
; X64-AVX-NEXT: callq __floatuntitf at PLT
-; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovaps %xmm0, vf128(%rip)
; X64-AVX-NEXT: popq %rax
; X64-AVX-NEXT: retq
entry:
@@ -1005,7 +1005,7 @@ define dso_local i32 @TestConst128(fp128 %v) nounwind {
; X64-SSE-LABEL: TestConst128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: callq __gttf2 at PLT
; X64-SSE-NEXT: xorl %ecx, %ecx
; X64-SSE-NEXT: testl %eax, %eax
@@ -1037,7 +1037,7 @@ define dso_local i32 @TestConst128(fp128 %v) nounwind {
; X64-AVX-LABEL: TestConst128:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: pushq %rax
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
+; X64-AVX-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-AVX-NEXT: callq __gttf2 at PLT
; X64-AVX-NEXT: xorl %ecx, %ecx
; X64-AVX-NEXT: testl %eax, %eax
@@ -1259,8 +1259,8 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
; X64-SSE-NEXT: # %bb.1: # %if.then
; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: callq __trunctfdf2 at PLT
-; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT: orps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: callq __extenddftf2 at PLT
; X64-SSE-NEXT: addq $8, %rsp
; X64-SSE-NEXT: .LBB26_2: # %cleanup
@@ -1287,8 +1287,8 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
; X32-NEXT: addl $16, %esp
; X32-NEXT: fstpl {{[0-9]+}}(%esp)
; X32-NEXT: testb $-128, {{[0-9]+}}(%esp)
-; X32-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
-; X32-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X32-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
+; X32-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X32-NEXT: jne .LBB26_3
; X32-NEXT: # %bb.2: # %if.then
; X32-NEXT: fstp %st(1)
@@ -1323,7 +1323,7 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
; X64-AVX-NEXT: # %bb.1: # %if.then
; X64-AVX-NEXT: pushq %rax
; X64-AVX-NEXT: callq __trunctfdf2 at PLT
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [+Inf,+Inf]
; X64-AVX-NEXT: # xmm1 = mem[0,0]
; X64-AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/fp128-compare.ll b/llvm/test/CodeGen/X86/fp128-compare.ll
index 8aa4e55443820..3851e59a08e35 100644
--- a/llvm/test/CodeGen/X86/fp128-compare.ll
+++ b/llvm/test/CodeGen/X86/fp128-compare.ll
@@ -9,7 +9,7 @@ define i32 @TestComp128GT(fp128 %d1, fp128 %d2) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq __gttf2
+; CHECK-NEXT: callq __gttf2 at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setg %cl
@@ -28,7 +28,7 @@ define i32 @TestComp128GE(fp128 %d1, fp128 %d2) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq __getf2
+; CHECK-NEXT: callq __getf2 at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setns %cl
@@ -47,7 +47,7 @@ define i32 @TestComp128LT(fp128 %d1, fp128 %d2) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq __lttf2
+; CHECK-NEXT: callq __lttf2 at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: sets %cl
@@ -69,7 +69,7 @@ define i32 @TestComp128LE(fp128 %d1, fp128 %d2) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq __letf2
+; CHECK-NEXT: callq __letf2 at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setle %cl
@@ -88,7 +88,7 @@ define i32 @TestComp128EQ(fp128 %d1, fp128 %d2) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq __eqtf2
+; CHECK-NEXT: callq __eqtf2 at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: sete %cl
@@ -107,7 +107,7 @@ define i32 @TestComp128NE(fp128 %d1, fp128 %d2) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq __netf2
+; CHECK-NEXT: callq __netf2 at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setne %cl
@@ -131,12 +131,12 @@ define i32 @TestComp128UEQ(fp128 %d1, fp128 %d2) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq __eqtf2
+; CHECK-NEXT: callq __eqtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: sete %bl
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq __unordtf2
+; CHECK-NEXT: callq __unordtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setne %al
; CHECK-NEXT: orb %bl, %al
@@ -162,12 +162,12 @@ define i32 @TestComp128ONE(fp128 %d1, fp128 %d2) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq __eqtf2
+; CHECK-NEXT: callq __eqtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setne %bl
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq __unordtf2
+; CHECK-NEXT: callq __unordtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: sete %al
; CHECK-NEXT: andb %bl, %al
@@ -190,7 +190,7 @@ define fp128 @TestMax(fp128 %x, fp128 %y) {
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq __gttf2
+; CHECK-NEXT: callq __gttf2 at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jg .LBB8_2
diff --git a/llvm/test/CodeGen/X86/fp128-extract.ll b/llvm/test/CodeGen/X86/fp128-extract.ll
index a9fd8a1d1f2bf..bcd0e2900b281 100644
--- a/llvm/test/CodeGen/X86/fp128-extract.ll
+++ b/llvm/test/CodeGen/X86/fp128-extract.ll
@@ -8,11 +8,11 @@ define fp128 @TestExtract(<2 x double> %x) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq __extenddftf2
+; CHECK-NEXT: callq __extenddftf2 at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq __extenddftf2
+; CHECK-NEXT: callq __extenddftf2 at PLT
; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $40, %rsp
diff --git a/llvm/test/CodeGen/X86/fp128-i128.ll b/llvm/test/CodeGen/X86/fp128-i128.ll
index a9e932304dadb..07f73ed0b9ef6 100644
--- a/llvm/test/CodeGen/X86/fp128-i128.ll
+++ b/llvm/test/CodeGen/X86/fp128-i128.ll
@@ -138,13 +138,13 @@ define fp128 @TestI128_1(fp128 %x) #0 {
; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; SSE-NEXT: movq %rcx, (%rsp)
; SSE-NEXT: movaps (%rsp), %xmm0
-; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
+; SSE-NEXT: movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: callq __lttf2 at PLT
; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: testl %eax, %eax
; SSE-NEXT: sets %cl
; SSE-NEXT: shlq $4, %rcx
-; SSE-NEXT: movaps {{\.LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
+; SSE-NEXT: movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
; SSE-NEXT: addq $40, %rsp
; SSE-NEXT: retq
;
@@ -158,13 +158,13 @@ define fp128 @TestI128_1(fp128 %x) #0 {
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX-NEXT: movq %rcx, (%rsp)
; AVX-NEXT: vmovaps (%rsp), %xmm0
-; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
+; AVX-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; AVX-NEXT: callq __lttf2 at PLT
; AVX-NEXT: xorl %ecx, %ecx
; AVX-NEXT: testl %eax, %eax
; AVX-NEXT: sets %cl
; AVX-NEXT: shlq $4, %rcx
-; AVX-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
+; AVX-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
; AVX-NEXT: addq $40, %rsp
; AVX-NEXT: retq
entry:
@@ -236,7 +236,7 @@ define fp128 @TestI128_3(fp128 %x, i32* nocapture readnone %ex) #0 {
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE-NEXT: jmp .LBB4_3
; SSE-NEXT: .LBB4_2: # %if.then
-; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
+; SSE-NEXT: movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: callq __multf3 at PLT
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
@@ -263,7 +263,7 @@ define fp128 @TestI128_3(fp128 %x, i32* nocapture readnone %ex) #0 {
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX-NEXT: jmp .LBB4_3
; AVX-NEXT: .LBB4_2: # %if.then
-; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
+; AVX-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; AVX-NEXT: callq __multf3 at PLT
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
@@ -345,12 +345,12 @@ entry:
define dso_local void @TestShift128_2() #2 {
; CHECK-LABEL: TestShift128_2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq v128(%rip), %rax
; CHECK-NEXT: shlq $32, %rax
-; CHECK-NEXT: movq {{.*}}(%rip), %rcx
-; CHECK-NEXT: orq v128_2+{{.*}}(%rip), %rax
-; CHECK-NEXT: movq %rcx, {{.*}}(%rip)
-; CHECK-NEXT: movq %rax, v128+{{.*}}(%rip)
+; CHECK-NEXT: movq v128_2(%rip), %rcx
+; CHECK-NEXT: orq v128_2+8(%rip), %rax
+; CHECK-NEXT: movq %rcx, v128(%rip)
+; CHECK-NEXT: movq %rax, v128+8(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i128, i128* @v128, align 16
@@ -423,12 +423,12 @@ declare dso_local void @foo(fp128) #1
define fp128 @TestFABS_LD(fp128 %x) #0 {
; SSE-LABEL: TestFABS_LD:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: TestFABS_LD:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
entry:
%call = tail call fp128 @fabsl(fp128 %x) #2
@@ -460,15 +460,15 @@ define dso_local void @TestCopySign({ fp128, fp128 }* noalias nocapture sret({ f
; SSE-NEXT: jle .LBB10_1
; SSE-NEXT: # %bb.2: # %if.then
; SSE-NEXT: movaps %xmm0, %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: jmp .LBB10_3
; SSE-NEXT: .LBB10_1:
; SSE-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; SSE-NEXT: .LBB10_3: # %cleanup
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
-; SSE-NEXT: andps {{.*}}(%rip), %xmm2
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: orps %xmm2, %xmm0
; SSE-NEXT: movaps %xmm1, (%rbx)
; SSE-NEXT: movaps %xmm0, 16(%rbx)
@@ -496,15 +496,15 @@ define dso_local void @TestCopySign({ fp128, fp128 }* noalias nocapture sret({ f
; AVX-NEXT: testl %ebp, %ebp
; AVX-NEXT: jle .LBB10_1
; AVX-NEXT: # %bb.2: # %if.then
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm2
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX-NEXT: jmp .LBB10_3
; AVX-NEXT: .LBB10_1:
; AVX-NEXT: vmovaps (%rsp), %xmm2 # 16-byte Reload
; AVX-NEXT: .LBB10_3: # %cleanup
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmovaps %xmm2, (%rbx)
; AVX-NEXT: vmovaps %xmm0, 16(%rbx)
diff --git a/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll b/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
index d2be7fb68900e..af5b0a7c83342 100644
--- a/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
+++ b/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
@@ -15,7 +15,7 @@ define fp128 @add(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: add:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __addtf3
+; CHECK-NEXT: callq __addtf3 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -60,7 +60,7 @@ define fp128 @sub(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: sub:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __subtf3
+; CHECK-NEXT: callq __subtf3 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -105,7 +105,7 @@ define fp128 @mul(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: mul:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __multf3
+; CHECK-NEXT: callq __multf3 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -150,7 +150,7 @@ define fp128 @div(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: div:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __divtf3
+; CHECK-NEXT: callq __divtf3 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -195,7 +195,7 @@ define fp128 @fma(fp128 %x, fp128 %y, fp128 %z) nounwind strictfp {
; CHECK-LABEL: fma:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq fmal
+; CHECK-NEXT: callq fmal at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -244,7 +244,7 @@ define fp128 @frem(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: frem:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq fmodl
+; CHECK-NEXT: callq fmodl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -289,7 +289,7 @@ define fp128 @ceil(fp128 %x) nounwind strictfp {
; CHECK-LABEL: ceil:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq ceill
+; CHECK-NEXT: callq ceill at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -330,7 +330,7 @@ define fp128 @cos(fp128 %x) nounwind strictfp {
; CHECK-LABEL: cos:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq cosl
+; CHECK-NEXT: callq cosl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -371,7 +371,7 @@ define fp128 @exp(fp128 %x) nounwind strictfp {
; CHECK-LABEL: exp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq expl
+; CHECK-NEXT: callq expl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -412,7 +412,7 @@ define fp128 @exp2(fp128 %x) nounwind strictfp {
; CHECK-LABEL: exp2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq exp2l
+; CHECK-NEXT: callq exp2l at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -453,7 +453,7 @@ define fp128 @floor(fp128 %x) nounwind strictfp {
; CHECK-LABEL: floor:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq floorl
+; CHECK-NEXT: callq floorl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -494,7 +494,7 @@ define fp128 @log(fp128 %x) nounwind strictfp {
; CHECK-LABEL: log:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq logl
+; CHECK-NEXT: callq logl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -535,7 +535,7 @@ define fp128 @log10(fp128 %x) nounwind strictfp {
; CHECK-LABEL: log10:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq log10l
+; CHECK-NEXT: callq log10l at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -576,7 +576,7 @@ define fp128 @log2(fp128 %x) nounwind strictfp {
; CHECK-LABEL: log2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq log2l
+; CHECK-NEXT: callq log2l at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -617,7 +617,7 @@ define fp128 @maxnum(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: maxnum:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq fmaxl
+; CHECK-NEXT: callq fmaxl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -662,7 +662,7 @@ define fp128 @minnum(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: minnum:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq fminl
+; CHECK-NEXT: callq fminl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -707,7 +707,7 @@ define fp128 @nearbyint(fp128 %x) nounwind strictfp {
; CHECK-LABEL: nearbyint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq nearbyintl
+; CHECK-NEXT: callq nearbyintl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -748,7 +748,7 @@ define fp128 @pow(fp128 %x, fp128 %y) nounwind strictfp {
; CHECK-LABEL: pow:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq powl
+; CHECK-NEXT: callq powl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -793,7 +793,7 @@ define fp128 @powi(fp128 %x, i32 %y) nounwind strictfp {
; CHECK-LABEL: powi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __powitf2
+; CHECK-NEXT: callq __powitf2 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -835,7 +835,7 @@ define fp128 @rint(fp128 %x) nounwind strictfp {
; CHECK-LABEL: rint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq rintl
+; CHECK-NEXT: callq rintl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -876,7 +876,7 @@ define fp128 @round(fp128 %x) nounwind strictfp {
; CHECK-LABEL: round:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq roundl
+; CHECK-NEXT: callq roundl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -917,7 +917,7 @@ define fp128 @roundeven(fp128 %x) nounwind strictfp {
; CHECK-LABEL: roundeven:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq roundevenl
+; CHECK-NEXT: callq roundevenl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -958,7 +958,7 @@ define fp128 @sin(fp128 %x) nounwind strictfp {
; CHECK-LABEL: sin:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq sinl
+; CHECK-NEXT: callq sinl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -999,7 +999,7 @@ define fp128 @sqrt(fp128 %x) nounwind strictfp {
; CHECK-LABEL: sqrt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq sqrtl
+; CHECK-NEXT: callq sqrtl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -1040,7 +1040,7 @@ define fp128 @trunc(fp128 %x) nounwind strictfp {
; CHECK-LABEL: trunc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq truncl
+; CHECK-NEXT: callq truncl at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -1081,7 +1081,7 @@ define i32 @lrint(fp128 %x) nounwind strictfp {
; CHECK-LABEL: lrint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq lrintl
+; CHECK-NEXT: callq lrintl at PLT
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
;
@@ -1104,7 +1104,7 @@ define i64 @llrint(fp128 %x) nounwind strictfp {
; CHECK-LABEL: llrint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq llrintl
+; CHECK-NEXT: callq llrintl at PLT
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
;
@@ -1127,7 +1127,7 @@ define i32 @lround(fp128 %x) nounwind strictfp {
; CHECK-LABEL: lround:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq lroundl
+; CHECK-NEXT: callq lroundl at PLT
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
;
@@ -1150,7 +1150,7 @@ define i64 @llround(fp128 %x) nounwind strictfp {
; CHECK-LABEL: llround:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq llroundl
+; CHECK-NEXT: callq llroundl at PLT
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
;
@@ -1177,7 +1177,7 @@ define i64 @cmp(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movq %rsi, %r14
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq __eqtf2
+; CHECK-NEXT: callq __eqtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovneq %r14, %rbx
; CHECK-NEXT: movq %rbx, %rax
@@ -1223,7 +1223,7 @@ define i64 @cmps(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movq %rsi, %r14
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq __eqtf2
+; CHECK-NEXT: callq __eqtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovneq %r14, %rbx
; CHECK-NEXT: movq %rbx, %rax
@@ -1272,12 +1272,12 @@ define i64 @cmp_ueq_q(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 {
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movq %rsi, %r14
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq __eqtf2
+; CHECK-NEXT: callq __eqtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: sete %bpl
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq __unordtf2
+; CHECK-NEXT: callq __unordtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setne %al
; CHECK-NEXT: orb %bpl, %al
@@ -1355,12 +1355,12 @@ define i64 @cmp_one_q(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 {
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movq %rsi, %r14
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq __eqtf2
+; CHECK-NEXT: callq __eqtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setne %bpl
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq __unordtf2
+; CHECK-NEXT: callq __unordtf2 at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: sete %al
; CHECK-NEXT: testb %bpl, %al
diff --git a/llvm/test/CodeGen/X86/fp128-libcalls.ll b/llvm/test/CodeGen/X86/fp128-libcalls.ll
index a16a99288eb91..ae1125bacf8af 100644
--- a/llvm/test/CodeGen/X86/fp128-libcalls.ll
+++ b/llvm/test/CodeGen/X86/fp128-libcalls.ll
@@ -15,8 +15,8 @@ define dso_local void @Test128Add(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Add:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __addtf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq __addtf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -58,9 +58,9 @@ define dso_local void @Test128_1Add(fp128 %d1) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: callq __addtf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: movaps vf128(%rip), %xmm0
+; CHECK-NEXT: callq __addtf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -102,8 +102,8 @@ define dso_local void @Test128Sub(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Sub:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __subtf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq __subtf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -145,9 +145,9 @@ define dso_local void @Test128_1Sub(fp128 %d1) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: callq __subtf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: movaps vf128(%rip), %xmm0
+; CHECK-NEXT: callq __subtf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -189,8 +189,8 @@ define dso_local void @Test128Mul(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Mul:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __multf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq __multf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -232,9 +232,9 @@ define dso_local void @Test128_1Mul(fp128 %d1) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: callq __multf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: movaps vf128(%rip), %xmm0
+; CHECK-NEXT: callq __multf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -276,8 +276,8 @@ define dso_local void @Test128Div(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Div:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq __divtf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq __divtf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -319,9 +319,9 @@ define dso_local void @Test128_1Div(fp128 %d1) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: callq __divtf3
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: movaps vf128(%rip), %xmm0
+; CHECK-NEXT: callq __divtf3 at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -363,8 +363,8 @@ define dso_local void @Test128Rem(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Rem:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq fmodl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq fmodl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -406,9 +406,9 @@ define dso_local void @Test128_1Rem(fp128 %d1) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm0
-; CHECK-NEXT: callq fmodl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: movaps vf128(%rip), %xmm0
+; CHECK-NEXT: callq fmodl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -450,8 +450,8 @@ define dso_local void @Test128Sqrt(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Sqrt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq sqrtl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq sqrtl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -489,8 +489,8 @@ define dso_local void @Test128Sin(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Sin:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq sinl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq sinl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -528,8 +528,8 @@ define dso_local void @Test128Cos(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Cos:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq cosl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq cosl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -567,8 +567,8 @@ define dso_local void @Test128Ceil(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Ceil:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq ceill
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq ceill at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -606,8 +606,8 @@ define dso_local void @Test128Floor(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Floor:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq floorl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq floorl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -645,8 +645,8 @@ define dso_local void @Test128Trunc(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Trunc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq truncl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq truncl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -684,8 +684,8 @@ define dso_local void @Test128Nearbyint(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Nearbyint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq nearbyintl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq nearbyintl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -723,8 +723,8 @@ define dso_local void @Test128Rint(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Rint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq rintl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq rintl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
@@ -762,8 +762,8 @@ define dso_local void @Test128Round(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Round:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq roundl
-; CHECK-NEXT: movaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: callq roundl at PLT
+; CHECK-NEXT: movaps %xmm0, vf128(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/fp128-load.ll b/llvm/test/CodeGen/X86/fp128-load.ll
index 913f2a48c7602..1673921d450ab 100644
--- a/llvm/test/CodeGen/X86/fp128-load.ll
+++ b/llvm/test/CodeGen/X86/fp128-load.ll
@@ -10,7 +10,7 @@
define fp128 @get_fp128() {
; CHECK-LABEL: get_fp128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: movaps my_fp128(%rip), %xmm0
; CHECK-NEXT: retq
entry:
%0 = load fp128, fp128* @my_fp128, align 16
diff --git a/llvm/test/CodeGen/X86/fp128-select.ll b/llvm/test/CodeGen/X86/fp128-select.ll
index 65e930e26d323..3799f410afa29 100644
--- a/llvm/test/CodeGen/X86/fp128-select.ll
+++ b/llvm/test/CodeGen/X86/fp128-select.ll
@@ -14,7 +14,7 @@ define void @test_select(fp128* %p, fp128* %q, i1 zeroext %c) {
; SSE-NEXT: testl %edx, %edx
; SSE-NEXT: jne .LBB0_1
; SSE-NEXT: # %bb.2:
-; SSE-NEXT: movaps {{.*}}(%rip), %xmm0
+; SSE-NEXT: movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: movaps %xmm0, (%rsi)
; SSE-NEXT: retq
; SSE-NEXT: .LBB0_1:
@@ -50,18 +50,18 @@ define fp128 @test_select_cc(fp128, fp128) {
; SSE-NEXT: .cfi_offset %rbx, -16
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: callq __netf2
+; SSE-NEXT: callq __netf2 at PLT
; SSE-NEXT: movl %eax, %ebx
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; SSE-NEXT: callq __eqtf2
+; SSE-NEXT: callq __eqtf2 at PLT
; SSE-NEXT: testl %eax, %eax
; SSE-NEXT: je .LBB1_1
; SSE-NEXT: # %bb.2: # %BB0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: jmp .LBB1_3
; SSE-NEXT: .LBB1_1:
-; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
+; SSE-NEXT: movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: .LBB1_3: # %BB0
; SSE-NEXT: testl %ebx, %ebx
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
@@ -96,13 +96,13 @@ define fp128 @test_select_cc(fp128, fp128) {
; NOSSE-NEXT: movq %rdx, %rbx
; NOSSE-NEXT: movq %rsi, %r14
; NOSSE-NEXT: movq %rdi, %r15
-; NOSSE-NEXT: callq __netf2
+; NOSSE-NEXT: callq __netf2 at PLT
; NOSSE-NEXT: movl %eax, %ebp
; NOSSE-NEXT: movq %r15, %rdi
; NOSSE-NEXT: movq %r14, %rsi
; NOSSE-NEXT: movq %rbx, %rdx
; NOSSE-NEXT: movq %r12, %rcx
-; NOSSE-NEXT: callq __eqtf2
+; NOSSE-NEXT: callq __eqtf2 at PLT
; NOSSE-NEXT: movl %eax, %ecx
; NOSSE-NEXT: xorl %eax, %eax
; NOSSE-NEXT: testl %ecx, %ecx
diff --git a/llvm/test/CodeGen/X86/fp80-strict-libcalls.ll b/llvm/test/CodeGen/X86/fp80-strict-libcalls.ll
index 6b29ffbb976e9..4d50b15e5c185 100644
--- a/llvm/test/CodeGen/X86/fp80-strict-libcalls.ll
+++ b/llvm/test/CodeGen/X86/fp80-strict-libcalls.ll
@@ -27,7 +27,7 @@ define x86_fp80 @fma(x86_fp80 %x, x86_fp80 %y, x86_fp80 %z) nounwind strictfp {
; X64-NEXT: fstpt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq fmal
+; X64-NEXT: callq fmal at PLT
; X64-NEXT: addq $56, %rsp
; X64-NEXT: retq
entry:
@@ -56,7 +56,7 @@ define x86_fp80 @frem(x86_fp80 %x, x86_fp80 %y) nounwind strictfp {
; X64-NEXT: fstpt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq fmodl
+; X64-NEXT: callq fmodl at PLT
; X64-NEXT: addq $40, %rsp
; X64-NEXT: retq
entry:
@@ -81,7 +81,7 @@ define x86_fp80 @ceil(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq ceill
+; X64-NEXT: callq ceill at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -106,7 +106,7 @@ define x86_fp80 @cos(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq cosl
+; X64-NEXT: callq cosl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -131,7 +131,7 @@ define x86_fp80 @exp(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq expl
+; X64-NEXT: callq expl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -156,7 +156,7 @@ define x86_fp80 @exp2(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq exp2l
+; X64-NEXT: callq exp2l at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -181,7 +181,7 @@ define x86_fp80 @floor(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq floorl
+; X64-NEXT: callq floorl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -206,7 +206,7 @@ define x86_fp80 @log(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq logl
+; X64-NEXT: callq logl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -231,7 +231,7 @@ define x86_fp80 @log10(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq log10l
+; X64-NEXT: callq log10l at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -256,7 +256,7 @@ define x86_fp80 @log2(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq log2l
+; X64-NEXT: callq log2l at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -285,7 +285,7 @@ define x86_fp80 @maxnum(x86_fp80 %x, x86_fp80 %y) nounwind strictfp {
; X64-NEXT: fstpt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq fmaxl
+; X64-NEXT: callq fmaxl at PLT
; X64-NEXT: addq $40, %rsp
; X64-NEXT: retq
entry:
@@ -314,7 +314,7 @@ define x86_fp80 @minnum(x86_fp80 %x, x86_fp80 %y) nounwind strictfp {
; X64-NEXT: fstpt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq fminl
+; X64-NEXT: callq fminl at PLT
; X64-NEXT: addq $40, %rsp
; X64-NEXT: retq
entry:
@@ -339,7 +339,7 @@ define x86_fp80 @nearbyint(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq nearbyintl
+; X64-NEXT: callq nearbyintl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -368,7 +368,7 @@ define x86_fp80 @pow(x86_fp80 %x, x86_fp80 %y) nounwind strictfp {
; X64-NEXT: fstpt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq powl
+; X64-NEXT: callq powl at PLT
; X64-NEXT: addq $40, %rsp
; X64-NEXT: retq
entry:
@@ -396,7 +396,7 @@ define x86_fp80 @powi(x86_fp80 %x, i32 %y) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq __powixf2
+; X64-NEXT: callq __powixf2 at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -421,7 +421,7 @@ define x86_fp80 @rint(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq rintl
+; X64-NEXT: callq rintl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -446,7 +446,7 @@ define x86_fp80 @round(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq roundl
+; X64-NEXT: callq roundl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -471,7 +471,7 @@ define x86_fp80 @roundeven(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq roundevenl
+; X64-NEXT: callq roundevenl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -496,7 +496,7 @@ define x86_fp80 @sin(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq sinl
+; X64-NEXT: callq sinl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -521,7 +521,7 @@ define x86_fp80 @trunc(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq truncl
+; X64-NEXT: callq truncl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -546,7 +546,7 @@ define i32 @lrint(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq lrintl
+; X64-NEXT: callq lrintl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -571,7 +571,7 @@ define i64 @llrint(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq llrintl
+; X64-NEXT: callq llrintl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -596,7 +596,7 @@ define i32 @lround(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq lroundl
+; X64-NEXT: callq lroundl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
@@ -621,7 +621,7 @@ define i64 @llround(x86_fp80 %x) nounwind strictfp {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: wait
-; X64-NEXT: callq llroundl
+; X64-NEXT: callq llroundl at PLT
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/fp80-strict-scalar.ll b/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
index da638c2e4ff2a..818ca08ae2d23 100644
--- a/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
+++ b/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
@@ -588,7 +588,7 @@ define i64 @fp80_to_uint64(x86_fp80 %x) #0 {
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp
; X86-NEXT: fldt 8(%ebp)
-; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fcom %st(1)
; X86-NEXT: wait
; X86-NEXT: fnstsw %ax
@@ -624,7 +624,7 @@ define i64 @fp80_to_uint64(x86_fp80 %x) #0 {
; X64-LABEL: fp80_to_uint64:
; X64: # %bb.0:
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: wait
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: fcomi %st(1), %st
@@ -905,7 +905,7 @@ define x86_fp80 @uint64_to_fp80(i64 %x) #0 {
; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: shrl $31, %ecx
; X86-NEXT: fildll (%esp)
-; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X86-NEXT: wait
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
@@ -919,7 +919,7 @@ define x86_fp80 @uint64_to_fp80(i64 %x) #0 {
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: sets %al
; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
-; X64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rax,4)
+; X64-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%rax,4)
; X64-NEXT: wait
; X64-NEXT: retq
%result = call x86_fp80 @llvm.experimental.constrained.uitofp.f80.i64(i64 %x,
diff --git a/llvm/test/CodeGen/X86/fptosi-constant.ll b/llvm/test/CodeGen/X86/fptosi-constant.ll
index 7baeff3246e5d..83dac957d9fec 100644
--- a/llvm/test/CodeGen/X86/fptosi-constant.ll
+++ b/llvm/test/CodeGen/X86/fptosi-constant.ll
@@ -6,7 +6,7 @@
define i32 @constant_v2f64_to_i32() {
; CHECK-LABEL: constant_v2f64_to_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvtsd2si {{.*}}(%rip), %eax
+; CHECK-NEXT: cvtsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
; CHECK-NEXT: retq
%r = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> <double 5.0e+09, double undef>)
ret i32 %r
@@ -15,7 +15,7 @@ define i32 @constant_v2f64_to_i32() {
define i32 @constant_v2f64_to_i32_round_to_zero() {
; CHECK-LABEL: constant_v2f64_to_i32_round_to_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %eax
+; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
; CHECK-NEXT: retq
%r = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> <double 5.0e+09, double undef>)
ret i32 %r
@@ -24,7 +24,7 @@ define i32 @constant_v2f64_to_i32_round_to_zero() {
define i64 @constant_v2f64_to_i64() {
; CHECK-LABEL: constant_v2f64_to_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvtsd2si {{.*}}(%rip), %rax
+; CHECK-NEXT: cvtsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
; CHECK-NEXT: retq
%r = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> <double 5.0e+19, double undef>)
ret i64 %r
@@ -33,7 +33,7 @@ define i64 @constant_v2f64_to_i64() {
define i64 @constant_v2f64_to_i64_round_to_zero() {
; CHECK-LABEL: constant_v2f64_to_i64_round_to_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rax
+; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
; CHECK-NEXT: retq
%r = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> <double 5.0e+19, double undef>)
ret i64 %r
@@ -42,7 +42,7 @@ define i64 @constant_v2f64_to_i64_round_to_zero() {
define <4 x i32> @constant_v2f64_to_v4i32() {
; CHECK-LABEL: constant_v2f64_to_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvtpd2dq {{.*}}(%rip), %xmm0
+; CHECK-NEXT: cvtpd2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%r = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> <double 5.0e+09, double 5.0e+09>)
ret <4 x i32> %r
@@ -51,7 +51,7 @@ define <4 x i32> @constant_v2f64_to_v4i32() {
define <4 x i32> @constant_v2f64_to_v4i32_round_to_zero() {
; CHECK-LABEL: constant_v2f64_to_v4i32_round_to_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvttpd2dq {{.*}}(%rip), %xmm0
+; CHECK-NEXT: cvttpd2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%r = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> <double 5.0e+09, double 5.0e+09>)
ret <4 x i32> %r
@@ -60,7 +60,7 @@ define <4 x i32> @constant_v2f64_to_v4i32_round_to_zero() {
define i32 @constant_v4f32_to_i32() {
; CHECK-LABEL: constant_v4f32_to_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvtss2si {{.*}}(%rip), %eax
+; CHECK-NEXT: cvtss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
; CHECK-NEXT: retq
%r = call i32 @llvm.x86.sse.cvtss2si(<4 x float> <float 5.0e+09, float undef, float undef, float undef>)
ret i32 %r
@@ -69,7 +69,7 @@ define i32 @constant_v4f32_to_i32() {
define i32 @constant_v4f32_to_i32_round_to_zero() {
; CHECK-LABEL: constant_v4f32_to_i32_round_to_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvttss2si {{.*}}(%rip), %eax
+; CHECK-NEXT: cvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
; CHECK-NEXT: retq
%r = call i32 @llvm.x86.sse.cvttss2si(<4 x float> <float 5.0e+09, float undef, float undef, float undef>)
ret i32 %r
@@ -80,7 +80,7 @@ define i32 @constant_v4f32_to_i32_round_to_zero() {
define i64 @constant_v4f32_to_i64() {
; CHECK-LABEL: constant_v4f32_to_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvtss2si {{.*}}(%rip), %rax
+; CHECK-NEXT: cvtss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
; CHECK-NEXT: retq
%r = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> <float 9223372036854775808.0, float undef, float undef, float undef>)
ret i64 %r
@@ -89,7 +89,7 @@ define i64 @constant_v4f32_to_i64() {
define i64 @constant_v4f32_to_i64_round_to_zero() {
; CHECK-LABEL: constant_v4f32_to_i64_round_to_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rax
+; CHECK-NEXT: cvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
; CHECK-NEXT: retq
%r = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> <float 9223372036854775808.0, float undef, float undef, float undef>)
ret i64 %r
@@ -98,7 +98,7 @@ define i64 @constant_v4f32_to_i64_round_to_zero() {
define <4 x i32> @constant_v4f32_to_v4i32() {
; CHECK-LABEL: constant_v4f32_to_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvtps2dq {{.*}}(%rip), %xmm0
+; CHECK-NEXT: cvtps2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%r = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> <float 5.0e+09, float 5.0e+09, float 5.0e+09, float 5.0e+09>)
ret <4 x i32> %r
@@ -107,7 +107,7 @@ define <4 x i32> @constant_v4f32_to_v4i32() {
define <4 x i32> @constant_v4f32_to_v4i32_round_to_zero() {
; CHECK-LABEL: constant_v4f32_to_v4i32_round_to_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: cvttps2dq {{.*}}(%rip), %xmm0
+; CHECK-NEXT: cvttps2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%r = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> <float 5.0e+09, float 5.0e+09, float 5.0e+09, float 5.0e+09>)
ret <4 x i32> %r
diff --git a/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll b/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
index 37d8ace804e59..7a8c3a78f9c32 100644
--- a/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
@@ -105,7 +105,7 @@ define i8 @test_signed_i8_f32(float %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -117,7 +117,7 @@ define i8 @test_signed_i8_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB1_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -176,7 +176,7 @@ define i13 @test_signed_i13_f32(float %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -188,7 +188,7 @@ define i13 @test_signed_i13_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB2_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -248,7 +248,7 @@ define i16 @test_signed_i16_f32(float %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -260,7 +260,7 @@ define i16 @test_signed_i16_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB3_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -320,7 +320,7 @@ define i19 @test_signed_i19_f32(float %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -332,7 +332,7 @@ define i19 @test_signed_i19_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB4_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -362,8 +362,8 @@ define i19 @test_signed_i19_f32(float %f) nounwind {
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
-; X86-SSE-NEXT: maxss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: maxss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: retl
@@ -372,8 +372,8 @@ define i19 @test_signed_i19_f32(float %f) nounwind {
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomiss %xmm0, %xmm0
-; X64-NEXT: maxss {{.*}}(%rip), %xmm0
-; X64-NEXT: minss {{.*}}(%rip), %xmm0
+; X64-NEXT: maxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttss2si %xmm0, %ecx
; X64-NEXT: cmovnpl %ecx, %eax
; X64-NEXT: retq
@@ -393,7 +393,7 @@ define i32 @test_signed_i32_f32(float %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -405,7 +405,7 @@ define i32 @test_signed_i32_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB5_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -434,7 +434,7 @@ define i32 @test_signed_i32_f32(float %f) nounwind {
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: cvttss2si %xmm0, %eax
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax
@@ -445,7 +445,7 @@ define i32 @test_signed_i32_f32(float %f) nounwind {
; X64-LABEL: test_signed_i32_f32:
; X64: # %bb.0:
; X64-NEXT: cvttss2si %xmm0, %eax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
; X64-NEXT: cmovbel %eax, %ecx
; X64-NEXT: xorl %eax, %eax
@@ -471,7 +471,7 @@ define i50 @test_signed_i50_f32(float %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -489,7 +489,7 @@ define i50 @test_signed_i50_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB6_4:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -537,12 +537,12 @@ define i50 @test_signed_i50_f32(float %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -557,10 +557,10 @@ define i50 @test_signed_i50_f32(float %f) nounwind {
; X64-LABEL: test_signed_i50_f32:
; X64: # %bb.0:
; X64-NEXT: cvttss2si %xmm0, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $-562949953421312, %rcx # imm = 0xFFFE000000000000
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $562949953421311, %rdx # imm = 0x1FFFFFFFFFFFF
; X64-NEXT: cmovbeq %rcx, %rdx
; X64-NEXT: xorl %eax, %eax
@@ -586,7 +586,7 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -604,7 +604,7 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB7_4:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -652,12 +652,12 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -672,7 +672,7 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; X64-LABEL: test_signed_i64_f32:
; X64: # %bb.0:
; X64-NEXT: cvttss2si %xmm0, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: cmovbeq %rax, %rcx
; X64-NEXT: xorl %eax, %eax
@@ -695,7 +695,7 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp
@@ -723,7 +723,7 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB8_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -789,7 +789,7 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %ebp, %ebp
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-8, %ebx
; X86-SSE-NEXT: movl $0, %ecx
; X86-SSE-NEXT: movl $0, %edx
@@ -801,7 +801,7 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB8_2:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmoval %eax, %edi
; X86-SSE-NEXT: cmoval %eax, %edx
@@ -834,11 +834,11 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
; X64-NEXT: # xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-34359738368, %rsi # imm = 0xFFFFFFF800000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $34359738367, %rsi # imm = 0x7FFFFFFFF
; X64-NEXT: cmovaq %rsi, %rdx
; X64-NEXT: movq $-1, %rsi
@@ -864,7 +864,7 @@ define i128 @test_signed_i128_f32(float %f) nounwind {
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp
@@ -888,7 +888,7 @@ define i128 @test_signed_i128_f32(float %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB9_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -964,7 +964,7 @@ define i128 @test_signed_i128_f32(float %f) nounwind {
; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: cmovbl %ecx, %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -973,7 +973,7 @@ define i128 @test_signed_i128_f32(float %f) nounwind {
; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %ebx, %ebp
; X86-SSE-NEXT: movl $-1, %ebx
@@ -1005,11 +1005,11 @@ define i128 @test_signed_i128_f32(float %f) nounwind {
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
; X64-NEXT: # xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: cmovaq %rsi, %rdx
; X64-NEXT: movq $-1, %rsi
@@ -1125,7 +1125,7 @@ define i8 @test_signed_i8_f64(double %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1137,7 +1137,7 @@ define i8 @test_signed_i8_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB11_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1196,7 +1196,7 @@ define i13 @test_signed_i13_f64(double %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1208,7 +1208,7 @@ define i13 @test_signed_i13_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB12_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1268,7 +1268,7 @@ define i16 @test_signed_i16_f64(double %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1280,7 +1280,7 @@ define i16 @test_signed_i16_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB13_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1340,7 +1340,7 @@ define i19 @test_signed_i19_f64(double %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1352,7 +1352,7 @@ define i19 @test_signed_i19_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB14_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1382,8 +1382,8 @@ define i19 @test_signed_i19_f64(double %f) nounwind {
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
-; X86-SSE-NEXT: maxsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: retl
@@ -1392,8 +1392,8 @@ define i19 @test_signed_i19_f64(double %f) nounwind {
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomisd %xmm0, %xmm0
-; X64-NEXT: maxsd {{.*}}(%rip), %xmm0
-; X64-NEXT: minsd {{.*}}(%rip), %xmm0
+; X64-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttsd2si %xmm0, %ecx
; X64-NEXT: cmovnpl %ecx, %eax
; X64-NEXT: retq
@@ -1413,7 +1413,7 @@ define i32 @test_signed_i32_f64(double %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1425,7 +1425,7 @@ define i32 @test_signed_i32_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB15_2:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1455,8 +1455,8 @@ define i32 @test_signed_i32_f64(double %f) nounwind {
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
-; X86-SSE-NEXT: maxsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: retl
@@ -1465,8 +1465,8 @@ define i32 @test_signed_i32_f64(double %f) nounwind {
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomisd %xmm0, %xmm0
-; X64-NEXT: maxsd {{.*}}(%rip), %xmm0
-; X64-NEXT: minsd {{.*}}(%rip), %xmm0
+; X64-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttsd2si %xmm0, %ecx
; X64-NEXT: cmovnpl %ecx, %eax
; X64-NEXT: retq
@@ -1489,7 +1489,7 @@ define i50 @test_signed_i50_f64(double %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1507,7 +1507,7 @@ define i50 @test_signed_i50_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB16_4:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1555,12 +1555,12 @@ define i50 @test_signed_i50_f64(double %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -1576,8 +1576,8 @@ define i50 @test_signed_i50_f64(double %f) nounwind {
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomisd %xmm0, %xmm0
-; X64-NEXT: maxsd {{.*}}(%rip), %xmm0
-; X64-NEXT: minsd {{.*}}(%rip), %xmm0
+; X64-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttsd2si %xmm0, %rcx
; X64-NEXT: cmovnpq %rcx, %rax
; X64-NEXT: retq
@@ -1600,7 +1600,7 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1618,7 +1618,7 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB17_4:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1666,12 +1666,12 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -1686,7 +1686,7 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; X64-LABEL: test_signed_i64_f64:
; X64: # %bb.0:
; X64-NEXT: cvttsd2si %xmm0, %rax
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: cmovbeq %rax, %rcx
; X64-NEXT: xorl %eax, %eax
@@ -1709,7 +1709,7 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; X86-X87-NEXT: fstl {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fstl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Spill
; X86-X87-NEXT: fucompp
@@ -1737,7 +1737,7 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB18_6:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1803,7 +1803,7 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorl %ebp, %ebp
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-8, %ebx
; X86-SSE-NEXT: movl $0, %ecx
; X86-SSE-NEXT: movl $0, %edx
@@ -1815,7 +1815,7 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB18_2:
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmoval %eax, %edi
; X86-SSE-NEXT: cmoval %eax, %edx
@@ -1848,11 +1848,11 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; X64-NEXT: # xmm0 = mem[0],zero
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-34359738368, %rsi # imm = 0xFFFFFFF800000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $34359738367, %rsi # imm = 0x7FFFFFFFF
; X64-NEXT: cmovaq %rsi, %rdx
; X64-NEXT: movq $-1, %rsi
@@ -1878,7 +1878,7 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; X86-X87-NEXT: fstl {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fstl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Spill
; X86-X87-NEXT: fucompp
@@ -1902,7 +1902,7 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB19_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -1978,7 +1978,7 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: cmovbl %ecx, %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -1987,7 +1987,7 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %ebx, %ebp
; X86-SSE-NEXT: movl $-1, %ebx
@@ -2019,11 +2019,11 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; X64-NEXT: # xmm0 = mem[0],zero
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: cmovaq %rsi, %rdx
; X64-NEXT: movq $-1, %rsi
@@ -2153,7 +2153,7 @@ define i8 @test_signed_i8_f16(half %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2165,7 +2165,7 @@ define i8 @test_signed_i8_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB21_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2236,7 +2236,7 @@ define i13 @test_signed_i13_f16(half %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2248,7 +2248,7 @@ define i13 @test_signed_i13_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB22_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2320,7 +2320,7 @@ define i16 @test_signed_i16_f16(half %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2332,7 +2332,7 @@ define i16 @test_signed_i16_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB23_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2404,7 +2404,7 @@ define i19 @test_signed_i19_f16(half %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2416,7 +2416,7 @@ define i19 @test_signed_i19_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB24_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2451,8 +2451,8 @@ define i19 @test_signed_i19_f16(half %f) nounwind {
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
-; X86-SSE-NEXT: maxss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: maxss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: addl $12, %esp
@@ -2465,8 +2465,8 @@ define i19 @test_signed_i19_f16(half %f) nounwind {
; X64-NEXT: callq __gnu_h2f_ieee at PLT
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomiss %xmm0, %xmm0
-; X64-NEXT: maxss {{.*}}(%rip), %xmm0
-; X64-NEXT: minss {{.*}}(%rip), %xmm0
+; X64-NEXT: maxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttss2si %xmm0, %ecx
; X64-NEXT: cmovnpl %ecx, %eax
; X64-NEXT: popq %rcx
@@ -2489,7 +2489,7 @@ define i32 @test_signed_i32_f16(half %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2501,7 +2501,7 @@ define i32 @test_signed_i32_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB25_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2535,7 +2535,7 @@ define i32 @test_signed_i32_f16(half %f) nounwind {
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: cvttss2si %xmm0, %eax
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax
@@ -2550,7 +2550,7 @@ define i32 @test_signed_i32_f16(half %f) nounwind {
; X64-NEXT: movzwl %di, %edi
; X64-NEXT: callq __gnu_h2f_ieee at PLT
; X64-NEXT: cvttss2si %xmm0, %eax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
; X64-NEXT: cmovbel %eax, %ecx
; X64-NEXT: xorl %eax, %eax
@@ -2579,7 +2579,7 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2597,7 +2597,7 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB26_4:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2649,12 +2649,12 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -2672,10 +2672,10 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
; X64-NEXT: movzwl %di, %edi
; X64-NEXT: callq __gnu_h2f_ieee at PLT
; X64-NEXT: cvttss2si %xmm0, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $-562949953421312, %rcx # imm = 0xFFFE000000000000
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $562949953421311, %rdx # imm = 0x1FFFFFFFFFFFF
; X64-NEXT: cmovbeq %rcx, %rdx
; X64-NEXT: xorl %eax, %eax
@@ -2704,7 +2704,7 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2722,7 +2722,7 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB27_4:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2774,12 +2774,12 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -2797,7 +2797,7 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; X64-NEXT: movzwl %di, %edi
; X64-NEXT: callq __gnu_h2f_ieee at PLT
; X64-NEXT: cvttss2si %xmm0, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: cmovbeq %rax, %rcx
; X64-NEXT: xorl %eax, %eax
@@ -2823,7 +2823,7 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp
@@ -2851,7 +2851,7 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB28_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -2923,7 +2923,7 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; X86-SSE-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload
; X86-SSE-NEXT: # xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %ebp, %ebp
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-8, %ebx
; X86-SSE-NEXT: movl $0, %ecx
; X86-SSE-NEXT: movl $0, %edx
@@ -2935,7 +2935,7 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB28_2:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmoval %eax, %edi
; X86-SSE-NEXT: cmoval %eax, %edx
@@ -2970,11 +2970,11 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
; X64-NEXT: # xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-34359738368, %rsi # imm = 0xFFFFFFF800000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $34359738367, %rsi # imm = 0x7FFFFFFFF
; X64-NEXT: cmovaq %rsi, %rdx
; X64-NEXT: movq $-1, %rsi
@@ -3002,7 +3002,7 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp
@@ -3026,7 +3026,7 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB29_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3108,7 +3108,7 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload
; X86-SSE-NEXT: # xmm0 = mem[0],zero,zero,zero
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: cmovbl %ecx, %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -3117,7 +3117,7 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %ebx, %ebp
; X86-SSE-NEXT: movl $-1, %ebx
@@ -3151,11 +3151,11 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
; X64-NEXT: # xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: cmovaq %rsi, %rdx
; X64-NEXT: movq $-1, %rsi
@@ -3311,7 +3311,7 @@ define i8 @test_signed_i8_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3323,7 +3323,7 @@ define i8 @test_signed_i8_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB31_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3359,13 +3359,13 @@ define i8 @test_signed_i8_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $128, %ecx
; X86-SSE-NEXT: cmovael %eax, %ecx
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3389,13 +3389,13 @@ define i8 @test_signed_i8_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fists -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
; X64-NEXT: movl $128, %ecx
; X64-NEXT: cmovael %eax, %ecx
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3422,7 +3422,7 @@ define i13 @test_signed_i13_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3434,7 +3434,7 @@ define i13 @test_signed_i13_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB32_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3470,7 +3470,7 @@ define i13 @test_signed_i13_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3479,7 +3479,7 @@ define i13 @test_signed_i13_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB32_2:
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3502,7 +3502,7 @@ define i13 @test_signed_i13_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: fists -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3511,7 +3511,7 @@ define i13 @test_signed_i13_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: .LBB32_2:
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3538,7 +3538,7 @@ define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3550,7 +3550,7 @@ define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB33_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3586,7 +3586,7 @@ define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3595,7 +3595,7 @@ define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB33_2:
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3618,7 +3618,7 @@ define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: fists -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3627,7 +3627,7 @@ define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: .LBB33_2:
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3654,7 +3654,7 @@ define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3666,7 +3666,7 @@ define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB34_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3702,7 +3702,7 @@ define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw (%esp)
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3711,7 +3711,7 @@ define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB34_2:
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3733,7 +3733,7 @@ define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: fistl -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3742,7 +3742,7 @@ define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: .LBB34_2:
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3768,7 +3768,7 @@ define i32 @test_signed_i32_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3780,7 +3780,7 @@ define i32 @test_signed_i32_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB35_2:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3816,7 +3816,7 @@ define i32 @test_signed_i32_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw (%esp)
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3825,7 +3825,7 @@ define i32 @test_signed_i32_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB35_2:
-; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3847,7 +3847,7 @@ define i32 @test_signed_i32_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: fistl -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3856,7 +3856,7 @@ define i32 @test_signed_i32_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: .LBB35_2:
-; X64-NEXT: fldl {{.*}}(%rip)
+; X64-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3885,7 +3885,7 @@ define i50 @test_signed_i50_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3903,7 +3903,7 @@ define i50 @test_signed_i50_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB36_4:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -3950,7 +3950,7 @@ define i50 @test_signed_i50_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3958,7 +3958,7 @@ define i50 @test_signed_i50_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -3984,7 +3984,7 @@ define i50 @test_signed_i50_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fld %st(0)
; X64-NEXT: fistpll -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -3995,7 +3995,7 @@ define i50 @test_signed_i50_f80(x86_fp80 %f) nounwind {
; X64-NEXT: .LBB36_1:
; X64-NEXT: movabsq $-562949953421312, %rax # imm = 0xFFFE000000000000
; X64-NEXT: .LBB36_3:
-; X64-NEXT: fldl {{.*}}(%rip)
+; X64-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -4024,7 +4024,7 @@ define i64 @test_signed_i64_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -4042,7 +4042,7 @@ define i64 @test_signed_i64_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB37_4:
-; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -4089,7 +4089,7 @@ define i64 @test_signed_i64_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -4097,7 +4097,7 @@ define i64 @test_signed_i64_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -4123,7 +4123,7 @@ define i64 @test_signed_i64_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fld %st(0)
; X64-NEXT: fistpll -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -4134,7 +4134,7 @@ define i64 @test_signed_i64_f80(x86_fp80 %f) nounwind {
; X64-NEXT: .LBB37_1:
; X64-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
; X64-NEXT: .LBB37_3:
-; X64-NEXT: fldt {{.*}}(%rip)
+; X64-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -4161,7 +4161,7 @@ define i100 @test_signed_i100_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fstpt {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fld %st(1)
; X86-X87-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
; X86-X87-NEXT: fxch %st(1)
@@ -4190,7 +4190,7 @@ define i100 @test_signed_i100_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB38_6:
-; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -4258,7 +4258,7 @@ define i100 @test_signed_i100_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-SSE-NEXT: xorl %ebp, %ebp
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -4273,7 +4273,7 @@ define i100 @test_signed_i100_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB38_2:
-; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -4310,14 +4310,14 @@ define i100 @test_signed_i100_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: callq __fixxfti at PLT
; X64-NEXT: xorl %ecx, %ecx
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fldt {{[-0-9]+}}(%r{{[sb]}}p) # 10-byte Folded Reload
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-34359738368, %rsi # imm = 0xFFFFFFF800000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: fldt {{.*}}(%rip)
+; X64-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
@@ -4347,7 +4347,7 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: fstpt {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fld %st(1)
; X86-X87-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
; X86-X87-NEXT: fxch %st(1)
@@ -4372,7 +4372,7 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB39_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1)
@@ -4449,7 +4449,7 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: calll __fixxfti
; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: xorl %ecx, %ecx
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -4461,7 +4461,7 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
-; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
@@ -4497,14 +4497,14 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fstpt (%rsp)
; X64-NEXT: callq __fixxfti at PLT
; X64-NEXT: xorl %ecx, %ecx
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fldt {{[-0-9]+}}(%r{{[sb]}}p) # 10-byte Folded Reload
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
; X64-NEXT: cmovbq %rcx, %rax
; X64-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
; X64-NEXT: cmovbq %rsi, %rdx
-; X64-NEXT: fldt {{.*}}(%rip)
+; X64-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
diff --git a/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll b/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
index 18bc6400c5834..4bf6fe99c0717 100644
--- a/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
@@ -107,7 +107,7 @@ define i8 @test_unsigned_i8_f32(float %f) nounwind {
; X86-X87-NEXT: .LBB1_1:
; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB1_3:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -168,7 +168,7 @@ define i13 @test_unsigned_i13_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB2_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -230,7 +230,7 @@ define i16 @test_unsigned_i16_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB3_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -293,7 +293,7 @@ define i19 @test_unsigned_i19_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB4_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -312,7 +312,7 @@ define i19 @test_unsigned_i19_f32(float %f) nounwind {
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: maxss %xmm1, %xmm0
-; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %eax
; X86-SSE-NEXT: retl
;
@@ -320,7 +320,7 @@ define i19 @test_unsigned_i19_f32(float %f) nounwind {
; X64: # %bb.0:
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: maxss %xmm1, %xmm0
-; X64-NEXT: minss {{.*}}(%rip), %xmm0
+; X64-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttss2si %xmm0, %eax
; X64-NEXT: retq
%x = call i19 @llvm.fptoui.sat.i19.f32(float %f)
@@ -352,7 +352,7 @@ define i32 @test_unsigned_i32_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB5_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -381,7 +381,7 @@ define i32 @test_unsigned_i32_f32(float %f) nounwind {
; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: ucomiss %xmm1, %xmm0
; X86-SSE-NEXT: cmovael %ecx, %edx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %edx, %eax
; X86-SSE-NEXT: retl
@@ -393,7 +393,7 @@ define i32 @test_unsigned_i32_f32(float %f) nounwind {
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: ucomiss %xmm1, %xmm0
; X64-NEXT: cmovael %eax, %ecx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movl $-1, %eax
; X64-NEXT: cmovbel %ecx, %eax
; X64-NEXT: retq
@@ -407,7 +407,7 @@ define i50 @test_unsigned_i50_f32(float %f) nounwind {
; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $16, %esp
; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx
@@ -449,7 +449,7 @@ define i50 @test_unsigned_i50_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB6_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -503,7 +503,7 @@ define i50 @test_unsigned_i50_f32(float %f) nounwind {
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: .LBB6_4:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -519,7 +519,7 @@ define i50 @test_unsigned_i50_f32(float %f) nounwind {
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: ucomiss %xmm1, %xmm0
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $1125899906842623, %rax # imm = 0x3FFFFFFFFFFFF
; X64-NEXT: cmovbeq %rcx, %rax
; X64-NEXT: retq
@@ -534,7 +534,7 @@ define i64 @test_unsigned_i64_f32(float %f) nounwind {
; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $20, %esp
; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx
@@ -576,7 +576,7 @@ define i64 @test_unsigned_i64_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB7_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -627,7 +627,7 @@ define i64 @test_unsigned_i64_f32(float %f) nounwind {
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB7_4:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ecx
; X86-SSE-NEXT: cmoval %ecx, %edx
; X86-SSE-NEXT: cmoval %ecx, %eax
@@ -649,7 +649,7 @@ define i64 @test_unsigned_i64_f32(float %f) nounwind {
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: ucomiss %xmm1, %xmm0
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movq $-1, %rax
; X64-NEXT: cmovbeq %rcx, %rax
; X64-NEXT: retq
@@ -698,7 +698,7 @@ define i100 @test_unsigned_i100_f32(float %f) nounwind {
; X86-X87-NEXT: .LBB8_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -759,7 +759,7 @@ define i100 @test_unsigned_i100_f32(float %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB8_2:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $15, %ebx
; X86-SSE-NEXT: cmovbel %edi, %ebx
; X86-SSE-NEXT: movl $-1, %edi
@@ -790,7 +790,7 @@ define i100 @test_unsigned_i100_f32(float %f) nounwind {
; X64-NEXT: ucomiss %xmm0, %xmm1
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm1
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: cmovaq %rcx, %rax
; X64-NEXT: movabsq $68719476735, %rcx # imm = 0xFFFFFFFFF
@@ -843,7 +843,7 @@ define i128 @test_unsigned_i128_f32(float %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB9_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -900,7 +900,7 @@ define i128 @test_unsigned_i128_f32(float %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB9_2:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx
@@ -929,7 +929,7 @@ define i128 @test_unsigned_i128_f32(float %f) nounwind {
; X64-NEXT: ucomiss %xmm0, %xmm1
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm1
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: cmovaq %rcx, %rax
; X64-NEXT: cmovaq %rcx, %rdx
@@ -1043,7 +1043,7 @@ define i8 @test_unsigned_i8_f64(double %f) nounwind {
; X86-X87-NEXT: .LBB11_1:
; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB11_3:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1104,7 +1104,7 @@ define i13 @test_unsigned_i13_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB12_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1166,7 +1166,7 @@ define i16 @test_unsigned_i16_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB13_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1229,7 +1229,7 @@ define i19 @test_unsigned_i19_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB14_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1248,7 +1248,7 @@ define i19 @test_unsigned_i19_f64(double %f) nounwind {
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorpd %xmm1, %xmm1
; X86-SSE-NEXT: maxsd %xmm1, %xmm0
-; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %eax
; X86-SSE-NEXT: retl
;
@@ -1256,7 +1256,7 @@ define i19 @test_unsigned_i19_f64(double %f) nounwind {
; X64: # %bb.0:
; X64-NEXT: xorpd %xmm1, %xmm1
; X64-NEXT: maxsd %xmm1, %xmm0
-; X64-NEXT: minsd {{.*}}(%rip), %xmm0
+; X64-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttsd2si %xmm0, %eax
; X64-NEXT: retq
%x = call i19 @llvm.fptoui.sat.i19.f64(double %f)
@@ -1288,7 +1288,7 @@ define i32 @test_unsigned_i32_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB15_2:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1307,7 +1307,7 @@ define i32 @test_unsigned_i32_f64(double %f) nounwind {
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorpd %xmm1, %xmm1
; X86-SSE-NEXT: maxsd %xmm1, %xmm0
-; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx
; X86-SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; X86-SSE-NEXT: movapd %xmm0, %xmm2
@@ -1337,7 +1337,7 @@ define i50 @test_unsigned_i50_f64(double %f) nounwind {
; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $16, %esp
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx
@@ -1379,7 +1379,7 @@ define i50 @test_unsigned_i50_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB16_6:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1433,7 +1433,7 @@ define i50 @test_unsigned_i50_f64(double %f) nounwind {
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: .LBB16_4:
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -1446,7 +1446,7 @@ define i50 @test_unsigned_i50_f64(double %f) nounwind {
; X64: # %bb.0:
; X64-NEXT: xorpd %xmm1, %xmm1
; X64-NEXT: maxsd %xmm1, %xmm0
-; X64-NEXT: minsd {{.*}}(%rip), %xmm0
+; X64-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttsd2si %xmm0, %rax
; X64-NEXT: retq
%x = call i50 @llvm.fptoui.sat.i50.f64(double %f)
@@ -1460,7 +1460,7 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $20, %esp
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx
@@ -1502,7 +1502,7 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB17_6:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1553,7 +1553,7 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB17_4:
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ecx
; X86-SSE-NEXT: cmoval %ecx, %edx
; X86-SSE-NEXT: cmoval %ecx, %eax
@@ -1575,7 +1575,7 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; X64-NEXT: xorpd %xmm1, %xmm1
; X64-NEXT: ucomisd %xmm1, %xmm0
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movq $-1, %rax
; X64-NEXT: cmovbeq %rcx, %rax
; X64-NEXT: retq
@@ -1624,7 +1624,7 @@ define i100 @test_unsigned_i100_f64(double %f) nounwind {
; X86-X87-NEXT: .LBB18_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1685,7 +1685,7 @@ define i100 @test_unsigned_i100_f64(double %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB18_2:
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $15, %ebx
; X86-SSE-NEXT: cmovbel %edi, %ebx
; X86-SSE-NEXT: movl $-1, %edi
@@ -1716,7 +1716,7 @@ define i100 @test_unsigned_i100_f64(double %f) nounwind {
; X64-NEXT: ucomisd %xmm0, %xmm1
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm1
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: cmovaq %rcx, %rax
; X64-NEXT: movabsq $68719476735, %rcx # imm = 0xFFFFFFFFF
@@ -1769,7 +1769,7 @@ define i128 @test_unsigned_i128_f64(double %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB19_6:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -1826,7 +1826,7 @@ define i128 @test_unsigned_i128_f64(double %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB19_2:
-; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx
@@ -1855,7 +1855,7 @@ define i128 @test_unsigned_i128_f64(double %f) nounwind {
; X64-NEXT: ucomisd %xmm0, %xmm1
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: ucomisd {{.*}}(%rip), %xmm1
+; X64-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: cmovaq %rcx, %rax
; X64-NEXT: cmovaq %rcx, %rdx
@@ -1983,7 +1983,7 @@ define i8 @test_unsigned_i8_f16(half %f) nounwind {
; X86-X87-NEXT: .LBB21_1:
; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB21_3:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2056,7 +2056,7 @@ define i13 @test_unsigned_i13_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB22_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2130,7 +2130,7 @@ define i16 @test_unsigned_i16_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB23_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2205,7 +2205,7 @@ define i19 @test_unsigned_i19_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB24_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2229,7 +2229,7 @@ define i19 @test_unsigned_i19_f16(half %f) nounwind {
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: maxss %xmm1, %xmm0
-; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %eax
; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: retl
@@ -2241,7 +2241,7 @@ define i19 @test_unsigned_i19_f16(half %f) nounwind {
; X64-NEXT: callq __gnu_h2f_ieee at PLT
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: maxss %xmm1, %xmm0
-; X64-NEXT: minss {{.*}}(%rip), %xmm0
+; X64-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: cvttss2si %xmm0, %eax
; X64-NEXT: popq %rcx
; X64-NEXT: retq
@@ -2276,7 +2276,7 @@ define i32 @test_unsigned_i32_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB25_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2310,7 +2310,7 @@ define i32 @test_unsigned_i32_f16(half %f) nounwind {
; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: ucomiss %xmm1, %xmm0
; X86-SSE-NEXT: cmovael %ecx, %edx
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %edx, %eax
; X86-SSE-NEXT: addl $12, %esp
@@ -2326,7 +2326,7 @@ define i32 @test_unsigned_i32_f16(half %f) nounwind {
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: ucomiss %xmm1, %xmm0
; X64-NEXT: cmovael %eax, %ecx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movl $-1, %eax
; X64-NEXT: cmovbel %ecx, %eax
; X64-NEXT: popq %rcx
@@ -2343,7 +2343,7 @@ define i50 @test_unsigned_i50_f16(half %f) nounwind {
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: calll __gnu_h2f_ieee
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
@@ -2385,7 +2385,7 @@ define i50 @test_unsigned_i50_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB26_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2443,7 +2443,7 @@ define i50 @test_unsigned_i50_f16(half %f) nounwind {
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: .LBB26_4:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax
@@ -2462,7 +2462,7 @@ define i50 @test_unsigned_i50_f16(half %f) nounwind {
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: ucomiss %xmm1, %xmm0
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movabsq $1125899906842623, %rax # imm = 0x3FFFFFFFFFFFF
; X64-NEXT: cmovbeq %rcx, %rax
; X64-NEXT: popq %rcx
@@ -2480,7 +2480,7 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: calll __gnu_h2f_ieee
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
@@ -2522,7 +2522,7 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB27_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2577,7 +2577,7 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB27_4:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ecx
; X86-SSE-NEXT: cmoval %ecx, %edx
; X86-SSE-NEXT: cmoval %ecx, %eax
@@ -2602,7 +2602,7 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: ucomiss %xmm1, %xmm0
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: movq $-1, %rax
; X64-NEXT: cmovbeq %rcx, %rax
; X64-NEXT: popq %rcx
@@ -2654,7 +2654,7 @@ define i100 @test_unsigned_i100_f16(half %f) nounwind {
; X86-X87-NEXT: .LBB28_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2721,7 +2721,7 @@ define i100 @test_unsigned_i100_f16(half %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB28_2:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $15, %ebx
; X86-SSE-NEXT: cmovbel %edi, %ebx
; X86-SSE-NEXT: movl $-1, %edi
@@ -2754,7 +2754,7 @@ define i100 @test_unsigned_i100_f16(half %f) nounwind {
; X64-NEXT: ucomiss %xmm0, %xmm1
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm1
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: cmovaq %rcx, %rax
; X64-NEXT: movabsq $68719476735, %rcx # imm = 0xFFFFFFFFF
@@ -2809,7 +2809,7 @@ define i128 @test_unsigned_i128_f16(half %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB29_6:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -2872,7 +2872,7 @@ define i128 @test_unsigned_i128_f16(half %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB29_2:
-; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx
@@ -2903,7 +2903,7 @@ define i128 @test_unsigned_i128_f16(half %f) nounwind {
; X64-NEXT: ucomiss %xmm0, %xmm1
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: ucomiss {{.*}}(%rip), %xmm1
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: cmovaq %rcx, %rax
; X64-NEXT: cmovaq %rcx, %rdx
@@ -3051,7 +3051,7 @@ define i8 @test_unsigned_i8_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: .LBB31_1:
; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB31_3:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3083,7 +3083,7 @@ define i8 @test_unsigned_i8_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: cmovael %eax, %ecx
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3110,7 +3110,7 @@ define i8 @test_unsigned_i8_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
; X64-NEXT: cmovael %eax, %ecx
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -3146,7 +3146,7 @@ define i13 @test_unsigned_i13_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB32_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3181,7 +3181,7 @@ define i13 @test_unsigned_i13_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB32_2:
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3210,7 +3210,7 @@ define i13 @test_unsigned_i13_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
; X64-NEXT: .LBB32_2:
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -3246,7 +3246,7 @@ define i16 @test_unsigned_i16_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB33_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3281,7 +3281,7 @@ define i16 @test_unsigned_i16_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB33_2:
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3310,7 +3310,7 @@ define i16 @test_unsigned_i16_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
; X64-NEXT: .LBB33_2:
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -3347,7 +3347,7 @@ define i19 @test_unsigned_i19_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB34_2:
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3382,7 +3382,7 @@ define i19 @test_unsigned_i19_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB34_2:
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3411,7 +3411,7 @@ define i19 @test_unsigned_i19_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
; X64-NEXT: .LBB34_2:
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -3447,7 +3447,7 @@ define i32 @test_unsigned_i32_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB35_2:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3482,7 +3482,7 @@ define i32 @test_unsigned_i32_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB35_2:
-; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3511,7 +3511,7 @@ define i32 @test_unsigned_i32_f80(x86_fp80 %f) nounwind {
; X64-NEXT: # %bb.1:
; X64-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
; X64-NEXT: .LBB35_2:
-; X64-NEXT: fldl {{.*}}(%rip)
+; X64-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -3528,7 +3528,7 @@ define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $16, %esp
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx
@@ -3570,7 +3570,7 @@ define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB36_6:
-; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3595,7 +3595,7 @@ define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: pushl %esi
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: setbe %cl
@@ -3625,7 +3625,7 @@ define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl %eax, %esi
; X86-SSE-NEXT: .LBB36_2:
-; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3640,7 +3640,7 @@ define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind {
; X64-LABEL: test_unsigned_i50_f80:
; X64: # %bb.0:
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: setbe %al
@@ -3664,7 +3664,7 @@ define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: fldl {{.*}}(%rip)
+; X64-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -3682,7 +3682,7 @@ define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $20, %esp
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
-; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx
@@ -3724,7 +3724,7 @@ define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB37_6:
-; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3747,7 +3747,7 @@ define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: setbe %bl
@@ -3777,7 +3777,7 @@ define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %ecx, %edx
; X86-SSE-NEXT: .LBB37_2:
-; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3791,7 +3791,7 @@ define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind {
; X64-LABEL: test_unsigned_i64_f80:
; X64: # %bb.0:
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-NEXT: flds {{.*}}(%rip)
+; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: setbe %al
@@ -3815,7 +3815,7 @@ define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1)
; X64-NEXT: cmovaeq %rax, %rcx
-; X64-NEXT: fldt {{.*}}(%rip)
+; X64-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -3869,7 +3869,7 @@ define i100 @test_unsigned_i100_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: .LBB38_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -3933,7 +3933,7 @@ define i100 @test_unsigned_i100_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB38_2:
-; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -3970,7 +3970,7 @@ define i100 @test_unsigned_i100_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fstp %st(1)
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: fldt {{.*}}(%rip)
+; X64-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
@@ -4028,7 +4028,7 @@ define i128 @test_unsigned_i128_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB39_6:
-; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-X87-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax
@@ -4088,7 +4088,7 @@ define i128 @test_unsigned_i128_f80(x86_fp80 %f) nounwind {
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB39_2:
-; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0)
@@ -4123,7 +4123,7 @@ define i128 @test_unsigned_i128_f80(x86_fp80 %f) nounwind {
; X64-NEXT: fstp %st(1)
; X64-NEXT: cmovbq %rcx, %rdx
; X64-NEXT: cmovbq %rcx, %rax
-; X64-NEXT: fldt {{.*}}(%rip)
+; X64-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1)
; X64-NEXT: fucompi %st(1), %st
; X64-NEXT: fstp %st(0)
diff --git a/llvm/test/CodeGen/X86/freeze.ll b/llvm/test/CodeGen/X86/freeze.ll
index cf015d3c892cf..91a62eda1132f 100644
--- a/llvm/test/CodeGen/X86/freeze.ll
+++ b/llvm/test/CodeGen/X86/freeze.ll
@@ -39,12 +39,12 @@ define half @freeze_half() {
; X86ASM-NEXT: pushq %rax
; X86ASM-NEXT: .cfi_def_cfa_offset 16
; X86ASM-NEXT: xorl %edi, %edi
-; X86ASM-NEXT: callq __gnu_h2f_ieee
-; X86ASM-NEXT: callq __gnu_f2h_ieee
+; X86ASM-NEXT: callq __gnu_h2f_ieee at PLT
+; X86ASM-NEXT: callq __gnu_f2h_ieee at PLT
; X86ASM-NEXT: movzwl %ax, %edi
-; X86ASM-NEXT: callq __gnu_h2f_ieee
+; X86ASM-NEXT: callq __gnu_h2f_ieee at PLT
; X86ASM-NEXT: addss %xmm0, %xmm0
-; X86ASM-NEXT: callq __gnu_f2h_ieee
+; X86ASM-NEXT: callq __gnu_f2h_ieee at PLT
; X86ASM-NEXT: popq %rcx
; X86ASM-NEXT: .cfi_def_cfa_offset 8
; X86ASM-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll
index fa7fd2b22acbd..af3dab5a2dea2 100644
--- a/llvm/test/CodeGen/X86/ftrunc.ll
+++ b/llvm/test/CodeGen/X86/ftrunc.ll
@@ -40,7 +40,7 @@ define double @trunc_unsigned_f64(double %x) #0 {
; SSE2-NEXT: cmovaeq %rcx, %rax
; SSE2-NEXT: movq %rax, %xmm1
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
-; SSE2-NEXT: subpd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movapd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2-NEXT: addsd %xmm1, %xmm0
@@ -69,16 +69,16 @@ define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 {
; SSE2-NEXT: cvttps2dq %xmm0, %xmm3
; SSE2-NEXT: subps %xmm2, %xmm0
; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE2-NEXT: xorps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: andps %xmm1, %xmm3
; SSE2-NEXT: andnps %xmm0, %xmm1
; SSE2-NEXT: orps %xmm3, %xmm1
; SSE2-NEXT: movaps {{.*#+}} xmm0 = [65535,65535,65535,65535]
; SSE2-NEXT: andps %xmm1, %xmm0
-; SSE2-NEXT: orps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrld $16, %xmm1
-; SSE2-NEXT: por {{.*}}(%rip), %xmm1
-; SSE2-NEXT: subps {{.*}}(%rip), %xmm1
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: addps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -122,10 +122,10 @@ define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [4294967295,4294967295]
; SSE2-NEXT: pand %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlq $32, %xmm1
-; SSE2-NEXT: por {{.*}}(%rip), %xmm1
-; SSE2-NEXT: subpd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: addpd %xmm0, %xmm1
; SSE2-NEXT: movapd %xmm1, %xmm0
; SSE2-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/funnel-shift-rot.ll b/llvm/test/CodeGen/X86/funnel-shift-rot.ll
index a777a0d0adc9b..a06037fc927b3 100644
--- a/llvm/test/CodeGen/X86/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/X86/funnel-shift-rot.ll
@@ -130,9 +130,9 @@ define i32 @rotl_i32(i32 %x, i32 %z) nounwind {
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X32-SSE2-LABEL: rotl_v4i32:
; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE2-NEXT: pslld $23, %xmm1
-; X32-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -324,9 +324,9 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: pxor %xmm2, %xmm2
; X32-SSE2-NEXT: psubd %xmm1, %xmm2
-; X32-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X32-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X32-SSE2-NEXT: pslld $23, %xmm2
-; X32-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X32-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X32-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/h-registers-3.ll b/llvm/test/CodeGen/X86/h-registers-3.ll
index 564b1e8e15b23..8e14bf3a6ee18 100644
--- a/llvm/test/CodeGen/X86/h-registers-3.ll
+++ b/llvm/test/CodeGen/X86/h-registers-3.ll
@@ -7,7 +7,7 @@ define zeroext i8 @foo() nounwind ssp {
; X86-LABEL: foo:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
-; X86-NEXT: calll bar
+; X86-NEXT: calll bar at PLT
; X86-NEXT: movb %ah, %al
; X86-NEXT: addl $12, %esp
; X86-NEXT: retl
@@ -16,7 +16,7 @@ define zeroext i8 @foo() nounwind ssp {
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: shrl $8, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
@@ -27,7 +27,7 @@ define zeroext i8 @foo() nounwind ssp {
; X32: # %bb.0: # %entry
; X32-NEXT: pushq %rax
; X32-NEXT: xorl %eax, %eax
-; X32-NEXT: callq bar
+; X32-NEXT: callq bar at PLT
; X32-NEXT: # kill: def $ax killed $ax def $eax
; X32-NEXT: shrl $8, %eax
; X32-NEXT: # kill: def $al killed $al killed $eax
diff --git a/llvm/test/CodeGen/X86/haddsub-3.ll b/llvm/test/CodeGen/X86/haddsub-3.ll
index 7f791fc76ac5f..baf7be7afccb1 100644
--- a/llvm/test/CodeGen/X86/haddsub-3.ll
+++ b/llvm/test/CodeGen/X86/haddsub-3.ll
@@ -70,7 +70,7 @@ define <4 x double> @PR41414(i64 %x, <4 x double> %y) {
; SSE2: # %bb.0:
; SSE2-NEXT: movq %rdi, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
-; SSE2-NEXT: subpd {{.*}}(%rip), %xmm2
+; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm3
; SSE2-NEXT: unpcklpd {{.*#+}} xmm3 = xmm3[0],xmm2[0]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
@@ -86,7 +86,7 @@ define <4 x double> @PR41414(i64 %x, <4 x double> %y) {
; SSSE3: # %bb.0:
; SSSE3-NEXT: movq %rdi, %xmm2
; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
-; SSSE3-NEXT: subpd {{.*}}(%rip), %xmm2
+; SSSE3-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSSE3-NEXT: haddpd %xmm2, %xmm2
; SSSE3-NEXT: divpd %xmm2, %xmm1
; SSSE3-NEXT: divpd %xmm2, %xmm0
@@ -99,7 +99,7 @@ define <4 x double> @PR41414(i64 %x, <4 x double> %y) {
; AVX1: # %bb.0:
; AVX1-NEXT: vmovq %rdi, %xmm1
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
-; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vhaddpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: vdivpd %ymm1, %ymm0, %ymm0
@@ -111,7 +111,7 @@ define <4 x double> @PR41414(i64 %x, <4 x double> %y) {
; AVX2: # %bb.0:
; AVX2-NEXT: vmovq %rdi, %xmm1
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
-; AVX2-NEXT: vsubpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
; AVX2-NEXT: vaddsd %xmm1, %xmm2, %xmm1
; AVX2-NEXT: vbroadcastsd %xmm1, %ymm1
diff --git a/llvm/test/CodeGen/X86/haddsub-broadcast.ll b/llvm/test/CodeGen/X86/haddsub-broadcast.ll
index 8290d63cdccf7..bf0ac0abb04d1 100644
--- a/llvm/test/CodeGen/X86/haddsub-broadcast.ll
+++ b/llvm/test/CodeGen/X86/haddsub-broadcast.ll
@@ -8,7 +8,7 @@ define <4 x double> @PR43402(i64 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
-; CHECK-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; CHECK-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; CHECK-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; CHECK-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/half-constrained.ll b/llvm/test/CodeGen/X86/half-constrained.ll
index 2082e1df67bf7..82638cdeb5732 100644
--- a/llvm/test/CodeGen/X86/half-constrained.ll
+++ b/llvm/test/CodeGen/X86/half-constrained.ll
@@ -33,14 +33,14 @@ define float @half_to_float() strictfp {
; X64-NOF16C: ## %bb.0:
; X64-NOF16C-NEXT: pushq %rax
; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16
-; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi
+; X64-NOF16C-NEXT: movzwl _a(%rip), %edi
; X64-NOF16C-NEXT: callq ___extendhfsf2
; X64-NOF16C-NEXT: popq %rax
; X64-NOF16C-NEXT: retq
;
; X64-F16C-LABEL: half_to_float:
; X64-F16C: ## %bb.0:
-; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax
+; X64-F16C-NEXT: movzwl _a(%rip), %eax
; X64-F16C-NEXT: vmovd %eax, %xmm0
; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0
; X64-F16C-NEXT: retq
@@ -74,7 +74,7 @@ define double @half_to_double() strictfp {
; X64-NOF16C: ## %bb.0:
; X64-NOF16C-NEXT: pushq %rax
; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16
-; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi
+; X64-NOF16C-NEXT: movzwl _a(%rip), %edi
; X64-NOF16C-NEXT: callq ___extendhfsf2
; X64-NOF16C-NEXT: cvtss2sd %xmm0, %xmm0
; X64-NOF16C-NEXT: popq %rax
@@ -82,7 +82,7 @@ define double @half_to_double() strictfp {
;
; X64-F16C-LABEL: half_to_double:
; X64-F16C: ## %bb.0:
-; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax
+; X64-F16C-NEXT: movzwl _a(%rip), %eax
; X64-F16C-NEXT: vmovd %eax, %xmm0
; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0
; X64-F16C-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0
@@ -117,7 +117,7 @@ define x86_fp80 @half_to_fp80() strictfp {
; X64-NOF16C: ## %bb.0:
; X64-NOF16C-NEXT: pushq %rax
; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16
-; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi
+; X64-NOF16C-NEXT: movzwl _a(%rip), %edi
; X64-NOF16C-NEXT: callq ___extendhfsf2
; X64-NOF16C-NEXT: movss %xmm0, {{[0-9]+}}(%rsp)
; X64-NOF16C-NEXT: flds {{[0-9]+}}(%rsp)
@@ -127,7 +127,7 @@ define x86_fp80 @half_to_fp80() strictfp {
;
; X64-F16C-LABEL: half_to_fp80:
; X64-F16C: ## %bb.0:
-; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax
+; X64-F16C-NEXT: movzwl _a(%rip), %eax
; X64-F16C-NEXT: vmovd %eax, %xmm0
; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0
; X64-F16C-NEXT: vmovss %xmm0, -{{[0-9]+}}(%rsp)
@@ -169,7 +169,7 @@ define void @float_to_half(float %0) strictfp {
; X64-NOF16C-NEXT: pushq %rax
; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16
; X64-NOF16C-NEXT: callq ___truncsfhf2
-; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip)
+; X64-NOF16C-NEXT: movw %ax, _a(%rip)
; X64-NOF16C-NEXT: popq %rax
; X64-NOF16C-NEXT: retq
;
@@ -178,7 +178,7 @@ define void @float_to_half(float %0) strictfp {
; X64-F16C-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-F16C-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X64-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; X64-F16C-NEXT: vpextrw $0, %xmm0, {{.*}}(%rip)
+; X64-F16C-NEXT: vpextrw $0, %xmm0, _a(%rip)
; X64-F16C-NEXT: retq
%2 = tail call half @llvm.experimental.constrained.fptrunc.f16.f32(float %0, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
store half %2, half* @a, align 2
@@ -215,7 +215,7 @@ define void @double_to_half(double %0) strictfp {
; X64-NOF16C-NEXT: pushq %rax
; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16
; X64-NOF16C-NEXT: callq ___truncdfhf2
-; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip)
+; X64-NOF16C-NEXT: movw %ax, _a(%rip)
; X64-NOF16C-NEXT: popq %rax
; X64-NOF16C-NEXT: retq
;
@@ -224,7 +224,7 @@ define void @double_to_half(double %0) strictfp {
; X64-F16C-NEXT: pushq %rax
; X64-F16C-NEXT: .cfi_def_cfa_offset 16
; X64-F16C-NEXT: callq ___truncdfhf2
-; X64-F16C-NEXT: movw %ax, {{.*}}(%rip)
+; X64-F16C-NEXT: movw %ax, _a(%rip)
; X64-F16C-NEXT: popq %rax
; X64-F16C-NEXT: retq
%2 = tail call half @llvm.experimental.constrained.fptrunc.f16.f64(double %0, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
@@ -265,7 +265,7 @@ define void @fp80_to_half(x86_fp80 %0) strictfp {
; X64-NOF16C-NEXT: fstpt (%rsp)
; X64-NOF16C-NEXT: wait
; X64-NOF16C-NEXT: callq ___truncxfhf2
-; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip)
+; X64-NOF16C-NEXT: movw %ax, _a(%rip)
; X64-NOF16C-NEXT: addq $24, %rsp
; X64-NOF16C-NEXT: retq
;
@@ -277,7 +277,7 @@ define void @fp80_to_half(x86_fp80 %0) strictfp {
; X64-F16C-NEXT: fstpt (%rsp)
; X64-F16C-NEXT: wait
; X64-F16C-NEXT: callq ___truncxfhf2
-; X64-F16C-NEXT: movw %ax, {{.*}}(%rip)
+; X64-F16C-NEXT: movw %ax, _a(%rip)
; X64-F16C-NEXT: addq $24, %rsp
; X64-F16C-NEXT: retq
%2 = tail call half @llvm.experimental.constrained.fptrunc.f16.f80(x86_fp80 %0, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
@@ -332,30 +332,30 @@ define void @add() strictfp {
; X64-NOF16C: ## %bb.0:
; X64-NOF16C-NEXT: pushq %rax
; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16
-; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi
+; X64-NOF16C-NEXT: movzwl _a(%rip), %edi
; X64-NOF16C-NEXT: callq ___extendhfsf2
; X64-NOF16C-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
-; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi
+; X64-NOF16C-NEXT: movzwl _b(%rip), %edi
; X64-NOF16C-NEXT: callq ___extendhfsf2
; X64-NOF16C-NEXT: addss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 4-byte Folded Reload
; X64-NOF16C-NEXT: callq ___truncsfhf2
-; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip)
+; X64-NOF16C-NEXT: movw %ax, _c(%rip)
; X64-NOF16C-NEXT: popq %rax
; X64-NOF16C-NEXT: retq
;
; X64-F16C-LABEL: add:
; X64-F16C: ## %bb.0:
-; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax
+; X64-F16C-NEXT: movzwl _a(%rip), %eax
; X64-F16C-NEXT: vmovd %eax, %xmm0
; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0
-; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax
+; X64-F16C-NEXT: movzwl _b(%rip), %eax
; X64-F16C-NEXT: vmovd %eax, %xmm1
; X64-F16C-NEXT: vcvtph2ps %xmm1, %xmm1
; X64-F16C-NEXT: vaddss %xmm1, %xmm0, %xmm0
; X64-F16C-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-F16C-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X64-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; X64-F16C-NEXT: vpextrw $0, %xmm0, {{.*}}(%rip)
+; X64-F16C-NEXT: vpextrw $0, %xmm0, _c(%rip)
; X64-F16C-NEXT: retq
%1 = load half, half* @a, align 2
%2 = tail call float @llvm.experimental.constrained.fpext.f32.f16(half %1, metadata !"fpexcept.strict") #0
diff --git a/llvm/test/CodeGen/X86/hidden-vis-2.ll b/llvm/test/CodeGen/X86/hidden-vis-2.ll
index a29445f416b2f..4e20e5eade0e0 100644
--- a/llvm/test/CodeGen/X86/hidden-vis-2.ll
+++ b/llvm/test/CodeGen/X86/hidden-vis-2.ll
@@ -12,7 +12,7 @@ define i32 @t() nounwind readonly {
;
; x86_64-darwin9-LABEL: t:
; x86_64-darwin9: ## %bb.0: ## %entry
-; x86_64-darwin9-NEXT: movl {{.*}}(%rip), %eax
+; x86_64-darwin9-NEXT: movl _x(%rip), %eax
; x86_64-darwin9-NEXT: retq
entry:
%0 = load i32, i32* @x, align 4 ; <i32> [#uses=1]
diff --git a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index fc4a17d4cfabf..a8f41c2680f2f 100644
--- a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -499,7 +499,7 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1
-; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -508,7 +508,7 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; X86-SSE2-NEXT: retl
;
@@ -525,7 +525,7 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pxor %xmm2, %xmm2
; X64-SSE2-NEXT: pslld $23, %xmm1
-; X64-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; X64-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -534,7 +534,7 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-SSE2-NEXT: pmuludq %xmm3, %xmm1
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X64-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; X64-SSE2-NEXT: retq
%t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
@@ -586,7 +586,7 @@ define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1
-; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -595,7 +595,7 @@ define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; X86-SSE2-NEXT: retl
;
@@ -612,7 +612,7 @@ define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pxor %xmm2, %xmm2
; X64-SSE2-NEXT: pslld $23, %xmm1
-; X64-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; X64-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -621,7 +621,7 @@ define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X64-SSE2-NEXT: pmuludq %xmm3, %xmm1
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X64-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; X64-SSE2-NEXT: retq
%t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
diff --git a/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index 29667b4f728c7..8b00fa8c2b64f 100644
--- a/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -461,7 +461,7 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_splat_eq:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pslld $23, %xmm1
-; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
@@ -487,7 +487,7 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-SSE2-LABEL: vec_4xi32_splat_eq:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pslld $23, %xmm1
-; X64-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
@@ -510,7 +510,7 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_nonsplat_eq:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pslld $23, %xmm1
-; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,16776960,2147483648]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
@@ -537,7 +537,7 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-SSE2-LABEL: vec_4xi32_nonsplat_eq:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pslld $23, %xmm1
-; X64-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,16776960,2147483648]
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
@@ -563,12 +563,12 @@ define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X86-SSE2-NEXT: movl $1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1
-; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X86-SSE2-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X86-SSE2-NEXT: pand %xmm2, %xmm0
@@ -590,12 +590,12 @@ define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X64-SSE2-NEXT: movl $1, %eax
; X64-SSE2-NEXT: movd %eax, %xmm2
; X64-SSE2-NEXT: pslld $23, %xmm1
-; X64-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X64-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X64-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X64-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X64-SSE2-NEXT: pand %xmm2, %xmm0
@@ -611,7 +611,7 @@ define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef1_eq:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pslld $23, %xmm1
-; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
@@ -637,7 +637,7 @@ define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X64-SSE2-LABEL: vec_4xi32_nonsplat_undef1_eq:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pslld $23, %xmm1
-; X64-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
@@ -661,12 +661,12 @@ define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X86-SSE2-NEXT: movl $1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1
-; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X86-SSE2-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X86-SSE2-NEXT: pand %xmm2, %xmm0
@@ -688,12 +688,12 @@ define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; X64-SSE2-NEXT: movl $1, %eax
; X64-SSE2-NEXT: movd %eax, %xmm2
; X64-SSE2-NEXT: pslld $23, %xmm1
-; X64-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X64-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X64-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X64-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X64-SSE2-NEXT: pand %xmm2, %xmm0
diff --git a/llvm/test/CodeGen/X86/hoist-invariant-load.ll b/llvm/test/CodeGen/X86/hoist-invariant-load.ll
index 73cf898223bc6..63ccbb818bfdd 100644
--- a/llvm/test/CodeGen/X86/hoist-invariant-load.ll
+++ b/llvm/test/CodeGen/X86/hoist-invariant-load.ll
@@ -41,8 +41,8 @@ define void @test(i8* %x) uwtable ssp {
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $10000, %ebp ## imm = 0x2710
-; CHECK-NEXT: movq {{.*}}(%rip), %r14
-; CHECK-NEXT: movq _objc_msgSend@{{.*}}(%rip), %r15
+; CHECK-NEXT: movq L_OBJC_SELECTOR_REFERENCES_(%rip), %r14
+; CHECK-NEXT: movq _objc_msgSend at GOTPCREL(%rip), %r15
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_1: ## %for.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
@@ -92,8 +92,8 @@ define void @test_unordered(i8* %x) uwtable ssp {
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $10000, %ebp ## imm = 0x2710
-; CHECK-NEXT: movq {{.*}}(%rip), %r14
-; CHECK-NEXT: movq _objc_msgSend@{{.*}}(%rip), %r15
+; CHECK-NEXT: movq L_OBJC_SELECTOR_REFERENCES_(%rip), %r14
+; CHECK-NEXT: movq _objc_msgSend at GOTPCREL(%rip), %r15
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_1: ## %for.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
@@ -138,11 +138,11 @@ define void @test_volatile(i8* %x) uwtable ssp {
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $10000, %ebp ## imm = 0x2710
-; CHECK-NEXT: movq _objc_msgSend@{{.*}}(%rip), %r14
+; CHECK-NEXT: movq _objc_msgSend at GOTPCREL(%rip), %r14
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB2_1: ## %for.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movq {{.*}}(%rip), %rsi
+; CHECK-NEXT: movq L_OBJC_SELECTOR_REFERENCES_(%rip), %rsi
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: callq *%r14
; CHECK-NEXT: decl %ebp
@@ -181,11 +181,11 @@ define void @test_seq_cst(i8* %x) uwtable ssp {
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $10000, %ebp ## imm = 0x2710
-; CHECK-NEXT: movq _objc_msgSend@{{.*}}(%rip), %r14
+; CHECK-NEXT: movq _objc_msgSend at GOTPCREL(%rip), %r14
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB3_1: ## %for.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movq {{.*}}(%rip), %rsi
+; CHECK-NEXT: movq L_OBJC_SELECTOR_REFERENCES_(%rip), %rsi
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: callq *%r14
; CHECK-NEXT: decl %ebp
diff --git a/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll b/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
index 843be403a63d1..987de633c72f2 100644
--- a/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
+++ b/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
@@ -211,7 +211,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v8i16:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI2_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -220,7 +220,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X86-AVX-LABEL: test_reduce_v8i16:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI2_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
; X86-AVX-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -242,7 +242,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v8i16:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -251,7 +251,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X64-AVX-LABEL: test_reduce_v8i16:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
; X64-AVX-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -305,7 +305,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v16i8:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI3_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -317,7 +317,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X86-AVX-LABEL: test_reduce_v16i8:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI3_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -360,7 +360,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v16i8:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -372,7 +372,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X64-AVX-LABEL: test_reduce_v16i8:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -724,7 +724,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X86-SSE42-LABEL: test_reduce_v16i16:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: pmaxsw %xmm1, %xmm0
-; X86-SSE42-NEXT: pxor LCPI6_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -735,7 +735,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI6_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
; X86-AVX1-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -747,7 +747,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X86-AVX2: ## %bb.0:
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI6_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
; X86-AVX2-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -772,7 +772,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-SSE42-LABEL: test_reduce_v16i16:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: pmaxsw %xmm1, %xmm0
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -783,7 +783,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -795,7 +795,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-AVX2: ## %bb.0:
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -807,7 +807,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
; X64-AVX512-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -871,7 +871,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X86-SSE42-LABEL: test_reduce_v32i8:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: pmaxsb %xmm1, %xmm0
-; X86-SSE42-NEXT: pxor LCPI7_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -885,7 +885,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI7_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -899,7 +899,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X86-AVX2: ## %bb.0:
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI7_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -949,7 +949,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-SSE42-LABEL: test_reduce_v32i8:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: pmaxsb %xmm1, %xmm0
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -963,7 +963,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -977,7 +977,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-AVX2: ## %bb.0:
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -991,7 +991,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1481,7 +1481,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-SSE42-NEXT: pmaxsw %xmm3, %xmm1
; X86-SSE42-NEXT: pmaxsw %xmm2, %xmm1
; X86-SSE42-NEXT: pmaxsw %xmm0, %xmm1
-; X86-SSE42-NEXT: pxor LCPI10_0, %xmm1
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE42-NEXT: phminposuw %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1495,7 +1495,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2
; X86-AVX1-NEXT: vpmaxsw %xmm2, %xmm1, %xmm1
; X86-AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI10_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
; X86-AVX1-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1508,7 +1508,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI10_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
; X86-AVX2-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1537,7 +1537,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-SSE42-NEXT: pmaxsw %xmm3, %xmm1
; X64-SSE42-NEXT: pmaxsw %xmm2, %xmm1
; X64-SSE42-NEXT: pmaxsw %xmm0, %xmm1
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm1
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE42-NEXT: phminposuw %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1551,7 +1551,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2
; X64-AVX1-NEXT: vpmaxsw %xmm2, %xmm1, %xmm1
; X64-AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1564,7 +1564,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1578,7 +1578,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
; X64-AVX512-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1657,7 +1657,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X86-SSE42-NEXT: pmaxsb %xmm3, %xmm1
; X86-SSE42-NEXT: pmaxsb %xmm2, %xmm1
; X86-SSE42-NEXT: pmaxsb %xmm0, %xmm1
-; X86-SSE42-NEXT: pxor LCPI11_0, %xmm1
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE42-NEXT: movdqa %xmm1, %xmm0
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminub %xmm1, %xmm0
@@ -1674,7 +1674,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X86-AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm2
; X86-AVX1-NEXT: vpmaxsb %xmm2, %xmm1, %xmm1
; X86-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI11_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1689,7 +1689,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X86-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI11_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1751,7 +1751,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-SSE42-NEXT: pmaxsb %xmm3, %xmm1
; X64-SSE42-NEXT: pmaxsb %xmm2, %xmm1
; X64-SSE42-NEXT: pmaxsb %xmm0, %xmm1
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm1
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE42-NEXT: movdqa %xmm1, %xmm0
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminub %xmm1, %xmm0
@@ -1768,7 +1768,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm2
; X64-AVX1-NEXT: vpmaxsb %xmm2, %xmm1, %xmm1
; X64-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1783,7 +1783,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1799,7 +1799,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1850,7 +1850,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v16i16_v8i16:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI12_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1859,7 +1859,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X86-AVX-LABEL: test_reduce_v16i16_v8i16:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI12_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
; X86-AVX-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1882,7 +1882,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v16i16_v8i16:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1891,7 +1891,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X64-AVX-LABEL: test_reduce_v16i16_v8i16:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
; X64-AVX-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1927,7 +1927,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v32i16_v8i16:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI13_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1936,7 +1936,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X86-AVX-LABEL: test_reduce_v32i16_v8i16:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI13_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
; X86-AVX-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1959,7 +1959,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v32i16_v8i16:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -1968,7 +1968,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X64-AVX-LABEL: test_reduce_v32i16_v8i16:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
; X64-AVX-NEXT: xorl $32767, %eax ## imm = 0x7FFF
@@ -2023,7 +2023,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v32i8_v16i8:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI14_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2035,7 +2035,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X86-AVX-LABEL: test_reduce_v32i8_v16i8:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI14_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -2079,7 +2079,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v32i8_v16i8:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2091,7 +2091,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X64-AVX-LABEL: test_reduce_v32i8_v16i8:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -2151,7 +2151,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v64i8_v16i8:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI15_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2163,7 +2163,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X86-AVX-LABEL: test_reduce_v64i8_v16i8:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI15_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -2207,7 +2207,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v64i8_v16i8:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2219,7 +2219,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X64-AVX-LABEL: test_reduce_v64i8_v16i8:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll b/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
index 8bc6dd0d1532e..622c6fab8b107 100644
--- a/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
+++ b/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
@@ -213,7 +213,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v8i16:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI2_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -222,7 +222,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X86-AVX-LABEL: test_reduce_v8i16:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI2_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
; X86-AVX-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -244,7 +244,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v8i16:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -253,7 +253,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) {
;
; X64-AVX-LABEL: test_reduce_v8i16:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
; X64-AVX-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -307,7 +307,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v16i8:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI3_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -319,7 +319,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X86-AVX-LABEL: test_reduce_v16i8:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI3_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -362,7 +362,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v16i8:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -374,7 +374,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
; X64-AVX-LABEL: test_reduce_v16i8:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -728,7 +728,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X86-SSE42-LABEL: test_reduce_v16i16:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: pminsw %xmm1, %xmm0
-; X86-SSE42-NEXT: pxor LCPI6_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -739,7 +739,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI6_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
; X86-AVX1-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -751,7 +751,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X86-AVX2: ## %bb.0:
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI6_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
; X86-AVX2-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -776,7 +776,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-SSE42-LABEL: test_reduce_v16i16:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: pminsw %xmm1, %xmm0
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -787,7 +787,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -799,7 +799,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-AVX2: ## %bb.0:
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -811,7 +811,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) {
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
; X64-AVX512-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -875,7 +875,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X86-SSE42-LABEL: test_reduce_v32i8:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: pminsb %xmm1, %xmm0
-; X86-SSE42-NEXT: pxor LCPI7_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -889,7 +889,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI7_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -903,7 +903,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X86-AVX2: ## %bb.0:
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI7_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -953,7 +953,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-SSE42-LABEL: test_reduce_v32i8:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: pminsb %xmm1, %xmm0
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -967,7 +967,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -981,7 +981,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-AVX2: ## %bb.0:
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -995,7 +995,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1485,7 +1485,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-SSE42-NEXT: pminsw %xmm3, %xmm1
; X86-SSE42-NEXT: pminsw %xmm2, %xmm1
; X86-SSE42-NEXT: pminsw %xmm0, %xmm1
-; X86-SSE42-NEXT: pxor LCPI10_0, %xmm1
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE42-NEXT: phminposuw %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1499,7 +1499,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm2
; X86-AVX1-NEXT: vpminsw %xmm2, %xmm1, %xmm1
; X86-AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI10_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
; X86-AVX1-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1512,7 +1512,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI10_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
; X86-AVX2-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1541,7 +1541,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-SSE42-NEXT: pminsw %xmm3, %xmm1
; X64-SSE42-NEXT: pminsw %xmm2, %xmm1
; X64-SSE42-NEXT: pminsw %xmm0, %xmm1
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm1
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE42-NEXT: phminposuw %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1555,7 +1555,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm2
; X64-AVX1-NEXT: vpminsw %xmm2, %xmm1, %xmm1
; X64-AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1568,7 +1568,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1582,7 +1582,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
; X64-AVX512-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1661,7 +1661,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X86-SSE42-NEXT: pminsb %xmm3, %xmm1
; X86-SSE42-NEXT: pminsb %xmm2, %xmm1
; X86-SSE42-NEXT: pminsb %xmm0, %xmm1
-; X86-SSE42-NEXT: pxor LCPI11_0, %xmm1
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE42-NEXT: movdqa %xmm1, %xmm0
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminub %xmm1, %xmm0
@@ -1678,7 +1678,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X86-AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm2
; X86-AVX1-NEXT: vpminsb %xmm2, %xmm1, %xmm1
; X86-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpxor LCPI11_0, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1693,7 +1693,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X86-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpxor LCPI11_0, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1755,7 +1755,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-SSE42-NEXT: pminsb %xmm3, %xmm1
; X64-SSE42-NEXT: pminsb %xmm2, %xmm1
; X64-SSE42-NEXT: pminsb %xmm0, %xmm1
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm1
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE42-NEXT: movdqa %xmm1, %xmm0
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminub %xmm1, %xmm0
@@ -1772,7 +1772,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm2
; X64-AVX1-NEXT: vpminsb %xmm2, %xmm1, %xmm1
; X64-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1787,7 +1787,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1803,7 +1803,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) {
; X64-AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX512-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1854,7 +1854,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v16i16_v8i16:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI12_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1863,7 +1863,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X86-AVX-LABEL: test_reduce_v16i16_v8i16:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI12_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
; X86-AVX-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1886,7 +1886,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v16i16_v8i16:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1895,7 +1895,7 @@ define i16 @test_reduce_v16i16_v8i16(<16 x i16> %a0) {
;
; X64-AVX-LABEL: test_reduce_v16i16_v8i16:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
; X64-AVX-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1931,7 +1931,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v32i16_v8i16:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI13_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
; X86-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1940,7 +1940,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X86-AVX-LABEL: test_reduce_v32i16_v8i16:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI13_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
; X86-AVX-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1963,7 +1963,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v32i16_v8i16:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
; X64-SSE42-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -1972,7 +1972,7 @@ define i16 @test_reduce_v32i16_v8i16(<32 x i16> %a0) {
;
; X64-AVX-LABEL: test_reduce_v32i16_v8i16:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
; X64-AVX-NEXT: xorl $32768, %eax ## imm = 0x8000
@@ -2027,7 +2027,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v32i8_v16i8:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI14_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2039,7 +2039,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X86-AVX-LABEL: test_reduce_v32i8_v16i8:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI14_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -2083,7 +2083,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v32i8_v16i8:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2095,7 +2095,7 @@ define i8 @test_reduce_v32i8_v16i8(<32 x i8> %a0) {
;
; X64-AVX-LABEL: test_reduce_v32i8_v16i8:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -2155,7 +2155,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X86-SSE42-LABEL: test_reduce_v64i8_v16i8:
; X86-SSE42: ## %bb.0:
-; X86-SSE42-NEXT: pxor LCPI15_0, %xmm0
+; X86-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: psrlw $8, %xmm1
; X86-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2167,7 +2167,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X86-AVX-LABEL: test_reduce_v64i8_v16i8:
; X86-AVX: ## %bb.0:
-; X86-AVX-NEXT: vpxor LCPI15_0, %xmm0, %xmm0
+; X86-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -2211,7 +2211,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X64-SSE42-LABEL: test_reduce_v64i8_v16i8:
; X64-SSE42: ## %bb.0:
-; X64-SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: psrlw $8, %xmm1
; X64-SSE42-NEXT: pminub %xmm0, %xmm1
@@ -2223,7 +2223,7 @@ define i8 @test_reduce_v64i8_v16i8(<64 x i8> %a0) {
;
; X64-AVX-LABEL: test_reduce_v64i8_v16i8:
; X64-AVX: ## %bb.0:
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/i128-sdiv.ll b/llvm/test/CodeGen/X86/i128-sdiv.ll
index 4e9aaa276b3fb..f583af498ba65 100644
--- a/llvm/test/CodeGen/X86/i128-sdiv.ll
+++ b/llvm/test/CodeGen/X86/i128-sdiv.ll
@@ -147,7 +147,7 @@ define i128 @test3(i128 %x) nounwind {
; X64-NEXT: pushq %rax
; X64-NEXT: movq $-3, %rdx
; X64-NEXT: movq $-5, %rcx
-; X64-NEXT: callq __divti3
+; X64-NEXT: callq __divti3 at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
%tmp = sdiv i128 %x, -73786976294838206467
diff --git a/llvm/test/CodeGen/X86/i128-udiv.ll b/llvm/test/CodeGen/X86/i128-udiv.ll
index 71a4eb5bc77ec..05049dc6254a6 100644
--- a/llvm/test/CodeGen/X86/i128-udiv.ll
+++ b/llvm/test/CodeGen/X86/i128-udiv.ll
@@ -71,7 +71,7 @@ define i128 @test2(i128 %x) nounwind {
; X64-NEXT: pushq %rax
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movq $-4, %rcx
-; X64-NEXT: callq __udivti3
+; X64-NEXT: callq __udivti3 at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
%tmp = udiv i128 %x, -73786976294838206464
@@ -120,7 +120,7 @@ define i128 @test3(i128 %x) nounwind {
; X64-NEXT: pushq %rax
; X64-NEXT: movq $-3, %rdx
; X64-NEXT: movq $-5, %rcx
-; X64-NEXT: callq __udivti3
+; X64-NEXT: callq __udivti3 at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
%tmp = udiv i128 %x, -73786976294838206467
diff --git a/llvm/test/CodeGen/X86/i64-to-float.ll b/llvm/test/CodeGen/X86/i64-to-float.ll
index f7a2d330206e6..21d3e3a5589b8 100644
--- a/llvm/test/CodeGen/X86/i64-to-float.ll
+++ b/llvm/test/CodeGen/X86/i64-to-float.ll
@@ -14,7 +14,7 @@ define <2 x double> @mask_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_sitofp_2i64_2f64:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; X86-SSE-NEXT: retl
;
@@ -32,14 +32,14 @@ define <2 x double> @mask_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X86-AVX512DQ-LABEL: mask_sitofp_2i64_2f64:
; X86-AVX512DQ: # %bb.0:
-; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X86-AVX512DQ-NEXT: retl
;
; X64-SSE-LABEL: mask_sitofp_2i64_2f64:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; X64-SSE-NEXT: retq
;
@@ -57,7 +57,7 @@ define <2 x double> @mask_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X64-AVX512DQ-LABEL: mask_sitofp_2i64_2f64:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%and = and <2 x i64> %a, <i64 255, i64 65535>
@@ -69,7 +69,7 @@ define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_uitofp_2i64_2f64:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; X86-SSE-NEXT: retl
;
@@ -87,14 +87,14 @@ define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X86-AVX512DQ-LABEL: mask_uitofp_2i64_2f64:
; X86-AVX512DQ: # %bb.0:
-; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X86-AVX512DQ-NEXT: retl
;
; X64-SSE-LABEL: mask_uitofp_2i64_2f64:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; X64-SSE-NEXT: retq
;
@@ -112,7 +112,7 @@ define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X64-AVX512DQ-LABEL: mask_uitofp_2i64_2f64:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%and = and <2 x i64> %a, <i64 255, i64 65535>
@@ -124,7 +124,7 @@ define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_sitofp_4i64_4f32:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X86-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X86-SSE-NEXT: retl
;
@@ -132,7 +132,7 @@ define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX-NEXT: vzeroupper
; X86-AVX-NEXT: retl
@@ -140,14 +140,14 @@ define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-AVX512F-LABEL: mask_sitofp_4i64_4f32:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0
-; X86-AVX512F-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX512F-NEXT: vzeroupper
; X86-AVX512F-NEXT: retl
;
; X86-AVX512DQ-LABEL: mask_sitofp_4i64_4f32:
; X86-AVX512DQ: # %bb.0:
-; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; X86-AVX512DQ-NEXT: vzeroupper
; X86-AVX512DQ-NEXT: retl
@@ -155,7 +155,7 @@ define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X64-SSE-LABEL: mask_sitofp_4i64_4f32:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X64-SSE-NEXT: retq
;
@@ -163,7 +163,7 @@ define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-AVX-NEXT: vzeroupper
; X64-AVX-NEXT: retq
@@ -171,14 +171,14 @@ define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X64-AVX512F-LABEL: mask_sitofp_4i64_4f32:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vpmovqd %ymm0, %xmm0
-; X64-AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-AVX512F-NEXT: vzeroupper
; X64-AVX512F-NEXT: retq
;
; X64-AVX512DQ-LABEL: mask_sitofp_4i64_4f32:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; X64-AVX512DQ-NEXT: vzeroupper
; X64-AVX512DQ-NEXT: retq
@@ -191,7 +191,7 @@ define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_uitofp_4i64_4f32:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X86-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X86-SSE-NEXT: retl
;
@@ -199,7 +199,7 @@ define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX-NEXT: vzeroupper
; X86-AVX-NEXT: retl
@@ -207,14 +207,14 @@ define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-AVX512F-LABEL: mask_uitofp_4i64_4f32:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0
-; X86-AVX512F-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX512F-NEXT: vzeroupper
; X86-AVX512F-NEXT: retl
;
; X86-AVX512DQ-LABEL: mask_uitofp_4i64_4f32:
; X86-AVX512DQ: # %bb.0:
-; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; X86-AVX512DQ-NEXT: vzeroupper
; X86-AVX512DQ-NEXT: retl
@@ -222,7 +222,7 @@ define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X64-SSE-LABEL: mask_uitofp_4i64_4f32:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X64-SSE-NEXT: retq
;
@@ -230,7 +230,7 @@ define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-AVX-NEXT: vzeroupper
; X64-AVX-NEXT: retq
@@ -238,14 +238,14 @@ define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X64-AVX512F-LABEL: mask_uitofp_4i64_4f32:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vpmovqd %ymm0, %xmm0
-; X64-AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-AVX512F-NEXT: vzeroupper
; X64-AVX512F-NEXT: retq
;
; X64-AVX512DQ-LABEL: mask_uitofp_4i64_4f32:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; X64-AVX512DQ-NEXT: vzeroupper
; X64-AVX512DQ-NEXT: retq
@@ -270,7 +270,7 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; X86-SSE-NEXT: por %xmm2, %xmm3
; X86-SSE-NEXT: pand %xmm3, %xmm0
-; X86-SSE-NEXT: pandn {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE-NEXT: por %xmm0, %xmm3
; X86-SSE-NEXT: pxor %xmm3, %xmm1
; X86-SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483903,0,2147483903,0]
@@ -283,7 +283,7 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; X86-SSE-NEXT: por %xmm0, %xmm1
; X86-SSE-NEXT: pand %xmm1, %xmm3
-; X86-SSE-NEXT: pandn {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: por %xmm3, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -305,16 +305,16 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X86-AVX512F-LABEL: clamp_sitofp_2i64_2f64:
; X86-AVX512F: # %bb.0:
-; X86-AVX512F-NEXT: vpmaxsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X86-AVX512F-NEXT: vpminsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-AVX512F-NEXT: retl
;
; X86-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64:
; X86-AVX512DQ: # %bb.0:
-; X86-AVX512DQ-NEXT: vpmaxsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X86-AVX512DQ-NEXT: vpminsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512DQ-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX512DQ-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X86-AVX512DQ-NEXT: retl
;
@@ -333,7 +333,7 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X64-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; X64-SSE-NEXT: por %xmm2, %xmm3
; X64-SSE-NEXT: pand %xmm3, %xmm0
-; X64-SSE-NEXT: pandn {{.*}}(%rip), %xmm3
+; X64-SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; X64-SSE-NEXT: por %xmm0, %xmm3
; X64-SSE-NEXT: pxor %xmm3, %xmm1
; X64-SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483903,2147483903]
@@ -346,7 +346,7 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; X64-SSE-NEXT: por %xmm0, %xmm1
; X64-SSE-NEXT: pand %xmm1, %xmm3
-; X64-SSE-NEXT: pandn {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: por %xmm3, %xmm1
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -366,16 +366,16 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X64-AVX512F-LABEL: clamp_sitofp_2i64_2f64:
; X64-AVX512F: # %bb.0:
-; X64-AVX512F-NEXT: vpmaxsq {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX512F-NEXT: vpminsq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-AVX512F-NEXT: retq
;
; X64-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmaxsq {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX512DQ-NEXT: vpminsq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%clo = icmp slt <2 x i64> %a, <i64 -255, i64 -255>
diff --git a/llvm/test/CodeGen/X86/immediate_merging.ll b/llvm/test/CodeGen/X86/immediate_merging.ll
index 49cf4c5949d8b..2c8e61515e617 100644
--- a/llvm/test/CodeGen/X86/immediate_merging.ll
+++ b/llvm/test/CodeGen/X86/immediate_merging.ll
@@ -36,18 +36,18 @@ define dso_local i32 @foo() optsize {
; X64-LABEL: foo:
; X64: # %bb.0: # %entry
; X64-NEXT: movl $1234, %eax # imm = 0x4D2
-; X64-NEXT: movl %eax, {{.*}}(%rip)
-; X64-NEXT: movl %eax, {{.*}}(%rip)
-; X64-NEXT: movl $12, {{.*}}(%rip)
-; X64-NEXT: cmpl $12, {{.*}}(%rip)
+; X64-NEXT: movl %eax, a(%rip)
+; X64-NEXT: movl %eax, b(%rip)
+; X64-NEXT: movl $12, c(%rip)
+; X64-NEXT: cmpl $12, e(%rip)
; X64-NEXT: jne .LBB0_2
; X64-NEXT: # %bb.1: # %if.then
-; X64-NEXT: movl $1, {{.*}}(%rip)
+; X64-NEXT: movl $1, x(%rip)
; X64-NEXT: .LBB0_2: # %if.end
-; X64-NEXT: movl $1234, {{.*}}(%rip) # imm = 0x4D2
+; X64-NEXT: movl $1234, f(%rip) # imm = 0x4D2
; X64-NEXT: movl $555, %eax # imm = 0x22B
-; X64-NEXT: movl %eax, {{.*}}(%rip)
-; X64-NEXT: addl %eax, {{.*}}(%rip)
+; X64-NEXT: movl %eax, h(%rip)
+; X64-NEXT: addl %eax, i(%rip)
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
entry:
@@ -97,18 +97,18 @@ define dso_local i32 @foo_pgso() !prof !14 {
; X64-LABEL: foo_pgso:
; X64: # %bb.0: # %entry
; X64-NEXT: movl $1234, %eax # imm = 0x4D2
-; X64-NEXT: movl %eax, {{.*}}(%rip)
-; X64-NEXT: movl %eax, {{.*}}(%rip)
-; X64-NEXT: movl $12, {{.*}}(%rip)
-; X64-NEXT: cmpl $12, {{.*}}(%rip)
+; X64-NEXT: movl %eax, a(%rip)
+; X64-NEXT: movl %eax, b(%rip)
+; X64-NEXT: movl $12, c(%rip)
+; X64-NEXT: cmpl $12, e(%rip)
; X64-NEXT: jne .LBB1_2
; X64-NEXT: # %bb.1: # %if.then
-; X64-NEXT: movl $1, {{.*}}(%rip)
+; X64-NEXT: movl $1, x(%rip)
; X64-NEXT: .LBB1_2: # %if.end
-; X64-NEXT: movl $1234, {{.*}}(%rip) # imm = 0x4D2
+; X64-NEXT: movl $1234, f(%rip) # imm = 0x4D2
; X64-NEXT: movl $555, %eax # imm = 0x22B
-; X64-NEXT: movl %eax, {{.*}}(%rip)
-; X64-NEXT: addl %eax, {{.*}}(%rip)
+; X64-NEXT: movl %eax, h(%rip)
+; X64-NEXT: addl %eax, i(%rip)
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
entry:
@@ -144,8 +144,8 @@ define dso_local i32 @foo2() {
;
; X64-LABEL: foo2:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl $1234, {{.*}}(%rip) # imm = 0x4D2
-; X64-NEXT: movl $1234, {{.*}}(%rip) # imm = 0x4D2
+; X64-NEXT: movl $1234, a(%rip) # imm = 0x4D2
+; X64-NEXT: movl $1234, b(%rip) # imm = 0x4D2
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
entry:
@@ -176,9 +176,9 @@ define dso_local void @foomemset() optsize {
; X64-LABEL: foomemset:
; X64: # %bb.0: # %entry
; X64-NEXT: movabsq $2387225703656530209, %rax # imm = 0x2121212121212121
-; X64-NEXT: movq %rax, AA+{{.*}}(%rip)
-; X64-NEXT: movq %rax, AA+{{.*}}(%rip)
-; X64-NEXT: movq %rax, {{.*}}(%rip)
+; X64-NEXT: movq %rax, AA+16(%rip)
+; X64-NEXT: movq %rax, AA+8(%rip)
+; X64-NEXT: movq %rax, AA(%rip)
; X64-NEXT: retq
entry:
call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([100 x i8], [100 x i8]* @AA, i32 0, i32 0), i8 33, i32 24, i1 false)
@@ -203,9 +203,9 @@ define dso_local void @foomemset_pgso() !prof !14 {
; X64-LABEL: foomemset_pgso:
; X64: # %bb.0: # %entry
; X64-NEXT: movabsq $2387225703656530209, %rax # imm = 0x2121212121212121
-; X64-NEXT: movq %rax, AA+{{.*}}(%rip)
-; X64-NEXT: movq %rax, AA+{{.*}}(%rip)
-; X64-NEXT: movq %rax, {{.*}}(%rip)
+; X64-NEXT: movq %rax, AA+16(%rip)
+; X64-NEXT: movq %rax, AA+8(%rip)
+; X64-NEXT: movq %rax, AA(%rip)
; X64-NEXT: retq
entry:
call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([100 x i8], [100 x i8]* @AA, i32 0, i32 0), i8 33, i32 24, i1 false)
diff --git a/llvm/test/CodeGen/X86/imul-lea.ll b/llvm/test/CodeGen/X86/imul-lea.ll
index 777222ec0bf23..9d27794e9c4e2 100644
--- a/llvm/test/CodeGen/X86/imul-lea.ll
+++ b/llvm/test/CodeGen/X86/imul-lea.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
define i32 @test() {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
-; CHECK-NEXT: calll foo
+; CHECK-NEXT: calll foo at PLT
; CHECK-NEXT: leal (%eax,%eax,8), %eax
; CHECK-NEXT: retl
%tmp.0 = tail call i32 @foo( )
diff --git a/llvm/test/CodeGen/X86/inline-0bh.ll b/llvm/test/CodeGen/X86/inline-0bh.ll
index 1ea78f91c2398..d1d747fdc5d44 100644
--- a/llvm/test/CodeGen/X86/inline-0bh.ll
+++ b/llvm/test/CodeGen/X86/inline-0bh.ll
@@ -5,11 +5,13 @@
define i32 @PR31007() {
; CHECK-LABEL: PR31007:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: #APP
-; CHECK: addb $11, %al
-; CHECK: #NO_APP
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: retq
+; CHECK-NEXT: #APP
+; CHECK-EMPTY:
+; CHECK-NEXT: addb $11, %al
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
entry:
call void asm sideeffect inteldialect "add al,$$0bH", "~{al},~{flags},~{dirflag},~{fpsr},~{flags}"()
ret i32 0
diff --git a/llvm/test/CodeGen/X86/inline-asm-flag-output.ll b/llvm/test/CodeGen/X86/inline-asm-flag-output.ll
index 8b0d573d8cb7c..1c89ce94c86c7 100644
--- a/llvm/test/CodeGen/X86/inline-asm-flag-output.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-flag-output.ll
@@ -882,7 +882,7 @@ define void @test_cca_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jbe .LBB28_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB28_2: # %exit
; X32-NEXT: retl
;
@@ -894,7 +894,7 @@ define void @test_cca_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jbe .LBB28_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB28_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -922,7 +922,7 @@ define void @test_ccae_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jb .LBB29_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB29_2: # %exit
; X32-NEXT: retl
;
@@ -934,7 +934,7 @@ define void @test_ccae_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jb .LBB29_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB29_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -962,7 +962,7 @@ define void @test_ccb_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jae .LBB30_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB30_2: # %exit
; X32-NEXT: retl
;
@@ -974,7 +974,7 @@ define void @test_ccb_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jae .LBB30_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB30_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1002,7 +1002,7 @@ define void @test_ccbe_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: ja .LBB31_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB31_2: # %exit
; X32-NEXT: retl
;
@@ -1014,7 +1014,7 @@ define void @test_ccbe_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: ja .LBB31_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB31_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1042,7 +1042,7 @@ define void @test_ccc_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jae .LBB32_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB32_2: # %exit
; X32-NEXT: retl
;
@@ -1054,7 +1054,7 @@ define void @test_ccc_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jae .LBB32_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB32_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1082,7 +1082,7 @@ define void @test_cce_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jne .LBB33_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB33_2: # %exit
; X32-NEXT: retl
;
@@ -1094,7 +1094,7 @@ define void @test_cce_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jne .LBB33_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB33_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1122,7 +1122,7 @@ define void @test_ccz_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jne .LBB34_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB34_2: # %exit
; X32-NEXT: retl
;
@@ -1134,7 +1134,7 @@ define void @test_ccz_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jne .LBB34_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB34_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1162,7 +1162,7 @@ define void @test_ccg_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jle .LBB35_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB35_2: # %exit
; X32-NEXT: retl
;
@@ -1174,7 +1174,7 @@ define void @test_ccg_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jle .LBB35_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB35_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1202,7 +1202,7 @@ define void @test_ccge_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jl .LBB36_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB36_2: # %exit
; X32-NEXT: retl
;
@@ -1214,7 +1214,7 @@ define void @test_ccge_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jl .LBB36_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB36_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1242,7 +1242,7 @@ define void @test_ccl_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jge .LBB37_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB37_2: # %exit
; X32-NEXT: retl
;
@@ -1254,7 +1254,7 @@ define void @test_ccl_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jge .LBB37_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB37_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1282,7 +1282,7 @@ define void @test_ccle_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jg .LBB38_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB38_2: # %exit
; X32-NEXT: retl
;
@@ -1294,7 +1294,7 @@ define void @test_ccle_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jg .LBB38_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB38_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1322,7 +1322,7 @@ define void @test_ccna_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: ja .LBB39_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB39_2: # %exit
; X32-NEXT: retl
;
@@ -1334,7 +1334,7 @@ define void @test_ccna_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: ja .LBB39_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB39_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1362,7 +1362,7 @@ define void @test_ccnae_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jae .LBB40_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB40_2: # %exit
; X32-NEXT: retl
;
@@ -1374,7 +1374,7 @@ define void @test_ccnae_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jae .LBB40_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB40_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1402,7 +1402,7 @@ define void @test_ccnb_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jb .LBB41_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB41_2: # %exit
; X32-NEXT: retl
;
@@ -1414,7 +1414,7 @@ define void @test_ccnb_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jb .LBB41_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB41_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1442,7 +1442,7 @@ define void @test_ccnbe_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jbe .LBB42_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB42_2: # %exit
; X32-NEXT: retl
;
@@ -1454,7 +1454,7 @@ define void @test_ccnbe_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jbe .LBB42_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB42_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1482,7 +1482,7 @@ define void @test_ccnc_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jb .LBB43_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB43_2: # %exit
; X32-NEXT: retl
;
@@ -1494,7 +1494,7 @@ define void @test_ccnc_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jb .LBB43_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB43_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1522,7 +1522,7 @@ define void @test_ccne_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: je .LBB44_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB44_2: # %exit
; X32-NEXT: retl
;
@@ -1534,7 +1534,7 @@ define void @test_ccne_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: je .LBB44_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB44_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1562,7 +1562,7 @@ define void @test_ccnz_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: je .LBB45_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB45_2: # %exit
; X32-NEXT: retl
;
@@ -1574,7 +1574,7 @@ define void @test_ccnz_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: je .LBB45_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB45_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1602,7 +1602,7 @@ define void @test_ccng_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jg .LBB46_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB46_2: # %exit
; X32-NEXT: retl
;
@@ -1614,7 +1614,7 @@ define void @test_ccng_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jg .LBB46_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB46_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1642,7 +1642,7 @@ define void @test_ccnge_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jge .LBB47_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB47_2: # %exit
; X32-NEXT: retl
;
@@ -1654,7 +1654,7 @@ define void @test_ccnge_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jge .LBB47_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB47_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1682,7 +1682,7 @@ define void @test_ccnl_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jl .LBB48_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB48_2: # %exit
; X32-NEXT: retl
;
@@ -1694,7 +1694,7 @@ define void @test_ccnl_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jl .LBB48_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB48_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1722,7 +1722,7 @@ define void @test_ccnle_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jle .LBB49_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB49_2: # %exit
; X32-NEXT: retl
;
@@ -1734,7 +1734,7 @@ define void @test_ccnle_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jle .LBB49_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB49_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1762,7 +1762,7 @@ define void @test_ccno_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jo .LBB50_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB50_2: # %exit
; X32-NEXT: retl
;
@@ -1774,7 +1774,7 @@ define void @test_ccno_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jo .LBB50_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB50_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1802,7 +1802,7 @@ define void @test_ccnp_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jp .LBB51_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB51_2: # %exit
; X32-NEXT: retl
;
@@ -1814,7 +1814,7 @@ define void @test_ccnp_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jp .LBB51_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB51_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1842,7 +1842,7 @@ define void @test_ccns_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: js .LBB52_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB52_2: # %exit
; X32-NEXT: retl
;
@@ -1854,7 +1854,7 @@ define void @test_ccns_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: js .LBB52_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB52_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1882,7 +1882,7 @@ define void @test_cco_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jno .LBB53_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB53_2: # %exit
; X32-NEXT: retl
;
@@ -1894,7 +1894,7 @@ define void @test_cco_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jno .LBB53_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB53_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1922,7 +1922,7 @@ define void @test_ccp_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jnp .LBB54_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB54_2: # %exit
; X32-NEXT: retl
;
@@ -1934,7 +1934,7 @@ define void @test_ccp_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jnp .LBB54_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB54_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
@@ -1962,7 +1962,7 @@ define void @test_ccs_branch(i64 %nr, i64* %addr) nounwind {
; X32-NEXT: #NO_APP
; X32-NEXT: jns .LBB55_2
; X32-NEXT: # %bb.1: # %then
-; X32-NEXT: calll bar
+; X32-NEXT: calll bar at PLT
; X32-NEXT: .LBB55_2: # %exit
; X32-NEXT: retl
;
@@ -1974,7 +1974,7 @@ define void @test_ccs_branch(i64 %nr, i64* %addr) nounwind {
; X64-NEXT: #NO_APP
; X64-NEXT: jns .LBB55_2
; X64-NEXT: # %bb.1: # %then
-; X64-NEXT: callq bar
+; X64-NEXT: callq bar at PLT
; X64-NEXT: .LBB55_2: # %exit
; X64-NEXT: popq %rax
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/inline-asm-fpstack.ll b/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
index 9454d46929f36..d0090d7f2e71e 100644
--- a/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
@@ -56,7 +56,7 @@ define void @test5(double %X) {
; CHECK-LABEL: test5:
; CHECK: ## %bb.0:
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
-; CHECK-NEXT: fadds LCPI4_0
+; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: frob
; CHECK-NEXT: ## InlineAsm End
@@ -113,7 +113,7 @@ entry:
define void @testPR4185() {
; CHECK-LABEL: testPR4185:
; CHECK: ## %bb.0: ## %return
-; CHECK-NEXT: flds LCPI6_0
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fld %st(0)
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fistpl %st
@@ -135,7 +135,7 @@ return:
define void @testPR4185b() {
; CHECK-LABEL: testPR4185b:
; CHECK: ## %bb.0: ## %return
-; CHECK-NEXT: flds LCPI7_0
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fistl %st
; CHECK-NEXT: ## InlineAsm End
@@ -209,9 +209,9 @@ define void @testPR4485(x86_fp80* %a) {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: fldt (%eax)
-; CHECK-NEXT: flds LCPI10_0
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fmul %st, %st(1)
-; CHECK-NEXT: flds LCPI10_1
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fmul %st, %st(2)
; CHECK-NEXT: fxch %st(2)
; CHECK-NEXT: ## InlineAsm Start
@@ -409,7 +409,7 @@ entry:
define i32 @PR10602() nounwind ssp {
; CHECK-LABEL: PR10602:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: flds LCPI19_0
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fld %st(0)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: ## InlineAsm Start
diff --git a/llvm/test/CodeGen/X86/innermost-loop-alignment.ll b/llvm/test/CodeGen/X86/innermost-loop-alignment.ll
index fef30fd287168..a97e9a86a7556 100644
--- a/llvm/test/CodeGen/X86/innermost-loop-alignment.ll
+++ b/llvm/test/CodeGen/X86/innermost-loop-alignment.ll
@@ -7,33 +7,153 @@ declare void @foo()
define void @test(i32 %n, i32 %m) {
; DEFAULT-LABEL: test:
-; DEFAULT: .p2align 4, 0x90
+; DEFAULT: # %bb.0: # %entry
+; DEFAULT-NEXT: pushl %ebp
+; DEFAULT-NEXT: .cfi_def_cfa_offset 8
+; DEFAULT-NEXT: pushl %ebx
+; DEFAULT-NEXT: .cfi_def_cfa_offset 12
+; DEFAULT-NEXT: pushl %edi
+; DEFAULT-NEXT: .cfi_def_cfa_offset 16
+; DEFAULT-NEXT: pushl %esi
+; DEFAULT-NEXT: .cfi_def_cfa_offset 20
+; DEFAULT-NEXT: subl $12, %esp
+; DEFAULT-NEXT: .cfi_def_cfa_offset 32
+; DEFAULT-NEXT: .cfi_offset %esi, -20
+; DEFAULT-NEXT: .cfi_offset %edi, -16
+; DEFAULT-NEXT: .cfi_offset %ebx, -12
+; DEFAULT-NEXT: .cfi_offset %ebp, -8
+; DEFAULT-NEXT: xorl %esi, %esi
+; DEFAULT-NEXT: movl {{[0-9]+}}(%esp), %edi
+; DEFAULT-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; DEFAULT-NEXT: .p2align 4, 0x90
; DEFAULT-NEXT: .LBB0_1: # %outer
; DEFAULT-NEXT: # =>This Loop Header: Depth=1
; DEFAULT-NEXT: # Child Loop BB0_2 Depth 2
-; DEFAULT: .p2align 4, 0x90
+; DEFAULT-NEXT: movl %edi, %ebp
+; DEFAULT-NEXT: .p2align 4, 0x90
; DEFAULT-NEXT: .LBB0_2: # %inner
; DEFAULT-NEXT: # Parent Loop BB0_1 Depth=1
-
+; DEFAULT-NEXT: # => This Inner Loop Header: Depth=2
+; DEFAULT-NEXT: calll foo at PLT
+; DEFAULT-NEXT: decl %ebp
+; DEFAULT-NEXT: jne .LBB0_2
+; DEFAULT-NEXT: # %bb.3: # %outer_bb
+; DEFAULT-NEXT: # in Loop: Header=BB0_1 Depth=1
+; DEFAULT-NEXT: incl %esi
+; DEFAULT-NEXT: cmpl %ebx, %esi
+; DEFAULT-NEXT: jne .LBB0_1
+; DEFAULT-NEXT: # %bb.4: # %exit
+; DEFAULT-NEXT: addl $12, %esp
+; DEFAULT-NEXT: .cfi_def_cfa_offset 20
+; DEFAULT-NEXT: popl %esi
+; DEFAULT-NEXT: .cfi_def_cfa_offset 16
+; DEFAULT-NEXT: popl %edi
+; DEFAULT-NEXT: .cfi_def_cfa_offset 12
+; DEFAULT-NEXT: popl %ebx
+; DEFAULT-NEXT: .cfi_def_cfa_offset 8
+; DEFAULT-NEXT: popl %ebp
+; DEFAULT-NEXT: .cfi_def_cfa_offset 4
+; DEFAULT-NEXT: retl
+;
; ALIGN32-LABEL: test:
-; ALIGN32: .p2align 4, 0x90
+; ALIGN32: # %bb.0: # %entry
+; ALIGN32-NEXT: pushl %ebp
+; ALIGN32-NEXT: .cfi_def_cfa_offset 8
+; ALIGN32-NEXT: pushl %ebx
+; ALIGN32-NEXT: .cfi_def_cfa_offset 12
+; ALIGN32-NEXT: pushl %edi
+; ALIGN32-NEXT: .cfi_def_cfa_offset 16
+; ALIGN32-NEXT: pushl %esi
+; ALIGN32-NEXT: .cfi_def_cfa_offset 20
+; ALIGN32-NEXT: subl $12, %esp
+; ALIGN32-NEXT: .cfi_def_cfa_offset 32
+; ALIGN32-NEXT: .cfi_offset %esi, -20
+; ALIGN32-NEXT: .cfi_offset %edi, -16
+; ALIGN32-NEXT: .cfi_offset %ebx, -12
+; ALIGN32-NEXT: .cfi_offset %ebp, -8
+; ALIGN32-NEXT: xorl %esi, %esi
+; ALIGN32-NEXT: movl {{[0-9]+}}(%esp), %edi
+; ALIGN32-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; ALIGN32-NEXT: .p2align 4, 0x90
; ALIGN32-NEXT: .LBB0_1: # %outer
; ALIGN32-NEXT: # =>This Loop Header: Depth=1
; ALIGN32-NEXT: # Child Loop BB0_2 Depth 2
-; ALIGN32: .p2align 5, 0x90
+; ALIGN32-NEXT: movl %edi, %ebp
+; ALIGN32-NEXT: .p2align 5, 0x90
; ALIGN32-NEXT: .LBB0_2: # %inner
; ALIGN32-NEXT: # Parent Loop BB0_1 Depth=1
; ALIGN32-NEXT: # => This Inner Loop Header: Depth=2
-
+; ALIGN32-NEXT: calll foo at PLT
+; ALIGN32-NEXT: decl %ebp
+; ALIGN32-NEXT: jne .LBB0_2
+; ALIGN32-NEXT: # %bb.3: # %outer_bb
+; ALIGN32-NEXT: # in Loop: Header=BB0_1 Depth=1
+; ALIGN32-NEXT: incl %esi
+; ALIGN32-NEXT: cmpl %ebx, %esi
+; ALIGN32-NEXT: jne .LBB0_1
+; ALIGN32-NEXT: # %bb.4: # %exit
+; ALIGN32-NEXT: addl $12, %esp
+; ALIGN32-NEXT: .cfi_def_cfa_offset 20
+; ALIGN32-NEXT: popl %esi
+; ALIGN32-NEXT: .cfi_def_cfa_offset 16
+; ALIGN32-NEXT: popl %edi
+; ALIGN32-NEXT: .cfi_def_cfa_offset 12
+; ALIGN32-NEXT: popl %ebx
+; ALIGN32-NEXT: .cfi_def_cfa_offset 8
+; ALIGN32-NEXT: popl %ebp
+; ALIGN32-NEXT: .cfi_def_cfa_offset 4
+; ALIGN32-NEXT: retl
+;
; ALIGN64-LABEL: test:
-; ALIGN64: .p2align 5, 0x90
+; ALIGN64: # %bb.0: # %entry
+; ALIGN64-NEXT: pushl %ebp
+; ALIGN64-NEXT: .cfi_def_cfa_offset 8
+; ALIGN64-NEXT: pushl %ebx
+; ALIGN64-NEXT: .cfi_def_cfa_offset 12
+; ALIGN64-NEXT: pushl %edi
+; ALIGN64-NEXT: .cfi_def_cfa_offset 16
+; ALIGN64-NEXT: pushl %esi
+; ALIGN64-NEXT: .cfi_def_cfa_offset 20
+; ALIGN64-NEXT: subl $12, %esp
+; ALIGN64-NEXT: .cfi_def_cfa_offset 32
+; ALIGN64-NEXT: .cfi_offset %esi, -20
+; ALIGN64-NEXT: .cfi_offset %edi, -16
+; ALIGN64-NEXT: .cfi_offset %ebx, -12
+; ALIGN64-NEXT: .cfi_offset %ebp, -8
+; ALIGN64-NEXT: xorl %esi, %esi
+; ALIGN64-NEXT: movl {{[0-9]+}}(%esp), %edi
+; ALIGN64-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; ALIGN64-NEXT: .p2align 5, 0x90
; ALIGN64-NEXT: .LBB0_1: # %outer
; ALIGN64-NEXT: # =>This Loop Header: Depth=1
; ALIGN64-NEXT: # Child Loop BB0_2 Depth 2
-; ALIGN64: .p2align 6, 0x90
+; ALIGN64-NEXT: movl %edi, %ebp
+; ALIGN64-NEXT: .p2align 6, 0x90
; ALIGN64-NEXT: .LBB0_2: # %inner
; ALIGN64-NEXT: # Parent Loop BB0_1 Depth=1
; ALIGN64-NEXT: # => This Inner Loop Header: Depth=2
+; ALIGN64-NEXT: calll foo at PLT
+; ALIGN64-NEXT: decl %ebp
+; ALIGN64-NEXT: jne .LBB0_2
+; ALIGN64-NEXT: # %bb.3: # %outer_bb
+; ALIGN64-NEXT: # in Loop: Header=BB0_1 Depth=1
+; ALIGN64-NEXT: incl %esi
+; ALIGN64-NEXT: cmpl %ebx, %esi
+; ALIGN64-NEXT: jne .LBB0_1
+; ALIGN64-NEXT: # %bb.4: # %exit
+; ALIGN64-NEXT: addl $12, %esp
+; ALIGN64-NEXT: .cfi_def_cfa_offset 20
+; ALIGN64-NEXT: popl %esi
+; ALIGN64-NEXT: .cfi_def_cfa_offset 16
+; ALIGN64-NEXT: popl %edi
+; ALIGN64-NEXT: .cfi_def_cfa_offset 12
+; ALIGN64-NEXT: popl %ebx
+; ALIGN64-NEXT: .cfi_def_cfa_offset 8
+; ALIGN64-NEXT: popl %ebp
+; ALIGN64-NEXT: .cfi_def_cfa_offset 4
+; ALIGN64-NEXT: retl
+
+
entry:
br label %outer
diff --git a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
index 3aa1abae99f32..749ca979b4915 100644
--- a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
+++ b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
@@ -16,7 +16,7 @@ define <16 x i8> @elt0_v16i8(i8 %x) {
; X86-SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-SSE2-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; X86-SSE2-NEXT: andnps %xmm1, %xmm0
-; X86-SSE2-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: elt0_v16i8:
@@ -24,7 +24,7 @@ define <16 x i8> @elt0_v16i8(i8 %x) {
; X64-SSE2-NEXT: movd %edi, %xmm1
; X64-SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; X64-SSE2-NEXT: pandn %xmm1, %xmm0
-; X64-SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: retq
;
; X86-SSE4-LABEL: elt0_v16i8:
@@ -393,7 +393,7 @@ define <8 x i64> @elt5_v8i64(i64 %x) {
; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0]
; X86-AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; X86-AVX1-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
+; X86-AVX1-NEXT: vinsertf128 $1, {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
; X86-AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
; X86-AVX1-NEXT: retl
;
@@ -410,7 +410,7 @@ define <8 x i64> @elt5_v8i64(i64 %x) {
; X86-AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0]
; X86-AVX2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; X86-AVX2-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
+; X86-AVX2-NEXT: vinsertf128 $1, {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
; X86-AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
; X86-AVX2-NEXT: retl
;
@@ -428,7 +428,7 @@ define <8 x i64> @elt5_v8i64(i64 %x) {
; X86-AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; X86-AVX512F-NEXT: vmovaps {{.*#+}} xmm2 = [4,0,0,0]
; X86-AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; X86-AVX512F-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
+; X86-AVX512F-NEXT: vinsertf128 $1, {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl
;
diff --git a/llvm/test/CodeGen/X86/insertelement-ones.ll b/llvm/test/CodeGen/X86/insertelement-ones.ll
index 9b316714ebbc7..fcc8b4b44f4a4 100644
--- a/llvm/test/CodeGen/X86/insertelement-ones.ll
+++ b/llvm/test/CodeGen/X86/insertelement-ones.ll
@@ -280,12 +280,12 @@ define <16 x i16> @insert_v16i16_x12345x789ABCDEx(<16 x i16> %a) {
;
; AVX1-LABEL: insert_v16i16_x12345x789ABCDEx:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: insert_v16i16_x12345x789ABCDEx:
@@ -327,7 +327,7 @@ define <16 x i8> @insert_v16i8_x123456789ABCDEx(<16 x i8> %a) {
; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: pandn %xmm2, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0]
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq
@@ -340,7 +340,7 @@ define <16 x i8> @insert_v16i8_x123456789ABCDEx(<16 x i8> %a) {
; SSE3-NEXT: movd %eax, %xmm2
; SSE3-NEXT: pandn %xmm2, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0]
; SSE3-NEXT: por %xmm2, %xmm0
; SSE3-NEXT: retq
@@ -389,7 +389,7 @@ define <32 x i8> @insert_v32i8_x123456789ABCDEzGHIJKLMNOPQRSTxx(<32 x i8> %a) {
; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0]
; SSE2-NEXT: por %xmm4, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1]
; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: pand %xmm2, %xmm1
@@ -409,7 +409,7 @@ define <32 x i8> @insert_v32i8_x123456789ABCDEzGHIJKLMNOPQRSTxx(<32 x i8> %a) {
; SSE3-NEXT: movdqa %xmm3, %xmm4
; SSE3-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0]
; SSE3-NEXT: por %xmm4, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1]
; SSE3-NEXT: por %xmm3, %xmm1
; SSE3-NEXT: pand %xmm2, %xmm1
diff --git a/llvm/test/CodeGen/X86/insertelement-var-index.ll b/llvm/test/CodeGen/X86/insertelement-var-index.ll
index 133d6c75029ca..1d20007f2f573 100644
--- a/llvm/test/CodeGen/X86/insertelement-var-index.ll
+++ b/llvm/test/CodeGen/X86/insertelement-var-index.ll
@@ -720,7 +720,7 @@ define <16 x i8> @arg_i8_v16i8(<16 x i8> %v, i8 %x, i32 %y) nounwind {
; AVX512BW-LABEL: arg_i8_v16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastb %esi, %xmm1
-; AVX512BW-NEXT: vpcmpeqb {{.*}}(%rip), %xmm1, %k1
+; AVX512BW-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512BW-NEXT: vpbroadcastb %edi, %xmm0 {%k1}
; AVX512BW-NEXT: retq
%ins = insertelement <16 x i8> %v, i8 %x, i32 %y
@@ -758,7 +758,7 @@ define <8 x i16> @arg_i16_v8i16(<8 x i16> %v, i16 %x, i32 %y) nounwind {
; AVX512BW-LABEL: arg_i16_v8i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastw %esi, %xmm1
-; AVX512BW-NEXT: vpcmpeqw {{.*}}(%rip), %xmm1, %k1
+; AVX512BW-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512BW-NEXT: vpbroadcastw %edi, %xmm0 {%k1}
; AVX512BW-NEXT: retq
%ins = insertelement <8 x i16> %v, i16 %x, i32 %y
@@ -787,7 +787,7 @@ define <4 x i32> @arg_i32_v4i32(<4 x i32> %v, i32 %x, i32 %y) nounwind {
; AVX512-LABEL: arg_i32_v4i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %esi, %xmm1
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512-NEXT: vpbroadcastd %edi, %xmm0 {%k1}
; AVX512-NEXT: retq
%ins = insertelement <4 x i32> %v, i32 %x, i32 %y
@@ -817,7 +817,7 @@ define <2 x i64> @arg_i64_v2i64(<2 x i64> %v, i64 %x, i32 %y) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %esi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %xmm1
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512-NEXT: vpbroadcastq %rdi, %xmm0 {%k1}
; AVX512-NEXT: retq
%ins = insertelement <2 x i64> %v, i64 %x, i32 %y
@@ -840,7 +840,7 @@ define <4 x float> @arg_f32_v4f32(<4 x float> %v, float %x, i32 %y) nounwind {
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
; SSE41-NEXT: movd %edi, %xmm0
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; SSE41-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: retq
@@ -850,7 +850,7 @@ define <4 x float> @arg_f32_v4f32(<4 x float> %v, float %x, i32 %y) nounwind {
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
; AVX1-NEXT: vmovd %edi, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -859,14 +859,14 @@ define <4 x float> @arg_f32_v4f32(<4 x float> %v, float %x, i32 %y) nounwind {
; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
; AVX2-NEXT: vmovd %edi, %xmm2
; AVX2-NEXT: vpbroadcastd %xmm2, %xmm2
-; AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: arg_f32_v4f32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %edi, %xmm2
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
; AVX512-NEXT: vbroadcastss %xmm1, %xmm0 {%k1}
; AVX512-NEXT: retq
%ins = insertelement <4 x float> %v, float %x, i32 %y
@@ -890,7 +890,7 @@ define <2 x double> @arg_f64_v2f64(<2 x double> %v, double %x, i32 %y) nounwind
; SSE41-NEXT: movslq %edi, %rax
; SSE41-NEXT: movq %rax, %xmm0
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE41-NEXT: pcmpeqq {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: retq
@@ -901,7 +901,7 @@ define <2 x double> @arg_f64_v2f64(<2 x double> %v, double %x, i32 %y) nounwind
; AVX1-NEXT: movslq %edi, %rax
; AVX1-NEXT: vmovq %rax, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -911,7 +911,7 @@ define <2 x double> @arg_f64_v2f64(<2 x double> %v, double %x, i32 %y) nounwind
; AVX2-NEXT: movslq %edi, %rax
; AVX2-NEXT: vmovq %rax, %xmm2
; AVX2-NEXT: vpbroadcastq %xmm2, %xmm2
-; AVX2-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -919,7 +919,7 @@ define <2 x double> @arg_f64_v2f64(<2 x double> %v, double %x, i32 %y) nounwind
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %edi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %xmm2
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
; AVX512-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
; AVX512-NEXT: retq
%ins = insertelement <2 x double> %v, double %x, i32 %y
@@ -960,7 +960,7 @@ define <16 x i8> @load_i8_v16i8(<16 x i8> %v, i8* %p, i32 %y) nounwind {
; AVX512BW-LABEL: load_i8_v16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastb %esi, %xmm1
-; AVX512BW-NEXT: vpcmpeqb {{.*}}(%rip), %xmm1, %k1
+; AVX512BW-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512BW-NEXT: vpbroadcastb (%rdi), %xmm0 {%k1}
; AVX512BW-NEXT: retq
%x = load i8, i8* %p
@@ -1002,7 +1002,7 @@ define <8 x i16> @load_i16_v8i16(<8 x i16> %v, i16* %p, i32 %y) nounwind {
; AVX512BW-LABEL: load_i16_v8i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastw %esi, %xmm1
-; AVX512BW-NEXT: vpcmpeqw {{.*}}(%rip), %xmm1, %k1
+; AVX512BW-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512BW-NEXT: vpbroadcastw (%rdi), %xmm0 {%k1}
; AVX512BW-NEXT: retq
%x = load i16, i16* %p
@@ -1034,7 +1034,7 @@ define <4 x i32> @load_i32_v4i32(<4 x i32> %v, i32* %p, i32 %y) nounwind {
; AVX512-LABEL: load_i32_v4i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %esi, %xmm1
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512-NEXT: vpbroadcastd (%rdi), %xmm0 {%k1}
; AVX512-NEXT: retq
%x = load i32, i32* %p
@@ -1067,7 +1067,7 @@ define <2 x i64> @load_i64_v2i64(<2 x i64> %v, i64* %p, i32 %y) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %esi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %xmm1
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512-NEXT: vpbroadcastq (%rdi), %xmm0 {%k1}
; AVX512-NEXT: retq
%x = load i64, i64* %p
@@ -1093,7 +1093,7 @@ define <4 x float> @load_f32_v4f32(<4 x float> %v, float* %p, i32 %y) nounwind {
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0,0,0]
; SSE41-NEXT: movd %esi, %xmm0
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; SSE41-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
@@ -1103,7 +1103,7 @@ define <4 x float> @load_f32_v4f32(<4 x float> %v, float* %p, i32 %y) nounwind {
; AVX1-NEXT: vbroadcastss (%rdi), %xmm1
; AVX1-NEXT: vmovd %esi, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1112,14 +1112,14 @@ define <4 x float> @load_f32_v4f32(<4 x float> %v, float* %p, i32 %y) nounwind {
; AVX2-NEXT: vbroadcastss (%rdi), %xmm1
; AVX2-NEXT: vmovd %esi, %xmm2
; AVX2-NEXT: vpbroadcastd %xmm2, %xmm2
-; AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: load_f32_v4f32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %esi, %xmm1
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512-NEXT: vbroadcastss (%rdi), %xmm0 {%k1}
; AVX512-NEXT: retq
%x = load float, float* %p
@@ -1145,7 +1145,7 @@ define <2 x double> @load_f64_v2f64(<2 x double> %v, double* %p, i32 %y) nounwin
; SSE41-NEXT: movslq %esi, %rax
; SSE41-NEXT: movq %rax, %xmm0
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE41-NEXT: pcmpeqq {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: retq
@@ -1156,7 +1156,7 @@ define <2 x double> @load_f64_v2f64(<2 x double> %v, double* %p, i32 %y) nounwin
; AVX1-NEXT: movslq %esi, %rax
; AVX1-NEXT: vmovq %rax, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1166,7 +1166,7 @@ define <2 x double> @load_f64_v2f64(<2 x double> %v, double* %p, i32 %y) nounwin
; AVX2-NEXT: movslq %esi, %rax
; AVX2-NEXT: vmovq %rax, %xmm2
; AVX2-NEXT: vpbroadcastq %xmm2, %xmm2
-; AVX2-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -1174,7 +1174,7 @@ define <2 x double> @load_f64_v2f64(<2 x double> %v, double* %p, i32 %y) nounwin
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %esi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %xmm1
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = mem[0,0]
; AVX512-NEXT: retq
%x = load double, double* %p
@@ -1227,7 +1227,7 @@ define <32 x i8> @arg_i8_v32i8(<32 x i8> %v, i8 %x, i32 %y) nounwind {
; AVX512BW-LABEL: arg_i8_v32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastb %esi, %ymm1
-; AVX512BW-NEXT: vpcmpeqb {{.*}}(%rip), %ymm1, %k1
+; AVX512BW-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512BW-NEXT: vpbroadcastb %edi, %ymm0 {%k1}
; AVX512BW-NEXT: retq
%ins = insertelement <32 x i8> %v, i8 %x, i32 %y
@@ -1279,7 +1279,7 @@ define <16 x i16> @arg_i16_v16i16(<16 x i16> %v, i16 %x, i32 %y) nounwind {
; AVX512BW-LABEL: arg_i16_v16i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastw %esi, %ymm1
-; AVX512BW-NEXT: vpcmpeqw {{.*}}(%rip), %ymm1, %k1
+; AVX512BW-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512BW-NEXT: vpbroadcastw %edi, %ymm0 {%k1}
; AVX512BW-NEXT: retq
%ins = insertelement <16 x i16> %v, i16 %x, i32 %y
@@ -1316,7 +1316,7 @@ define <8 x i32> @arg_i32_v8i32(<8 x i32> %v, i32 %x, i32 %y) nounwind {
; AVX512-LABEL: arg_i32_v8i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %esi, %ymm1
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %ymm1, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512-NEXT: vpbroadcastd %edi, %ymm0 {%k1}
; AVX512-NEXT: retq
%ins = insertelement <8 x i32> %v, i32 %x, i32 %y
@@ -1354,7 +1354,7 @@ define <4 x i64> @arg_i64_v4i64(<4 x i64> %v, i64 %x, i32 %y) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %esi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %ymm1
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %ymm1, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512-NEXT: vpbroadcastq %rdi, %ymm0 {%k1}
; AVX512-NEXT: retq
%ins = insertelement <4 x i64> %v, i64 %x, i32 %y
@@ -1379,8 +1379,8 @@ define <8 x float> @arg_f32_v8f32(<8 x float> %v, float %x, i32 %y) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: vmovd %edi, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %xmm3
-; AVX1-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX1-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -1390,14 +1390,14 @@ define <8 x float> @arg_f32_v8f32(<8 x float> %v, float %x, i32 %y) nounwind {
; AVX2-NEXT: vbroadcastss %xmm1, %ymm1
; AVX2-NEXT: vmovd %edi, %xmm2
; AVX2-NEXT: vpbroadcastd %xmm2, %ymm2
-; AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: arg_f32_v8f32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %edi, %ymm2
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %ymm2, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %k1
; AVX512-NEXT: vbroadcastss %xmm1, %ymm0 {%k1}
; AVX512-NEXT: retq
%ins = insertelement <8 x float> %v, float %x, i32 %y
@@ -1423,8 +1423,8 @@ define <4 x double> @arg_f64_v4f64(<4 x double> %v, double %x, i32 %y) nounwind
; AVX1-NEXT: movslq %edi, %rax
; AVX1-NEXT: vmovq %rax, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %xmm3
-; AVX1-NEXT: vpcmpeqq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX1-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -1435,7 +1435,7 @@ define <4 x double> @arg_f64_v4f64(<4 x double> %v, double %x, i32 %y) nounwind
; AVX2-NEXT: movslq %edi, %rax
; AVX2-NEXT: vmovq %rax, %xmm2
; AVX2-NEXT: vpbroadcastq %xmm2, %ymm2
-; AVX2-NEXT: vpcmpeqq {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -1443,7 +1443,7 @@ define <4 x double> @arg_f64_v4f64(<4 x double> %v, double %x, i32 %y) nounwind
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %edi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %ymm2
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %ymm2, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %k1
; AVX512-NEXT: vbroadcastsd %xmm1, %ymm0 {%k1}
; AVX512-NEXT: retq
%ins = insertelement <4 x double> %v, double %x, i32 %y
@@ -1498,7 +1498,7 @@ define <32 x i8> @load_i8_v32i8(<32 x i8> %v, i8* %p, i32 %y) nounwind {
; AVX512BW-LABEL: load_i8_v32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastb %esi, %ymm1
-; AVX512BW-NEXT: vpcmpeqb {{.*}}(%rip), %ymm1, %k1
+; AVX512BW-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512BW-NEXT: vpbroadcastb (%rdi), %ymm0 {%k1}
; AVX512BW-NEXT: retq
%x = load i8, i8* %p
@@ -1554,7 +1554,7 @@ define <16 x i16> @load_i16_v16i16(<16 x i16> %v, i16* %p, i32 %y) nounwind {
; AVX512BW-LABEL: load_i16_v16i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastw %esi, %ymm1
-; AVX512BW-NEXT: vpcmpeqw {{.*}}(%rip), %ymm1, %k1
+; AVX512BW-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512BW-NEXT: vpbroadcastw (%rdi), %ymm0 {%k1}
; AVX512BW-NEXT: retq
%x = load i16, i16* %p
@@ -1594,7 +1594,7 @@ define <8 x i32> @load_i32_v8i32(<8 x i32> %v, i32* %p, i32 %y) nounwind {
; AVX512-LABEL: load_i32_v8i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %esi, %ymm1
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %ymm1, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512-NEXT: vpbroadcastd (%rdi), %ymm0 {%k1}
; AVX512-NEXT: retq
%x = load i32, i32* %p
@@ -1635,7 +1635,7 @@ define <4 x i64> @load_i64_v4i64(<4 x i64> %v, i64* %p, i32 %y) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %esi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %ymm1
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %ymm1, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512-NEXT: vpbroadcastq (%rdi), %ymm0 {%k1}
; AVX512-NEXT: retq
%x = load i64, i64* %p
@@ -1660,8 +1660,8 @@ define <8 x float> @load_f32_v8f32(<8 x float> %v, float* %p, i32 %y) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vmovd %esi, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm2
-; AVX1-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vbroadcastss (%rdi), %ymm2
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
@@ -1672,14 +1672,14 @@ define <8 x float> @load_f32_v8f32(<8 x float> %v, float* %p, i32 %y) nounwind {
; AVX2-NEXT: vbroadcastss (%rdi), %ymm1
; AVX2-NEXT: vmovd %esi, %xmm2
; AVX2-NEXT: vpbroadcastd %xmm2, %ymm2
-; AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: load_f32_v8f32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastd %esi, %ymm1
-; AVX512-NEXT: vpcmpeqd {{.*}}(%rip), %ymm1, %k1
+; AVX512-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512-NEXT: vbroadcastss (%rdi), %ymm0 {%k1}
; AVX512-NEXT: retq
%x = load float, float* %p
@@ -1705,8 +1705,8 @@ define <4 x double> @load_f64_v4f64(<4 x double> %v, double* %p, i32 %y) nounwin
; AVX1-NEXT: movslq %esi, %rax
; AVX1-NEXT: vmovq %rax, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm2
-; AVX1-NEXT: vpcmpeqq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vbroadcastsd (%rdi), %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
@@ -1718,7 +1718,7 @@ define <4 x double> @load_f64_v4f64(<4 x double> %v, double* %p, i32 %y) nounwin
; AVX2-NEXT: movslq %esi, %rax
; AVX2-NEXT: vmovq %rax, %xmm2
; AVX2-NEXT: vpbroadcastq %xmm2, %ymm2
-; AVX2-NEXT: vpcmpeqq {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -1726,7 +1726,7 @@ define <4 x double> @load_f64_v4f64(<4 x double> %v, double* %p, i32 %y) nounwin
; AVX512: # %bb.0:
; AVX512-NEXT: movslq %esi, %rax
; AVX512-NEXT: vpbroadcastq %rax, %ymm1
-; AVX512-NEXT: vpcmpeqq {{.*}}(%rip), %ymm1, %k1
+; AVX512-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512-NEXT: vbroadcastsd (%rdi), %ymm0 {%k1}
; AVX512-NEXT: retq
%x = load double, double* %p
diff --git a/llvm/test/CodeGen/X86/insertps-combine.ll b/llvm/test/CodeGen/X86/insertps-combine.ll
index 7b761aecaedca..195fabae23d81 100644
--- a/llvm/test/CodeGen/X86/insertps-combine.ll
+++ b/llvm/test/CodeGen/X86/insertps-combine.ll
@@ -163,7 +163,7 @@ define <4 x float> @insertps_zero_from_v2f64(<4 x float> %a0, <2 x double>* %a1)
; SSE-LABEL: insertps_zero_from_v2f64:
; SSE: # %bb.0:
; SSE-NEXT: movapd (%rdi), %xmm1
-; SSE-NEXT: addpd {{.*}}(%rip), %xmm1
+; SSE-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
; SSE-NEXT: movapd %xmm1, (%rdi)
; SSE-NEXT: retq
@@ -171,7 +171,7 @@ define <4 x float> @insertps_zero_from_v2f64(<4 x float> %a0, <2 x double>* %a1)
; AVX-LABEL: insertps_zero_from_v2f64:
; AVX: # %bb.0:
; AVX-NEXT: vmovapd (%rdi), %xmm1
-; AVX-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
; AVX-NEXT: vmovapd %xmm1, (%rdi)
; AVX-NEXT: retq
@@ -187,7 +187,7 @@ define <4 x float> @insertps_zero_from_v2i64(<4 x float> %a0, <2 x i64>* %a1) no
; SSE-LABEL: insertps_zero_from_v2i64:
; SSE: # %bb.0:
; SSE-NEXT: movdqa (%rdi), %xmm1
-; SSE-NEXT: paddq {{.*}}(%rip), %xmm1
+; SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
; SSE-NEXT: movdqa %xmm1, (%rdi)
; SSE-NEXT: retq
@@ -195,7 +195,7 @@ define <4 x float> @insertps_zero_from_v2i64(<4 x float> %a0, <2 x i64>* %a1) no
; AVX-LABEL: insertps_zero_from_v2i64:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqa (%rdi), %xmm1
-; AVX-NEXT: vpaddq {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
; AVX-NEXT: vmovdqa %xmm1, (%rdi)
; AVX-NEXT: retq
@@ -211,7 +211,7 @@ define <4 x float> @insertps_zero_from_v8i16(<4 x float> %a0, <8 x i16>* %a1) no
; SSE-LABEL: insertps_zero_from_v8i16:
; SSE: # %bb.0:
; SSE-NEXT: movdqa (%rdi), %xmm1
-; SSE-NEXT: paddw {{.*}}(%rip), %xmm1
+; SSE-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
; SSE-NEXT: movdqa %xmm1, (%rdi)
; SSE-NEXT: retq
@@ -219,7 +219,7 @@ define <4 x float> @insertps_zero_from_v8i16(<4 x float> %a0, <8 x i16>* %a1) no
; AVX-LABEL: insertps_zero_from_v8i16:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqa (%rdi), %xmm1
-; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
; AVX-NEXT: vmovdqa %xmm1, (%rdi)
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/isint.ll b/llvm/test/CodeGen/X86/isint.ll
index 5f6cd64ff03aa..8a56f49a6c755 100644
--- a/llvm/test/CodeGen/X86/isint.ll
+++ b/llvm/test/CodeGen/X86/isint.ll
@@ -69,7 +69,7 @@ define void @isint_branch(double %d) nounwind {
; CHECK64-NEXT: jp .LBB2_2
; CHECK64-NEXT: # %bb.1: # %true
; CHECK64-NEXT: pushq %rax
-; CHECK64-NEXT: callq foo
+; CHECK64-NEXT: callq foo at PLT
; CHECK64-NEXT: popq %rax
; CHECK64-NEXT: .LBB2_2: # %false
; CHECK64-NEXT: retq
@@ -83,7 +83,7 @@ define void @isint_branch(double %d) nounwind {
; CHECK32-NEXT: jne .LBB2_2
; CHECK32-NEXT: jp .LBB2_2
; CHECK32-NEXT: # %bb.1: # %true
-; CHECK32-NEXT: calll foo
+; CHECK32-NEXT: calll foo at PLT
; CHECK32-NEXT: .LBB2_2: # %false
; CHECK32-NEXT: retl
%i = fptosi double %d to i32
diff --git a/llvm/test/CodeGen/X86/keylocker-intrinsics.ll b/llvm/test/CodeGen/X86/keylocker-intrinsics.ll
index 15716f3169f85..2fe034e745d2c 100644
--- a/llvm/test/CodeGen/X86/keylocker-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/keylocker-intrinsics.ll
@@ -548,7 +548,7 @@ entry:
define i8 @test_mm_aesenc256kl_u8_global(<2 x i64> %data, <2 x i64>* %out) {
; X64-LABEL: test_mm_aesenc256kl_u8_global:
; X64: # %bb.0: # %entry
-; X64-NEXT: aesenc256kl {{.*}}(%rip), %xmm0
+; X64-NEXT: aesenc256kl foo(%rip), %xmm0
; X64-NEXT: sete %al
; X64-NEXT: movaps %xmm0, (%rdi)
; X64-NEXT: retq
@@ -574,7 +574,7 @@ define i8 @test_mm_aesdecwide256kl_u8_global(<2 x i64> %v0, <2 x i64> %v1, <2 x
; X64: # %bb.0: # %entry
; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10
; X64-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; X64-NEXT: aesdecwide256kl {{.*}}(%rip)
+; X64-NEXT: aesdecwide256kl foo(%rip)
; X64-NEXT: sete %al
; X64-NEXT: movaps %xmm0, (%rdi)
; X64-NEXT: movaps %xmm1, (%rsi)
diff --git a/llvm/test/CodeGen/X86/known-bits-vector.ll b/llvm/test/CodeGen/X86/known-bits-vector.ll
index 2a8ea368edb03..5170894e6330a 100644
--- a/llvm/test/CodeGen/X86/known-bits-vector.ll
+++ b/llvm/test/CodeGen/X86/known-bits-vector.ll
@@ -74,14 +74,14 @@ define <4 x float> @knownbits_insert_uitofp(<4 x i32> %a0, i16 %a1, i16 %a2) nou
define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_sext:
; X32: # %bb.0:
-; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_sext:
; X64: # %bb.0:
-; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-NEXT: retq
@@ -94,14 +94,14 @@ define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind {
define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_shuffle_sext:
; X32: # %bb.0:
-; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_shuffle_sext:
; X64: # %bb.0:
-; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-NEXT: retq
@@ -115,14 +115,14 @@ define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind {
define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:
; X32: # %bb.0:
-; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X32-NEXT: vpmovsxwd %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:
; X64: # %bb.0:
-; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X64-NEXT: vpmovsxwd %xmm0, %xmm0
; X64-NEXT: retq
@@ -136,14 +136,14 @@ define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounw
define <4 x float> @knownbits_mask_shuffle_uitofp(<4 x i32> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_uitofp:
; X32: # %bb.0:
-; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq
@@ -173,16 +173,16 @@ define <4 x float> @knownbits_mask_or_shuffle_uitofp(<4 x i32> %a0) nounwind {
define <4 x float> @knownbits_mask_xor_shuffle_uitofp(<4 x i32> %a0) nounwind {
; X32-LABEL: knownbits_mask_xor_shuffle_uitofp:
; X32: # %bb.0:
-; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vxorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_xor_shuffle_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq
@@ -384,8 +384,8 @@ declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; X32-LABEL: knownbits_mask_concat_uitofp:
; X32: # %bb.0:
-; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
; X32-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3]
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -394,8 +394,8 @@ define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) n
;
; X64-LABEL: knownbits_mask_concat_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
; X64-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3]
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -432,16 +432,16 @@ define <4 x float> @knownbits_lshr_bitcast_shuffle_uitofp(<2 x i64> %a0, <4 x i3
define <4 x float> @knownbits_smax_smin_shuffle_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_smax_smin_shuffle_uitofp:
; X32: # %bb.0:
-; X32-NEXT: vpminsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpmaxsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_smax_smin_shuffle_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq
@@ -457,14 +457,14 @@ declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x float> @knownbits_umin_shuffle_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_umin_shuffle_uitofp:
; X32: # %bb.0:
-; X32-NEXT: vpminud {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_umin_shuffle_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq
@@ -495,16 +495,16 @@ declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x float> @knownbits_mask_umax_shuffle_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_mask_umax_shuffle_uitofp:
; X32: # %bb.0:
-; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpmaxud {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_umax_shuffle_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq
@@ -540,7 +540,7 @@ define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {
; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X32-NEXT: vpsrld $16, %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X32-NEXT: vsubps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0
; X32-NEXT: retl
;
@@ -550,7 +550,7 @@ define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {
; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X64-NEXT: vpsrld $16, %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X64-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0
; X64-NEXT: retq
%1 = sub <4 x i32> zeroinitializer, %a0
@@ -563,7 +563,7 @@ define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {
define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_or_abs_uitofp:
; X32: # %bb.0:
-; X32-NEXT: vpor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
; X32-NEXT: vpabsd %xmm0, %xmm0
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
@@ -571,7 +571,7 @@ define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) {
;
; X64-LABEL: knownbits_or_abs_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
; X64-NEXT: vpabsd %xmm0, %xmm0
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
@@ -593,8 +593,8 @@ define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32>
; X32-NEXT: andl $-16, %esp
; X32-NEXT: subl $16, %esp
; X32-NEXT: vmovaps 8(%ebp), %xmm3
-; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2
-; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
@@ -605,8 +605,8 @@ define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32>
;
; X64-LABEL: knownbits_and_select_shuffle_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %xmm2, %xmm2
-; X64-NEXT: vandps {{.*}}(%rip), %xmm3, %xmm3
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; X64-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
@@ -630,7 +630,7 @@ define <4 x float> @knownbits_lshr_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x
; X32-NEXT: subl $16, %esp
; X32-NEXT: vmovaps 8(%ebp), %xmm3
; X32-NEXT: vpsrld $5, %xmm2, %xmm2
-; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
@@ -642,7 +642,7 @@ define <4 x float> @knownbits_lshr_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x
; X64-LABEL: knownbits_lshr_and_select_shuffle_uitofp:
; X64: # %bb.0:
; X64-NEXT: vpsrld $5, %xmm2, %xmm2
-; X64-NEXT: vandps {{.*}}(%rip), %xmm3, %xmm3
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; X64-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
diff --git a/llvm/test/CodeGen/X86/known-signbits-vector.ll b/llvm/test/CodeGen/X86/known-signbits-vector.ll
index 3f22dbe316e74..6488fe17cbc9f 100644
--- a/llvm/test/CodeGen/X86/known-signbits-vector.ll
+++ b/llvm/test/CodeGen/X86/known-signbits-vector.ll
@@ -96,7 +96,7 @@ define <4 x double> @signbits_ashr_sitofp_0(<4 x i64> %a0) nounwind {
;
; X64-AVX2-LABEL: signbits_ashr_sitofp_0:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1073741824,536870912,268435456,134217728]
; X64-AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
@@ -309,7 +309,7 @@ define <2 x double> @signbits_sext_shl_sitofp(<2 x i16> %a0) nounwind {
; X64-AVX2-LABEL: signbits_sext_shl_sitofp:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpmovsxwq %xmm0, %xmm0
-; X64-AVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-AVX2-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-AVX2-NEXT: retq
@@ -402,7 +402,7 @@ define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4
;
; X64-AVX2-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [4,8]
; X64-AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsubq %xmm2, %xmm0, %xmm0
@@ -515,7 +515,7 @@ define <4 x i32> @signbits_mask_ashr_smax(<4 x i32> %a0, <4 x i32> %a1) {
; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-AVX1-LABEL: signbits_mask_ashr_smax:
@@ -524,7 +524,7 @@ define <4 x i32> @signbits_mask_ashr_smax(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X64-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: signbits_mask_ashr_smax:
@@ -534,7 +534,7 @@ define <4 x i32> @signbits_mask_ashr_smax(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX2-NEXT: vpsravd %xmm2, %xmm1, %xmm1
; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
%2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
@@ -553,7 +553,7 @@ define <4 x i32> @signbits_mask_ashr_smin(<4 x i32> %a0, <4 x i32> %a1) {
; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-AVX1-LABEL: signbits_mask_ashr_smin:
@@ -562,7 +562,7 @@ define <4 x i32> @signbits_mask_ashr_smin(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X64-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: signbits_mask_ashr_smin:
@@ -572,7 +572,7 @@ define <4 x i32> @signbits_mask_ashr_smin(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX2-NEXT: vpsravd %xmm2, %xmm1, %xmm1
; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
%2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
@@ -591,7 +591,7 @@ define <4 x i32> @signbits_mask_ashr_umax(<4 x i32> %a0, <4 x i32> %a1) {
; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-AVX1-LABEL: signbits_mask_ashr_umax:
@@ -600,7 +600,7 @@ define <4 x i32> @signbits_mask_ashr_umax(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X64-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: signbits_mask_ashr_umax:
@@ -610,7 +610,7 @@ define <4 x i32> @signbits_mask_ashr_umax(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX2-NEXT: vpsravd %xmm2, %xmm1, %xmm1
; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
%2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
@@ -629,7 +629,7 @@ define <4 x i32> @signbits_mask_ashr_umin(<4 x i32> %a0, <4 x i32> %a1) {
; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpminud %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-AVX1-LABEL: signbits_mask_ashr_umin:
@@ -638,7 +638,7 @@ define <4 x i32> @signbits_mask_ashr_umin(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X64-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: signbits_mask_ashr_umin:
@@ -648,7 +648,7 @@ define <4 x i32> @signbits_mask_ashr_umin(<4 x i32> %a0, <4 x i32> %a1) {
; X64-AVX2-NEXT: vpsravd %xmm2, %xmm1, %xmm1
; X64-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
%2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
@@ -674,7 +674,7 @@ define void @cross_bb_signbits_insert_subvec(<32 x i8>* %ptr, <32 x i8> %x, <32
; X86-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
; X86-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X86-NEXT: vandnps %ymm1, %ymm0, %ymm1
-; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: vorps %ymm1, %ymm0, %ymm0
; X86-NEXT: vmovaps %ymm0, (%eax)
; X86-NEXT: vzeroupper
@@ -688,7 +688,7 @@ define void @cross_bb_signbits_insert_subvec(<32 x i8>* %ptr, <32 x i8> %x, <32
; X64-AVX1-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
; X64-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X64-AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm1
-; X64-AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, (%rdi)
; X64-AVX1-NEXT: vzeroupper
@@ -698,7 +698,7 @@ define void @cross_bb_signbits_insert_subvec(<32 x i8>* %ptr, <32 x i8> %x, <32
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X64-AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0
-; X64-AVX2-NEXT: vpblendvb %ymm0, {{.*}}(%rip), %ymm1, %ymm0
+; X64-AVX2-NEXT: vpblendvb %ymm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; X64-AVX2-NEXT: vmovdqa %ymm0, (%rdi)
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/large-pic-string.ll b/llvm/test/CodeGen/X86/large-pic-string.ll
index e677ed85c6632..009e1618ac13b 100644
--- a/llvm/test/CodeGen/X86/large-pic-string.ll
+++ b/llvm/test/CodeGen/X86/large-pic-string.ll
@@ -8,7 +8,7 @@ define void @pr38385() {
; CHECK-LABEL: pr38385:
; CHECK: # %bb.0:
; CHECK-NEXT: .L0$pb:
-; CHECK-NEXT: leaq .L0${{.*}}(%rip), %rax
+; CHECK-NEXT: leaq .L0$pb(%rip), %rax
; CHECK-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L0$pb, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: movabsq $.L.str at GOTOFF, %rax
diff --git a/llvm/test/CodeGen/X86/lea-recursion.ll b/llvm/test/CodeGen/X86/lea-recursion.ll
index bdd7b73e2d003..99c628c437bbb 100644
--- a/llvm/test/CodeGen/X86/lea-recursion.ll
+++ b/llvm/test/CodeGen/X86/lea-recursion.ll
@@ -15,34 +15,34 @@
define dso_local void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
-; CHECK-NEXT: movl {{.*}}(%rip), %ecx
+; CHECK-NEXT: movl g0(%rip), %eax
+; CHECK-NEXT: movl g1(%rip), %ecx
; CHECK-NEXT: leal (%rax,%rcx), %edx
; CHECK-NEXT: leal 1(%rax,%rcx), %eax
-; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
-; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT: movl %eax, g0+4(%rip)
+; CHECK-NEXT: movl g1+4(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rdx), %ecx
; CHECK-NEXT: leal 2(%rax,%rdx), %eax
-; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
-; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT: movl %eax, g0+8(%rip)
+; CHECK-NEXT: movl g1+8(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rcx), %edx
; CHECK-NEXT: leal 2(%rax,%rcx), %eax
-; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
-; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT: movl %eax, g0+12(%rip)
+; CHECK-NEXT: movl g1+12(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rdx), %ecx
; CHECK-NEXT: leal 2(%rax,%rdx), %eax
-; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
-; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT: movl %eax, g0+16(%rip)
+; CHECK-NEXT: movl g1+16(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rcx), %edx
; CHECK-NEXT: leal 2(%rax,%rcx), %eax
-; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
-; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT: movl %eax, g0+20(%rip)
+; CHECK-NEXT: movl g1+20(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rdx), %ecx
; CHECK-NEXT: leal 2(%rax,%rdx), %eax
-; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
-; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT: movl %eax, g0+24(%rip)
+; CHECK-NEXT: movl g1+24(%rip), %eax
; CHECK-NEXT: leal 2(%rax,%rcx), %eax
-; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT: movl %eax, g0+28(%rip)
; CHECK-NEXT: retq
entry:
%tmp4 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 0) ; <i32> [#uses=1]
diff --git a/llvm/test/CodeGen/X86/lifetime-alias.ll b/llvm/test/CodeGen/X86/lifetime-alias.ll
index 010dc33b5051c..e0b9e225ed5e1 100644
--- a/llvm/test/CodeGen/X86/lifetime-alias.ll
+++ b/llvm/test/CodeGen/X86/lifetime-alias.ll
@@ -46,7 +46,7 @@ define i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__g
; CHECK-NEXT: movb $21, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movabsq $7308613581744070988, %rax # imm = 0x656D69547473614C
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movups {{.*}}(%rip), %xmm1
+; CHECK-NEXT: movups .L.str.1(%rip), %xmm1
; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
@@ -70,9 +70,9 @@ define i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__g
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: movq %rax, do_not_optimize{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, do_not_optimize(%rip)
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: movq %rax, do_not_optimize{{.*}}(%rip)
+; CHECK-NEXT: movq %rax, do_not_optimize(%rip)
; CHECK-NEXT: cmpb $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: jns .LBB0_1
; CHECK-NEXT: # %bb.2: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50
diff --git a/llvm/test/CodeGen/X86/limited-prec.ll b/llvm/test/CodeGen/X86/limited-prec.ll
index 68ba8e21bb530..b2b722841eff3 100644
--- a/llvm/test/CodeGen/X86/limited-prec.ll
+++ b/llvm/test/CodeGen/X86/limited-prec.ll
@@ -8,7 +8,7 @@ define float @f1(float %x) nounwind noinline {
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $20, %esp
; precision6-NEXT: flds {{[0-9]+}}(%esp)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fnstcw (%esp)
; precision6-NEXT: movzwl (%esp), %eax
; precision6-NEXT: orl $3072, %eax # imm = 0xC00
@@ -20,10 +20,10 @@ define float @f1(float %x) nounwind noinline {
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1)
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
@@ -36,7 +36,7 @@ define float @f1(float %x) nounwind noinline {
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00
@@ -48,12 +48,12 @@ define float @f1(float %x) nounwind noinline {
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1)
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
@@ -66,7 +66,7 @@ define float @f1(float %x) nounwind noinline {
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00
@@ -78,16 +78,16 @@ define float @f1(float %x) nounwind noinline {
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1)
@@ -122,10 +122,10 @@ define float @f2(float %x) nounwind noinline {
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1)
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
@@ -149,12 +149,12 @@ define float @f2(float %x) nounwind noinline {
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1)
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
@@ -178,16 +178,16 @@ define float @f2(float %x) nounwind noinline {
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1)
@@ -211,7 +211,7 @@ define float @f3(float %x) nounwind noinline {
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $20, %esp
; precision6-NEXT: flds {{[0-9]+}}(%esp)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fnstcw (%esp)
; precision6-NEXT: movzwl (%esp), %eax
; precision6-NEXT: orl $3072, %eax # imm = 0xC00
@@ -223,10 +223,10 @@ define float @f3(float %x) nounwind noinline {
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1)
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
@@ -239,7 +239,7 @@ define float @f3(float %x) nounwind noinline {
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00
@@ -251,12 +251,12 @@ define float @f3(float %x) nounwind noinline {
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1)
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
@@ -269,7 +269,7 @@ define float @f3(float %x) nounwind noinline {
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00
@@ -281,16 +281,16 @@ define float @f3(float %x) nounwind noinline {
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1)
@@ -324,12 +324,12 @@ define float @f4(float %x) nounwind noinline {
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1)
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fildl {{[0-9]+}}(%esp)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: faddp %st, %st(1)
; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl
@@ -348,16 +348,16 @@ define float @f4(float %x) nounwind noinline {
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1)
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fildl {{[0-9]+}}(%esp)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: faddp %st, %st(1)
; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl
@@ -376,20 +376,20 @@ define float @f4(float %x) nounwind noinline {
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1)
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fildl {{[0-9]+}}(%esp)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl
@@ -416,10 +416,10 @@ define float @f5(float %x) nounwind noinline {
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1)
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl
@@ -438,14 +438,14 @@ define float @f5(float %x) nounwind noinline {
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1)
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl
@@ -464,18 +464,18 @@ define float @f5(float %x) nounwind noinline {
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1)
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl
@@ -502,12 +502,12 @@ define float @f6(float %x) nounwind noinline {
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1)
-; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fildl {{[0-9]+}}(%esp)
-; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: faddp %st, %st(1)
; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl
@@ -526,14 +526,14 @@ define float @f6(float %x) nounwind noinline {
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1)
-; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fildl {{[0-9]+}}(%esp)
-; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: faddp %st, %st(1)
; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl
@@ -552,18 +552,18 @@ define float @f6(float %x) nounwind noinline {
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1)
-; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fildl {{[0-9]+}}(%esp)
-; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/live-out-reg-info.ll b/llvm/test/CodeGen/X86/live-out-reg-info.ll
index 461cc1dc6fdb3..f56397e88fd34 100644
--- a/llvm/test/CodeGen/X86/live-out-reg-info.ll
+++ b/llvm/test/CodeGen/X86/live-out-reg-info.ll
@@ -15,7 +15,7 @@ define void @foo(i32 %a) {
; CHECK-NEXT: # %bb.1: # %true
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB0_2: # %false
diff --git a/llvm/test/CodeGen/X86/load-chain.ll b/llvm/test/CodeGen/X86/load-chain.ll
index cb75cfb603977..f47a79cd5ea7e 100644
--- a/llvm/test/CodeGen/X86/load-chain.ll
+++ b/llvm/test/CodeGen/X86/load-chain.ll
@@ -13,7 +13,7 @@ define void @translate(i16* %ptr) nounwind {
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $-32707, %ebp # imm = 0x803D
; CHECK-NEXT: andl (%rdi), %ebp
-; CHECK-NEXT: callq maybe_mutate
+; CHECK-NEXT: callq maybe_mutate at PLT
; CHECK-NEXT: orl $514, %ebp # imm = 0x202
; CHECK-NEXT: movw %bp, (%rbx)
; CHECK-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/load-local-v3i1.ll b/llvm/test/CodeGen/X86/load-local-v3i1.ll
index f471c637a5923..316ba03910d68 100644
--- a/llvm/test/CodeGen/X86/load-local-v3i1.ll
+++ b/llvm/test/CodeGen/X86/load-local-v3i1.ll
@@ -110,12 +110,12 @@ define void @local_load_v3i1(i32 addrspace(1)* %out, i32 addrspace(1)* %in, <3 x
; CHECK-NEXT: movl %ebp, %esi
; CHECK-NEXT: movl %ebx, %edx
; CHECK-NEXT: movl %r15d, %ecx
-; CHECK-NEXT: callq masked_load_v3
+; CHECK-NEXT: callq masked_load_v3 at PLT
; CHECK-NEXT: movq %r14, %rdi
; CHECK-NEXT: movl %ebp, %esi
; CHECK-NEXT: movl %ebx, %edx
; CHECK-NEXT: movl %r15d, %ecx
-; CHECK-NEXT: callq masked_store4_v3
+; CHECK-NEXT: callq masked_store4_v3 at PLT
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
diff --git a/llvm/test/CodeGen/X86/load-local-v4i5.ll b/llvm/test/CodeGen/X86/load-local-v4i5.ll
index cb382a59436e7..4ee08665456e8 100644
--- a/llvm/test/CodeGen/X86/load-local-v4i5.ll
+++ b/llvm/test/CodeGen/X86/load-local-v4i5.ll
@@ -6,7 +6,7 @@
define void @_start() {
; CHECK-LABEL: _start:
; CHECK: # %bb.0: # %Entry
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl __unnamed_1(%rip), %eax
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb -{{[0-9]+}}(%rsp), %cl
; CHECK-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
diff --git a/llvm/test/CodeGen/X86/load-partial.ll b/llvm/test/CodeGen/X86/load-partial.ll
index 9e999bb073ee4..27030aed8a47d 100644
--- a/llvm/test/CodeGen/X86/load-partial.ll
+++ b/llvm/test/CodeGen/X86/load-partial.ll
@@ -305,25 +305,25 @@ define <4 x double> @load_double4_0u2u(double* nocapture readonly dereferenceabl
define dso_local i32 @load_partial_illegal_type() {
; SSE2-LABEL: load_partial_illegal_type:
; SSE2: # %bb.0:
-; SSE2-NEXT: movzwl {{.*}}(%rip), %eax
+; SSE2-NEXT: movzwl h(%rip), %eax
; SSE2-NEXT: movd %eax, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: retq
;
; SSSE3-LABEL: load_partial_illegal_type:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: movzwl {{.*}}(%rip), %eax
+; SSSE3-NEXT: movzwl h(%rip), %eax
; SSSE3-NEXT: movd %eax, %xmm0
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,xmm0[3,u,u,u,u,u,u,u,u,u,u,u,u]
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movd %xmm0, %eax
; SSSE3-NEXT: retq
;
; SSE41-LABEL: load_partial_illegal_type:
; SSE41: # %bb.0:
-; SSE41-NEXT: movzwl {{.*}}(%rip), %eax
+; SSE41-NEXT: movzwl h(%rip), %eax
; SSE41-NEXT: movd %eax, %xmm0
; SSE41-NEXT: movl $2, %eax
; SSE41-NEXT: pinsrb $2, %eax, %xmm0
@@ -332,7 +332,7 @@ define dso_local i32 @load_partial_illegal_type() {
;
; AVX-LABEL: load_partial_illegal_type:
; AVX: # %bb.0:
-; AVX-NEXT: movzwl {{.*}}(%rip), %eax
+; AVX-NEXT: movzwl h(%rip), %eax
; AVX-NEXT: vmovd %eax, %xmm0
; AVX-NEXT: movl $2, %eax
; AVX-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/load-scalar-as-vector.ll b/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
index ad6a21823b850..17142ee3940bf 100644
--- a/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
+++ b/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
@@ -555,13 +555,13 @@ define <4 x float> @fadd_op1_constant(float* %p) nounwind {
; SSE-LABEL: fadd_op1_constant:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-NEXT: addss {{.*}}(%rip), %xmm0
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fadd_op1_constant:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load float, float* %p
%b = fadd float %x, 42.0
@@ -573,13 +573,13 @@ define <2 x double> @fsub_op1_constant(double* %p) nounwind {
; SSE-LABEL: fsub_op1_constant:
; SSE: # %bb.0:
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fsub_op1_constant:
; AVX: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load double, double* %p
%b = fsub double %x, 42.0
@@ -609,13 +609,13 @@ define <4 x float> @fmul_op1_constant(float* %p) nounwind {
; SSE-LABEL: fmul_op1_constant:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fmul_op1_constant:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load float, float* %p
%b = fmul float %x, 42.0
@@ -627,13 +627,13 @@ define <2 x double> @fdiv_op1_constant(double* %p) nounwind {
; SSE-LABEL: fdiv_op1_constant:
; SSE: # %bb.0:
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: divsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fdiv_op1_constant:
; AVX: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vdivsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load double, double* %p
%b = fdiv double %x, 42.0
@@ -665,7 +665,7 @@ define <4 x float> @frem_op1_constant(float* %p) nounwind {
; SSE-NEXT: pushq %rax
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE-NEXT: callq fmodf
+; SSE-NEXT: callq fmodf at PLT
; SSE-NEXT: popq %rax
; SSE-NEXT: retq
;
@@ -674,7 +674,7 @@ define <4 x float> @frem_op1_constant(float* %p) nounwind {
; AVX-NEXT: pushq %rax
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX-NEXT: callq fmodf
+; AVX-NEXT: callq fmodf at PLT
; AVX-NEXT: popq %rax
; AVX-NEXT: retq
%x = load float, float* %p
@@ -689,7 +689,7 @@ define <2 x double> @frem_op0_constant(double* %p) nounwind {
; SSE-NEXT: pushq %rax
; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: callq fmod
+; SSE-NEXT: callq fmod at PLT
; SSE-NEXT: popq %rax
; SSE-NEXT: retq
;
@@ -698,7 +698,7 @@ define <2 x double> @frem_op0_constant(double* %p) nounwind {
; AVX-NEXT: pushq %rax
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: callq fmod
+; AVX-NEXT: callq fmod at PLT
; AVX-NEXT: popq %rax
; AVX-NEXT: retq
%x = load double, double* %p
diff --git a/llvm/test/CodeGen/X86/lower-bitcast.ll b/llvm/test/CodeGen/X86/lower-bitcast.ll
index d41d2ea83bc26..7aebf591a2743 100644
--- a/llvm/test/CodeGen/X86/lower-bitcast.ll
+++ b/llvm/test/CodeGen/X86/lower-bitcast.ll
@@ -8,7 +8,7 @@
define double @test1(double %A) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%1 = bitcast double %A to <2 x i32>
%add = add <2 x i32> %1, <i32 3, i32 5>
@@ -32,7 +32,7 @@ define i64 @test3(i64 %A) {
; CHECK-LABEL: test3:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %xmm0
-; CHECK-NEXT: addps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movq %xmm0, %rax
; CHECK-NEXT: retq
%1 = bitcast i64 %A to <2 x float>
@@ -48,7 +48,7 @@ define i64 @test4(i64 %A) {
; CHECK-LABEL: test4:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movq %xmm0, %rax
; CHECK-NEXT: retq
%1 = bitcast i64 %A to <2 x i32>
@@ -60,7 +60,7 @@ define i64 @test4(i64 %A) {
define double @test5(double %A) {
; CHECK-LABEL: test5:
; CHECK: # %bb.0:
-; CHECK-NEXT: addps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%1 = bitcast double %A to <2 x float>
%add = fadd <2 x float> %1, <float 3.0, float 5.0>
@@ -74,7 +74,7 @@ define double @test5(double %A) {
define double @test6(double %A) {
; CHECK-LABEL: test6:
; CHECK: # %bb.0:
-; CHECK-NEXT: paddw {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%1 = bitcast double %A to <4 x i16>
%add = add <4 x i16> %1, <i16 3, i16 4, i16 5, i16 6>
@@ -101,7 +101,7 @@ define double @test7(double %A, double %B) {
define double @test8(double %A) {
; CHECK-LABEL: test8:
; CHECK: # %bb.0:
-; CHECK-NEXT: paddb {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%1 = bitcast double %A to <8 x i8>
%add = add <8 x i8> %1, <i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10>
diff --git a/llvm/test/CodeGen/X86/lower-vec-shift.ll b/llvm/test/CodeGen/X86/lower-vec-shift.ll
index 9bfba2c3c124c..724846f4a3c5e 100644
--- a/llvm/test/CodeGen/X86/lower-vec-shift.ll
+++ b/llvm/test/CodeGen/X86/lower-vec-shift.ll
@@ -78,7 +78,7 @@ define <4 x i32> @test3(<4 x i32> %a) {
;
; AVX2-LABEL: test3:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
%lshr = lshr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
ret <4 x i32> %lshr
@@ -102,7 +102,7 @@ define <4 x i32> @test4(<4 x i32> %a) {
;
; AVX2-LABEL: test4:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
%lshr = lshr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
ret <4 x i32> %lshr
@@ -178,7 +178,7 @@ define <4 x i32> @test7(<4 x i32> %a) {
;
; AVX2-LABEL: test7:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
%lshr = ashr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
ret <4 x i32> %lshr
@@ -202,7 +202,7 @@ define <4 x i32> @test8(<4 x i32> %a) {
;
; AVX2-LABEL: test8:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
%lshr = ashr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
ret <4 x i32> %lshr
@@ -258,8 +258,8 @@ define <8 x i32> @test10(<8 x i32>* %a) {
define <16 x i16> @test11(<16 x i16> %a) {
; SSE-LABEL: test11:
; SSE: # %bb.0:
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: test11:
@@ -276,7 +276,7 @@ define <16 x i16> @test11(<16 x i16> %a) {
;
; AVX2-LABEL: test11:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
%lshr = shl <16 x i16> %a, <i16 1, i16 3, i16 1, i16 1, i16 1, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 1, i16 1, i16 1, i16 3, i16 1>
ret <16 x i16> %lshr
diff --git a/llvm/test/CodeGen/X86/lrshrink.ll b/llvm/test/CodeGen/X86/lrshrink.ll
index f1997eb70332a..ea1f96b18f1b9 100644
--- a/llvm/test/CodeGen/X86/lrshrink.ll
+++ b/llvm/test/CodeGen/X86/lrshrink.ll
@@ -28,13 +28,13 @@ define i64 @test(i1 %a, i64 %r1, i64 %r2, i64 %s1, i64 %s2, i64 %t1, i64 %t2) {
; CHECK-NEXT: .LBB0_2: # %else
; CHECK-NEXT: addq %r9, %r14
; CHECK-NEXT: addq %rsi, %r15
-; CHECK-NEXT: callq _Z3foov
+; CHECK-NEXT: callq _Z3foov at PLT
; CHECK-NEXT: movl %eax, %ebx
; CHECK-NEXT: addq %r15, %rbx
-; CHECK-NEXT: callq _Z3foov
+; CHECK-NEXT: callq _Z3foov at PLT
; CHECK-NEXT: movl %eax, %r15d
; CHECK-NEXT: addq %rbx, %r15
-; CHECK-NEXT: callq _Z3foov
+; CHECK-NEXT: callq _Z3foov at PLT
; CHECK-NEXT: movl %eax, %eax
; CHECK-NEXT: addq %r15, %rax
; CHECK-NEXT: addq %r14, %rax
diff --git a/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll b/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
index cb37086459dd5..3c35cb0138416 100644
--- a/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
+++ b/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
@@ -17,9 +17,9 @@ define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r
; GENERIC-NEXT: movl 4(%rdx), %ebx
; GENERIC-NEXT: decl %ecx
; GENERIC-NEXT: leaq 20(%rdx), %r11
-; GENERIC-NEXT: movq _Te0@{{.*}}(%rip), %r9
-; GENERIC-NEXT: movq _Te1@{{.*}}(%rip), %r8
-; GENERIC-NEXT: movq _Te3@{{.*}}(%rip), %r10
+; GENERIC-NEXT: movq _Te0 at GOTPCREL(%rip), %r9
+; GENERIC-NEXT: movq _Te1 at GOTPCREL(%rip), %r8
+; GENERIC-NEXT: movq _Te3 at GOTPCREL(%rip), %r10
; GENERIC-NEXT: movq %rcx, %r14
; GENERIC-NEXT: .p2align 4, 0x90
; GENERIC-NEXT: LBB0_1: ## %bb
@@ -99,9 +99,9 @@ define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r
; ATOM-NEXT: movl (%rdx), %r15d
; ATOM-NEXT: movl 4(%rdx), %eax
; ATOM-NEXT: leaq 20(%rdx), %r11
-; ATOM-NEXT: movq _Te0@{{.*}}(%rip), %r9
-; ATOM-NEXT: movq _Te1@{{.*}}(%rip), %r8
-; ATOM-NEXT: movq _Te3@{{.*}}(%rip), %r10
+; ATOM-NEXT: movq _Te0 at GOTPCREL(%rip), %r9
+; ATOM-NEXT: movq _Te1 at GOTPCREL(%rip), %r8
+; ATOM-NEXT: movq _Te3 at GOTPCREL(%rip), %r10
; ATOM-NEXT: decl %ecx
; ATOM-NEXT: movq %rcx, %r14
; ATOM-NEXT: .p2align 4, 0x90
diff --git a/llvm/test/CodeGen/X86/lsr-sort.ll b/llvm/test/CodeGen/X86/lsr-sort.ll
index 1a809525706ec..ca98408f144da 100644
--- a/llvm/test/CodeGen/X86/lsr-sort.ll
+++ b/llvm/test/CodeGen/X86/lsr-sort.ll
@@ -12,7 +12,7 @@ define dso_local i32 @foo(i32 %N) nounwind {
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movw %ax, {{.*}}(%rip)
+; CHECK-NEXT: movw %ax, X(%rip)
; CHECK-NEXT: incl %eax
; CHECK-NEXT: cmpl %eax, %edi
; CHECK-NEXT: jne .LBB0_1
diff --git a/llvm/test/CodeGen/X86/machine-combiner.ll b/llvm/test/CodeGen/X86/machine-combiner.ll
index cab9c86d7d0b3..ece61ed3ffa0f 100644
--- a/llvm/test/CodeGen/X86/machine-combiner.ll
+++ b/llvm/test/CodeGen/X86/machine-combiner.ll
@@ -1074,13 +1074,13 @@ define double @reassociate_adds_from_calls() {
; SSE: # %bb.0:
; SSE-NEXT: subq $24, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 32
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; SSE-NEXT: # xmm1 = mem[0],zero
; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
@@ -1094,13 +1094,13 @@ define double @reassociate_adds_from_calls() {
; AVX: # %bb.0:
; AVX-NEXT: subq $24, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 32
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; AVX-NEXT: # xmm1 = mem[0],zero
; AVX-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload
@@ -1125,13 +1125,13 @@ define double @already_reassociated() {
; SSE: # %bb.0:
; SSE-NEXT: subq $24, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 32
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
-; SSE-NEXT: callq bar
+; SSE-NEXT: callq bar at PLT
; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; SSE-NEXT: # xmm1 = mem[0],zero
; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
@@ -1145,13 +1145,13 @@ define double @already_reassociated() {
; AVX: # %bb.0:
; AVX-NEXT: subq $24, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 32
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
-; AVX-NEXT: callq bar
+; AVX-NEXT: callq bar at PLT
; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; AVX-NEXT: # xmm1 = mem[0],zero
; AVX-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/X86/machine-cp.ll b/llvm/test/CodeGen/X86/machine-cp.ll
index 935c7e9cb939c..c868524a1bb3f 100644
--- a/llvm/test/CodeGen/X86/machine-cp.ll
+++ b/llvm/test/CodeGen/X86/machine-cp.ll
@@ -106,7 +106,7 @@ define <16 x float> @foo(<16 x float> %x) {
; CHECK-NEXT: movaps %xmm3, %xmm2
; CHECK-NEXT: cmpltps %xmm0, %xmm2
; CHECK-NEXT: movaps %xmm2, %xmm4
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm4
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; CHECK-NEXT: movaps %xmm4, %xmm10
; CHECK-NEXT: andnps %xmm2, %xmm10
; CHECK-NEXT: movaps %xmm8, %xmm5
@@ -148,7 +148,7 @@ define <16 x float> @foo(<16 x float> %x) {
; CHECK-NEXT: andps %xmm3, %xmm14
; CHECK-NEXT: orps %xmm14, %xmm2
; CHECK-NEXT: andps %xmm3, %xmm10
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm4
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; CHECK-NEXT: cvttps2dq %xmm9, %xmm1
; CHECK-NEXT: cvtdq2ps %xmm1, %xmm1
; CHECK-NEXT: andps %xmm1, %xmm4
diff --git a/llvm/test/CodeGen/X86/machine-cse.ll b/llvm/test/CodeGen/X86/machine-cse.ll
index 124928bd75228..e989a782fad7b 100644
--- a/llvm/test/CodeGen/X86/machine-cse.ll
+++ b/llvm/test/CodeGen/X86/machine-cse.ll
@@ -18,9 +18,9 @@ define fastcc i8* @t(i32 %base) nounwind {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: .LBB0_2: # %bb2
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
entry:
%0 = zext i32 %base to i64
%1 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0
@@ -65,7 +65,7 @@ define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
; CHECK-NEXT: leal (%rsi,%rsi,2), %esi
; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq printf
+; CHECK-NEXT: callq printf at PLT
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_3: # %for.body53.us
@@ -186,12 +186,12 @@ define i32 @t2() nounwind {
; CHECK-LABEL: t2:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: movl $42, {{.*}}(%rip)
-; CHECK-NEXT: callq t2_func
+; CHECK-NEXT: movl $42, t2_global(%rip)
+; CHECK-NEXT: callq t2_func at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB4_2
; CHECK-NEXT: # %bb.1: # %a
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl t2_global(%rip), %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB4_2: # %b
diff --git a/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll b/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
index 07b607fdaf609..834f49022ff38 100644
--- a/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
+++ b/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
@@ -25,7 +25,7 @@ define void @PR24199(i32 %a0) {
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: .LBB0_3: # %if.end
; CHECK-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Reload
; CHECK-NEXT: # xmm2 = mem[0],zero,zero,zero
@@ -42,7 +42,7 @@ define void @PR24199(i32 %a0) {
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: addss %xmm0, %xmm0
; CHECK-NEXT: addss %xmm1, %xmm0
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %rbx
diff --git a/llvm/test/CodeGen/X86/madd.ll b/llvm/test/CodeGen/X86/madd.ll
index 96ced9f1d2a78..8e58497fa8093 100644
--- a/llvm/test/CodeGen/X86/madd.ll
+++ b/llvm/test/CodeGen/X86/madd.ll
@@ -1987,12 +1987,12 @@ define <16 x i32> @pmaddwd_32(<32 x i16> %A, <32 x i16> %B) {
define <4 x i32> @pmaddwd_const(<8 x i16> %A) {
; SSE2-LABEL: pmaddwd_const:
; SSE2: # %bb.0:
-; SSE2-NEXT: pmaddwd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; AVX-LABEL: pmaddwd_const:
; AVX: # %bb.0:
-; AVX-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%a = sext <8 x i16> %A to <8 x i32>
%m = mul nsw <8 x i32> %a, <i32 32767, i32 -32768, i32 0, i32 0, i32 1, i32 7, i32 42, i32 32>
@@ -2077,15 +2077,15 @@ define <4 x i32> @pmaddwd_negative2(<8 x i16> %A) {
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX1-NEXT: vpmovsxwd %xmm1, %xmm1
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX256-LABEL: pmaddwd_negative2:
; AVX256: # %bb.0:
; AVX256-NEXT: vpmovsxwd %xmm0, %ymm0
-; AVX256-NEXT: vpmulld {{.*}}(%rip), %ymm0, %ymm0
+; AVX256-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX256-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX256-NEXT: vphaddd %xmm1, %xmm0, %xmm0
; AVX256-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/mask-negated-bool.ll b/llvm/test/CodeGen/X86/mask-negated-bool.ll
index 5a3c3be8d8443..d1857c975c745 100644
--- a/llvm/test/CodeGen/X86/mask-negated-bool.ll
+++ b/llvm/test/CodeGen/X86/mask-negated-bool.ll
@@ -27,7 +27,7 @@ define i32 @mask_negated_zext_bool2(i1 zeroext %x) {
define <4 x i32> @mask_negated_zext_bool_vec(<4 x i1> %x) {
; CHECK-LABEL: mask_negated_zext_bool_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%ext = zext <4 x i1> %x to <4 x i32>
%neg = sub <4 x i32> zeroinitializer, %ext
@@ -61,7 +61,7 @@ define i32 @mask_negated_sext_bool2(i1 zeroext %x) {
define <4 x i32> @mask_negated_sext_bool_vec(<4 x i1> %x) {
; CHECK-LABEL: mask_negated_sext_bool_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%ext = sext <4 x i1> %x to <4 x i32>
%neg = sub <4 x i32> zeroinitializer, %ext
diff --git a/llvm/test/CodeGen/X86/masked_expandload.ll b/llvm/test/CodeGen/X86/masked_expandload.ll
index ccae7e18f3617..dc6362d499a1d 100644
--- a/llvm/test/CodeGen/X86/masked_expandload.ll
+++ b/llvm/test/CodeGen/X86/masked_expandload.ll
@@ -3510,7 +3510,7 @@ define <16 x i8> @expandload_v16i8_v16i8(i8* %base, <16 x i8> %src0, <16 x i8> %
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: je LBB12_32
; SSE2-NEXT: LBB12_31: ## %cond.load57
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movzbl (%rdi), %eax
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0]
diff --git a/llvm/test/CodeGen/X86/masked_gather.ll b/llvm/test/CodeGen/X86/masked_gather.ll
index 3bb06d7c731f3..b8ef01f7f479e 100644
--- a/llvm/test/CodeGen/X86/masked_gather.ll
+++ b/llvm/test/CodeGen/X86/masked_gather.ll
@@ -1043,7 +1043,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $2, %al
; SSE-NEXT: je .LBB4_5
; SSE-NEXT: .LBB4_4: # %cond.load1
-; SSE-NEXT: pinsrd $1, c+{{.*}}(%rip), %xmm0
+; SSE-NEXT: pinsrd $1, c+12(%rip), %xmm0
; SSE-NEXT: .LBB4_5: # %else2
; SSE-NEXT: testb $4, %al
; SSE-NEXT: jne .LBB4_6
@@ -1054,16 +1054,16 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $16, %al
; SSE-NEXT: je .LBB4_10
; SSE-NEXT: .LBB4_11: # %cond.load10
-; SSE-NEXT: pinsrd $0, c+{{.*}}(%rip), %xmm1
+; SSE-NEXT: pinsrd $0, c+12(%rip), %xmm1
; SSE-NEXT: testb $32, %al
; SSE-NEXT: jne .LBB4_13
; SSE-NEXT: jmp .LBB4_14
; SSE-NEXT: .LBB4_6: # %cond.load4
-; SSE-NEXT: pinsrd $2, c+{{.*}}(%rip), %xmm0
+; SSE-NEXT: pinsrd $2, c+12(%rip), %xmm0
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je .LBB4_9
; SSE-NEXT: .LBB4_8: # %cond.load7
-; SSE-NEXT: pinsrd $3, c+{{.*}}(%rip), %xmm0
+; SSE-NEXT: pinsrd $3, c+12(%rip), %xmm0
; SSE-NEXT: testb $16, %al
; SSE-NEXT: jne .LBB4_11
; SSE-NEXT: .LBB4_10:
@@ -1071,7 +1071,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $32, %al
; SSE-NEXT: je .LBB4_14
; SSE-NEXT: .LBB4_13: # %cond.load13
-; SSE-NEXT: pinsrd $1, c+{{.*}}(%rip), %xmm1
+; SSE-NEXT: pinsrd $1, c+12(%rip), %xmm1
; SSE-NEXT: .LBB4_14: # %else14
; SSE-NEXT: testb $64, %al
; SSE-NEXT: jne .LBB4_15
@@ -1079,7 +1079,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: je .LBB4_18
; SSE-NEXT: .LBB4_17: # %cond.load19
-; SSE-NEXT: pinsrd $3, c+{{.*}}(%rip), %xmm1
+; SSE-NEXT: pinsrd $3, c+12(%rip), %xmm1
; SSE-NEXT: .LBB4_18: # %else20
; SSE-NEXT: pxor %xmm4, %xmm4
; SSE-NEXT: movdqa %xmm2, %xmm5
@@ -1096,7 +1096,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: jne .LBB4_22
; SSE-NEXT: jmp .LBB4_23
; SSE-NEXT: .LBB4_15: # %cond.load16
-; SSE-NEXT: pinsrd $2, c+{{.*}}(%rip), %xmm1
+; SSE-NEXT: pinsrd $2, c+12(%rip), %xmm1
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: jne .LBB4_17
; SSE-NEXT: jmp .LBB4_18
@@ -1105,7 +1105,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $2, %al
; SSE-NEXT: je .LBB4_23
; SSE-NEXT: .LBB4_22: # %cond.load28
-; SSE-NEXT: pinsrd $1, c+{{.*}}(%rip), %xmm4
+; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm4
; SSE-NEXT: .LBB4_23: # %else31
; SSE-NEXT: testb $4, %al
; SSE-NEXT: jne .LBB4_24
@@ -1116,16 +1116,16 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $16, %al
; SSE-NEXT: je .LBB4_28
; SSE-NEXT: .LBB4_29: # %cond.load43
-; SSE-NEXT: pinsrd $0, c+{{.*}}(%rip), %xmm5
+; SSE-NEXT: pinsrd $0, c+28(%rip), %xmm5
; SSE-NEXT: testb $32, %al
; SSE-NEXT: jne .LBB4_31
; SSE-NEXT: jmp .LBB4_32
; SSE-NEXT: .LBB4_24: # %cond.load33
-; SSE-NEXT: pinsrd $2, c+{{.*}}(%rip), %xmm4
+; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm4
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je .LBB4_27
; SSE-NEXT: .LBB4_26: # %cond.load38
-; SSE-NEXT: pinsrd $3, c+{{.*}}(%rip), %xmm4
+; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm4
; SSE-NEXT: testb $16, %al
; SSE-NEXT: jne .LBB4_29
; SSE-NEXT: .LBB4_28:
@@ -1133,7 +1133,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $32, %al
; SSE-NEXT: je .LBB4_32
; SSE-NEXT: .LBB4_31: # %cond.load48
-; SSE-NEXT: pinsrd $1, c+{{.*}}(%rip), %xmm5
+; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm5
; SSE-NEXT: .LBB4_32: # %else51
; SSE-NEXT: testb $64, %al
; SSE-NEXT: jne .LBB4_33
@@ -1141,7 +1141,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: je .LBB4_36
; SSE-NEXT: .LBB4_35: # %cond.load58
-; SSE-NEXT: pinsrd $3, c+{{.*}}(%rip), %xmm5
+; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm5
; SSE-NEXT: .LBB4_36: # %else61
; SSE-NEXT: pxor %xmm6, %xmm6
; SSE-NEXT: pcmpeqd %xmm6, %xmm2
@@ -1157,7 +1157,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: jne .LBB4_40
; SSE-NEXT: jmp .LBB4_41
; SSE-NEXT: .LBB4_33: # %cond.load53
-; SSE-NEXT: pinsrd $2, c+{{.*}}(%rip), %xmm5
+; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm5
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: jne .LBB4_35
; SSE-NEXT: jmp .LBB4_36
@@ -1166,7 +1166,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $2, %al
; SSE-NEXT: je .LBB4_41
; SSE-NEXT: .LBB4_40: # %cond.load69
-; SSE-NEXT: pinsrd $1, c+{{.*}}(%rip), %xmm2
+; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm2
; SSE-NEXT: .LBB4_41: # %else72
; SSE-NEXT: testb $4, %al
; SSE-NEXT: jne .LBB4_42
@@ -1177,16 +1177,16 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $16, %al
; SSE-NEXT: je .LBB4_46
; SSE-NEXT: .LBB4_47: # %cond.load84
-; SSE-NEXT: pinsrd $0, c+{{.*}}(%rip), %xmm3
+; SSE-NEXT: pinsrd $0, c+28(%rip), %xmm3
; SSE-NEXT: testb $32, %al
; SSE-NEXT: jne .LBB4_49
; SSE-NEXT: jmp .LBB4_50
; SSE-NEXT: .LBB4_42: # %cond.load74
-; SSE-NEXT: pinsrd $2, c+{{.*}}(%rip), %xmm2
+; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm2
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je .LBB4_45
; SSE-NEXT: .LBB4_44: # %cond.load79
-; SSE-NEXT: pinsrd $3, c+{{.*}}(%rip), %xmm2
+; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm2
; SSE-NEXT: testb $16, %al
; SSE-NEXT: jne .LBB4_47
; SSE-NEXT: .LBB4_46:
@@ -1194,19 +1194,19 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: testb $32, %al
; SSE-NEXT: je .LBB4_50
; SSE-NEXT: .LBB4_49: # %cond.load89
-; SSE-NEXT: pinsrd $1, c+{{.*}}(%rip), %xmm3
+; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm3
; SSE-NEXT: .LBB4_50: # %else92
; SSE-NEXT: testb $64, %al
; SSE-NEXT: je .LBB4_52
; SSE-NEXT: # %bb.51: # %cond.load94
-; SSE-NEXT: pinsrd $2, c+{{.*}}(%rip), %xmm3
+; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm3
; SSE-NEXT: .LBB4_52: # %else97
; SSE-NEXT: paddd %xmm4, %xmm0
; SSE-NEXT: paddd %xmm5, %xmm1
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: je .LBB4_54
; SSE-NEXT: # %bb.53: # %cond.load99
-; SSE-NEXT: pinsrd $3, c+{{.*}}(%rip), %xmm3
+; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm3
; SSE-NEXT: .LBB4_54: # %else102
; SSE-NEXT: paddd %xmm3, %xmm1
; SSE-NEXT: paddd %xmm2, %xmm0
@@ -1246,7 +1246,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_16
; AVX1-NEXT: .LBB4_15: # %cond.load19
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
-; AVX1-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpinsrd $3, c+12(%rip), %xmm3, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: .LBB4_16: # %else20
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
@@ -1280,7 +1280,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_32
; AVX1-NEXT: .LBB4_31: # %cond.load58
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
-; AVX1-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm4, %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
; AVX1-NEXT: .LBB4_32: # %else61
; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
@@ -1305,7 +1305,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_42
; AVX1-NEXT: .LBB4_41: # %cond.load84
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpinsrd $0, c+{{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpinsrd $0, c+28(%rip), %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: .LBB4_42: # %else87
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
@@ -1315,7 +1315,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_44
; AVX1-NEXT: # %bb.43: # %cond.load89
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
-; AVX1-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm3, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: .LBB4_44: # %else92
; AVX1-NEXT: vpaddd %xmm2, %xmm4, %xmm2
@@ -1323,7 +1323,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_46
; AVX1-NEXT: # %bb.45: # %cond.load94
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
-; AVX1-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm3, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: .LBB4_46: # %else97
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -1331,7 +1331,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_48
; AVX1-NEXT: # %bb.47: # %cond.load99
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: .LBB4_48: # %else102
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
@@ -1345,35 +1345,35 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB4_4
; AVX1-NEXT: .LBB4_3: # %cond.load1
-; AVX1-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm1, %xmm3
+; AVX1-NEXT: vpinsrd $1, c+12(%rip), %xmm1, %xmm3
; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7]
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: je .LBB4_6
; AVX1-NEXT: .LBB4_5: # %cond.load4
-; AVX1-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm1, %xmm3
+; AVX1-NEXT: vpinsrd $2, c+12(%rip), %xmm1, %xmm3
; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7]
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: je .LBB4_8
; AVX1-NEXT: .LBB4_7: # %cond.load7
-; AVX1-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm1, %xmm3
+; AVX1-NEXT: vpinsrd $3, c+12(%rip), %xmm1, %xmm3
; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7]
; AVX1-NEXT: testb $16, %al
; AVX1-NEXT: je .LBB4_10
; AVX1-NEXT: .LBB4_9: # %cond.load10
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
-; AVX1-NEXT: vpinsrd $0, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpinsrd $0, c+12(%rip), %xmm3, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: testb $32, %al
; AVX1-NEXT: je .LBB4_12
; AVX1-NEXT: .LBB4_11: # %cond.load13
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
-; AVX1-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpinsrd $1, c+12(%rip), %xmm3, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: testb $64, %al
; AVX1-NEXT: je .LBB4_14
; AVX1-NEXT: .LBB4_13: # %cond.load16
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
-; AVX1-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpinsrd $2, c+12(%rip), %xmm3, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: jne .LBB4_15
@@ -1383,35 +1383,35 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB4_20
; AVX1-NEXT: .LBB4_19: # %cond.load28
-; AVX1-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm3, %xmm4
+; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm3, %xmm4
; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7]
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: je .LBB4_22
; AVX1-NEXT: .LBB4_21: # %cond.load33
-; AVX1-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm3, %xmm4
+; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm3, %xmm4
; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7]
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: je .LBB4_24
; AVX1-NEXT: .LBB4_23: # %cond.load38
-; AVX1-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm3, %xmm4
+; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm3, %xmm4
; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7]
; AVX1-NEXT: testb $16, %al
; AVX1-NEXT: je .LBB4_26
; AVX1-NEXT: .LBB4_25: # %cond.load43
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
-; AVX1-NEXT: vpinsrd $0, c+{{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpinsrd $0, c+28(%rip), %xmm4, %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
; AVX1-NEXT: testb $32, %al
; AVX1-NEXT: je .LBB4_28
; AVX1-NEXT: .LBB4_27: # %cond.load48
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
-; AVX1-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm4, %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
; AVX1-NEXT: testb $64, %al
; AVX1-NEXT: je .LBB4_30
; AVX1-NEXT: .LBB4_29: # %cond.load53
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
-; AVX1-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm4, %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: jne .LBB4_31
@@ -1421,17 +1421,17 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB4_36
; AVX1-NEXT: .LBB4_35: # %cond.load69
-; AVX1-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm0, %xmm2
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7]
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: je .LBB4_38
; AVX1-NEXT: .LBB4_37: # %cond.load74
-; AVX1-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm0, %xmm2
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7]
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: je .LBB4_40
; AVX1-NEXT: .LBB4_39: # %cond.load79
-; AVX1-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm0, %xmm2
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7]
; AVX1-NEXT: testb $16, %al
; AVX1-NEXT: jne .LBB4_41
@@ -1468,7 +1468,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: je .LBB4_16
; AVX2-NEXT: .LBB4_15: # %cond.load19
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpinsrd $3, c+12(%rip), %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX2-NEXT: .LBB4_16: # %else20
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
@@ -1500,7 +1500,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: je .LBB4_32
; AVX2-NEXT: .LBB4_31: # %cond.load58
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vpinsrd $3, c+28(%rip), %xmm3, %xmm3
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
; AVX2-NEXT: .LBB4_32: # %else61
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
@@ -1529,7 +1529,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: je .LBB4_46
; AVX2-NEXT: .LBB4_45: # %cond.load94
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
-; AVX2-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vpinsrd $2, c+28(%rip), %xmm3, %xmm3
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
; AVX2-NEXT: .LBB4_46: # %else97
; AVX2-NEXT: vpaddd %ymm2, %ymm1, %ymm1
@@ -1537,7 +1537,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: je .LBB4_48
; AVX2-NEXT: # %bb.47: # %cond.load99
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX2-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpinsrd $3, c+28(%rip), %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX2-NEXT: .LBB4_48: # %else102
; AVX2-NEXT: vpaddd %ymm0, %ymm1, %ymm0
@@ -1547,35 +1547,35 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB4_4
; AVX2-NEXT: .LBB4_3: # %cond.load1
-; AVX2-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm1, %xmm2
+; AVX2-NEXT: vpinsrd $1, c+12(%rip), %xmm1, %xmm2
; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: je .LBB4_6
; AVX2-NEXT: .LBB4_5: # %cond.load4
-; AVX2-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm1, %xmm2
+; AVX2-NEXT: vpinsrd $2, c+12(%rip), %xmm1, %xmm2
; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: je .LBB4_8
; AVX2-NEXT: .LBB4_7: # %cond.load7
-; AVX2-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm1, %xmm2
+; AVX2-NEXT: vpinsrd $3, c+12(%rip), %xmm1, %xmm2
; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: testb $16, %al
; AVX2-NEXT: je .LBB4_10
; AVX2-NEXT: .LBB4_9: # %cond.load10
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2-NEXT: vpinsrd $0, c+{{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpinsrd $0, c+12(%rip), %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX2-NEXT: testb $32, %al
; AVX2-NEXT: je .LBB4_12
; AVX2-NEXT: .LBB4_11: # %cond.load13
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpinsrd $1, c+12(%rip), %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX2-NEXT: testb $64, %al
; AVX2-NEXT: je .LBB4_14
; AVX2-NEXT: .LBB4_13: # %cond.load16
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vpinsrd $2, c+12(%rip), %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: jne .LBB4_15
@@ -1585,35 +1585,35 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB4_20
; AVX2-NEXT: .LBB4_19: # %cond.load28
-; AVX2-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm2, %xmm3
+; AVX2-NEXT: vpinsrd $1, c+28(%rip), %xmm2, %xmm3
; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7]
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: je .LBB4_22
; AVX2-NEXT: .LBB4_21: # %cond.load33
-; AVX2-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm2, %xmm3
+; AVX2-NEXT: vpinsrd $2, c+28(%rip), %xmm2, %xmm3
; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7]
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: je .LBB4_24
; AVX2-NEXT: .LBB4_23: # %cond.load38
-; AVX2-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm2, %xmm3
+; AVX2-NEXT: vpinsrd $3, c+28(%rip), %xmm2, %xmm3
; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7]
; AVX2-NEXT: testb $16, %al
; AVX2-NEXT: je .LBB4_26
; AVX2-NEXT: .LBB4_25: # %cond.load43
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpinsrd $0, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vpinsrd $0, c+28(%rip), %xmm3, %xmm3
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
; AVX2-NEXT: testb $32, %al
; AVX2-NEXT: je .LBB4_28
; AVX2-NEXT: .LBB4_27: # %cond.load48
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vpinsrd $1, c+28(%rip), %xmm3, %xmm3
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
; AVX2-NEXT: testb $64, %al
; AVX2-NEXT: je .LBB4_30
; AVX2-NEXT: .LBB4_29: # %cond.load53
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vpinsrd $2, c+28(%rip), %xmm3, %xmm3
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: jne .LBB4_31
@@ -1623,29 +1623,29 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB4_36
; AVX2-NEXT: .LBB4_35: # %cond.load69
-; AVX2-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm0, %xmm3
+; AVX2-NEXT: vpinsrd $1, c+28(%rip), %xmm0, %xmm3
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7]
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: je .LBB4_38
; AVX2-NEXT: .LBB4_37: # %cond.load74
-; AVX2-NEXT: vpinsrd $2, c+{{.*}}(%rip), %xmm0, %xmm3
+; AVX2-NEXT: vpinsrd $2, c+28(%rip), %xmm0, %xmm3
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7]
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: je .LBB4_40
; AVX2-NEXT: .LBB4_39: # %cond.load79
-; AVX2-NEXT: vpinsrd $3, c+{{.*}}(%rip), %xmm0, %xmm3
+; AVX2-NEXT: vpinsrd $3, c+28(%rip), %xmm0, %xmm3
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7]
; AVX2-NEXT: testb $16, %al
; AVX2-NEXT: je .LBB4_42
; AVX2-NEXT: .LBB4_41: # %cond.load84
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
-; AVX2-NEXT: vpinsrd $0, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vpinsrd $0, c+28(%rip), %xmm3, %xmm3
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
; AVX2-NEXT: testb $32, %al
; AVX2-NEXT: je .LBB4_44
; AVX2-NEXT: .LBB4_43: # %cond.load89
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
-; AVX2-NEXT: vpinsrd $1, c+{{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vpinsrd $1, c+28(%rip), %xmm3, %xmm3
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
; AVX2-NEXT: testb $64, %al
; AVX2-NEXT: jne .LBB4_45
diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter.ll b/llvm/test/CodeGen/X86/masked_gather_scatter.ll
index ae736031a9cba..a6f116bcec1ba 100644
--- a/llvm/test/CodeGen/X86/masked_gather_scatter.ll
+++ b/llvm/test/CodeGen/X86/masked_gather_scatter.ll
@@ -474,10 +474,10 @@ define <8 x i32> @test9(%struct.ST* %base, <8 x i64> %ind1, <8 x i32>%ind5) {
; KNL_64-NEXT: vpsllq $32, %zmm0, %zmm0
; KNL_64-NEXT: vpaddq %zmm2, %zmm0, %zmm0
; KNL_64-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
-; KNL_64-NEXT: vpmuldq {{.*}}(%rip){1to8}, %zmm1, %zmm1
+; KNL_64-NEXT: vpmuldq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
; KNL_64-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; KNL_64-NEXT: vpaddq %zmm0, %zmm4, %zmm0
-; KNL_64-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; KNL_64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; KNL_64-NEXT: kxnorw %k0, %k0, %k1
; KNL_64-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; KNL_64-NEXT: retq
@@ -503,12 +503,12 @@ define <8 x i32> @test9(%struct.ST* %base, <8 x i64> %ind1, <8 x i32>%ind5) {
; SKX_SMALL-LABEL: test9:
; SKX_SMALL: # %bb.0: # %entry
; SKX_SMALL-NEXT: vpbroadcastq %rdi, %zmm2
-; SKX_SMALL-NEXT: vpmullq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; SKX_SMALL-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; SKX_SMALL-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
-; SKX_SMALL-NEXT: vpmuldq {{.*}}(%rip){1to8}, %zmm1, %zmm1
+; SKX_SMALL-NEXT: vpmuldq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
; SKX_SMALL-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX_SMALL-NEXT: vpaddq %zmm0, %zmm2, %zmm0
-; SKX_SMALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; SKX_SMALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; SKX_SMALL-NEXT: retq
@@ -517,13 +517,13 @@ define <8 x i32> @test9(%struct.ST* %base, <8 x i64> %ind1, <8 x i32>%ind5) {
; SKX_LARGE: # %bb.0: # %entry
; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2
; SKX_LARGE-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm0, %zmm2, %zmm0
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
@@ -531,12 +531,12 @@ define <8 x i32> @test9(%struct.ST* %base, <8 x i64> %ind1, <8 x i32>%ind5) {
;
; SKX_32-LABEL: test9:
; SKX_32: # %bb.0: # %entry
-; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm1, %ymm1
+; SKX_32-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm1, %ymm1
; SKX_32-NEXT: vpmovqd %zmm0, %ymm0
-; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
+; SKX_32-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd {{[0-9]+}}(%esp){1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
-; SKX_32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
+; SKX_32-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vpgatherdd (,%ymm1), %ymm0 {%k1}
; SKX_32-NEXT: retl
@@ -560,10 +560,10 @@ define <8 x i32> @test10(%struct.ST* %base, <8 x i64> %i1, <8 x i32>%ind5) {
; KNL_64-NEXT: vpsllq $32, %zmm0, %zmm0
; KNL_64-NEXT: vpaddq %zmm2, %zmm0, %zmm0
; KNL_64-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
-; KNL_64-NEXT: vpmuldq {{.*}}(%rip){1to8}, %zmm1, %zmm1
+; KNL_64-NEXT: vpmuldq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
; KNL_64-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; KNL_64-NEXT: vpaddq %zmm0, %zmm4, %zmm0
-; KNL_64-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; KNL_64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; KNL_64-NEXT: kxnorw %k0, %k0, %k1
; KNL_64-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; KNL_64-NEXT: retq
@@ -589,12 +589,12 @@ define <8 x i32> @test10(%struct.ST* %base, <8 x i64> %i1, <8 x i32>%ind5) {
; SKX_SMALL-LABEL: test10:
; SKX_SMALL: # %bb.0: # %entry
; SKX_SMALL-NEXT: vpbroadcastq %rdi, %zmm2
-; SKX_SMALL-NEXT: vpmullq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; SKX_SMALL-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; SKX_SMALL-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
-; SKX_SMALL-NEXT: vpmuldq {{.*}}(%rip){1to8}, %zmm1, %zmm1
+; SKX_SMALL-NEXT: vpmuldq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
; SKX_SMALL-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX_SMALL-NEXT: vpaddq %zmm0, %zmm2, %zmm0
-; SKX_SMALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; SKX_SMALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; SKX_SMALL-NEXT: retq
@@ -603,13 +603,13 @@ define <8 x i32> @test10(%struct.ST* %base, <8 x i64> %i1, <8 x i32>%ind5) {
; SKX_LARGE: # %bb.0: # %entry
; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2
; SKX_LARGE-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm0, %zmm2, %zmm0
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
@@ -617,12 +617,12 @@ define <8 x i32> @test10(%struct.ST* %base, <8 x i64> %i1, <8 x i32>%ind5) {
;
; SKX_32-LABEL: test10:
; SKX_32: # %bb.0: # %entry
-; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm1, %ymm1
+; SKX_32-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm1, %ymm1
; SKX_32-NEXT: vpmovqd %zmm0, %ymm0
-; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
+; SKX_32-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd {{[0-9]+}}(%esp){1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
-; SKX_32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
+; SKX_32-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vpgatherdd (,%ymm1), %ymm0 {%k1}
; SKX_32-NEXT: retl
@@ -2885,7 +2885,7 @@ declare void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double>, <2 x double*>, i32
define <16 x float> @zext_index(float* %base, <16 x i32> %ind) {
; KNL_64-LABEL: zext_index:
; KNL_64: # %bb.0:
-; KNL_64-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm1
+; KNL_64-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm1
; KNL_64-NEXT: kxnorw %k0, %k0, %k1
; KNL_64-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1}
; KNL_64-NEXT: retq
@@ -2893,21 +2893,21 @@ define <16 x float> @zext_index(float* %base, <16 x i32> %ind) {
; KNL_32-LABEL: zext_index:
; KNL_32: # %bb.0:
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; KNL_32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm1
+; KNL_32-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm1
; KNL_32-NEXT: kxnorw %k0, %k0, %k1
; KNL_32-NEXT: vgatherdps (%eax,%zmm1,4), %zmm0 {%k1}
; KNL_32-NEXT: retl
;
; SKX_SMALL-LABEL: zext_index:
; SKX_SMALL: # %bb.0:
-; SKX_SMALL-NEXT: vandps {{.*}}(%rip){1to16}, %zmm0, %zmm1
+; SKX_SMALL-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm1
; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1}
; SKX_SMALL-NEXT: retq
;
; SKX_LARGE-LABEL: zext_index:
; SKX_LARGE: # %bb.0:
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vandps (%rax){1to16}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1}
@@ -2916,7 +2916,7 @@ define <16 x float> @zext_index(float* %base, <16 x i32> %ind) {
; SKX_32-LABEL: zext_index:
; SKX_32: # %bb.0:
; SKX_32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SKX_32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm1
+; SKX_32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vgatherdps (%eax,%zmm1,4), %zmm0 {%k1}
; SKX_32-NEXT: retl
@@ -3184,7 +3184,7 @@ define <2 x i64> @gather_2i64_constant_indices(i64* %ptr, <2 x i1> %mask) {
; SKX_LARGE: # %bb.0:
; SKX_LARGE-NEXT: vpsllq $63, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpmovq2m %xmm0, %k1
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa (%rax), %xmm1
; SKX_LARGE-NEXT: vpxor %xmm0, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpgatherdq (%rdi,%xmm1,8), %xmm0 {%k1}
@@ -3241,7 +3241,7 @@ define <16 x i32> @gather_16i64_constant_indices(i32* %ptr, <16 x i1> %mask) {
; SKX_LARGE-NEXT: vpmovsxbd %xmm0, %zmm0
; SKX_LARGE-NEXT: vpslld $31, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpmovd2m %zmm0, %k1
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa64 (%rax), %zmm1
; SKX_LARGE-NEXT: vpxor %xmm0, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpgatherdd (%rdi,%zmm1,4), %zmm0 {%k1}
@@ -3300,7 +3300,7 @@ define void @scatter_2i64_constant_indices(i32* %ptr, <2 x i1> %mask, <2 x i32>
; SKX_LARGE: # %bb.0:
; SKX_LARGE-NEXT: vpsllq $63, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpmovq2m %xmm0, %k1
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa (%rax), %xmm0
; SKX_LARGE-NEXT: vpscatterdd %xmm1, (%rdi,%xmm0,4) {%k1}
; SKX_LARGE-NEXT: retq
@@ -3355,7 +3355,7 @@ define void @scatter_16i64_constant_indices(i32* %ptr, <16 x i1> %mask, <16 x i3
; SKX_LARGE-NEXT: vpmovsxbd %xmm0, %zmm0
; SKX_LARGE-NEXT: vpslld $31, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpmovd2m %zmm0, %k1
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa64 (%rax), %zmm0
; SKX_LARGE-NEXT: vpscatterdd %zmm1, (%rdi,%zmm0,4) {%k1}
; SKX_LARGE-NEXT: vzeroupper
@@ -3484,7 +3484,7 @@ define void @splat_ptr_scatter(i32* %ptr, <4 x i1> %mask, <4 x i32> %val) {
define <8 x i64> @pr45906(<8 x %struct.foo*> %ptr) {
; KNL_64-LABEL: pr45906:
; KNL_64: # %bb.0: # %bb
-; KNL_64-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; KNL_64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; KNL_64-NEXT: kxnorw %k0, %k0, %k1
; KNL_64-NEXT: vpgatherqq (,%zmm1), %zmm0 {%k1}
; KNL_64-NEXT: retq
@@ -3499,14 +3499,14 @@ define <8 x i64> @pr45906(<8 x %struct.foo*> %ptr) {
;
; SKX_SMALL-LABEL: pr45906:
; SKX_SMALL: # %bb.0: # %bb
-; SKX_SMALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
+; SKX_SMALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm1
; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vpgatherqq (,%zmm1), %zmm0 {%k1}
; SKX_SMALL-NEXT: retq
;
; SKX_LARGE-LABEL: pr45906:
; SKX_LARGE: # %bb.0: # %bb
-; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
+; SKX_LARGE-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vpgatherqq (,%zmm1), %zmm0 {%k1}
@@ -3514,7 +3514,7 @@ define <8 x i64> @pr45906(<8 x %struct.foo*> %ptr) {
;
; SKX_32-LABEL: pr45906:
; SKX_32: # %bb.0: # %bb
-; SKX_32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
+; SKX_32-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vpgatherdq (,%ymm1), %zmm0 {%k1}
; SKX_32-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/masked_load.ll b/llvm/test/CodeGen/X86/masked_load.ll
index d6d08ac581250..2e55a372ab576 100644
--- a/llvm/test/CodeGen/X86/masked_load.ll
+++ b/llvm/test/CodeGen/X86/masked_load.ll
@@ -4028,7 +4028,7 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, <16 x i8>* %addr, <16 x i
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: je LBB23_32
; SSE2-NEXT: LBB23_31: ## %cond.load43
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movzbl 15(%rdi), %eax
; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0]
@@ -4628,7 +4628,7 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, <32 x i8>* %addr, <32 x i
; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; SSE2-NEXT: je LBB24_64
; SSE2-NEXT: LBB24_63: ## %cond.load91
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: movzbl 31(%rdi), %eax
; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0]
@@ -4787,7 +4787,7 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, <32 x i8>* %addr, <32 x i
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: je LBB24_32
; SSE2-NEXT: LBB24_31: ## %cond.load43
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movzbl 15(%rdi), %ecx
; SSE2-NEXT: movd %ecx, %xmm0
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0]
diff --git a/llvm/test/CodeGen/X86/masked_store.ll b/llvm/test/CodeGen/X86/masked_store.ll
index 89955afd3fb62..aa8cea47b1769 100644
--- a/llvm/test/CodeGen/X86/masked_store.ll
+++ b/llvm/test/CodeGen/X86/masked_store.ll
@@ -5143,7 +5143,7 @@ define void @one_mask_bit_set1_variable(<4 x float>* %addr, <4 x float> %val, <4
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512F-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm1, %k0
+; AVX512F-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovups %zmm0, (%rdi) {%k1}
@@ -5152,14 +5152,14 @@ define void @one_mask_bit_set1_variable(<4 x float>* %addr, <4 x float> %val, <4
;
; AVX512VL-LABEL: one_mask_bit_set1_variable:
; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vptestmd {{.*}}(%rip){1to4}, %xmm1, %k1
+; AVX512VL-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %k1
; AVX512VL-NEXT: vmovups %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
;
; X86-AVX512-LABEL: one_mask_bit_set1_variable:
; X86-AVX512: ## %bb.0:
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX512-NEXT: vptestmd LCPI26_0{1to4}, %xmm1, %k1
+; X86-AVX512-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm1, %k1
; X86-AVX512-NEXT: vmovups %xmm0, (%eax) {%k1}
; X86-AVX512-NEXT: retl
%mask_signbit = and <4 x i32> %mask, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc.ll b/llvm/test/CodeGen/X86/masked_store_trunc.ll
index 53873481a30e5..80ef17c5c9a44 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc.ll
@@ -1822,7 +1822,7 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; SSE2-LABEL: truncstore_v2i64_v2i8:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
@@ -4251,7 +4251,7 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; SSE2-LABEL: truncstore_v4i32_v4i8:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
@@ -5862,7 +5862,7 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %p, <16 x i8> %ma
; AVX1-LABEL: truncstore_v16i16_v16i8:
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1
@@ -5986,7 +5986,7 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %p, <16 x i8> %ma
; AVX2-LABEL: truncstore_v16i16_v16i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
; AVX2-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1
@@ -6257,7 +6257,7 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %p, <8 x i16> %mask)
; SSE2-LABEL: truncstore_v8i16_v8i8:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: pcmpeqw %xmm1, %xmm2
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
index 9bf23917b375f..035a1fbd0d10f 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
@@ -351,8 +351,8 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %p, <8 x i32> %mask
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512F-NEXT: vpminsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; AVX512F-NEXT: vpmaxsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512F-NEXT: vpmovqd %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
@@ -360,8 +360,8 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %p, <8 x i32> %mask
; AVX512VL-LABEL: truncstore_v8i64_v8i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512VL-NEXT: vpminsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; AVX512VL-NEXT: vpmaxsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512VL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512VL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512VL-NEXT: vpmovqd %zmm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
@@ -370,8 +370,8 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %p, <8 x i32> %mask
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmaxsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovqd %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -916,8 +916,8 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %p, <8 x i32> %mask
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmaxsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovqw %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -925,8 +925,8 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %p, <8 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v8i64_v8i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; AVX512BWVL-NEXT: vpmaxsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovqw %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -1468,8 +1468,8 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %p, <8 x i32> %mask)
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmaxsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovqb %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -1477,8 +1477,8 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %p, <8 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v8i64_v8i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
-; AVX512BWVL-NEXT: vpmaxsq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovqb %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -1696,8 +1696,8 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %p, <4 x i32> %mask
; AVX512VL-LABEL: truncstore_v4i64_v4i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vpminsq {{.*}}(%rip){1to4}, %ymm0, %ymm0
-; AVX512VL-NEXT: vpmaxsq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512VL-NEXT: vpmovqd %ymm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
@@ -2024,8 +2024,8 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %p, <4 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v4i64_v4i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{.*}}(%rip){1to4}, %ymm0, %ymm0
-; AVX512BWVL-NEXT: vpmaxsq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovqw %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -2350,8 +2350,8 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %p, <4 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v4i64_v4i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{.*}}(%rip){1to4}, %ymm0, %ymm0
-; AVX512BWVL-NEXT: vpmaxsq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovqb %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -2382,7 +2382,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm4, %xmm5
; SSE2-NEXT: pand %xmm5, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm5
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE2-NEXT: por %xmm0, %xmm5
; SSE2-NEXT: pxor %xmm5, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [18446744069414584320,18446744069414584320]
@@ -2395,7 +2395,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm5
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: por %xmm5, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
@@ -2499,8 +2499,8 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX512VL-LABEL: truncstore_v2i64_v2i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vpminsq {{.*}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vpmaxsq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vpmovqd %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
;
@@ -2542,7 +2542,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm4, %xmm5
; SSE2-NEXT: pand %xmm5, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm5
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE2-NEXT: por %xmm0, %xmm5
; SSE2-NEXT: pxor %xmm5, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [18446744071562035200,18446744071562035200]
@@ -2555,7 +2555,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm5
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: por %xmm5, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
@@ -2681,8 +2681,8 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; AVX512BWVL-LABEL: truncstore_v2i64_v2i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{.*}}(%rip), %xmm0, %xmm0
-; AVX512BWVL-NEXT: vpmaxsq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@@ -2712,7 +2712,7 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm4, %xmm5
; SSE2-NEXT: pand %xmm5, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm5
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE2-NEXT: por %xmm0, %xmm5
; SSE2-NEXT: pxor %xmm5, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [18446744071562067840,18446744071562067840]
@@ -2725,9 +2725,9 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm5
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: por %xmm5, %xmm3
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: packuswb %xmm3, %xmm3
; SSE2-NEXT: packuswb %xmm3, %xmm3
; SSE2-NEXT: packuswb %xmm3, %xmm3
@@ -2850,8 +2850,8 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; AVX512BWVL-LABEL: truncstore_v2i64_v2i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{.*}}(%rip), %xmm0, %xmm0
-; AVX512BWVL-NEXT: vpmaxsq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@@ -3532,8 +3532,8 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %p, <16 x i32>
; AVX512BW-LABEL: truncstore_v16i32_v16i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmaxsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovdw %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -3541,8 +3541,8 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %p, <16 x i32>
; AVX512BWVL-LABEL: truncstore_v16i32_v16i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BWVL-NEXT: vpminsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
-; AVX512BWVL-NEXT: vpmaxsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovdw %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -4203,8 +4203,8 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %p, <16 x i32> %m
; AVX512BW-LABEL: truncstore_v16i32_v16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmaxsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovdb %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -4212,8 +4212,8 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %p, <16 x i32> %m
; AVX512BWVL-LABEL: truncstore_v16i32_v16i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BWVL-NEXT: vpminsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
-; AVX512BWVL-NEXT: vpmaxsd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovdb %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -4592,8 +4592,8 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %p, <8 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v8i32_v8i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminsd {{.*}}(%rip){1to8}, %ymm0, %ymm0
-; AVX512BWVL-NEXT: vpmaxsd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovdw %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -4971,8 +4971,8 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %p, <8 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v8i32_v8i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminsd {{.*}}(%rip){1to8}, %ymm0, %ymm0
-; AVX512BWVL-NEXT: vpmaxsd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovdb %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -5150,8 +5150,8 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %p, <4 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v4i32_v4i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; AVX512BWVL-NEXT: vpmaxsd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovdw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <4 x i32> %mask, zeroinitializer
@@ -5180,7 +5180,7 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: pandn %xmm0, %xmm3
; SSE2-NEXT: por %xmm4, %xmm3
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: packuswb %xmm3, %xmm3
; SSE2-NEXT: packuswb %xmm3, %xmm3
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
@@ -5222,8 +5222,8 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; SSE4-LABEL: truncstore_v4i32_v4i8:
; SSE4: # %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
-; SSE4-NEXT: pminsd {{.*}}(%rip), %xmm0
-; SSE4-NEXT: pmaxsd {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: pmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: packssdw %xmm0, %xmm0
; SSE4-NEXT: packsswb %xmm0, %xmm0
; SSE4-NEXT: pcmpeqd %xmm1, %xmm2
@@ -5261,8 +5261,8 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; AVX1-LABEL: truncstore_v4i32_v4i8:
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
@@ -5391,8 +5391,8 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v4i32_v4i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; AVX512BWVL-NEXT: vpmaxsd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovdb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <4 x i32> %mask, zeroinitializer
@@ -6574,8 +6574,8 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, <32 x i8>* %p, <32 x i8> %ma
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmb %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminsw {{.*}}(%rip), %zmm0, %zmm0
-; AVX512BW-NEXT: vpmaxsw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -6583,8 +6583,8 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, <32 x i8>* %p, <32 x i8> %ma
; AVX512BWVL-LABEL: truncstore_v32i16_v32i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmb %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminsw {{.*}}(%rip), %zmm0, %zmm0
-; AVX512BWVL-NEXT: vpmaxsw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovwb %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -7211,8 +7211,8 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %p, <16 x i8> %ma
; AVX512BWVL-LABEL: truncstore_v16i16_v16i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmb %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
-; AVX512BWVL-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovwb %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -7508,8 +7508,8 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %p, <8 x i16> %mask)
; AVX512BWVL-LABEL: truncstore_v8i16_v8i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmw %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
-; AVX512BWVL-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovwb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <8 x i16> %mask, zeroinitializer
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
index 21ad6259a4633..f36097a2cd464 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
@@ -286,7 +286,7 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %p, <8 x i32> %mask
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512F-NEXT: vpminuq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512F-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512F-NEXT: vpmovqd %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
@@ -294,7 +294,7 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %p, <8 x i32> %mask
; AVX512VL-LABEL: truncstore_v8i64_v8i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512VL-NEXT: vpminuq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512VL-NEXT: vpmovqd %zmm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
@@ -303,7 +303,7 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %p, <8 x i32> %mask
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminuq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovqd %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -789,7 +789,7 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %p, <8 x i32> %mask
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminuq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovqw %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -797,7 +797,7 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %p, <8 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v8i64_v8i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovqw %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -1272,7 +1272,7 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %p, <8 x i32> %mask)
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminuq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovqb %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -1280,7 +1280,7 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %p, <8 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v8i64_v8i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovqb %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -1464,7 +1464,7 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %p, <4 x i32> %mask
; AVX512VL-LABEL: truncstore_v4i64_v4i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vpminuq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512VL-NEXT: vpmovqd %ymm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
@@ -1760,7 +1760,7 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %p, <4 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v4i64_v4i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovqw %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -2050,7 +2050,7 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %p, <4 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v4i64_v4i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovqb %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -2078,7 +2078,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE2-NEXT: por %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm0, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm4[0,2,2,3]
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
@@ -2139,7 +2139,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
; AVX1-NEXT: vmovapd {{.*#+}} xmm2 = [4294967295,4294967295]
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm3
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [9223372041149743103,9223372041149743103]
; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vblendvpd %xmm3, %xmm0, %xmm2, %xmm0
@@ -2155,7 +2155,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
; AVX2-NEXT: vmovapd {{.*#+}} xmm2 = [4294967295,4294967295]
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm3
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = [9223372041149743103,9223372041149743103]
; AVX2-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm3
; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm2, %xmm0
@@ -2178,7 +2178,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX512VL-LABEL: truncstore_v2i64_v2i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vpmovqd %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
;
@@ -2217,7 +2217,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE2-NEXT: por %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm0, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm4[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
@@ -2277,7 +2277,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; AVX: # %bb.0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX-NEXT: vmovapd {{.*#+}} xmm3 = [65535,65535]
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm4
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm4
; AVX-NEXT: vmovdqa {{.*#+}} xmm5 = [9223372036854841343,9223372036854841343]
; AVX-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm4
; AVX-NEXT: vblendvpd %xmm4, %xmm0, %xmm3, %xmm0
@@ -2340,7 +2340,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; AVX512BWVL-LABEL: truncstore_v2i64_v2i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@@ -2367,9 +2367,9 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE2-NEXT: por %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm0, %xmm4
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: packuswb %xmm4, %xmm4
; SSE2-NEXT: packuswb %xmm4, %xmm4
; SSE2-NEXT: packuswb %xmm4, %xmm4
@@ -2427,7 +2427,7 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; AVX: # %bb.0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX-NEXT: vmovapd {{.*#+}} xmm3 = [255,255]
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm4
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm4
; AVX-NEXT: vmovdqa {{.*#+}} xmm5 = [9223372036854776063,9223372036854776063]
; AVX-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm4
; AVX-NEXT: vblendvpd %xmm4, %xmm0, %xmm3, %xmm0
@@ -2489,7 +2489,7 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; AVX512BWVL-LABEL: truncstore_v2i64_v2i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@@ -3200,7 +3200,7 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %p, <16 x i32>
; AVX512BW-LABEL: truncstore_v16i32_v16i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminud {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovdw %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -3208,7 +3208,7 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %p, <16 x i32>
; AVX512BWVL-LABEL: truncstore_v16i32_v16i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BWVL-NEXT: vpminud {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovdw %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -3909,7 +3909,7 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %p, <16 x i32> %m
; AVX512BW-LABEL: truncstore_v16i32_v16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminud {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BW-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovdb %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -3917,7 +3917,7 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %p, <16 x i32> %m
; AVX512BWVL-LABEL: truncstore_v16i32_v16i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %zmm1, %zmm1, %k1
-; AVX512BWVL-NEXT: vpminud {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovdb %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -4320,7 +4320,7 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %p, <8 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v8i32_v8i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminud {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovdw %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -4717,7 +4717,7 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %p, <8 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v8i32_v8i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminud {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovdb %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -4738,7 +4738,7 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %p, <4 x i32> %mask
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147549183,2147549183,2147549183,2147549183]
; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm0, %xmm4
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm4[0,2,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
@@ -4782,7 +4782,7 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %p, <4 x i32> %mask
; SSE4-LABEL: truncstore_v4i32_v4i16:
; SSE4: # %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
-; SSE4-NEXT: pminud {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: packusdw %xmm0, %xmm0
; SSE4-NEXT: pcmpeqd %xmm1, %xmm2
; SSE4-NEXT: movmskps %xmm2, %eax
@@ -4819,7 +4819,7 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %p, <4 x i32> %mask
; AVX1-LABEL: truncstore_v4i32_v4i16:
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpackusdw %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmovmskps %xmm1, %eax
@@ -4944,7 +4944,7 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %p, <4 x i32> %mask
; AVX512BWVL-LABEL: truncstore_v4i32_v4i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovdw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <4 x i32> %mask, zeroinitializer
@@ -4964,9 +4964,9 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483903,2147483903,2147483903,2147483903]
; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm0, %xmm4
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: packuswb %xmm4, %xmm4
; SSE2-NEXT: packuswb %xmm4, %xmm4
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
@@ -5008,7 +5008,7 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; SSE4-LABEL: truncstore_v4i32_v4i8:
; SSE4: # %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
-; SSE4-NEXT: pminud {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: packusdw %xmm0, %xmm0
; SSE4-NEXT: packuswb %xmm0, %xmm0
; SSE4-NEXT: pcmpeqd %xmm1, %xmm2
@@ -5046,7 +5046,7 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; AVX1-LABEL: truncstore_v4i32_v4i8:
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpackusdw %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
@@ -5173,7 +5173,7 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %p, <4 x i32> %mask)
; AVX512BWVL-LABEL: truncstore_v4i32_v4i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmd %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovdb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <4 x i32> %mask, zeroinitializer
@@ -6383,7 +6383,7 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, <32 x i8>* %p, <32 x i8> %ma
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512BW-NEXT: vptestmb %zmm1, %zmm1, %k1
-; AVX512BW-NEXT: vpminuw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, (%rdi) {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -6391,7 +6391,7 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, <32 x i8>* %p, <32 x i8> %ma
; AVX512BWVL-LABEL: truncstore_v32i16_v32i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmb %ymm1, %ymm1, %k1
-; AVX512BWVL-NEXT: vpminuw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BWVL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BWVL-NEXT: vpmovwb %zmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -6772,7 +6772,7 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %p, <16 x i8> %ma
; AVX2-LABEL: truncstore_v16i16_v16i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
; AVX2-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1
@@ -6897,7 +6897,7 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %p, <16 x i8> %ma
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1
-; AVX512F-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: vpmovmskb %xmm1, %eax
@@ -7031,7 +7031,7 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %p, <16 x i8> %ma
; AVX512BWVL-LABEL: truncstore_v16i16_v16i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmb %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BWVL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovwb %ymm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
@@ -7048,7 +7048,7 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %p, <8 x i16> %mask)
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3
-; SSE2-NEXT: psubusw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: psubusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psubw %xmm3, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: pcmpeqw %xmm1, %xmm2
@@ -7117,7 +7117,7 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %p, <8 x i16> %mask)
; SSE4-LABEL: truncstore_v8i16_v8i8:
; SSE4: # %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
-; SSE4-NEXT: pminuw {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: packuswb %xmm0, %xmm0
; SSE4-NEXT: pcmpeqw %xmm1, %xmm2
; SSE4-NEXT: pcmpeqd %xmm1, %xmm1
@@ -7184,7 +7184,7 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %p, <8 x i16> %mask)
; AVX-LABEL: truncstore_v8i16_v8i8:
; AVX: # %bb.0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; AVX-NEXT: vpcmpeqw %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
@@ -7255,7 +7255,7 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %p, <8 x i16> %mask)
; AVX512F-NEXT: vpternlogq $15, %zmm1, %zmm1, %zmm1
; AVX512F-NEXT: vpmovsxwq %xmm1, %zmm1
; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0
-; AVX512F-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: testb $1, %al
@@ -7332,7 +7332,7 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %p, <8 x i16> %mask)
; AVX512BWVL-LABEL: truncstore_v8i16_v8i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmw %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovwb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <8 x i16> %mask, zeroinitializer
diff --git a/llvm/test/CodeGen/X86/mcu-abi.ll b/llvm/test/CodeGen/X86/mcu-abi.ll
index 8a9a466d0a67b..16e1ad718b3e0 100644
--- a/llvm/test/CodeGen/X86/mcu-abi.ll
+++ b/llvm/test/CodeGen/X86/mcu-abi.ll
@@ -124,7 +124,7 @@ define void @test_alignment_d() #0 {
; CHECK-NEXT: movl $1073741824, {{[0-9]+}}(%esp) # imm = 0x40000000
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: movl %esp, %eax
-; CHECK-NEXT: calll food
+; CHECK-NEXT: calll food at PLT
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: retl
entry:
@@ -141,7 +141,7 @@ define void @test_alignment_i() #0 {
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $2, (%esp)
; CHECK-NEXT: movl %esp, %eax
-; CHECK-NEXT: calll fooi
+; CHECK-NEXT: calll fooi at PLT
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: retl
entry:
@@ -156,7 +156,7 @@ define void @test_alignment_s() #0 {
; CHECK: # %bb.0:
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl %esp, %eax
-; CHECK-NEXT: calll foos
+; CHECK-NEXT: calll foos at PLT
; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl
%s = alloca %struct.S, align 4
@@ -173,7 +173,7 @@ define void @test_alignment_fp() #0 {
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: movl %esp, %eax
-; CHECK-NEXT: calll foofp
+; CHECK-NEXT: calll foofp at PLT
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/memcmp-minsize.ll b/llvm/test/CodeGen/X86/memcmp-minsize.ll
index 455c07d093dad..fec09f6b8d364 100644
--- a/llvm/test/CodeGen/X86/memcmp-minsize.ll
+++ b/llvm/test/CodeGen/X86/memcmp-minsize.ll
@@ -456,7 +456,7 @@ define i1 @length16_eq_const(i8* %X) nounwind minsize {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al
@@ -465,7 +465,7 @@ define i1 @length16_eq_const(i8* %X) nounwind minsize {
; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X64-SSE2-NEXT: sete %al
@@ -474,7 +474,7 @@ define i1 @length16_eq_const(i8* %X) nounwind minsize {
; X64-AVX-LABEL: length16_eq_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: sete %al
; X64-AVX-NEXT: retq
@@ -658,7 +658,7 @@ define i1 @length32_eq_const(i8* %X) nounwind minsize {
; X64-AVX1-LABEL: length32_eq_const:
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: setne %al
; X64-AVX1-NEXT: vzeroupper
@@ -667,7 +667,7 @@ define i1 @length32_eq_const(i8* %X) nounwind minsize {
; X64-AVX2-LABEL: length32_eq_const:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: setne %al
; X64-AVX2-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
index 878e0cd256c14..84b454776c325 100644
--- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
+++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
@@ -1480,7 +1480,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al
@@ -1490,7 +1490,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al
; X86-SSE41-NEXT: retl
@@ -1498,7 +1498,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X64-SSE2-NEXT: sete %al
@@ -1507,7 +1507,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X64-SSE41-LABEL: length16_eq_const:
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: sete %al
; X64-SSE41-NEXT: retq
@@ -1515,7 +1515,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X64-AVX-LABEL: length16_eq_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: sete %al
; X64-AVX-NEXT: retq
@@ -1823,8 +1823,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -1836,8 +1836,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 8(%eax), %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al
@@ -1847,8 +1847,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -1859,8 +1859,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
; X64-SSE41-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: setne %al
@@ -1870,8 +1870,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
; X64-AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: setne %al
@@ -2312,8 +2312,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 15(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2325,8 +2325,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 15(%eax), %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al
@@ -2336,8 +2336,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movdqu 15(%rdi), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2348,8 +2348,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
; X64-SSE41-NEXT: movdqu 15(%rdi), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: setne %al
@@ -2359,8 +2359,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
; X64-AVX-NEXT: vmovdqu 15(%rdi), %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: setne %al
@@ -2816,8 +2816,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2829,8 +2829,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al
@@ -2840,8 +2840,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movdqu 16(%rdi), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2852,8 +2852,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
; X64-SSE41-NEXT: movdqu 16(%rdi), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: setne %al
@@ -2862,7 +2862,7 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-AVX1-LABEL: length32_eq_const:
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: setne %al
; X64-AVX1-NEXT: vzeroupper
@@ -2871,7 +2871,7 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-AVX2-LABEL: length32_eq_const:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: setne %al
; X64-AVX2-NEXT: vzeroupper
@@ -2880,7 +2880,7 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-AVX512-LABEL: length32_eq_const:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vmovdqu (%rdi), %ymm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: vptest %ymm0, %ymm0
; X64-AVX512-NEXT: setne %al
; X64-AVX512-NEXT: vzeroupper
@@ -3293,9 +3293,9 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: pand %xmm0, %xmm2
; X86-SSE2-NEXT: pmovmskb %xmm2, %eax
@@ -3309,9 +3309,9 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE41-NEXT: por %xmm1, %xmm2
; X86-SSE41-NEXT: por %xmm0, %xmm2
; X86-SSE41-NEXT: ptest %xmm2, %xmm2
@@ -3323,9 +3323,9 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movdqu 16(%rdi), %xmm1
; X64-SSE2-NEXT: movdqu 32(%rdi), %xmm2
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm2
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-SSE2-NEXT: pand %xmm1, %xmm2
; X64-SSE2-NEXT: pand %xmm0, %xmm2
; X64-SSE2-NEXT: pmovmskb %xmm2, %eax
@@ -3338,9 +3338,9 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
; X64-SSE41-NEXT: movdqu 16(%rdi), %xmm1
; X64-SSE41-NEXT: movdqu 32(%rdi), %xmm2
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm2
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-SSE41-NEXT: por %xmm1, %xmm2
; X64-SSE41-NEXT: por %xmm0, %xmm2
; X64-SSE41-NEXT: ptest %xmm2, %xmm2
@@ -3351,8 +3351,8 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 32(%rdi), %xmm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: setne %al
@@ -3363,8 +3363,8 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %xmm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: setne %al
@@ -3375,8 +3375,8 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX512-NEXT: vmovdqu 32(%rdi), %xmm1
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vptest %ymm0, %ymm0
; X64-AVX512-NEXT: setne %al
@@ -3673,12 +3673,12 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE2-NEXT: movdqu 47(%eax), %xmm3
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pand %xmm3, %xmm2
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pand %xmm2, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -3692,12 +3692,12 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE41-NEXT: movdqu 47(%eax), %xmm3
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE41-NEXT: por %xmm3, %xmm2
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: por %xmm2, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al
@@ -3709,12 +3709,12 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-SSE2-NEXT: movdqu 16(%rdi), %xmm1
; X64-SSE2-NEXT: movdqu 32(%rdi), %xmm2
; X64-SSE2-NEXT: movdqu 47(%rdi), %xmm3
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm3
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm2
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-SSE2-NEXT: pand %xmm3, %xmm2
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: pand %xmm2, %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -3727,12 +3727,12 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-SSE41-NEXT: movdqu 16(%rdi), %xmm1
; X64-SSE41-NEXT: movdqu 32(%rdi), %xmm2
; X64-SSE41-NEXT: movdqu 47(%rdi), %xmm3
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm3
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm2
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-SSE41-NEXT: por %xmm3, %xmm2
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE41-NEXT: por %xmm2, %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: sete %al
@@ -3742,8 +3742,8 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 31(%rdi), %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -3754,8 +3754,8 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 31(%rdi), %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
@@ -3766,8 +3766,8 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX512-NEXT: vmovdqu 31(%rdi), %ymm1
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vptest %ymm0, %ymm0
; X64-AVX512-NEXT: sete %al
@@ -4079,12 +4079,12 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE2-NEXT: movdqu 48(%eax), %xmm3
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pand %xmm3, %xmm2
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pand %xmm2, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -4098,12 +4098,12 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE41-NEXT: movdqu 48(%eax), %xmm3
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE41-NEXT: por %xmm3, %xmm2
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: por %xmm2, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al
@@ -4115,12 +4115,12 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-SSE2-NEXT: movdqu 16(%rdi), %xmm1
; X64-SSE2-NEXT: movdqu 32(%rdi), %xmm2
; X64-SSE2-NEXT: movdqu 48(%rdi), %xmm3
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm3
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm2
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-SSE2-NEXT: pand %xmm3, %xmm2
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE2-NEXT: pand %xmm2, %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -4133,12 +4133,12 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-SSE41-NEXT: movdqu 16(%rdi), %xmm1
; X64-SSE41-NEXT: movdqu 32(%rdi), %xmm2
; X64-SSE41-NEXT: movdqu 48(%rdi), %xmm3
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm3
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm2
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-SSE41-NEXT: por %xmm3, %xmm2
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE41-NEXT: por %xmm2, %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: sete %al
@@ -4148,8 +4148,8 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 32(%rdi), %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -4160,8 +4160,8 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
@@ -4171,7 +4171,7 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX512BW-LABEL: length64_eq_const:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k0
; X64-AVX512BW-NEXT: kortestq %k0, %k0
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -4180,7 +4180,7 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX512F-LABEL: length64_eq_const:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
; X64-AVX512F-NEXT: kortestw %k0, %k0
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -4202,7 +4202,7 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F-LABEL: length64_eq_const:
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k0
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -4424,9 +4424,9 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 32(%rdi), %ymm1
; X64-AVX1-NEXT: vmovups 64(%rdi), %ymm2
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm2, %ymm2
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; X64-AVX1-NEXT: vorps %ymm2, %ymm1, %ymm1
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
@@ -4439,9 +4439,9 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
; X64-AVX2-NEXT: vmovdqu 64(%rdi), %ymm2
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm2, %ymm2
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; X64-AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
@@ -4453,8 +4453,8 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512BW-NEXT: vmovdqu 64(%rdi), %ymm1
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm1, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k1
; X64-AVX512BW-NEXT: kortestq %k1, %k0
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -4464,8 +4464,8 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512F-NEXT: vmovdqu 64(%rdi), %ymm1
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm1, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
+; X64-AVX512F-NEXT: vpcmpneqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k1
; X64-AVX512F-NEXT: kortestw %k1, %k0
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -4492,8 +4492,8 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-MIC-AVX512F-NEXT: vmovdqu 64(%rdi), %ymm1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm1, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k1, %k0
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -4723,12 +4723,12 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-AVX1-NEXT: vmovups 32(%rdi), %ymm1
; X64-AVX1-NEXT: vmovups 64(%rdi), %ymm2
; X64-AVX1-NEXT: vmovups 95(%rdi), %ymm3
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm3, %ymm3
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm2, %ymm2
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; X64-AVX1-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX1-NEXT: vorps %ymm2, %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -4741,12 +4741,12 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
; X64-AVX2-NEXT: vmovdqu 64(%rdi), %ymm2
; X64-AVX2-NEXT: vmovdqu 95(%rdi), %ymm3
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm3, %ymm3
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm2, %ymm2
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; X64-AVX2-NEXT: vpor %ymm3, %ymm2, %ymm2
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
@@ -4757,8 +4757,8 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512BW-NEXT: vmovdqu64 63(%rdi), %zmm1
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+63(%rip), %zmm1, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k1
; X64-AVX512BW-NEXT: kortestq %k0, %k1
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -4768,8 +4768,8 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512F-NEXT: vmovdqu64 63(%rdi), %zmm1
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+63(%rip), %zmm1, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-AVX512F-NEXT: kortestw %k0, %k1
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -4800,8 +4800,8 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-MIC-AVX512F-NEXT: vmovdqu64 63(%rdi), %zmm1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+63(%rip), %zmm1, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k1
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -5031,12 +5031,12 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-AVX1-NEXT: vmovups 32(%rdi), %ymm1
; X64-AVX1-NEXT: vmovups 64(%rdi), %ymm2
; X64-AVX1-NEXT: vmovups 96(%rdi), %ymm3
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm3, %ymm3
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm2, %ymm2
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; X64-AVX1-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX1-NEXT: vorps %ymm2, %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -5049,12 +5049,12 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
; X64-AVX2-NEXT: vmovdqu 64(%rdi), %ymm2
; X64-AVX2-NEXT: vmovdqu 96(%rdi), %ymm3
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm3, %ymm3
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm2, %ymm2
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; X64-AVX2-NEXT: vpor %ymm3, %ymm2, %ymm2
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
@@ -5065,8 +5065,8 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512BW-NEXT: vmovdqu64 64(%rdi), %zmm1
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+64(%rip), %zmm1, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k1
; X64-AVX512BW-NEXT: kortestq %k0, %k1
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -5076,8 +5076,8 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-AVX512F-NEXT: kortestw %k0, %k1
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -5108,8 +5108,8 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-MIC-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k1
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -5342,10 +5342,10 @@ define i1 @length192_eq_const(i8* %X) nounwind {
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512BW-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-AVX512BW-NEXT: vmovdqu64 128(%rdi), %zmm2
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+64(%rip), %zmm1, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k1
; X64-AVX512BW-NEXT: korq %k0, %k1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+128(%rip), %zmm2, %k1
; X64-AVX512BW-NEXT: kortestq %k1, %k0
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -5356,10 +5356,10 @@ define i1 @length192_eq_const(i8* %X) nounwind {
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-AVX512F-NEXT: vmovdqu64 128(%rdi), %zmm2
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-AVX512F-NEXT: korw %k0, %k1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+128(%rip), %zmm2, %k1
; X64-AVX512F-NEXT: kortestw %k1, %k0
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -5381,10 +5381,10 @@ define i1 @length192_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-MIC-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-MIC-AVX512F-NEXT: vmovdqu64 128(%rdi), %zmm2
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-MIC-AVX512F-NEXT: korw %k0, %k1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+128(%rip), %zmm2, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k1, %k0
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -5627,11 +5627,11 @@ define i1 @length255_eq_const(i8* %X) nounwind {
; X64-AVX512BW-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-AVX512BW-NEXT: vmovdqu64 128(%rdi), %zmm2
; X64-AVX512BW-NEXT: vmovdqu64 191(%rdi), %zmm3
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm3, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+191(%rip), %zmm3, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+128(%rip), %zmm2, %k1
; X64-AVX512BW-NEXT: korq %k0, %k1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm1, %k1
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k2
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+64(%rip), %zmm1, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k2
; X64-AVX512BW-NEXT: korq %k1, %k2, %k1
; X64-AVX512BW-NEXT: kortestq %k0, %k1
; X64-AVX512BW-NEXT: sete %al
@@ -5644,11 +5644,11 @@ define i1 @length255_eq_const(i8* %X) nounwind {
; X64-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-AVX512F-NEXT: vmovdqu64 128(%rdi), %zmm2
; X64-AVX512F-NEXT: vmovdqu64 191(%rdi), %zmm3
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm3, %k0
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+191(%rip), %zmm3, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+128(%rip), %zmm2, %k1
; X64-AVX512F-NEXT: korw %k0, %k1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k1
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k2
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k2
; X64-AVX512F-NEXT: korw %k1, %k2, %k1
; X64-AVX512F-NEXT: kortestw %k0, %k1
; X64-AVX512F-NEXT: sete %al
@@ -5672,11 +5672,11 @@ define i1 @length255_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-MIC-AVX512F-NEXT: vmovdqu64 128(%rdi), %zmm2
; X64-MIC-AVX512F-NEXT: vmovdqu64 191(%rdi), %zmm3
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm3, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+191(%rip), %zmm3, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+128(%rip), %zmm2, %k1
; X64-MIC-AVX512F-NEXT: korw %k0, %k1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k2
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k2
; X64-MIC-AVX512F-NEXT: korw %k1, %k2, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k1
; X64-MIC-AVX512F-NEXT: sete %al
@@ -5920,11 +5920,11 @@ define i1 @length256_eq_const(i8* %X) nounwind {
; X64-AVX512BW-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-AVX512BW-NEXT: vmovdqu64 128(%rdi), %zmm2
; X64-AVX512BW-NEXT: vmovdqu64 192(%rdi), %zmm3
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm3, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+192(%rip), %zmm3, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+128(%rip), %zmm2, %k1
; X64-AVX512BW-NEXT: korq %k0, %k1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm1, %k1
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k2
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+64(%rip), %zmm1, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k2
; X64-AVX512BW-NEXT: korq %k1, %k2, %k1
; X64-AVX512BW-NEXT: kortestq %k0, %k1
; X64-AVX512BW-NEXT: sete %al
@@ -5937,11 +5937,11 @@ define i1 @length256_eq_const(i8* %X) nounwind {
; X64-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-AVX512F-NEXT: vmovdqu64 128(%rdi), %zmm2
; X64-AVX512F-NEXT: vmovdqu64 192(%rdi), %zmm3
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm3, %k0
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+192(%rip), %zmm3, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+128(%rip), %zmm2, %k1
; X64-AVX512F-NEXT: korw %k0, %k1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k1
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k2
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k2
; X64-AVX512F-NEXT: korw %k1, %k2, %k1
; X64-AVX512F-NEXT: kortestw %k0, %k1
; X64-AVX512F-NEXT: sete %al
@@ -5965,11 +5965,11 @@ define i1 @length256_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
; X64-MIC-AVX512F-NEXT: vmovdqu64 128(%rdi), %zmm2
; X64-MIC-AVX512F-NEXT: vmovdqu64 192(%rdi), %zmm3
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm3, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm2, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+192(%rip), %zmm3, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+128(%rip), %zmm2, %k1
; X64-MIC-AVX512F-NEXT: korw %k0, %k1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k2
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k2
; X64-MIC-AVX512F-NEXT: korw %k1, %k2, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k1
; X64-MIC-AVX512F-NEXT: sete %al
diff --git a/llvm/test/CodeGen/X86/memcmp-optsize.ll b/llvm/test/CodeGen/X86/memcmp-optsize.ll
index 1d67355d6ff43..ab5cc93ca41c2 100644
--- a/llvm/test/CodeGen/X86/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/X86/memcmp-optsize.ll
@@ -590,7 +590,7 @@ define i1 @length16_eq_const(i8* %X) nounwind optsize {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al
@@ -599,7 +599,7 @@ define i1 @length16_eq_const(i8* %X) nounwind optsize {
; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X64-SSE2-NEXT: sete %al
@@ -608,7 +608,7 @@ define i1 @length16_eq_const(i8* %X) nounwind optsize {
; X64-AVX-LABEL: length16_eq_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: sete %al
; X64-AVX-NEXT: retq
@@ -715,8 +715,8 @@ define i1 @length24_eq_const(i8* %X) nounwind optsize {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -727,8 +727,8 @@ define i1 @length24_eq_const(i8* %X) nounwind optsize {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -739,8 +739,8 @@ define i1 @length24_eq_const(i8* %X) nounwind optsize {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
; X64-AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: setne %al
@@ -854,8 +854,8 @@ define i1 @length32_eq_const(i8* %X) nounwind optsize {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -866,8 +866,8 @@ define i1 @length32_eq_const(i8* %X) nounwind optsize {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movdqu 16(%rdi), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -877,7 +877,7 @@ define i1 @length32_eq_const(i8* %X) nounwind optsize {
; X64-AVX1-LABEL: length32_eq_const:
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: setne %al
; X64-AVX1-NEXT: vzeroupper
@@ -886,7 +886,7 @@ define i1 @length32_eq_const(i8* %X) nounwind optsize {
; X64-AVX2-LABEL: length32_eq_const:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: setne %al
; X64-AVX2-NEXT: vzeroupper
@@ -994,8 +994,8 @@ define i1 @length64_eq_const(i8* %X) nounwind optsize {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 32(%rdi), %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -1006,8 +1006,8 @@ define i1 @length64_eq_const(i8* %X) nounwind optsize {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
diff --git a/llvm/test/CodeGen/X86/memcmp-pgso.ll b/llvm/test/CodeGen/X86/memcmp-pgso.ll
index 7ea412e893ca9..b39f0d70a56b9 100644
--- a/llvm/test/CodeGen/X86/memcmp-pgso.ll
+++ b/llvm/test/CodeGen/X86/memcmp-pgso.ll
@@ -590,7 +590,7 @@ define i1 @length16_eq_const(i8* %X) nounwind !prof !14 {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al
@@ -599,7 +599,7 @@ define i1 @length16_eq_const(i8* %X) nounwind !prof !14 {
; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X64-SSE2-NEXT: sete %al
@@ -608,7 +608,7 @@ define i1 @length16_eq_const(i8* %X) nounwind !prof !14 {
; X64-AVX-LABEL: length16_eq_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: sete %al
; X64-AVX-NEXT: retq
@@ -715,8 +715,8 @@ define i1 @length24_eq_const(i8* %X) nounwind !prof !14 {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -727,8 +727,8 @@ define i1 @length24_eq_const(i8* %X) nounwind !prof !14 {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -739,8 +739,8 @@ define i1 @length24_eq_const(i8* %X) nounwind !prof !14 {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
; X64-AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: setne %al
@@ -854,8 +854,8 @@ define i1 @length32_eq_const(i8* %X) nounwind !prof !14 {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -866,8 +866,8 @@ define i1 @length32_eq_const(i8* %X) nounwind !prof !14 {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movdqu 16(%rdi), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -877,7 +877,7 @@ define i1 @length32_eq_const(i8* %X) nounwind !prof !14 {
; X64-AVX1-LABEL: length32_eq_const:
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: setne %al
; X64-AVX1-NEXT: vzeroupper
@@ -886,7 +886,7 @@ define i1 @length32_eq_const(i8* %X) nounwind !prof !14 {
; X64-AVX2-LABEL: length32_eq_const:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: setne %al
; X64-AVX2-NEXT: vzeroupper
@@ -994,8 +994,8 @@ define i1 @length64_eq_const(i8* %X) nounwind !prof !14 {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 32(%rdi), %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -1006,8 +1006,8 @@ define i1 @length64_eq_const(i8* %X) nounwind !prof !14 {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
diff --git a/llvm/test/CodeGen/X86/memcmp.ll b/llvm/test/CodeGen/X86/memcmp.ll
index e05573544335f..d498d85711f80 100644
--- a/llvm/test/CodeGen/X86/memcmp.ll
+++ b/llvm/test/CodeGen/X86/memcmp.ll
@@ -1485,7 +1485,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al
@@ -1495,7 +1495,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al
; X86-SSE41-NEXT: retl
@@ -1503,7 +1503,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X64-SSE2-NEXT: sete %al
@@ -1512,7 +1512,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X64-SSE41-LABEL: length16_eq_const:
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: sete %al
; X64-SSE41-NEXT: retq
@@ -1520,7 +1520,7 @@ define i1 @length16_eq_const(i8* %X) nounwind {
; X64-AVX-LABEL: length16_eq_const:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: sete %al
; X64-AVX-NEXT: retq
@@ -1756,8 +1756,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -1769,8 +1769,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 8(%eax), %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al
@@ -1780,8 +1780,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -1792,8 +1792,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
; X64-SSE41-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: setne %al
@@ -1803,8 +1803,8 @@ define i1 @length24_eq_const(i8* %X) nounwind {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
; X64-AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: setne %al
@@ -2152,8 +2152,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 15(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2165,8 +2165,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 15(%eax), %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al
@@ -2176,8 +2176,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movdqu 15(%rdi), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2188,8 +2188,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
; X64-SSE41-NEXT: movdqu 15(%rdi), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: setne %al
@@ -2199,8 +2199,8 @@ define i1 @length31_eq_const(i8* %X) nounwind {
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
; X64-AVX-NEXT: vmovdqu 15(%rdi), %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vptest %xmm0, %xmm0
; X64-AVX-NEXT: setne %al
@@ -2563,8 +2563,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2576,8 +2576,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al
@@ -2587,8 +2587,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: movdqu 16(%rdi), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm1
-; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE2-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: pand %xmm1, %xmm0
; X64-SSE2-NEXT: pmovmskb %xmm0, %eax
; X64-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -2599,8 +2599,8 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: movdqu (%rdi), %xmm0
; X64-SSE41-NEXT: movdqu 16(%rdi), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; X64-SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE41-NEXT: por %xmm1, %xmm0
; X64-SSE41-NEXT: ptest %xmm0, %xmm0
; X64-SSE41-NEXT: setne %al
@@ -2609,7 +2609,7 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-AVX1-LABEL: length32_eq_const:
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: setne %al
; X64-AVX1-NEXT: vzeroupper
@@ -2618,7 +2618,7 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-AVX2-LABEL: length32_eq_const:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: setne %al
; X64-AVX2-NEXT: vzeroupper
@@ -2627,7 +2627,7 @@ define i1 @length32_eq_const(i8* %X) nounwind {
; X64-AVX512-LABEL: length32_eq_const:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vmovdqu (%rdi), %ymm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: vptest %ymm0, %ymm0
; X64-AVX512-NEXT: setne %al
; X64-AVX512-NEXT: vzeroupper
@@ -2854,8 +2854,8 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 32(%rdi), %xmm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: setne %al
@@ -2866,8 +2866,8 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %xmm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: setne %al
@@ -2878,8 +2878,8 @@ define i1 @length48_eq_const(i8* %X) nounwind {
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX512-NEXT: vmovdqu 32(%rdi), %xmm1
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vptest %ymm0, %ymm0
; X64-AVX512-NEXT: setne %al
@@ -3080,8 +3080,8 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 31(%rdi), %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -3092,8 +3092,8 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 31(%rdi), %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
@@ -3104,8 +3104,8 @@ define i1 @length63_eq_const(i8* %X) nounwind {
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX512-NEXT: vmovdqu 31(%rdi), %ymm1
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vptest %ymm0, %ymm0
; X64-AVX512-NEXT: sete %al
@@ -3321,8 +3321,8 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovups (%rdi), %ymm0
; X64-AVX1-NEXT: vmovups 32(%rdi), %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX1-NEXT: vptest %ymm0, %ymm0
; X64-AVX1-NEXT: sete %al
@@ -3333,8 +3333,8 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqu (%rdi), %ymm0
; X64-AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm1, %ymm1
-; X64-AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vptest %ymm0, %ymm0
; X64-AVX2-NEXT: sete %al
@@ -3344,7 +3344,7 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX512BW-LABEL: length64_eq_const:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k0
; X64-AVX512BW-NEXT: kortestq %k0, %k0
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -3353,7 +3353,7 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-AVX512F-LABEL: length64_eq_const:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
; X64-AVX512F-NEXT: kortestw %k0, %k0
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -3375,7 +3375,7 @@ define i1 @length64_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F-LABEL: length64_eq_const:
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k0
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -3601,8 +3601,8 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512BW-NEXT: vmovdqu 64(%rdi), %ymm1
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm1, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k1
; X64-AVX512BW-NEXT: kortestq %k1, %k0
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -3612,8 +3612,8 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512F-NEXT: vmovdqu 64(%rdi), %ymm1
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm1, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
+; X64-AVX512F-NEXT: vpcmpneqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k1
; X64-AVX512F-NEXT: kortestw %k1, %k0
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -3634,8 +3634,8 @@ define i1 @length96_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-MIC-AVX512F-NEXT: vmovdqu 64(%rdi), %ymm1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm1, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k1, %k0
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -3858,8 +3858,8 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512BW-NEXT: vmovdqu64 63(%rdi), %zmm1
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+63(%rip), %zmm1, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k1
; X64-AVX512BW-NEXT: kortestq %k0, %k1
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -3869,8 +3869,8 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512F-NEXT: vmovdqu64 63(%rdi), %zmm1
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+63(%rip), %zmm1, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-AVX512F-NEXT: kortestw %k0, %k1
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -3891,8 +3891,8 @@ define i1 @length127_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-MIC-AVX512F-NEXT: vmovdqu64 63(%rdi), %zmm1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+63(%rip), %zmm1, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k1
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
@@ -4115,8 +4115,8 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512BW-NEXT: vmovdqu64 64(%rdi), %zmm1
-; X64-AVX512BW-NEXT: vpcmpneqb .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512BW-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str+64(%rip), %zmm1, %k0
+; X64-AVX512BW-NEXT: vpcmpneqb .L.str(%rip), %zmm0, %k1
; X64-AVX512BW-NEXT: kortestq %k0, %k1
; X64-AVX512BW-NEXT: sete %al
; X64-AVX512BW-NEXT: vzeroupper
@@ -4126,8 +4126,8 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
-; X64-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k0
+; X64-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-AVX512F-NEXT: kortestw %k0, %k1
; X64-AVX512F-NEXT: sete %al
; X64-AVX512F-NEXT: vzeroupper
@@ -4148,8 +4148,8 @@ define i1 @length128_eq_const(i8* %X) nounwind {
; X64-MIC-AVX512F: # %bb.0:
; X64-MIC-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; X64-MIC-AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
-; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+{{.*}}(%rip), %zmm1, %k0
-; X64-MIC-AVX512F-NEXT: vpcmpneqd {{.*}}(%rip), %zmm0, %k1
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str+64(%rip), %zmm1, %k0
+; X64-MIC-AVX512F-NEXT: vpcmpneqd .L.str(%rip), %zmm0, %k1
; X64-MIC-AVX512F-NEXT: kortestw %k0, %k1
; X64-MIC-AVX512F-NEXT: sete %al
; X64-MIC-AVX512F-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll b/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll
index 77e97626b1c60..98deed1cf6389 100644
--- a/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll
+++ b/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll
@@ -9,11 +9,11 @@
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
define void @test1(i8* %a, i8* %b, i64 %s) nounwind {
-; NOFSRM-LABEL: test1
+; NOFSRM-LABEL: test1:
; NOFSRM: # %bb.0:
-; NOFSRM: jmp memcpy
+; NOFSRM-NEXT: jmp memcpy at PLT # TAILCALL
;
-; FSRM-LABEL: test1
+; FSRM-LABEL: test1:
; FSRM: # %bb.0:
; FSRM-NEXT: movq %rdx, %rcx
; FSRM-NEXT: rep;movsb (%rsi), %es:(%rdi)
diff --git a/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll b/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll
index bca99064d5d17..a1cdf82befede 100644
--- a/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll
+++ b/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll
@@ -24,7 +24,7 @@ define void @test1(%struct.large* nocapture %x) nounwind {
; NOFAST32-NEXT: movl $1024, %ecx # imm = 0x400
; NOFAST32-NEXT: movl %esp, %edi
; NOFAST32-NEXT: rep;movsl (%esi), %es:(%edi)
-; NOFAST32-NEXT: calll foo
+; NOFAST32-NEXT: calll foo at PLT
; NOFAST32-NEXT: addl $4100, %esp # imm = 0x1004
; NOFAST32-NEXT: popl %esi
; NOFAST32-NEXT: popl %edi
@@ -39,7 +39,7 @@ define void @test1(%struct.large* nocapture %x) nounwind {
; FAST32-NEXT: movl $4096, %ecx # imm = 0x1000
; FAST32-NEXT: movl %esp, %edi
; FAST32-NEXT: rep;movsb (%esi), %es:(%edi)
-; FAST32-NEXT: calll foo
+; FAST32-NEXT: calll foo at PLT
; FAST32-NEXT: addl $4100, %esp # imm = 0x1004
; FAST32-NEXT: popl %esi
; FAST32-NEXT: popl %edi
@@ -52,7 +52,7 @@ define void @test1(%struct.large* nocapture %x) nounwind {
; NOFAST-NEXT: movl $512, %ecx # imm = 0x200
; NOFAST-NEXT: movq %rsp, %rdi
; NOFAST-NEXT: rep;movsq (%rsi), %es:(%rdi)
-; NOFAST-NEXT: callq foo
+; NOFAST-NEXT: callq foo at PLT
; NOFAST-NEXT: addq $4104, %rsp # imm = 0x1008
; NOFAST-NEXT: retq
;
@@ -63,7 +63,7 @@ define void @test1(%struct.large* nocapture %x) nounwind {
; FAST-NEXT: movl $4096, %ecx # imm = 0x1000
; FAST-NEXT: movq %rsp, %rdi
; FAST-NEXT: rep;movsb (%rsi), %es:(%rdi)
-; FAST-NEXT: callq foo
+; FAST-NEXT: callq foo at PLT
; FAST-NEXT: addq $4104, %rsp # imm = 0x1008
; FAST-NEXT: retq
call void @foo(%struct.large* align 8 byval(%struct.large) %x)
@@ -81,7 +81,7 @@ define void @test2(%struct.large* nocapture %x) nounwind minsize {
; NOFAST32-NEXT: movl $1024, %ecx # imm = 0x400
; NOFAST32-NEXT: movl %esp, %edi
; NOFAST32-NEXT: rep;movsl (%esi), %es:(%edi)
-; NOFAST32-NEXT: calll foo
+; NOFAST32-NEXT: calll foo at PLT
; NOFAST32-NEXT: addl $4100, %esp # imm = 0x1004
; NOFAST32-NEXT: popl %esi
; NOFAST32-NEXT: popl %edi
@@ -96,7 +96,7 @@ define void @test2(%struct.large* nocapture %x) nounwind minsize {
; FAST32-NEXT: movl $4096, %ecx # imm = 0x1000
; FAST32-NEXT: movl %esp, %edi
; FAST32-NEXT: rep;movsb (%esi), %es:(%edi)
-; FAST32-NEXT: calll foo
+; FAST32-NEXT: calll foo at PLT
; FAST32-NEXT: addl $4100, %esp # imm = 0x1004
; FAST32-NEXT: popl %esi
; FAST32-NEXT: popl %edi
@@ -109,7 +109,7 @@ define void @test2(%struct.large* nocapture %x) nounwind minsize {
; NOFAST-NEXT: movl $512, %ecx # imm = 0x200
; NOFAST-NEXT: movq %rsp, %rdi
; NOFAST-NEXT: rep;movsq (%rsi), %es:(%rdi)
-; NOFAST-NEXT: callq foo
+; NOFAST-NEXT: callq foo at PLT
; NOFAST-NEXT: addq $4104, %rsp # imm = 0x1008
; NOFAST-NEXT: retq
;
@@ -120,7 +120,7 @@ define void @test2(%struct.large* nocapture %x) nounwind minsize {
; FAST-NEXT: movl $4096, %ecx # imm = 0x1000
; FAST-NEXT: movq %rsp, %rdi
; FAST-NEXT: rep;movsb (%rsi), %es:(%rdi)
-; FAST-NEXT: callq foo
+; FAST-NEXT: callq foo at PLT
; FAST-NEXT: addq $4104, %rsp # imm = 0x1008
; FAST-NEXT: retq
call void @foo(%struct.large* align 8 byval(%struct.large) %x)
@@ -142,7 +142,7 @@ define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize {
; NOFAST32-NEXT: movl $4095, %ecx # imm = 0xFFF
; NOFAST32-NEXT: movl %esp, %edi
; NOFAST32-NEXT: rep;movsb (%esi), %es:(%edi)
-; NOFAST32-NEXT: calll foo_oddsize
+; NOFAST32-NEXT: calll foo_oddsize at PLT
; NOFAST32-NEXT: addl $4100, %esp # imm = 0x1004
; NOFAST32-NEXT: popl %esi
; NOFAST32-NEXT: popl %edi
@@ -157,7 +157,7 @@ define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize {
; FAST32-NEXT: movl $4095, %ecx # imm = 0xFFF
; FAST32-NEXT: movl %esp, %edi
; FAST32-NEXT: rep;movsb (%esi), %es:(%edi)
-; FAST32-NEXT: calll foo_oddsize
+; FAST32-NEXT: calll foo_oddsize at PLT
; FAST32-NEXT: addl $4100, %esp # imm = 0x1004
; FAST32-NEXT: popl %esi
; FAST32-NEXT: popl %edi
@@ -170,7 +170,7 @@ define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize {
; NOFAST-NEXT: movl $4095, %ecx # imm = 0xFFF
; NOFAST-NEXT: movq %rsp, %rdi
; NOFAST-NEXT: rep;movsb (%rsi), %es:(%rdi)
-; NOFAST-NEXT: callq foo_oddsize
+; NOFAST-NEXT: callq foo_oddsize at PLT
; NOFAST-NEXT: addq $4104, %rsp # imm = 0x1008
; NOFAST-NEXT: retq
;
@@ -181,7 +181,7 @@ define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize {
; FAST-NEXT: movl $4095, %ecx # imm = 0xFFF
; FAST-NEXT: movq %rsp, %rdi
; FAST-NEXT: rep;movsb (%rsi), %es:(%rdi)
-; FAST-NEXT: callq foo_oddsize
+; FAST-NEXT: callq foo_oddsize at PLT
; FAST-NEXT: addq $4104, %rsp # imm = 0x1008
; FAST-NEXT: retq
call void @foo_oddsize(%struct.large_oddsize* align 8 byval(%struct.large_oddsize) %x)
diff --git a/llvm/test/CodeGen/X86/memcpy.ll b/llvm/test/CodeGen/X86/memcpy.ll
index 11c92fa2a2af0..aa27771a37bb0 100644
--- a/llvm/test/CodeGen/X86/memcpy.ll
+++ b/llvm/test/CodeGen/X86/memcpy.ll
@@ -140,11 +140,6 @@ entry:
}
define void @test3_pgso(i8* nocapture %A, i8* nocapture %B) nounwind noredzone !prof !14 {
-; LINUX-LABEL: test3_pgso:
-; LINUX: # %bb.0: # %entry
-; LINUX-NEXT: movl $64, %edx
-; LINUX-NEXT: jmp memcpy at PLT # TAILCALL
-;
; DARWIN-LABEL: test3_pgso:
; DARWIN: ## %bb.0: ## %entry
; DARWIN-NEXT: movq 56(%rsi), %rax
@@ -164,6 +159,42 @@ define void @test3_pgso(i8* nocapture %A, i8* nocapture %B) nounwind noredzone !
; DARWIN-NEXT: movq %rcx, 8(%rdi)
; DARWIN-NEXT: movq %rax, (%rdi)
; DARWIN-NEXT: retq
+;
+; LINUX-LABEL: test3_pgso:
+; LINUX: # %bb.0: # %entry
+; LINUX-NEXT: movl $64, %edx
+; LINUX-NEXT: jmp memcpy at PLT # TAILCALL
+;
+; LINUX-SKL-LABEL: test3_pgso:
+; LINUX-SKL: # %bb.0: # %entry
+; LINUX-SKL-NEXT: vmovups (%rsi), %ymm0
+; LINUX-SKL-NEXT: vmovups 32(%rsi), %ymm1
+; LINUX-SKL-NEXT: vmovups %ymm1, 32(%rdi)
+; LINUX-SKL-NEXT: vmovups %ymm0, (%rdi)
+; LINUX-SKL-NEXT: vzeroupper
+; LINUX-SKL-NEXT: retq
+;
+; LINUX-SKX-LABEL: test3_pgso:
+; LINUX-SKX: # %bb.0: # %entry
+; LINUX-SKX-NEXT: vmovups (%rsi), %ymm0
+; LINUX-SKX-NEXT: vmovups 32(%rsi), %ymm1
+; LINUX-SKX-NEXT: vmovups %ymm1, 32(%rdi)
+; LINUX-SKX-NEXT: vmovups %ymm0, (%rdi)
+; LINUX-SKX-NEXT: vzeroupper
+; LINUX-SKX-NEXT: retq
+;
+; LINUX-KNL-LABEL: test3_pgso:
+; LINUX-KNL: # %bb.0: # %entry
+; LINUX-KNL-NEXT: vmovups (%rsi), %zmm0
+; LINUX-KNL-NEXT: vmovups %zmm0, (%rdi)
+; LINUX-KNL-NEXT: retq
+;
+; LINUX-AVX512BW-LABEL: test3_pgso:
+; LINUX-AVX512BW: # %bb.0: # %entry
+; LINUX-AVX512BW-NEXT: vmovups (%rsi), %zmm0
+; LINUX-AVX512BW-NEXT: vmovups %zmm0, (%rdi)
+; LINUX-AVX512BW-NEXT: vzeroupper
+; LINUX-AVX512BW-NEXT: retq
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i1 false)
ret void
@@ -362,25 +393,25 @@ define void @test5(i8* nocapture %C) nounwind uwtable ssp {
;
; LINUX-SKL-LABEL: test5:
; LINUX-SKL: # %bb.0: # %entry
-; LINUX-SKL-NEXT: vmovups {{.*}}(%rip), %xmm0
+; LINUX-SKL-NEXT: vmovups .L.str(%rip), %xmm0
; LINUX-SKL-NEXT: vmovups %xmm0, (%rdi)
; LINUX-SKL-NEXT: retq
;
; LINUX-SKX-LABEL: test5:
; LINUX-SKX: # %bb.0: # %entry
-; LINUX-SKX-NEXT: vmovups {{.*}}(%rip), %xmm0
+; LINUX-SKX-NEXT: vmovups .L.str(%rip), %xmm0
; LINUX-SKX-NEXT: vmovups %xmm0, (%rdi)
; LINUX-SKX-NEXT: retq
;
; LINUX-KNL-LABEL: test5:
; LINUX-KNL: # %bb.0: # %entry
-; LINUX-KNL-NEXT: vmovups {{.*}}(%rip), %xmm0
+; LINUX-KNL-NEXT: vmovups .L.str(%rip), %xmm0
; LINUX-KNL-NEXT: vmovups %xmm0, (%rdi)
; LINUX-KNL-NEXT: retq
;
; LINUX-AVX512BW-LABEL: test5:
; LINUX-AVX512BW: # %bb.0: # %entry
-; LINUX-AVX512BW-NEXT: vmovups {{.*}}(%rip), %xmm0
+; LINUX-AVX512BW-NEXT: vmovups .L.str(%rip), %xmm0
; LINUX-AVX512BW-NEXT: vmovups %xmm0, (%rdi)
; LINUX-AVX512BW-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/memset-nonzero.ll b/llvm/test/CodeGen/X86/memset-nonzero.ll
index 84f084fedb572..4fad3a2de1a23 100644
--- a/llvm/test/CodeGen/X86/memset-nonzero.ll
+++ b/llvm/test/CodeGen/X86/memset-nonzero.ll
@@ -200,7 +200,7 @@ define void @memset_256_nonzero_bytes(i8* %x) {
; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: movl $256, %edx # imm = 0x100
; SSE-NEXT: movl $42, %esi
-; SSE-NEXT: callq memset
+; SSE-NEXT: callq memset at PLT
; SSE-NEXT: popq %rax
; SSE-NEXT: .cfi_def_cfa_offset 8
; SSE-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll b/llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll
index 7e0f3b7cbfb00..c02844ceb6175 100644
--- a/llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll
+++ b/llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll
@@ -494,14 +494,14 @@ define <16 x i16> @merge_16i16_i16_0uu3zzuuuuuzCuEF(i16* %ptr) nounwind uwtable
; AVX-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF:
; AVX: # %bb.0:
; AVX-NEXT: vmovups (%rdi), %ymm0
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
;
; X86-AVX-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: vmovups (%eax), %ymm0
-; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX-NEXT: retl
%ptr0 = getelementptr inbounds i16, i16* %ptr, i64 0
%ptr3 = getelementptr inbounds i16, i16* %ptr, i64 3
@@ -680,7 +680,7 @@ define <16 x i16> @merge_16i16_i16_0uu3zzuuuuuzCuEF_volatile(i16* %ptr) nounwind
define <2 x i8> @PR42846(<2 x i8>* %j, <2 x i8> %k) {
; AVX-LABEL: PR42846:
; AVX: # %bb.0:
-; AVX-NEXT: vmovdqa {{.*}}(%rip), %ymm0
+; AVX-NEXT: vmovdqa l(%rip), %ymm0
; AVX-NEXT: vpextrw $0, %xmm0, (%rdi)
; AVX-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll b/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll
index d24a710746d35..a0818e96bf215 100644
--- a/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll
+++ b/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll
@@ -131,14 +131,14 @@ define <8 x double> @merge_8f64_f64_1u3u5zu8(double* %ptr) nounwind uwtable noin
; ALL-LABEL: merge_8f64_f64_1u3u5zu8:
; ALL: # %bb.0:
; ALL-NEXT: vmovdqu64 8(%rdi), %zmm0
-; ALL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; ALL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; ALL-NEXT: retq
;
; X86-AVX512F-LABEL: merge_8f64_f64_1u3u5zu8:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: vmovdqu64 8(%eax), %zmm0
-; X86-AVX512F-NEXT: vpandq {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
+; X86-AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds double, double* %ptr, i64 1
%ptr2 = getelementptr inbounds double, double* %ptr, i64 3
@@ -210,14 +210,14 @@ define <8 x i64> @merge_8i64_i64_1u3u5zu8(i64* %ptr) nounwind uwtable noinline s
; ALL-LABEL: merge_8i64_i64_1u3u5zu8:
; ALL: # %bb.0:
; ALL-NEXT: vmovdqu64 8(%rdi), %zmm0
-; ALL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; ALL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; ALL-NEXT: retq
;
; X86-AVX512F-LABEL: merge_8i64_i64_1u3u5zu8:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: vmovdqu64 8(%eax), %zmm0
-; X86-AVX512F-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
+; X86-AVX512F-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i64, i64* %ptr, i64 1
%ptr2 = getelementptr inbounds i64, i64* %ptr, i64 3
@@ -429,14 +429,14 @@ define <16 x i32> @merge_16i32_i32_0uu3zzuuuuuzCuEF(i32* %ptr) nounwind uwtable
; ALL-LABEL: merge_16i32_i32_0uu3zzuuuuuzCuEF:
; ALL: # %bb.0:
; ALL-NEXT: vmovdqu64 (%rdi), %zmm0
-; ALL-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
+; ALL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; ALL-NEXT: retq
;
; X86-AVX512F-LABEL: merge_16i32_i32_0uu3zzuuuuuzCuEF:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: vmovdqu64 (%eax), %zmm0
-; X86-AVX512F-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
+; X86-AVX512F-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 0
%ptr3 = getelementptr inbounds i32, i32* %ptr, i64 3
diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
index 8ef3f307d0b58..d421516cd3009 100644
--- a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
+++ b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
@@ -55,7 +55,7 @@ define <4 x i32> @vec128_i32_signed_reg_reg(<4 x i32> %a1, <4 x i32> %a2) nounwi
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
-; SSE41-NEXT: por {{.*}}(%rip), %xmm2
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: pminsd %xmm1, %xmm3
; SSE41-NEXT: pmaxsd %xmm0, %xmm1
@@ -69,7 +69,7 @@ define <4 x i32> @vec128_i32_signed_reg_reg(<4 x i32> %a1, <4 x i32> %a2) nounwi
; AVX1-FALLBACK-LABEL: vec128_i32_signed_reg_reg:
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -94,7 +94,7 @@ define <4 x i32> @vec128_i32_signed_reg_reg(<4 x i32> %a1, <4 x i32> %a2) nounwi
; XOP-FALLBACK-LABEL: vec128_i32_signed_reg_reg:
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vpcomgtd %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -105,7 +105,7 @@ define <4 x i32> @vec128_i32_signed_reg_reg(<4 x i32> %a1, <4 x i32> %a2) nounwi
; XOPAVX1-LABEL: vec128_i32_signed_reg_reg:
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vpcomgtd %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -223,7 +223,7 @@ define <4 x i32> @vec128_i32_unsigned_reg_reg(<4 x i32> %a1, <4 x i32> %a2) noun
; SSE41-NEXT: pcmpeqd %xmm2, %xmm3
; SSE41-NEXT: pcmpeqd %xmm4, %xmm4
; SSE41-NEXT: pxor %xmm3, %xmm4
-; SSE41-NEXT: por {{.*}}(%rip), %xmm4
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: pmaxud %xmm0, %xmm1
; SSE41-NEXT: psubd %xmm2, %xmm1
; SSE41-NEXT: psrld $1, %xmm1
@@ -237,7 +237,7 @@ define <4 x i32> @vec128_i32_unsigned_reg_reg(<4 x i32> %a1, <4 x i32> %a2) noun
; AVX1-FALLBACK-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
; AVX1-FALLBACK-NEXT: vpxor %xmm4, %xmm3, %xmm3
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxud %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubd %xmm2, %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpsrld $1, %xmm1, %xmm1
@@ -263,7 +263,7 @@ define <4 x i32> @vec128_i32_unsigned_reg_reg(<4 x i32> %a1, <4 x i32> %a2) noun
; XOP-FALLBACK-LABEL: vec128_i32_unsigned_reg_reg:
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vpcomgtud %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminud %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxud %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -274,7 +274,7 @@ define <4 x i32> @vec128_i32_unsigned_reg_reg(<4 x i32> %a1, <4 x i32> %a2) noun
; XOPAVX1-LABEL: vec128_i32_unsigned_reg_reg:
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vpcomgtud %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminud %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -389,7 +389,7 @@ define <4 x i32> @vec128_i32_signed_mem_reg(<4 x i32>* %a1_addr, <4 x i32> %a2)
; SSE41-NEXT: movdqa (%rdi), %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE41-NEXT: por {{.*}}(%rip), %xmm2
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: pminsd %xmm0, %xmm3
; SSE41-NEXT: pmaxsd %xmm1, %xmm0
@@ -403,7 +403,7 @@ define <4 x i32> @vec128_i32_signed_mem_reg(<4 x i32>* %a1_addr, <4 x i32> %a2)
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsd %xmm0, %xmm1, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsd %xmm0, %xmm1, %xmm0
; AVX1-FALLBACK-NEXT: vpsubd %xmm3, %xmm0, %xmm0
@@ -430,7 +430,7 @@ define <4 x i32> @vec128_i32_signed_mem_reg(<4 x i32>* %a1_addr, <4 x i32> %a2)
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; XOP-FALLBACK-NEXT: vpcomgtd %xmm0, %xmm1, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsd %xmm0, %xmm1, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsd %xmm0, %xmm1, %xmm0
; XOP-FALLBACK-NEXT: vpsubd %xmm3, %xmm0, %xmm0
@@ -442,7 +442,7 @@ define <4 x i32> @vec128_i32_signed_mem_reg(<4 x i32>* %a1_addr, <4 x i32> %a2)
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vmovdqa (%rdi), %xmm1
; XOPAVX1-NEXT: vpcomgtd %xmm0, %xmm1, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsd %xmm0, %xmm1, %xmm3
; XOPAVX1-NEXT: vpmaxsd %xmm0, %xmm1, %xmm0
; XOPAVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0
@@ -558,7 +558,7 @@ define <4 x i32> @vec128_i32_signed_reg_mem(<4 x i32> %a1, <4 x i32>* %a2_addr)
; SSE41-NEXT: movdqa (%rdi), %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: pcmpgtd %xmm2, %xmm1
-; SSE41-NEXT: por {{.*}}(%rip), %xmm1
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: pminsd %xmm2, %xmm3
; SSE41-NEXT: pmaxsd %xmm0, %xmm2
@@ -573,7 +573,7 @@ define <4 x i32> @vec128_i32_signed_reg_mem(<4 x i32> %a1, <4 x i32>* %a2_addr)
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -600,7 +600,7 @@ define <4 x i32> @vec128_i32_signed_reg_mem(<4 x i32> %a1, <4 x i32>* %a2_addr)
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; XOP-FALLBACK-NEXT: vpcomgtd %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -612,7 +612,7 @@ define <4 x i32> @vec128_i32_signed_reg_mem(<4 x i32> %a1, <4 x i32>* %a2_addr)
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vmovdqa (%rdi), %xmm1
; XOPAVX1-NEXT: vpcomgtd %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -730,7 +730,7 @@ define <4 x i32> @vec128_i32_signed_mem_mem(<4 x i32>* %a1_addr, <4 x i32>* %a2_
; SSE41-NEXT: movdqa (%rsi), %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE41-NEXT: por {{.*}}(%rip), %xmm2
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: pminsd %xmm0, %xmm3
; SSE41-NEXT: pmaxsd %xmm1, %xmm0
@@ -745,7 +745,7 @@ define <4 x i32> @vec128_i32_signed_mem_mem(<4 x i32>* %a1_addr, <4 x i32>* %a2_
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -774,7 +774,7 @@ define <4 x i32> @vec128_i32_signed_mem_mem(<4 x i32>* %a1_addr, <4 x i32>* %a2_
; XOP-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; XOP-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; XOP-FALLBACK-NEXT: vpcomgtd %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -787,7 +787,7 @@ define <4 x i32> @vec128_i32_signed_mem_mem(<4 x i32>* %a1_addr, <4 x i32>* %a2_
; XOPAVX1-NEXT: vmovdqa (%rdi), %xmm0
; XOPAVX1-NEXT: vmovdqa (%rsi), %xmm1
; XOPAVX1-NEXT: vpcomgtd %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
@@ -968,7 +968,7 @@ define <2 x i64> @vec128_i64_signed_reg_reg(<2 x i64> %a1, <2 x i64> %a2) nounwi
; AVX1-FALLBACK-LABEL: vec128_i64_signed_reg_reg:
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -988,7 +988,7 @@ define <2 x i64> @vec128_i64_signed_reg_reg(<2 x i64> %a1, <2 x i64> %a2) nounwi
; AVX2-FALLBACK-LABEL: vec128_i64_signed_reg_reg:
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1008,7 +1008,7 @@ define <2 x i64> @vec128_i64_signed_reg_reg(<2 x i64> %a1, <2 x i64> %a2) nounwi
; XOP-LABEL: vec128_i64_signed_reg_reg:
; XOP: # %bb.0:
; XOP-NEXT: vpcomgtq %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; XOP-NEXT: vpcomltq %xmm1, %xmm0, %xmm4
; XOP-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; XOP-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1198,7 +1198,7 @@ define <2 x i64> @vec128_i64_unsigned_reg_reg(<2 x i64> %a1, <2 x i64> %a2) noun
; AVX1-FALLBACK-NEXT: vpxor %xmm2, %xmm1, %xmm3
; AVX1-FALLBACK-NEXT: vpxor %xmm2, %xmm0, %xmm2
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm4
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm4, %xmm5
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm5
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
; AVX1-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm2
; AVX1-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm1
@@ -1221,7 +1221,7 @@ define <2 x i64> @vec128_i64_unsigned_reg_reg(<2 x i64> %a1, <2 x i64> %a2) noun
; AVX2-FALLBACK-NEXT: vpxor %xmm2, %xmm1, %xmm3
; AVX2-FALLBACK-NEXT: vpxor %xmm2, %xmm0, %xmm2
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm4
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm4, %xmm5
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm5
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
; AVX2-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm2
; AVX2-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm1
@@ -1241,7 +1241,7 @@ define <2 x i64> @vec128_i64_unsigned_reg_reg(<2 x i64> %a1, <2 x i64> %a2) noun
; XOP-LABEL: vec128_i64_unsigned_reg_reg:
; XOP: # %bb.0:
; XOP-NEXT: vpcomgtuq %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; XOP-NEXT: vpcomltuq %xmm1, %xmm0, %xmm4
; XOP-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; XOP-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1431,7 +1431,7 @@ define <2 x i64> @vec128_i64_signed_mem_reg(<2 x i64>* %a1_addr, <2 x i64> %a2)
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm4, %xmm1, %xmm0, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
@@ -1452,7 +1452,7 @@ define <2 x i64> @vec128_i64_signed_mem_reg(<2 x i64>* %a1_addr, <2 x i64> %a2)
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm4, %xmm1, %xmm0, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
@@ -1473,7 +1473,7 @@ define <2 x i64> @vec128_i64_signed_mem_reg(<2 x i64>* %a1_addr, <2 x i64> %a2)
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %xmm1
; XOP-NEXT: vpcomgtq %xmm0, %xmm1, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; XOP-NEXT: vpcomltq %xmm0, %xmm1, %xmm4
; XOP-NEXT: vblendvpd %xmm4, %xmm1, %xmm0, %xmm4
; XOP-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
@@ -1665,7 +1665,7 @@ define <2 x i64> @vec128_i64_signed_reg_mem(<2 x i64> %a1, <2 x i64>* %a2_addr)
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1686,7 +1686,7 @@ define <2 x i64> @vec128_i64_signed_reg_mem(<2 x i64> %a1, <2 x i64>* %a2_addr)
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1707,7 +1707,7 @@ define <2 x i64> @vec128_i64_signed_reg_mem(<2 x i64> %a1, <2 x i64>* %a2_addr)
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %xmm1
; XOP-NEXT: vpcomgtq %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; XOP-NEXT: vpcomltq %xmm1, %xmm0, %xmm4
; XOP-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; XOP-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1900,7 +1900,7 @@ define <2 x i64> @vec128_i64_signed_mem_mem(<2 x i64>* %a1_addr, <2 x i64>* %a2_
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX1-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; AVX1-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1922,7 +1922,7 @@ define <2 x i64> @vec128_i64_signed_mem_mem(<2 x i64>* %a1_addr, <2 x i64>* %a2_
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX2-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX2-FALLBACK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; AVX2-FALLBACK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -1944,7 +1944,7 @@ define <2 x i64> @vec128_i64_signed_mem_mem(<2 x i64>* %a1_addr, <2 x i64>* %a2_
; XOP-NEXT: vmovdqa (%rdi), %xmm0
; XOP-NEXT: vmovdqa (%rsi), %xmm1
; XOP-NEXT: vpcomgtq %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm3
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; XOP-NEXT: vpcomltq %xmm1, %xmm0, %xmm4
; XOP-NEXT: vblendvpd %xmm4, %xmm0, %xmm1, %xmm4
; XOP-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
@@ -2055,7 +2055,7 @@ define <8 x i16> @vec128_i16_signed_reg_reg(<8 x i16> %a1, <8 x i16> %a2) nounwi
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pcmpgtw %xmm1, %xmm2
-; SSE-NEXT: por {{.*}}(%rip), %xmm2
+; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pminsw %xmm1, %xmm3
; SSE-NEXT: pmaxsw %xmm0, %xmm1
@@ -2069,7 +2069,7 @@ define <8 x i16> @vec128_i16_signed_reg_reg(<8 x i16> %a1, <8 x i16> %a2) nounwi
; AVX1-FALLBACK-LABEL: vec128_i16_signed_reg_reg:
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2081,7 +2081,7 @@ define <8 x i16> @vec128_i16_signed_reg_reg(<8 x i16> %a1, <8 x i16> %a2) nounwi
; AVX2-FALLBACK-LABEL: vec128_i16_signed_reg_reg:
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2093,7 +2093,7 @@ define <8 x i16> @vec128_i16_signed_reg_reg(<8 x i16> %a1, <8 x i16> %a2) nounwi
; XOP-LABEL: vec128_i16_signed_reg_reg:
; XOP: # %bb.0:
; XOP-NEXT: vpcomgtw %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; XOP-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2104,7 +2104,7 @@ define <8 x i16> @vec128_i16_signed_reg_reg(<8 x i16> %a1, <8 x i16> %a2) nounwi
; AVX512F-LABEL: vec128_i16_signed_reg_reg:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX512F-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2116,7 +2116,7 @@ define <8 x i16> @vec128_i16_signed_reg_reg(<8 x i16> %a1, <8 x i16> %a2) nounwi
; AVX512VL-FALLBACK-LABEL: vec128_i16_signed_reg_reg:
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2174,7 +2174,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun
; SSE2-NEXT: pxor %xmm3, %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm3
; SSE2-NEXT: pcmpgtw %xmm2, %xmm3
-; SSE2-NEXT: por {{.*}}(%rip), %xmm3
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psubusw %xmm1, %xmm2
; SSE2-NEXT: psubusw %xmm0, %xmm1
@@ -2195,7 +2195,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun
; SSE41-NEXT: pcmpeqw %xmm2, %xmm3
; SSE41-NEXT: pcmpeqd %xmm4, %xmm4
; SSE41-NEXT: pxor %xmm3, %xmm4
-; SSE41-NEXT: por {{.*}}(%rip), %xmm4
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: pmaxuw %xmm0, %xmm1
; SSE41-NEXT: psubw %xmm2, %xmm1
; SSE41-NEXT: psrlw $1, %xmm1
@@ -2209,7 +2209,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun
; AVX1-FALLBACK-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
; AVX1-FALLBACK-NEXT: vpxor %xmm4, %xmm3, %xmm3
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
@@ -2223,7 +2223,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun
; AVX2-FALLBACK-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
; AVX2-FALLBACK-NEXT: vpxor %xmm4, %xmm3, %xmm3
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm3, %xmm3
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
@@ -2234,7 +2234,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun
; XOP-LABEL: vec128_i16_unsigned_reg_reg:
; XOP: # %bb.0:
; XOP-NEXT: vpcomgtuw %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-NEXT: vpminuw %xmm1, %xmm0, %xmm3
; XOP-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2247,7 +2247,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun
; AVX512F-NEXT: vpminuw %xmm1, %xmm0, %xmm2
; AVX512F-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm3
; AVX512F-NEXT: vpternlogq $15, %zmm3, %zmm3, %zmm3
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm3, %xmm3
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512F-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubw %xmm2, %xmm1, %xmm1
; AVX512F-NEXT: vpsrlw $1, %xmm1, %xmm1
@@ -2261,7 +2261,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun
; AVX512VL-FALLBACK-NEXT: vpminuw %xmm1, %xmm0, %xmm2
; AVX512VL-FALLBACK-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
-; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{.*}}(%rip), %xmm3, %xmm4
+; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm4
; AVX512VL-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
@@ -2318,7 +2318,7 @@ define <8 x i16> @vec128_i16_signed_mem_reg(<8 x i16>* %a1_addr, <8 x i16> %a2)
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtw %xmm0, %xmm2
-; SSE-NEXT: por {{.*}}(%rip), %xmm2
+; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pminsw %xmm0, %xmm3
; SSE-NEXT: pmaxsw %xmm1, %xmm0
@@ -2332,7 +2332,7 @@ define <8 x i16> @vec128_i16_signed_mem_reg(<8 x i16>* %a1_addr, <8 x i16> %a2)
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsw %xmm0, %xmm1, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsw %xmm0, %xmm1, %xmm0
; AVX1-FALLBACK-NEXT: vpsubw %xmm3, %xmm0, %xmm0
@@ -2345,7 +2345,7 @@ define <8 x i16> @vec128_i16_signed_mem_reg(<8 x i16>* %a1_addr, <8 x i16> %a2)
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsw %xmm0, %xmm1, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsw %xmm0, %xmm1, %xmm0
; AVX2-FALLBACK-NEXT: vpsubw %xmm3, %xmm0, %xmm0
@@ -2358,7 +2358,7 @@ define <8 x i16> @vec128_i16_signed_mem_reg(<8 x i16>* %a1_addr, <8 x i16> %a2)
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %xmm1
; XOP-NEXT: vpcomgtw %xmm0, %xmm1, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-NEXT: vpminsw %xmm0, %xmm1, %xmm3
; XOP-NEXT: vpmaxsw %xmm0, %xmm1, %xmm0
; XOP-NEXT: vpsubw %xmm3, %xmm0, %xmm0
@@ -2370,7 +2370,7 @@ define <8 x i16> @vec128_i16_signed_mem_reg(<8 x i16>* %a1_addr, <8 x i16> %a2)
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm1
; AVX512F-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsw %xmm0, %xmm1, %xmm3
; AVX512F-NEXT: vpmaxsw %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: vpsubw %xmm3, %xmm0, %xmm0
@@ -2383,7 +2383,7 @@ define <8 x i16> @vec128_i16_signed_mem_reg(<8 x i16>* %a1_addr, <8 x i16> %a2)
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsw %xmm0, %xmm1, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %xmm0, %xmm1, %xmm0
; AVX512VL-FALLBACK-NEXT: vpsubw %xmm3, %xmm0, %xmm0
@@ -2441,7 +2441,7 @@ define <8 x i16> @vec128_i16_signed_reg_mem(<8 x i16> %a1, <8 x i16>* %a2_addr)
; SSE-NEXT: movdqa (%rdi), %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: pcmpgtw %xmm2, %xmm1
-; SSE-NEXT: por {{.*}}(%rip), %xmm1
+; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pminsw %xmm2, %xmm3
; SSE-NEXT: pmaxsw %xmm0, %xmm2
@@ -2456,7 +2456,7 @@ define <8 x i16> @vec128_i16_signed_reg_mem(<8 x i16> %a1, <8 x i16>* %a2_addr)
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2469,7 +2469,7 @@ define <8 x i16> @vec128_i16_signed_reg_mem(<8 x i16> %a1, <8 x i16>* %a2_addr)
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2482,7 +2482,7 @@ define <8 x i16> @vec128_i16_signed_reg_mem(<8 x i16> %a1, <8 x i16>* %a2_addr)
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa (%rdi), %xmm1
; XOP-NEXT: vpcomgtw %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; XOP-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2494,7 +2494,7 @@ define <8 x i16> @vec128_i16_signed_reg_mem(<8 x i16> %a1, <8 x i16>* %a2_addr)
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm1
; AVX512F-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX512F-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2507,7 +2507,7 @@ define <8 x i16> @vec128_i16_signed_reg_mem(<8 x i16> %a1, <8 x i16>* %a2_addr)
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2566,7 +2566,7 @@ define <8 x i16> @vec128_i16_signed_mem_mem(<8 x i16>* %a1_addr, <8 x i16>* %a2_
; SSE-NEXT: movdqa (%rsi), %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtw %xmm0, %xmm2
-; SSE-NEXT: por {{.*}}(%rip), %xmm2
+; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pminsw %xmm0, %xmm3
; SSE-NEXT: pmaxsw %xmm1, %xmm0
@@ -2581,7 +2581,7 @@ define <8 x i16> @vec128_i16_signed_mem_mem(<8 x i16>* %a1_addr, <8 x i16>* %a2_
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2595,7 +2595,7 @@ define <8 x i16> @vec128_i16_signed_mem_mem(<8 x i16>* %a1_addr, <8 x i16>* %a2_
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX2-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2609,7 +2609,7 @@ define <8 x i16> @vec128_i16_signed_mem_mem(<8 x i16>* %a1_addr, <8 x i16>* %a2_
; XOP-NEXT: vmovdqa (%rdi), %xmm0
; XOP-NEXT: vmovdqa (%rsi), %xmm1
; XOP-NEXT: vpcomgtw %xmm1, %xmm0, %xmm2
-; XOP-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; XOP-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2622,7 +2622,7 @@ define <8 x i16> @vec128_i16_signed_mem_mem(<8 x i16>* %a1_addr, <8 x i16>* %a2_
; AVX512F-NEXT: vmovdqa (%rdi), %xmm0
; AVX512F-NEXT: vmovdqa (%rsi), %xmm1
; AVX512F-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX512F-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2636,7 +2636,7 @@ define <8 x i16> @vec128_i16_signed_mem_mem(<8 x i16>* %a1_addr, <8 x i16>* %a2_
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsw %xmm1, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubw %xmm3, %xmm1, %xmm1
@@ -2715,7 +2715,7 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; SSE2-NEXT: por %xmm5, %xmm2
; SSE2-NEXT: psubb %xmm4, %xmm2
; SSE2-NEXT: psrlw $1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: movdqa %xmm3, %xmm4
@@ -2736,13 +2736,13 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtb %xmm1, %xmm2
-; SSE41-NEXT: por {{.*}}(%rip), %xmm2
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: pminsb %xmm1, %xmm3
; SSE41-NEXT: pmaxsb %xmm0, %xmm1
; SSE41-NEXT: psubb %xmm3, %xmm1
; SSE41-NEXT: psrlw $1, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm4 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
@@ -2759,12 +2759,12 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; AVX1-FALLBACK-LABEL: vec128_i8_signed_reg_reg:
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX1-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpmullw %xmm4, %xmm3, %xmm3
@@ -2781,16 +2781,16 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; AVX2-FALLBACK-LABEL: vec128_i8_signed_reg_reg:
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX2-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-FALLBACK-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-FALLBACK-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -2800,7 +2800,7 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; XOP-FALLBACK-LABEL: vec128_i8_signed_reg_reg:
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -2819,7 +2819,7 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; XOPAVX1-LABEL: vec128_i8_signed_reg_reg:
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -2838,7 +2838,7 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; XOPAVX2-LABEL: vec128_i8_signed_reg_reg:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOPAVX2-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOPAVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOPAVX2-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -2847,7 +2847,7 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; XOPAVX2-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; XOPAVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -2857,12 +2857,12 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; AVX512F-LABEL: vec128_i8_signed_reg_reg:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX512F-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512F-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512F-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -2875,12 +2875,12 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; AVX512VL-FALLBACK-LABEL: vec128_i8_signed_reg_reg:
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -2902,7 +2902,7 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; AVX512BW-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -2921,7 +2921,7 @@ define <16 x i8> @vec128_i8_signed_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounwin
; AVX512VLBW-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512VLBW-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -2949,11 +2949,11 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; SSE2-NEXT: pcmpeqb %xmm3, %xmm4
; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm2
-; SSE2-NEXT: por {{.*}}(%rip), %xmm2
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pmaxub %xmm0, %xmm1
; SSE2-NEXT: psubb %xmm3, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: movdqa %xmm2, %xmm4
@@ -2977,11 +2977,11 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; SSE41-NEXT: pcmpeqb %xmm2, %xmm3
; SSE41-NEXT: pcmpeqd %xmm4, %xmm4
; SSE41-NEXT: pxor %xmm3, %xmm4
-; SSE41-NEXT: por {{.*}}(%rip), %xmm4
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: pmaxub %xmm0, %xmm1
; SSE41-NEXT: psubb %xmm2, %xmm1
; SSE41-NEXT: psrlw $1, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm3 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero
@@ -3001,11 +3001,11 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; AVX1-FALLBACK-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
; AVX1-FALLBACK-NEXT: vpxor %xmm4, %xmm3, %xmm3
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX1-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpmullw %xmm4, %xmm2, %xmm2
@@ -3025,15 +3025,15 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; AVX2-FALLBACK-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
; AVX2-FALLBACK-NEXT: vpxor %xmm4, %xmm3, %xmm3
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm3, %xmm3
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX2-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-FALLBACK-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-FALLBACK-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -3043,7 +3043,7 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; XOP-FALLBACK-LABEL: vec128_i8_unsigned_reg_reg:
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vpcomgtub %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3062,7 +3062,7 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; XOPAVX1-LABEL: vec128_i8_unsigned_reg_reg:
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vpcomgtub %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminub %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3081,7 +3081,7 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; XOPAVX2-LABEL: vec128_i8_unsigned_reg_reg:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpcomgtub %xmm1, %xmm0, %xmm2
-; XOPAVX2-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX2-NEXT: vpminub %xmm1, %xmm0, %xmm3
; XOPAVX2-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; XOPAVX2-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3090,7 +3090,7 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; XOPAVX2-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; XOPAVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -3102,11 +3102,11 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; AVX512F-NEXT: vpminub %xmm1, %xmm0, %xmm2
; AVX512F-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3
; AVX512F-NEXT: vpternlogq $15, %zmm3, %zmm3, %zmm3
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm3, %xmm3
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512F-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512F-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512F-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3121,11 +3121,11 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; AVX512VL-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm2
; AVX512VL-FALLBACK-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
-; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{.*}}(%rip), %xmm3, %xmm4
+; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm4
; AVX512VL-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero,xmm4[8],zero,xmm4[9],zero,xmm4[10],zero,xmm4[11],zero,xmm4[12],zero,xmm4[13],zero,xmm4[14],zero,xmm4[15],zero
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3147,7 +3147,7 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; AVX512BW-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3166,7 +3166,7 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw
; AVX512VLBW-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512VLBW-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3208,7 +3208,7 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; SSE2-NEXT: por %xmm5, %xmm3
; SSE2-NEXT: psubb %xmm4, %xmm3
; SSE2-NEXT: psrlw $1, %xmm3
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm4
@@ -3229,13 +3229,13 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; SSE41-NEXT: movdqa (%rdi), %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: pcmpgtb %xmm0, %xmm3
-; SSE41-NEXT: por {{.*}}(%rip), %xmm3
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: movdqa %xmm2, %xmm1
; SSE41-NEXT: pminsb %xmm0, %xmm1
; SSE41-NEXT: pmaxsb %xmm2, %xmm0
; SSE41-NEXT: psubb %xmm1, %xmm0
; SSE41-NEXT: psrlw $1, %xmm0
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm4 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
@@ -3254,12 +3254,12 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsb %xmm0, %xmm1, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; AVX1-FALLBACK-NEXT: vpsubb %xmm3, %xmm0, %xmm0
; AVX1-FALLBACK-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX1-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpmullw %xmm4, %xmm3, %xmm3
@@ -3277,16 +3277,16 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsb %xmm0, %xmm1, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; AVX2-FALLBACK-NEXT: vpsubb %xmm3, %xmm0, %xmm0
; AVX2-FALLBACK-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX2-FALLBACK-NEXT: vpmullw %ymm2, %ymm0, %ymm0
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-FALLBACK-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-FALLBACK-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
; AVX2-FALLBACK-NEXT: vpaddb %xmm1, %xmm0, %xmm0
@@ -3297,7 +3297,7 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; XOP-FALLBACK-NEXT: vpcomgtb %xmm0, %xmm1, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsb %xmm0, %xmm1, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; XOP-FALLBACK-NEXT: vpsubb %xmm3, %xmm0, %xmm0
@@ -3317,7 +3317,7 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vmovdqa (%rdi), %xmm1
; XOPAVX1-NEXT: vpcomgtb %xmm0, %xmm1, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsb %xmm0, %xmm1, %xmm3
; XOPAVX1-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; XOPAVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0
@@ -3337,7 +3337,7 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vmovdqa (%rdi), %xmm1
; XOPAVX2-NEXT: vpcomgtb %xmm0, %xmm1, %xmm2
-; XOPAVX2-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX2-NEXT: vpminsb %xmm0, %xmm1, %xmm3
; XOPAVX2-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; XOPAVX2-NEXT: vpsubb %xmm3, %xmm0, %xmm0
@@ -3346,7 +3346,7 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; XOPAVX2-NEXT: vpmullw %ymm2, %ymm0, %ymm0
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; XOPAVX2-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
; XOPAVX2-NEXT: vpaddb %xmm1, %xmm0, %xmm0
@@ -3357,12 +3357,12 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm1
; AVX512F-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsb %xmm0, %xmm1, %xmm3
; AVX512F-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: vpsubb %xmm3, %xmm0, %xmm0
; AVX512F-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512F-NEXT: vpmullw %ymm2, %ymm0, %ymm0
@@ -3376,12 +3376,12 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsb %xmm0, %xmm1, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; AVX512VL-FALLBACK-NEXT: vpsubb %xmm3, %xmm0, %xmm0
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm2, %ymm0, %ymm0
@@ -3403,7 +3403,7 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; AVX512BW-FALLBACK-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; AVX512BW-FALLBACK-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %ymm2, %ymm0, %ymm0
@@ -3423,7 +3423,7 @@ define <16 x i8> @vec128_i8_signed_mem_reg(<16 x i8>* %a1_addr, <16 x i8> %a2) n
; AVX512VLBW-NEXT: vpmaxsb %xmm0, %xmm1, %xmm0
; AVX512VLBW-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX512VLBW-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512VLBW-NEXT: vpmullw %ymm2, %ymm0, %ymm0
@@ -3463,7 +3463,7 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: psubb %xmm4, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: movdqa %xmm2, %xmm4
@@ -3485,13 +3485,13 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; SSE41-NEXT: movdqa (%rdi), %xmm1
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtb %xmm1, %xmm2
-; SSE41-NEXT: por {{.*}}(%rip), %xmm2
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: pminsb %xmm1, %xmm3
; SSE41-NEXT: pmaxsb %xmm0, %xmm1
; SSE41-NEXT: psubb %xmm3, %xmm1
; SSE41-NEXT: psrlw $1, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm4 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
@@ -3509,12 +3509,12 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; AVX1-FALLBACK: # %bb.0:
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX1-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpmullw %xmm4, %xmm3, %xmm3
@@ -3532,16 +3532,16 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; AVX2-FALLBACK: # %bb.0:
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX2-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-FALLBACK-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-FALLBACK-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -3552,7 +3552,7 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; XOP-FALLBACK: # %bb.0:
; XOP-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; XOP-FALLBACK-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3572,7 +3572,7 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vmovdqa (%rdi), %xmm1
; XOPAVX1-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3592,7 +3592,7 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vmovdqa (%rdi), %xmm1
; XOPAVX2-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOPAVX2-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOPAVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOPAVX2-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3601,7 +3601,7 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; XOPAVX2-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; XOPAVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -3612,12 +3612,12 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm1
; AVX512F-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX512F-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512F-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512F-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3631,12 +3631,12 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %xmm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3658,7 +3658,7 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; AVX512BW-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3678,7 +3678,7 @@ define <16 x i8> @vec128_i8_signed_reg_mem(<16 x i8> %a1, <16 x i8>* %a2_addr) n
; AVX512VLBW-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512VLBW-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3719,7 +3719,7 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; SSE2-NEXT: por %xmm5, %xmm2
; SSE2-NEXT: psubb %xmm4, %xmm2
; SSE2-NEXT: psrlw $1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm4
@@ -3741,13 +3741,13 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; SSE41-NEXT: movdqa (%rsi), %xmm2
; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: pcmpgtb %xmm2, %xmm3
-; SSE41-NEXT: por {{.*}}(%rip), %xmm3
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pminsb %xmm2, %xmm0
; SSE41-NEXT: pmaxsb %xmm1, %xmm2
; SSE41-NEXT: psubb %xmm0, %xmm2
; SSE41-NEXT: psrlw $1, %xmm2
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm4 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
@@ -3766,12 +3766,12 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; AVX1-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX1-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX1-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX1-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX1-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX1-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-FALLBACK-NEXT: vpmullw %xmm4, %xmm3, %xmm3
@@ -3790,16 +3790,16 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; AVX2-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX2-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX2-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX2-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX2-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX2-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX2-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; AVX2-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-FALLBACK-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-FALLBACK-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2-FALLBACK-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -3811,7 +3811,7 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; XOP-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; XOP-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; XOP-FALLBACK-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOP-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOP-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOP-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOP-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOP-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3832,7 +3832,7 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; XOPAVX1-NEXT: vmovdqa (%rdi), %xmm0
; XOPAVX1-NEXT: vmovdqa (%rsi), %xmm1
; XOPAVX1-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOPAVX1-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOPAVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3853,7 +3853,7 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; XOPAVX2-NEXT: vmovdqa (%rdi), %xmm0
; XOPAVX2-NEXT: vmovdqa (%rsi), %xmm1
; XOPAVX2-NEXT: vpcomgtb %xmm1, %xmm0, %xmm2
-; XOPAVX2-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; XOPAVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; XOPAVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; XOPAVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; XOPAVX2-NEXT: vpsubb %xmm3, %xmm1, %xmm1
@@ -3862,7 +3862,7 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; XOPAVX2-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; XOPAVX2-NEXT: vpmullw %ymm2, %ymm1, %ymm1
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; XOPAVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
@@ -3874,12 +3874,12 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; AVX512F-NEXT: vmovdqa (%rdi), %xmm0
; AVX512F-NEXT: vmovdqa (%rsi), %xmm1
; AVX512F-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX512F-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512F-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512F-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512F-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3894,12 +3894,12 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rsi), %xmm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %xmm2, %xmm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512VL-FALLBACK-NEXT: vpminsb %xmm1, %xmm0, %xmm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VL-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3921,7 +3921,7 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; AVX512BW-FALLBACK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %ymm2, %ymm1, %ymm1
@@ -3942,7 +3942,7 @@ define <16 x i8> @vec128_i8_signed_mem_mem(<16 x i8>* %a1_addr, <16 x i8>* %a2_a
; AVX512VLBW-NEXT: vpmaxsb %xmm1, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlw $1, %xmm1, %xmm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero,xmm3[8],zero,xmm3[9],zero,xmm3[10],zero,xmm3[11],zero,xmm3[12],zero,xmm3[13],zero,xmm3[14],zero,xmm3[15],zero
; AVX512VLBW-NEXT: vpmullw %ymm2, %ymm1, %ymm1
diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
index 5b7576b864e1c..b5da974300039 100644
--- a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
+++ b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
@@ -1635,7 +1635,7 @@ define <16 x i16> @vec256_i16_signed_reg_reg(<16 x i16> %a1, <16 x i16> %a2) nou
; AVX2-LABEL: vec256_i16_signed_reg_reg:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -1691,7 +1691,7 @@ define <16 x i16> @vec256_i16_signed_reg_reg(<16 x i16> %a1, <16 x i16> %a2) nou
; AVX512F-LABEL: vec256_i16_signed_reg_reg:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX512F-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -1703,7 +1703,7 @@ define <16 x i16> @vec256_i16_signed_reg_reg(<16 x i16> %a1, <16 x i16> %a2) nou
; AVX512VL-FALLBACK-LABEL: vec256_i16_signed_reg_reg:
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -1786,7 +1786,7 @@ define <16 x i16> @vec256_i16_unsigned_reg_reg(<16 x i16> %a1, <16 x i16> %a2) n
; AVX2-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
; AVX2-NEXT: vpxor %ymm4, %ymm3, %ymm3
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubw %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1
@@ -1843,7 +1843,7 @@ define <16 x i16> @vec256_i16_unsigned_reg_reg(<16 x i16> %a1, <16 x i16> %a2) n
; AVX512F-NEXT: vpminuw %ymm1, %ymm0, %ymm2
; AVX512F-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm3
; AVX512F-NEXT: vpternlogq $15, %zmm3, %zmm3, %zmm3
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubw %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
@@ -1856,7 +1856,7 @@ define <16 x i16> @vec256_i16_unsigned_reg_reg(<16 x i16> %a1, <16 x i16> %a2) n
; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm2
; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
-; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{.*}}(%rip), %ymm3, %ymm4
+; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm4
; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
@@ -1936,7 +1936,7 @@ define <16 x i16> @vec256_i16_signed_mem_reg(<16 x i16>* %a1_addr, <16 x i16> %a
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm1
; AVX2-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsw %ymm0, %ymm1, %ymm3
; AVX2-NEXT: vpmaxsw %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsubw %ymm3, %ymm0, %ymm0
@@ -1995,7 +1995,7 @@ define <16 x i16> @vec256_i16_signed_mem_reg(<16 x i16>* %a1_addr, <16 x i16> %a
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm1
; AVX512F-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsw %ymm0, %ymm1, %ymm3
; AVX512F-NEXT: vpmaxsw %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: vpsubw %ymm3, %ymm0, %ymm0
@@ -2008,7 +2008,7 @@ define <16 x i16> @vec256_i16_signed_mem_reg(<16 x i16>* %a1_addr, <16 x i16> %a
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsw %ymm0, %ymm1, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm0, %ymm1, %ymm0
; AVX512VL-FALLBACK-NEXT: vpsubw %ymm3, %ymm0, %ymm0
@@ -2089,7 +2089,7 @@ define <16 x i16> @vec256_i16_signed_reg_mem(<16 x i16> %a1, <16 x i16>* %a2_add
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm1
; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -2148,7 +2148,7 @@ define <16 x i16> @vec256_i16_signed_reg_mem(<16 x i16> %a1, <16 x i16>* %a2_add
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm1
; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX512F-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -2161,7 +2161,7 @@ define <16 x i16> @vec256_i16_signed_reg_mem(<16 x i16> %a1, <16 x i16>* %a2_add
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -2244,7 +2244,7 @@ define <16 x i16> @vec256_i16_signed_mem_mem(<16 x i16>* %a1_addr, <16 x i16>* %
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vmovdqa (%rsi), %ymm1
; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -2306,7 +2306,7 @@ define <16 x i16> @vec256_i16_signed_mem_mem(<16 x i16>* %a1_addr, <16 x i16>* %
; AVX512F-NEXT: vmovdqa (%rdi), %ymm0
; AVX512F-NEXT: vmovdqa (%rsi), %ymm1
; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX512F-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -2320,7 +2320,7 @@ define <16 x i16> @vec256_i16_signed_mem_mem(<16 x i16>* %a1_addr, <16 x i16>* %
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm0
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rsi), %ymm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsw %ymm1, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubw %ymm3, %ymm1, %ymm1
@@ -2427,12 +2427,12 @@ define <32 x i8> @vec256_i8_signed_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounwin
; AVX2-LABEL: vec256_i8_signed_reg_reg:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -2525,12 +2525,12 @@ define <32 x i8> @vec256_i8_signed_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounwin
; AVX512F-LABEL: vec256_i8_signed_reg_reg:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -2547,12 +2547,12 @@ define <32 x i8> @vec256_i8_signed_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounwin
; AVX512VL-FALLBACK-LABEL: vec256_i8_signed_reg_reg:
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -2578,7 +2578,7 @@ define <32 x i8> @vec256_i8_signed_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounwin
; AVX512BW-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %zmm2, %zmm1, %zmm1
@@ -2596,7 +2596,7 @@ define <32 x i8> @vec256_i8_signed_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounwin
; AVX512VLBW-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VLBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512VLBW-NEXT: vpmullw %zmm2, %zmm1, %zmm1
@@ -2668,11 +2668,11 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw
; AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
; AVX2-NEXT: vpxor %ymm4, %ymm3, %ymm3
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpmullw %ymm4, %ymm2, %ymm2
@@ -2767,11 +2767,11 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw
; AVX512F-NEXT: vpminub %ymm1, %ymm0, %ymm2
; AVX512F-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm3
; AVX512F-NEXT: vpternlogq $15, %zmm3, %zmm3, %zmm3
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpmaxub %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpmullw %ymm4, %ymm2, %ymm2
@@ -2790,11 +2790,11 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw
; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm2
; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
-; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{.*}}(%rip), %ymm3, %ymm4
+; AVX512VL-FALLBACK-NEXT: vpternlogq $190, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm4
; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm3, %ymm2, %ymm2
@@ -2820,7 +2820,7 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw
; AVX512BW-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %zmm2, %zmm1, %zmm1
@@ -2838,7 +2838,7 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw
; AVX512VLBW-NEXT: vpmaxub %ymm1, %ymm0, %ymm1
; AVX512VLBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512VLBW-NEXT: vpmullw %zmm2, %zmm1, %zmm1
@@ -2908,12 +2908,12 @@ define <32 x i8> @vec256_i8_signed_mem_reg(<32 x i8>* %a1_addr, <32 x i8> %a2) n
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm1
; AVX2-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsb %ymm0, %ymm1, %ymm3
; AVX2-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsubb %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3009,12 +3009,12 @@ define <32 x i8> @vec256_i8_signed_mem_reg(<32 x i8>* %a1_addr, <32 x i8> %a2) n
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm1
; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm0, %ymm1, %ymm3
; AVX512F-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: vpsubb %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3032,12 +3032,12 @@ define <32 x i8> @vec256_i8_signed_mem_reg(<32 x i8>* %a1_addr, <32 x i8> %a2) n
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsb %ymm0, %ymm1, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512VL-FALLBACK-NEXT: vpsubb %ymm3, %ymm0, %ymm0
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3063,7 +3063,7 @@ define <32 x i8> @vec256_i8_signed_mem_reg(<32 x i8>* %a1_addr, <32 x i8> %a2) n
; AVX512BW-FALLBACK-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512BW-FALLBACK-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %zmm2, %zmm0, %zmm0
@@ -3082,7 +3082,7 @@ define <32 x i8> @vec256_i8_signed_mem_reg(<32 x i8>* %a1_addr, <32 x i8> %a2) n
; AVX512VLBW-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512VLBW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX512VLBW-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512VLBW-NEXT: vpmullw %zmm2, %zmm0, %zmm0
@@ -3151,12 +3151,12 @@ define <32 x i8> @vec256_i8_signed_reg_mem(<32 x i8> %a1, <32 x i8>* %a2_addr) n
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm1
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3252,12 +3252,12 @@ define <32 x i8> @vec256_i8_signed_reg_mem(<32 x i8> %a1, <32 x i8>* %a2_addr) n
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm1
; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3275,12 +3275,12 @@ define <32 x i8> @vec256_i8_signed_reg_mem(<32 x i8> %a1, <32 x i8>* %a2_addr) n
; AVX512VL-FALLBACK: # %bb.0:
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3306,7 +3306,7 @@ define <32 x i8> @vec256_i8_signed_reg_mem(<32 x i8> %a1, <32 x i8>* %a2_addr) n
; AVX512BW-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %zmm2, %zmm1, %zmm1
@@ -3325,7 +3325,7 @@ define <32 x i8> @vec256_i8_signed_reg_mem(<32 x i8> %a1, <32 x i8>* %a2_addr) n
; AVX512VLBW-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VLBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512VLBW-NEXT: vpmullw %zmm2, %zmm1, %zmm1
@@ -3396,12 +3396,12 @@ define <32 x i8> @vec256_i8_signed_mem_mem(<32 x i8>* %a1_addr, <32 x i8>* %a2_a
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vmovdqa (%rsi), %ymm1
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3500,12 +3500,12 @@ define <32 x i8> @vec256_i8_signed_mem_mem(<32 x i8>* %a1_addr, <32 x i8>* %a2_a
; AVX512F-NEXT: vmovdqa (%rdi), %ymm0
; AVX512F-NEXT: vmovdqa (%rsi), %ymm1
; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX512F-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3524,12 +3524,12 @@ define <32 x i8> @vec256_i8_signed_mem_mem(<32 x i8>* %a1_addr, <32 x i8>* %a2_a
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm0
; AVX512VL-FALLBACK-NEXT: vmovdqa (%rsi), %ymm1
; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm2
-; AVX512VL-FALLBACK-NEXT: vpor {{.*}}(%rip), %ymm2, %ymm2
+; AVX512VL-FALLBACK-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm3
; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VL-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VL-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512VL-FALLBACK-NEXT: vpmullw %ymm4, %ymm3, %ymm3
@@ -3555,7 +3555,7 @@ define <32 x i8> @vec256_i8_signed_mem_mem(<32 x i8>* %a1_addr, <32 x i8>* %a2_a
; AVX512BW-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512BW-FALLBACK-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-FALLBACK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512BW-FALLBACK-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512BW-FALLBACK-NEXT: vpmullw %zmm2, %zmm1, %zmm1
@@ -3575,7 +3575,7 @@ define <32 x i8> @vec256_i8_signed_mem_mem(<32 x i8>* %a1_addr, <32 x i8>* %a2_a
; AVX512VLBW-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VLBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpsrlw $1, %ymm1, %ymm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero,ymm3[16],zero,ymm3[17],zero,ymm3[18],zero,ymm3[19],zero,ymm3[20],zero,ymm3[21],zero,ymm3[22],zero,ymm3[23],zero,ymm3[24],zero,ymm3[25],zero,ymm3[26],zero,ymm3[27],zero,ymm3[28],zero,ymm3[29],zero,ymm3[30],zero,ymm3[31],zero
; AVX512VLBW-NEXT: vpmullw %zmm2, %zmm1, %zmm1
diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
index b19dd4586f5f7..ac1259d7d9459 100644
--- a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
+++ b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
@@ -803,7 +803,7 @@ define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwin
; AVX512BW-NEXT: vpmaxsb %zmm1, %zmm0, %zmm1
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm4 = zmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpmullw %zmm4, %zmm2, %zmm2
@@ -929,7 +929,7 @@ define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounw
; AVX512BW-NEXT: vpmaxub %zmm1, %zmm0, %zmm1
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm4 = zmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpmullw %zmm4, %zmm2, %zmm2
@@ -1057,7 +1057,7 @@ define <64 x i8> @vec512_i8_signed_mem_reg(<64 x i8>* %a1_addr, <64 x i8> %a2) n
; AVX512BW-NEXT: vpmaxsb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsubb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm4 = zmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpmullw %zmm4, %zmm2, %zmm2
@@ -1184,7 +1184,7 @@ define <64 x i8> @vec512_i8_signed_reg_mem(<64 x i8> %a1, <64 x i8>* %a2_addr) n
; AVX512BW-NEXT: vpmaxsb %zmm1, %zmm0, %zmm1
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm4 = zmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpmullw %zmm4, %zmm2, %zmm2
@@ -1314,7 +1314,7 @@ define <64 x i8> @vec512_i8_signed_mem_mem(<64 x i8>* %a1_addr, <64 x i8>* %a2_a
; AVX512BW-NEXT: vpmaxsb %zmm1, %zmm0, %zmm1
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm4 = zmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpmullw %zmm4, %zmm2, %zmm2
diff --git a/llvm/test/CodeGen/X86/min-legal-vector-width.ll b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
index 2f96af9a73321..9451165035629 100644
--- a/llvm/test/CodeGen/X86/min-legal-vector-width.ll
+++ b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
@@ -1586,10 +1586,10 @@ declare void @llvm.masked.store.v64i8.p0v64i8(<64 x i8>, <64 x i8>*, i32, <64 x
define dso_local i32 @v64i1_inline_asm() "min-legal-vector-width"="256" {
; CHECK-LABEL: v64i1_inline_asm:
; CHECK: # %bb.0:
-; CHECK-NEXT: kmovq {{.*}}(%rip), %k0
+; CHECK-NEXT: kmovq mem64_src(%rip), %k0
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: kmovq %k0, {{.*}}(%rip)
+; CHECK-NEXT: kmovq %k0, mem64_dst(%rip)
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: retq
%1 = alloca i32, align 4
@@ -1666,17 +1666,17 @@ define <32 x i8> @var_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind "min-leg
; CHECK: # %bb.0:
; CHECK-NEXT: vpsllw $4, %ymm0, %ymm2
; CHECK-NEXT: vpsrlw $4, %ymm0, %ymm3
-; CHECK-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm2, %ymm3
+; CHECK-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; CHECK-NEXT: vpsllw $5, %ymm1, %ymm1
; CHECK-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; CHECK-NEXT: vpsllw $2, %ymm0, %ymm2
; CHECK-NEXT: vpsrlw $6, %ymm0, %ymm3
-; CHECK-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm2, %ymm3
+; CHECK-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; CHECK-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; CHECK-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; CHECK-NEXT: vpsrlw $7, %ymm0, %ymm2
; CHECK-NEXT: vpaddb %ymm0, %ymm0, %ymm3
-; CHECK-NEXT: vpternlogq $248, {{.*}}(%rip), %ymm2, %ymm3
+; CHECK-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; CHECK-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; CHECK-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; CHECK-NEXT: retq
@@ -1691,7 +1691,7 @@ define <32 x i8> @splatvar_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind "mi
; CHECK-AVX512-LABEL: splatvar_rotate_v32i8:
; CHECK-AVX512: # %bb.0:
; CHECK-AVX512-NEXT: vpbroadcastb %xmm1, %xmm1
-; CHECK-AVX512-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-AVX512-NEXT: vpmovzxbq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
; CHECK-AVX512-NEXT: vpsllw %xmm2, %ymm0, %ymm3
; CHECK-AVX512-NEXT: vmovdqa {{.*#+}} xmm4 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
@@ -1711,7 +1711,7 @@ define <32 x i8> @splatvar_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind "mi
; CHECK-VBMI-LABEL: splatvar_rotate_v32i8:
; CHECK-VBMI: # %bb.0:
; CHECK-VBMI-NEXT: vpbroadcastb %xmm1, %xmm1
-; CHECK-VBMI-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-VBMI-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-VBMI-NEXT: vpmovzxbq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
; CHECK-VBMI-NEXT: vpsllw %xmm2, %ymm0, %ymm3
; CHECK-VBMI-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
@@ -1739,12 +1739,12 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-vector
; CHECK-AVX512-LABEL: constant_rotate_v32i8:
; CHECK-AVX512: # %bb.0:
; CHECK-AVX512-NEXT: vpsllw $4, %ymm0, %ymm1
-; CHECK-AVX512-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; CHECK-AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; CHECK-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [8192,24640,41088,57536,57344,41152,24704,8256,8192,24640,41088,57536,57344,41152,24704,8256]
; CHECK-AVX512-NEXT: # ymm2 = mem[0,1,0,1]
; CHECK-AVX512-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm1
; CHECK-AVX512-NEXT: vpsllw $2, %ymm1, %ymm3
-; CHECK-AVX512-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; CHECK-AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; CHECK-AVX512-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; CHECK-AVX512-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; CHECK-AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm3
@@ -1752,10 +1752,10 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-vector
; CHECK-AVX512-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; CHECK-AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
; CHECK-AVX512-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]
-; CHECK-AVX512-NEXT: vpsllvw {{.*}}(%rip), %ymm3, %ymm3
+; CHECK-AVX512-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; CHECK-AVX512-NEXT: vpsrlw $8, %ymm3, %ymm3
; CHECK-AVX512-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]
-; CHECK-AVX512-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-AVX512-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-AVX512-NEXT: vpsrlw $8, %ymm0, %ymm0
; CHECK-AVX512-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
; CHECK-AVX512-NEXT: vpor %ymm0, %ymm1, %ymm0
@@ -1764,12 +1764,12 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-vector
; CHECK-VBMI-LABEL: constant_rotate_v32i8:
; CHECK-VBMI: # %bb.0:
; CHECK-VBMI-NEXT: vpsllw $4, %ymm0, %ymm1
-; CHECK-VBMI-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; CHECK-VBMI-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; CHECK-VBMI-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [8192,24640,41088,57536,57344,41152,24704,8256,8192,24640,41088,57536,57344,41152,24704,8256]
; CHECK-VBMI-NEXT: # ymm2 = mem[0,1,0,1]
; CHECK-VBMI-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm1
; CHECK-VBMI-NEXT: vpsllw $2, %ymm1, %ymm3
-; CHECK-VBMI-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; CHECK-VBMI-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; CHECK-VBMI-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; CHECK-VBMI-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; CHECK-VBMI-NEXT: vpaddb %ymm1, %ymm1, %ymm3
@@ -1777,9 +1777,9 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-vector
; CHECK-VBMI-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; CHECK-VBMI-NEXT: vpxor %xmm2, %xmm2, %xmm2
; CHECK-VBMI-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]
-; CHECK-VBMI-NEXT: vpsllvw {{.*}}(%rip), %ymm3, %ymm3
+; CHECK-VBMI-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; CHECK-VBMI-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]
-; CHECK-VBMI-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-VBMI-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-VBMI-NEXT: vmovdqa {{.*#+}} ymm2 = [1,3,5,7,9,11,13,15,33,35,37,39,41,43,45,47,17,19,21,23,25,27,29,31,49,51,53,55,57,59,61,63]
; CHECK-VBMI-NEXT: vpermi2b %ymm3, %ymm0, %ymm2
; CHECK-VBMI-NEXT: vpor %ymm2, %ymm1, %ymm0
@@ -1795,7 +1795,7 @@ define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-v
; CHECK: # %bb.0:
; CHECK-NEXT: vpsllw $4, %ymm0, %ymm1
; CHECK-NEXT: vpsrlw $4, %ymm0, %ymm0
-; CHECK-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; CHECK-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; CHECK-NEXT: retq
%shl = shl <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
@@ -1808,8 +1808,8 @@ define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind "min-le
; CHECK: # %bb.0:
; CHECK-NEXT: vpsllw $4, %ymm0, %ymm1
; CHECK-NEXT: vpsrlw $4, %ymm0, %ymm0
-; CHECK-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
-; CHECK-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; CHECK-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%shl = shl <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
diff --git a/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll b/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
index 93e52ded59aff..85ff93a8a549f 100644
--- a/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
+++ b/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
@@ -29,7 +29,7 @@ define void @g() #0 {
; CHECK-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %.
-; CHECK-NEXT: calll m
+; CHECK-NEXT: calll m at PLT
; CHECK-NEXT: .LBB0_2: # %k.end
entry:
%p = load i8*, i8** @f
diff --git a/llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll b/llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
index 85fa9bb2a8f8b..7983d33ed2343 100644
--- a/llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
+++ b/llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
@@ -9,7 +9,7 @@
define void @t3() nounwind {
; X86-64-LABEL: t3:
; X86-64: ## %bb.0:
-; X86-64-NEXT: movq _g_v8qi@{{.*}}(%rip), %rax
+; X86-64-NEXT: movq _g_v8qi at GOTPCREL(%rip), %rax
; X86-64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-64-NEXT: movb $1, %al
; X86-64-NEXT: jmp _pass_v8qi ## TAILCALL
diff --git a/llvm/test/CodeGen/X86/mmx-arg-passing.ll b/llvm/test/CodeGen/X86/mmx-arg-passing.ll
index 4ea00b2e9ac13..d356d1586103d 100644
--- a/llvm/test/CodeGen/X86/mmx-arg-passing.ll
+++ b/llvm/test/CodeGen/X86/mmx-arg-passing.ll
@@ -20,7 +20,7 @@ define void @t1(x86_mmx %v1) nounwind {
; X86-64-LABEL: t1:
; X86-64: ## %bb.0:
; X86-64-NEXT: movdq2q %xmm0, %mm0
-; X86-64-NEXT: movq _u1@{{.*}}(%rip), %rax
+; X86-64-NEXT: movq _u1 at GOTPCREL(%rip), %rax
; X86-64-NEXT: movq %mm0, (%rax)
; X86-64-NEXT: retq
store x86_mmx %v1, x86_mmx* @u1, align 8
@@ -41,7 +41,7 @@ define void @t2(<1 x i64> %v1) nounwind {
;
; X86-64-LABEL: t2:
; X86-64: ## %bb.0:
-; X86-64-NEXT: movq _u2@{{.*}}(%rip), %rax
+; X86-64-NEXT: movq _u2 at GOTPCREL(%rip), %rax
; X86-64-NEXT: movq %rdi, (%rax)
; X86-64-NEXT: retq
%tmp = bitcast <1 x i64> %v1 to x86_mmx
diff --git a/llvm/test/CodeGen/X86/mmx-arith.ll b/llvm/test/CodeGen/X86/mmx-arith.ll
index 36dcdb967f1eb..d4f0f751c03ec 100644
--- a/llvm/test/CodeGen/X86/mmx-arith.ll
+++ b/llvm/test/CodeGen/X86/mmx-arith.ll
@@ -33,7 +33,7 @@ define void @test0(x86_mmx* %A, x86_mmx* %B) {
; X32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-NEXT: pmullw %xmm0, %xmm1
-; X32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: packuswb %xmm1, %xmm1
; X32-NEXT: movq %xmm1, (%eax)
; X32-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
@@ -73,7 +73,7 @@ define void @test0(x86_mmx* %A, x86_mmx* %B) {
; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X64-NEXT: pmullw %xmm0, %xmm1
-; X64-NEXT: pand {{.*}}(%rip), %xmm1
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: packuswb %xmm1, %xmm1
; X64-NEXT: movq %xmm1, (%rdi)
; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
@@ -661,7 +661,7 @@ define i64 @pr43922() {
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-8, %esp
; X32-NEXT: subl $8, %esp
-; X32-NEXT: movq {{\.LCPI[0-9]+_[0-9]+}}, %mm0 # mm0 = 0x7AAAAAAA7AAAAAAA
+; X32-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}, %mm0 # mm0 = 0x7AAAAAAA7AAAAAAA
; X32-NEXT: psrad $255, %mm0
; X32-NEXT: movq %mm0, (%esp)
; X32-NEXT: movl (%esp), %eax
@@ -673,7 +673,7 @@ define i64 @pr43922() {
;
; X64-LABEL: pr43922:
; X64: # %bb.0: # %entry
-; X64-NEXT: movq {{.*}}(%rip), %mm0 # mm0 = 0x7AAAAAAA7AAAAAAA
+; X64-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %mm0 # mm0 = 0x7AAAAAAA7AAAAAAA
; X64-NEXT: psrad $255, %mm0
; X64-NEXT: movq %mm0, %rax
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/mmx-bitcast.ll b/llvm/test/CodeGen/X86/mmx-bitcast.ll
index 053c54b8e0538..9e6328aeff833 100644
--- a/llvm/test/CodeGen/X86/mmx-bitcast.ll
+++ b/llvm/test/CodeGen/X86/mmx-bitcast.ll
@@ -61,7 +61,7 @@ define void @t4(<1 x i64> %A, <1 x i64> %B) {
; CHECK-NEXT: movq %rdi, %mm0
; CHECK-NEXT: movq %rsi, %mm1
; CHECK-NEXT: paddusw %mm0, %mm1
-; CHECK-NEXT: movq _R@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _R at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq %mm1, (%rax)
; CHECK-NEXT: emms
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/mmx-fold-zero.ll b/llvm/test/CodeGen/X86/mmx-fold-zero.ll
index ad918b3ec3995..d40146453cff0 100644
--- a/llvm/test/CodeGen/X86/mmx-fold-zero.ll
+++ b/llvm/test/CodeGen/X86/mmx-fold-zero.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
@@ -32,7 +32,7 @@ define double @mmx_zero(double, double, double, double) nounwind {
; X86-NEXT: paddw %mm2, %mm0
; X86-NEXT: paddw %mm6, %mm0
; X86-NEXT: pmuludq %mm3, %mm0
-; X86-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %mm0
+; X86-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}, %mm0
; X86-NEXT: paddw %mm1, %mm0
; X86-NEXT: pmuludq %mm7, %mm0
; X86-NEXT: pmuludq (%esp), %mm0 # 8-byte Folded Reload
@@ -70,7 +70,7 @@ define double @mmx_zero(double, double, double, double) nounwind {
; X64-NEXT: paddw %mm2, %mm0
; X64-NEXT: paddw %mm6, %mm0
; X64-NEXT: pmuludq %mm3, %mm0
-; X64-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}(%rip), %mm0
+; X64-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %mm0
; X64-NEXT: paddw %mm1, %mm0
; X64-NEXT: pmuludq %mm7, %mm0
; X64-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %mm0 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/X86/movmsk-cmp.ll b/llvm/test/CodeGen/X86/movmsk-cmp.ll
index 05cc7f089ee8a..4488aeb273f70 100644
--- a/llvm/test/CodeGen/X86/movmsk-cmp.ll
+++ b/llvm/test/CodeGen/X86/movmsk-cmp.ll
@@ -939,7 +939,7 @@ define i1 @allones_v16i8_and1(<16 x i8> %arg) {
;
; SKX-LABEL: allones_v16i8_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: retq
@@ -1213,7 +1213,7 @@ define i1 @allzeros_v16i8_and1(<16 x i8> %arg) {
;
; SKX-LABEL: allzeros_v16i8_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -1267,7 +1267,7 @@ define i1 @allones_v32i8_and1(<32 x i8> %arg) {
;
; SKX-LABEL: allones_v32i8_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -1321,7 +1321,7 @@ define i1 @allzeros_v32i8_and1(<32 x i8> %arg) {
;
; SKX-LABEL: allzeros_v32i8_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -1390,7 +1390,7 @@ define i1 @allones_v64i8_and1(<64 x i8> %arg) {
;
; SKX-LABEL: allones_v64i8_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestq %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -1455,7 +1455,7 @@ define i1 @allzeros_v64i8_and1(<64 x i8> %arg) {
;
; SKX-LABEL: allzeros_v64i8_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestq %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -1500,7 +1500,7 @@ define i1 @allones_v8i16_and1(<8 x i16> %arg) {
;
; SKX-LABEL: allones_v8i16_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: retq
@@ -1542,7 +1542,7 @@ define i1 @allzeros_v8i16_and1(<8 x i16> %arg) {
;
; SKX-LABEL: allzeros_v8i16_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -1600,7 +1600,7 @@ define i1 @allones_v16i16_and1(<16 x i16> %arg) {
;
; SKX-LABEL: allones_v16i16_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -1676,7 +1676,7 @@ define i1 @allones_v32i16_and1(<32 x i16> %arg) {
;
; SKX-LABEL: allones_v32i16_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -1748,7 +1748,7 @@ define i1 @allzeros_v32i16_and1(<32 x i16> %arg) {
;
; SKX-LABEL: allzeros_v32i16_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -1805,7 +1805,7 @@ define i1 @allzeros_v16i16_and1(<16 x i16> %arg) {
;
; SKX-LABEL: allzeros_v16i16_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -1837,7 +1837,7 @@ define i1 @allones_v4i32_and1(<4 x i32> %arg) {
; KNL-LABEL: allones_v4i32_and1:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; KNL-NEXT: vptestnmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -1846,7 +1846,7 @@ define i1 @allones_v4i32_and1(<4 x i32> %arg) {
;
; SKX-LABEL: allones_v4i32_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to4}, %xmm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $15, %al
; SKX-NEXT: sete %al
@@ -1878,7 +1878,7 @@ define i1 @allzeros_v4i32_and1(<4 x i32> %arg) {
; KNL-LABEL: allzeros_v4i32_and1:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; KNL-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -1887,7 +1887,7 @@ define i1 @allzeros_v4i32_and1(<4 x i32> %arg) {
;
; SKX-LABEL: allzeros_v4i32_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to4}, %xmm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -1934,7 +1934,7 @@ define i1 @allones_v8i32_and1(<8 x i32> %arg) {
; KNL-LABEL: allones_v8i32_and1:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: cmpb $-1, %al
; KNL-NEXT: sete %al
@@ -1943,7 +1943,7 @@ define i1 @allones_v8i32_and1(<8 x i32> %arg) {
;
; SKX-LABEL: allones_v8i32_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to8}, %ymm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -1990,7 +1990,7 @@ define i1 @allzeros_v8i32_and1(<8 x i32> %arg) {
; KNL-LABEL: allzeros_v8i32_and1:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb %al, %al
; KNL-NEXT: sete %al
@@ -1999,7 +1999,7 @@ define i1 @allzeros_v8i32_and1(<8 x i32> %arg) {
;
; SKX-LABEL: allzeros_v8i32_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to8}, %ymm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -2060,7 +2060,7 @@ define i1 @allones_v16i32_and1(<16 x i32> %arg) {
;
; AVX512-LABEL: allones_v16i32_and1:
; AVX512: # %bb.0:
-; AVX512-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; AVX512-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; AVX512-NEXT: kortestw %k0, %k0
; AVX512-NEXT: setb %al
; AVX512-NEXT: vzeroupper
@@ -2119,7 +2119,7 @@ define i1 @allzeros_v16i32_and1(<16 x i32> %arg) {
;
; AVX512-LABEL: allzeros_v16i32_and1:
; AVX512: # %bb.0:
-; AVX512-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; AVX512-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; AVX512-NEXT: kortestw %k0, %k0
; AVX512-NEXT: sete %al
; AVX512-NEXT: vzeroupper
@@ -2161,7 +2161,7 @@ define i1 @allones_v2i64_and1(<2 x i64> %arg) {
;
; SKX-LABEL: allones_v2i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $3, %al
; SKX-NEXT: sete %al
@@ -2203,7 +2203,7 @@ define i1 @allzeros_v2i64_and1(<2 x i64> %arg) {
;
; SKX-LABEL: allzeros_v2i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -2249,7 +2249,7 @@ define i1 @allones_v4i64_and1(<4 x i64> %arg) {
; KNL-LABEL: allones_v4i64_and1:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestnmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -2258,7 +2258,7 @@ define i1 @allones_v4i64_and1(<4 x i64> %arg) {
;
; SKX-LABEL: allones_v4i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to4}, %ymm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $15, %al
; SKX-NEXT: sete %al
@@ -2306,7 +2306,7 @@ define i1 @allzeros_v4i64_and1(<4 x i64> %arg) {
; KNL-LABEL: allzeros_v4i64_and1:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -2315,7 +2315,7 @@ define i1 @allzeros_v4i64_and1(<4 x i64> %arg) {
;
; SKX-LABEL: allzeros_v4i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to4}, %ymm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -2376,7 +2376,7 @@ define i1 @allones_v8i64_and1(<8 x i64> %arg) {
;
; KNL-LABEL: allones_v8i64_and1:
; KNL: # %bb.0:
-; KNL-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: cmpb $-1, %al
; KNL-NEXT: sete %al
@@ -2385,7 +2385,7 @@ define i1 @allones_v8i64_and1(<8 x i64> %arg) {
;
; SKX-LABEL: allones_v8i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -2445,7 +2445,7 @@ define i1 @allzeros_v8i64_and1(<8 x i64> %arg) {
;
; KNL-LABEL: allzeros_v8i64_and1:
; KNL: # %bb.0:
-; KNL-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb %al, %al
; KNL-NEXT: sete %al
@@ -2454,7 +2454,7 @@ define i1 @allzeros_v8i64_and1(<8 x i64> %arg) {
;
; SKX-LABEL: allzeros_v8i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -2493,7 +2493,7 @@ define i1 @allones_v16i8_and4(<16 x i8> %arg) {
;
; SKX-LABEL: allones_v16i8_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: retq
@@ -2531,7 +2531,7 @@ define i1 @allzeros_v16i8_and4(<16 x i8> %arg) {
;
; SKX-LABEL: allzeros_v16i8_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -2585,7 +2585,7 @@ define i1 @allones_v32i8_and4(<32 x i8> %arg) {
;
; SKX-LABEL: allones_v32i8_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -2639,7 +2639,7 @@ define i1 @allzeros_v32i8_and4(<32 x i8> %arg) {
;
; SKX-LABEL: allzeros_v32i8_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -2708,7 +2708,7 @@ define i1 @allones_v64i8_and4(<64 x i8> %arg) {
;
; SKX-LABEL: allones_v64i8_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestq %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -2773,7 +2773,7 @@ define i1 @allzeros_v64i8_and4(<64 x i8> %arg) {
;
; SKX-LABEL: allzeros_v64i8_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmb {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestq %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -2818,7 +2818,7 @@ define i1 @allones_v8i16_and4(<8 x i16> %arg) {
;
; SKX-LABEL: allones_v8i16_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: retq
@@ -2860,7 +2860,7 @@ define i1 @allzeros_v8i16_and4(<8 x i16> %arg) {
;
; SKX-LABEL: allzeros_v8i16_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -2918,7 +2918,7 @@ define i1 @allones_v16i16_and4(<16 x i16> %arg) {
;
; SKX-LABEL: allones_v16i16_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -2994,7 +2994,7 @@ define i1 @allones_v32i16_and4(<32 x i16> %arg) {
;
; SKX-LABEL: allones_v32i16_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -3066,7 +3066,7 @@ define i1 @allzeros_v32i16_and4(<32 x i16> %arg) {
;
; SKX-LABEL: allzeros_v32i16_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %zmm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; SKX-NEXT: kortestd %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -3123,7 +3123,7 @@ define i1 @allzeros_v16i16_and4(<16 x i16> %arg) {
;
; SKX-LABEL: allzeros_v16i16_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmw {{.*}}(%rip), %ymm0, %k0
+; SKX-NEXT: vptestmw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; SKX-NEXT: kortestw %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -3155,7 +3155,7 @@ define i1 @allones_v4i32_and4(<4 x i32> %arg) {
; KNL-LABEL: allones_v4i32_and4:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; KNL-NEXT: vptestnmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -3164,7 +3164,7 @@ define i1 @allones_v4i32_and4(<4 x i32> %arg) {
;
; SKX-LABEL: allones_v4i32_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to4}, %xmm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $15, %al
; SKX-NEXT: sete %al
@@ -3196,7 +3196,7 @@ define i1 @allzeros_v4i32_and4(<4 x i32> %arg) {
; KNL-LABEL: allzeros_v4i32_and4:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; KNL-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -3205,7 +3205,7 @@ define i1 @allzeros_v4i32_and4(<4 x i32> %arg) {
;
; SKX-LABEL: allzeros_v4i32_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to4}, %xmm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -3252,7 +3252,7 @@ define i1 @allones_v8i32_and4(<8 x i32> %arg) {
; KNL-LABEL: allones_v8i32_and4:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: cmpb $-1, %al
; KNL-NEXT: sete %al
@@ -3261,7 +3261,7 @@ define i1 @allones_v8i32_and4(<8 x i32> %arg) {
;
; SKX-LABEL: allones_v8i32_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to8}, %ymm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -3308,7 +3308,7 @@ define i1 @allzeros_v8i32_and4(<8 x i32> %arg) {
; KNL-LABEL: allzeros_v8i32_and4:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; KNL-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb %al, %al
; KNL-NEXT: sete %al
@@ -3317,7 +3317,7 @@ define i1 @allzeros_v8i32_and4(<8 x i32> %arg) {
;
; SKX-LABEL: allzeros_v8i32_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmd {{.*}}(%rip){1to8}, %ymm0, %k0
+; SKX-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -3378,7 +3378,7 @@ define i1 @allones_v16i32_and4(<16 x i32> %arg) {
;
; AVX512-LABEL: allones_v16i32_and4:
; AVX512: # %bb.0:
-; AVX512-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; AVX512-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; AVX512-NEXT: kortestw %k0, %k0
; AVX512-NEXT: setb %al
; AVX512-NEXT: vzeroupper
@@ -3437,7 +3437,7 @@ define i1 @allzeros_v16i32_and4(<16 x i32> %arg) {
;
; AVX512-LABEL: allzeros_v16i32_and4:
; AVX512: # %bb.0:
-; AVX512-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm0, %k0
+; AVX512-NEXT: vptestmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k0
; AVX512-NEXT: kortestw %k0, %k0
; AVX512-NEXT: sete %al
; AVX512-NEXT: vzeroupper
@@ -3479,7 +3479,7 @@ define i1 @allones_v2i64_and4(<2 x i64> %arg) {
;
; SKX-LABEL: allones_v2i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $3, %al
; SKX-NEXT: sete %al
@@ -3521,7 +3521,7 @@ define i1 @allzeros_v2i64_and4(<2 x i64> %arg) {
;
; SKX-LABEL: allzeros_v2i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -3567,7 +3567,7 @@ define i1 @allones_v4i64_and4(<4 x i64> %arg) {
; KNL-LABEL: allones_v4i64_and4:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestnmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -3576,7 +3576,7 @@ define i1 @allones_v4i64_and4(<4 x i64> %arg) {
;
; SKX-LABEL: allones_v4i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to4}, %ymm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $15, %al
; SKX-NEXT: sete %al
@@ -3624,7 +3624,7 @@ define i1 @allzeros_v4i64_and4(<4 x i64> %arg) {
; KNL-LABEL: allzeros_v4i64_and4:
; KNL: # %bb.0:
; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb $15, %al
; KNL-NEXT: sete %al
@@ -3633,7 +3633,7 @@ define i1 @allzeros_v4i64_and4(<4 x i64> %arg) {
;
; SKX-LABEL: allzeros_v4i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to4}, %ymm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
@@ -3694,7 +3694,7 @@ define i1 @allones_v8i64_and4(<8 x i64> %arg) {
;
; KNL-LABEL: allones_v8i64_and4:
; KNL: # %bb.0:
-; KNL-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: cmpb $-1, %al
; KNL-NEXT: sete %al
@@ -3703,7 +3703,7 @@ define i1 @allones_v8i64_and4(<8 x i64> %arg) {
;
; SKX-LABEL: allones_v8i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: setb %al
; SKX-NEXT: vzeroupper
@@ -3763,7 +3763,7 @@ define i1 @allzeros_v8i64_and4(<8 x i64> %arg) {
;
; KNL-LABEL: allzeros_v8i64_and4:
; KNL: # %bb.0:
-; KNL-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; KNL-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb %al, %al
; KNL-NEXT: sete %al
@@ -3772,7 +3772,7 @@ define i1 @allzeros_v8i64_and4(<8 x i64> %arg) {
;
; SKX-LABEL: allzeros_v8i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{.*}}(%rip){1to8}, %zmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/ms-inline-asm-redundant-clobber.ll b/llvm/test/CodeGen/X86/ms-inline-asm-redundant-clobber.ll
index 7b525e09851a4..2acda02f9d6a9 100644
--- a/llvm/test/CodeGen/X86/ms-inline-asm-redundant-clobber.ll
+++ b/llvm/test/CodeGen/X86/ms-inline-asm-redundant-clobber.ll
@@ -12,11 +12,13 @@ define dso_local void @foo() local_unnamed_addr {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
-; CHECK: clc
-; CHECK-NEXT: cmpxchg8b {{.*}}(%rip)
-; CHECK-NEXT: cmpxchg16b {{.*}}(%rip)
+; CHECK-EMPTY:
; CHECK-NEXT: clc
-; CHECK: #NO_APP
+; CHECK-NEXT: cmpxchg8b test_mem(%rip)
+; CHECK-NEXT: cmpxchg16b test_mem(%rip)
+; CHECK-NEXT: clc
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
; CHECK-NEXT: retq
entry:
tail call void asm sideeffect inteldialect "clc\0A\09cmpxchg8b $0\0A\09cmpxchg16b $1\0A\09clc", "=*m,=*m,~{eax},~{edx},~{flags},~{rax},~{rdx},~{dirflag},~{fpsr},~{flags}"([16 x i8]* nonnull @test_mem, [16 x i8]* nonnull @test_mem) #1
diff --git a/llvm/test/CodeGen/X86/mul-constant-result.ll b/llvm/test/CodeGen/X86/mul-constant-result.ll
index 4f443f8b029b0..ab0f0789aaca9 100644
--- a/llvm/test/CodeGen/X86/mul-constant-result.ll
+++ b/llvm/test/CodeGen/X86/mul-constant-result.ll
@@ -530,7 +530,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $1
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %esi
@@ -539,7 +539,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $2
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -548,7 +548,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $3
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -558,7 +558,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $4
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -568,7 +568,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $5
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -578,7 +578,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $6
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -588,7 +588,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $7
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -598,7 +598,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $8
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -608,7 +608,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $9
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -618,7 +618,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $10
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -628,7 +628,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $11
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -638,7 +638,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $12
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -648,7 +648,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $13
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -658,7 +658,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $14
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -668,7 +668,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $15
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -678,7 +678,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $16
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -688,7 +688,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $17
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -698,7 +698,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $18
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -708,7 +708,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $19
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -718,7 +718,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $20
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -728,7 +728,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $21
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -738,7 +738,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $22
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -748,7 +748,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $23
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -758,7 +758,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $24
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -768,7 +768,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $25
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -778,7 +778,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $26
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -788,7 +788,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $27
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -798,7 +798,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $28
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -808,7 +808,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $29
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -818,7 +818,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $30
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi
@@ -828,7 +828,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $31
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx
@@ -839,7 +839,7 @@ define i32 @foo() local_unnamed_addr #0 {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $32
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: calll mult
+; X86-NEXT: calll mult at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: xorl $32, %eax
@@ -874,192 +874,192 @@ define i32 @foo() local_unnamed_addr #0 {
; X64-HSW-NEXT: .cfi_offset %rbp, -16
; X64-HSW-NEXT: movl $1, %edi
; X64-HSW-NEXT: xorl %esi, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $1, %ebx
; X64-HSW-NEXT: movl $2, %edi
; X64-HSW-NEXT: movl $1, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $2, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $3, %edi
; X64-HSW-NEXT: movl $1, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %r14d
; X64-HSW-NEXT: xorl $3, %r14d
; X64-HSW-NEXT: movl $4, %edi
; X64-HSW-NEXT: movl $2, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $4, %ebx
; X64-HSW-NEXT: orl %r14d, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $5, %edi
; X64-HSW-NEXT: movl $2, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %r14d
; X64-HSW-NEXT: xorl $5, %r14d
; X64-HSW-NEXT: movl $6, %edi
; X64-HSW-NEXT: movl $3, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $6, %ebp
; X64-HSW-NEXT: orl %r14d, %ebp
; X64-HSW-NEXT: movl $7, %edi
; X64-HSW-NEXT: movl $3, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %r14d
; X64-HSW-NEXT: xorl $7, %r14d
; X64-HSW-NEXT: orl %ebp, %r14d
; X64-HSW-NEXT: orl %ebx, %r14d
; X64-HSW-NEXT: movl $8, %edi
; X64-HSW-NEXT: movl $4, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $8, %ebx
; X64-HSW-NEXT: movl $9, %edi
; X64-HSW-NEXT: movl $4, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $9, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $10, %edi
; X64-HSW-NEXT: movl $5, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $10, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $11, %edi
; X64-HSW-NEXT: movl $5, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %r15d
; X64-HSW-NEXT: xorl $11, %r15d
; X64-HSW-NEXT: orl %ebx, %r15d
; X64-HSW-NEXT: orl %r14d, %r15d
; X64-HSW-NEXT: movl $12, %edi
; X64-HSW-NEXT: movl $6, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $12, %ebx
; X64-HSW-NEXT: movl $13, %edi
; X64-HSW-NEXT: movl $6, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $13, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $14, %edi
; X64-HSW-NEXT: movl $7, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $14, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $15, %edi
; X64-HSW-NEXT: movl $7, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $15, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $16, %edi
; X64-HSW-NEXT: movl $8, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %r14d
; X64-HSW-NEXT: xorl $16, %r14d
; X64-HSW-NEXT: orl %ebp, %r14d
; X64-HSW-NEXT: orl %r15d, %r14d
; X64-HSW-NEXT: movl $17, %edi
; X64-HSW-NEXT: movl $8, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $17, %ebp
; X64-HSW-NEXT: movl $18, %edi
; X64-HSW-NEXT: movl $9, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $18, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $19, %edi
; X64-HSW-NEXT: movl $9, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $19, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $20, %edi
; X64-HSW-NEXT: movl $10, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $20, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $21, %edi
; X64-HSW-NEXT: movl $10, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $21, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $22, %edi
; X64-HSW-NEXT: movl $11, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %r15d
; X64-HSW-NEXT: xorl $22, %r15d
; X64-HSW-NEXT: orl %ebp, %r15d
; X64-HSW-NEXT: orl %r14d, %r15d
; X64-HSW-NEXT: movl $23, %edi
; X64-HSW-NEXT: movl $11, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $23, %ebp
; X64-HSW-NEXT: movl $24, %edi
; X64-HSW-NEXT: movl $12, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $24, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $25, %edi
; X64-HSW-NEXT: movl $12, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $25, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $26, %edi
; X64-HSW-NEXT: movl $13, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $26, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $27, %edi
; X64-HSW-NEXT: movl $13, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $27, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: movl $28, %edi
; X64-HSW-NEXT: movl $14, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $28, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $29, %edi
; X64-HSW-NEXT: movl $14, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebp
; X64-HSW-NEXT: xorl $29, %ebp
; X64-HSW-NEXT: orl %ebx, %ebp
; X64-HSW-NEXT: orl %r15d, %ebp
; X64-HSW-NEXT: movl $30, %edi
; X64-HSW-NEXT: movl $15, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %r14d
; X64-HSW-NEXT: xorl $30, %r14d
; X64-HSW-NEXT: movl $31, %edi
; X64-HSW-NEXT: movl $15, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $31, %ebx
; X64-HSW-NEXT: orl %r14d, %ebx
; X64-HSW-NEXT: orl %ebp, %ebx
; X64-HSW-NEXT: movl $32, %edi
; X64-HSW-NEXT: movl $16, %esi
-; X64-HSW-NEXT: callq mult
+; X64-HSW-NEXT: callq mult at PLT
; X64-HSW-NEXT: xorl $32, %eax
; X64-HSW-NEXT: xorl %ecx, %ecx
; X64-HSW-NEXT: orl %ebx, %eax
diff --git a/llvm/test/CodeGen/X86/mul128.ll b/llvm/test/CodeGen/X86/mul128.ll
index df7e5ddc6aeb2..fd517357d5fa1 100644
--- a/llvm/test/CodeGen/X86/mul128.ll
+++ b/llvm/test/CodeGen/X86/mul128.ll
@@ -106,15 +106,15 @@ define i128 @foo(i128 %t, i128 %u) {
define void @PR13897() nounwind {
; X64-LABEL: PR13897:
; X64: # %bb.0: # %"0x0"
-; X64-NEXT: movl {{.*}}(%rip), %ecx
+; X64-NEXT: movl bbb(%rip), %ecx
; X64-NEXT: movabsq $4294967297, %rdx # imm = 0x100000001
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: mulq %rdx
; X64-NEXT: addq %rcx, %rdx
; X64-NEXT: shlq $32, %rcx
; X64-NEXT: addq %rcx, %rdx
-; X64-NEXT: movq %rax, {{.*}}(%rip)
-; X64-NEXT: movq %rdx, aaa+{{.*}}(%rip)
+; X64-NEXT: movq %rax, aaa(%rip)
+; X64-NEXT: movq %rdx, aaa+8(%rip)
; X64-NEXT: retq
;
; X86-LABEL: PR13897:
diff --git a/llvm/test/CodeGen/X86/musttail-varargs.ll b/llvm/test/CodeGen/X86/musttail-varargs.ll
index e7842031ba1d3..067e7aefb3eac 100644
--- a/llvm/test/CodeGen/X86/musttail-varargs.ll
+++ b/llvm/test/CodeGen/X86/musttail-varargs.ll
@@ -334,7 +334,7 @@ define void @h_thunk(%struct.Foo* %this, ...) {
; LINUX-NEXT: jmpq *%r11 # TAILCALL
; LINUX-NEXT: .LBB2_2: # %else
; LINUX-NEXT: movq 16(%rdi), %r11
-; LINUX-NEXT: movl $42, {{.*}}(%rip)
+; LINUX-NEXT: movl $42, g(%rip)
; LINUX-NEXT: jmpq *%r11 # TAILCALL
;
; LINUX-X32-LABEL: h_thunk:
@@ -347,7 +347,7 @@ define void @h_thunk(%struct.Foo* %this, ...) {
; LINUX-X32-NEXT: jmpq *%r11 # TAILCALL
; LINUX-X32-NEXT: .LBB2_2: # %else
; LINUX-X32-NEXT: movl 8(%edi), %r11d
-; LINUX-X32-NEXT: movl $42, {{.*}}(%rip)
+; LINUX-X32-NEXT: movl $42, g(%rip)
; LINUX-X32-NEXT: movl %edi, %edi
; LINUX-X32-NEXT: jmpq *%r11 # TAILCALL
;
@@ -360,7 +360,7 @@ define void @h_thunk(%struct.Foo* %this, ...) {
; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL
; WINDOWS-NEXT: .LBB2_2: # %else
; WINDOWS-NEXT: movq 16(%rcx), %rax
-; WINDOWS-NEXT: movl $42, {{.*}}(%rip)
+; WINDOWS-NEXT: movl $42, g(%rip)
; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL
;
; X86-LABEL: h_thunk:
diff --git a/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll
index bd770c3bb7a8b..f0917be887448 100644
--- a/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll
@@ -10,17 +10,17 @@ target triple = "x86_64-unknown-unknown"
define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 {
; CHECK-LABEL: reverse_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: pxor %xmm1, %xmm1
-; CHECK-NEXT: movdqa %xmm0, %xmm2
-; CHECK-NEXT: punpcklbw %xmm1, %xmm
-; CHECK-NEXT: pshufd $78, %xmm2, %xmm2
-; CHECK-NEXT: pshuflw $27, %xmm2, %xmm2
-; CHECK-NEXT: pshufhw $27, %xmm2, %xmm2
-; CHECK-NEXT: punpckhbw %xmm1, %xmm0
-; CHECK-NEXT: pshufd $78, %xmm0, %xmm0
-; CHECK-NEXT: pshuflw $27, %xmm0, %xmm0
-; CHECK-NEXT: pshufhw $27, %xmm0, %xmm0
-; CHECK-NEXT: packuswb %xmm2, %xmm0
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: movdqa %xmm0, %xmm2
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
+; CHECK-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
+; CHECK-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
+; CHECK-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
+; CHECK-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
+; CHECK-NEXT: packuswb %xmm2, %xmm0
; CHECK-NEXT: retq
%res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a)
@@ -30,9 +30,9 @@ define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 {
define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 {
; CHECK-LABEL: reverse_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd $78, %xmm0, %xmm
-; CHECK-NEXT: pshuflw $27, %xmm0, %xmm0
-; CHECK-NEXT: pshufhw $27, %xmm0, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
+; CHECK-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a)
ret <8 x i16> %res
@@ -41,7 +41,7 @@ define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 {
define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
; CHECK-LABEL: reverse_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd $27, %xmm0, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a)
ret <4 x i32> %res
@@ -50,7 +50,7 @@ define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 {
; CHECK-LABEL: reverse_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd $78, %xmm0, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a)
ret <2 x i64> %res
@@ -59,7 +59,7 @@ define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 {
define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
; CHECK-LABEL: reverse_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: shufps $27, %xmm0, %xmm0
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
; CHECK-NEXT: retq
%res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a)
ret <4 x float> %res
@@ -68,7 +68,7 @@ define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
define <2 x double> @reverse_v2f64(<2 x double> %a) #0 {
; CHECK-LABEL: reverse_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: shufps $78, %xmm0, %xmm0
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3,0,1]
; CHECK-NEXT: retq
%res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a)
ret <2 x double> %res
@@ -78,10 +78,10 @@ define <2 x double> @reverse_v2f64(<2 x double> %a) #0 {
define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
; CHECK-LABEL: reverse_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: movdqa %xmm0, %xmm1
-; CHECK-NEXT: psrlw $8, %xmm1
-; CHECK-NEXT: psllw $8, %xmm0
-; CHECK-NEXT: por %xmm1, %xmm0
+; CHECK-NEXT: movdqa %xmm0, %xmm1
+; CHECK-NEXT: psrlw $8, %xmm1
+; CHECK-NEXT: psllw $8, %xmm0
+; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
ret <2 x i8> %res
@@ -91,8 +91,8 @@ define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
; CHECK-LABEL: reverse_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd $27, %xmm1, %xmm2
-; CHECK-NEXT: pshufd $27, %xmm0, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,2,1,0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,2,1,0]
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
@@ -103,16 +103,17 @@ define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
; CHECK-LABEL: reverse_v16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps %xmm1, %xmm4
-; CHECK-NEXT: movaps %xmm0, %xmm5
-; CHECK-NEXT: shufps $27, %xmm3, %xmm
-; CHECK-NEXT: shufps $27, %xmm2, %xmm2
-; CHECK-NEXT: shufps $27, %xmm1, %xmm4
-; CHECK-NEXT: shufps $27, %xmm0, %xmm5
-; CHECK-NEXT: movaps %xmm3, %xmm0
-; CHECK-NEXT: movaps %xmm2, %xmm1
-; CHECK-NEXT: movaps %xmm4, %xmm2
-; CHECK-NEXT: movaps %xmm5, %xmm3
+; CHECK-NEXT: movaps %xmm1, %xmm4
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,2,1,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,2,1,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,2],xmm1[1,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,2],xmm0[1,0]
+; CHECK-NEXT: movaps %xmm3, %xmm0
+; CHECK-NEXT: movaps %xmm2, %xmm1
+; CHECK-NEXT: movaps %xmm4, %xmm2
+; CHECK-NEXT: movaps %xmm5, %xmm3
+; CHECK-NEXT: retq
%res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
ret <16 x float> %res
diff --git a/llvm/test/CodeGen/X86/narrow_op-1.ll b/llvm/test/CodeGen/X86/narrow_op-1.ll
index 8e6eda095156b..0254c11a7b946 100644
--- a/llvm/test/CodeGen/X86/narrow_op-1.ll
+++ b/llvm/test/CodeGen/X86/narrow_op-1.ll
@@ -7,7 +7,7 @@
define dso_local void @t1() nounwind optsize ssp {
; CHECK-LABEL: t1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orb $1, bfi+{{.*}}(%rip)
+; CHECK-NEXT: orb $1, bfi+10(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i32, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
@@ -20,7 +20,7 @@ entry:
define dso_local void @t2() nounwind optsize ssp {
; CHECK-LABEL: t2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl $16842752, bfi+{{.*}}(%rip) # imm = 0x1010000
+; CHECK-NEXT: orl $16842752, bfi+8(%rip) # imm = 0x1010000
; CHECK-NEXT: retq
entry:
%0 = load i32, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
diff --git a/llvm/test/CodeGen/X86/neg_fp.ll b/llvm/test/CodeGen/X86/neg_fp.ll
index a82d51a236f52..b71565603d747 100644
--- a/llvm/test/CodeGen/X86/neg_fp.ll
+++ b/llvm/test/CodeGen/X86/neg_fp.ll
@@ -10,7 +10,7 @@ define float @negfp(float %a, float %b) nounwind {
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: subss {{[0-9]+}}(%esp), %xmm0
-; CHECK-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp)
; CHECK-NEXT: popl %eax
diff --git a/llvm/test/CodeGen/X86/negate.ll b/llvm/test/CodeGen/X86/negate.ll
index 4026ed3b67ba7..38751d954b05e 100644
--- a/llvm/test/CodeGen/X86/negate.ll
+++ b/llvm/test/CodeGen/X86/negate.ll
@@ -54,7 +54,7 @@ define i8 @negate_zero_or_minsigned(i8 %x) {
define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) {
; CHECK-LABEL: negate_zero_or_minsigned_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
%neg = sub <4 x i32> zeroinitializer, %signbit
diff --git a/llvm/test/CodeGen/X86/negative-sin.ll b/llvm/test/CodeGen/X86/negative-sin.ll
index 9f00dbb01ff69..f24507d3a4f38 100644
--- a/llvm/test/CodeGen/X86/negative-sin.ll
+++ b/llvm/test/CodeGen/X86/negative-sin.ll
@@ -11,7 +11,7 @@ define double @strict(double %e) nounwind {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vsubsd %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: callq sin
+; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vsubsd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: popq %rax
@@ -55,8 +55,8 @@ define double @semi_strict1(double %e) nounwind {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vsubsd %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: callq sin
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: callq sin at PLT
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
%f = fsub double 0.0, %e
@@ -71,7 +71,7 @@ define double @semi_strict2(double %e) nounwind {
; CHECK-LABEL: semi_strict2:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq sin
+; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll b/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll
index 18441ee651e9a..e21d4de178719 100644
--- a/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll
+++ b/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll
@@ -22,7 +22,7 @@ define void @foo(i32 %N) nounwind {
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: cvtsi2sd %ebp, %xmm0
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: decl %ebp
; CHECK-NEXT: cmpl %ebp, %ebx
; CHECK-NEXT: jne .LBB0_2
diff --git a/llvm/test/CodeGen/X86/no-sse-x86.ll b/llvm/test/CodeGen/X86/no-sse-x86.ll
index b3af3161a7945..4c79b328a2072 100644
--- a/llvm/test/CodeGen/X86/no-sse-x86.ll
+++ b/llvm/test/CodeGen/X86/no-sse-x86.ll
@@ -13,19 +13,19 @@ define void @test() nounwind {
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss %xmm0, (%esp)
-; CHECK-NEXT: calll foo1
+; CHECK-NEXT: calll foo1 at PLT
; CHECK-NEXT: fstps f
; CHECK-NEXT: fldl d
; CHECK-NEXT: fstpl (%esp)
-; CHECK-NEXT: calll foo2
+; CHECK-NEXT: calll foo2 at PLT
; CHECK-NEXT: fstpl d
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss %xmm0, (%esp)
-; CHECK-NEXT: calll foo3
+; CHECK-NEXT: calll foo3 at PLT
; CHECK-NEXT: fstps f
; CHECK-NEXT: fldl d
; CHECK-NEXT: fstpl (%esp)
-; CHECK-NEXT: calll foo4
+; CHECK-NEXT: calll foo4 at PLT
; CHECK-NEXT: fstpl d
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
@@ -35,19 +35,19 @@ define void @test() nounwind {
; NOSSE-NEXT: subl $12, %esp
; NOSSE-NEXT: flds f
; NOSSE-NEXT: fstps (%esp)
-; NOSSE-NEXT: calll foo1
+; NOSSE-NEXT: calll foo1 at PLT
; NOSSE-NEXT: fstps f
; NOSSE-NEXT: fldl d
; NOSSE-NEXT: fstpl (%esp)
-; NOSSE-NEXT: calll foo2
+; NOSSE-NEXT: calll foo2 at PLT
; NOSSE-NEXT: fstpl d
; NOSSE-NEXT: flds f
; NOSSE-NEXT: fstps (%esp)
-; NOSSE-NEXT: calll foo3
+; NOSSE-NEXT: calll foo3 at PLT
; NOSSE-NEXT: fstps f
; NOSSE-NEXT: fldl d
; NOSSE-NEXT: fstpl (%esp)
-; NOSSE-NEXT: calll foo4
+; NOSSE-NEXT: calll foo4 at PLT
; NOSSE-NEXT: fstpl d
; NOSSE-NEXT: addl $12, %esp
; NOSSE-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/nobt.ll b/llvm/test/CodeGen/X86/nobt.ll
index b994b7f950fd2..b915e45c1c8a4 100644
--- a/llvm/test/CodeGen/X86/nobt.ll
+++ b/llvm/test/CodeGen/X86/nobt.ll
@@ -11,7 +11,7 @@ define void @test2(i32 %x, i32 %n) nounwind {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb
-; CHECK-NEXT: calll foo
+; CHECK-NEXT: calll foo at PLT
; CHECK-NEXT: .LBB0_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry:
@@ -36,7 +36,7 @@ define void @test3(i32 %x, i32 %n) nounwind {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_2
; CHECK-NEXT: # %bb.1: # %bb
-; CHECK-NEXT: calll foo
+; CHECK-NEXT: calll foo at PLT
; CHECK-NEXT: .LBB1_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry:
@@ -61,7 +61,7 @@ define void @test4(i32 %x, i32 %n) nounwind {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB2_2
; CHECK-NEXT: # %bb.1: # %bb
-; CHECK-NEXT: calll foo
+; CHECK-NEXT: calll foo at PLT
; CHECK-NEXT: .LBB2_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry:
@@ -86,7 +86,7 @@ define void @test5(i32 %x, i32 %n) nounwind {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_2
; CHECK-NEXT: # %bb.1: # %bb
-; CHECK-NEXT: calll foo
+; CHECK-NEXT: calll foo at PLT
; CHECK-NEXT: .LBB3_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/nontemporal-loads.ll b/llvm/test/CodeGen/X86/nontemporal-loads.ll
index 830f623745584..16e684b633349 100644
--- a/llvm/test/CodeGen/X86/nontemporal-loads.ll
+++ b/llvm/test/CodeGen/X86/nontemporal-loads.ll
@@ -1857,7 +1857,7 @@ define i32 @PR39256(float* %ptr) {
; SSE-LABEL: PR39256:
; SSE: # %bb.0: # %entry
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-NEXT: ucomiss {{.*}}(%rip), %xmm0
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: setb (%rax)
; SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; SSE-NEXT: retq
@@ -1865,7 +1865,7 @@ define i32 @PR39256(float* %ptr) {
; AVX-LABEL: PR39256:
; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vucomiss {{.*}}(%rip), %xmm0
+; AVX-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX-NEXT: setb (%rax)
; AVX-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; AVX-NEXT: retq
@@ -1873,7 +1873,7 @@ define i32 @PR39256(float* %ptr) {
; AVX512-LABEL: PR39256:
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX512-NEXT: vucomiss {{.*}}(%rip), %xmm0
+; AVX512-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX512-NEXT: setb (%rax)
; AVX512-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; AVX512-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/nontemporal.ll b/llvm/test/CodeGen/X86/nontemporal.ll
index ae80496bcdc24..40f976bf4960a 100644
--- a/llvm/test/CodeGen/X86/nontemporal.ll
+++ b/llvm/test/CodeGen/X86/nontemporal.ll
@@ -20,21 +20,21 @@ define i32 @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4
; X86-SSE-NEXT: movl 8(%ebp), %esi
; X86-SSE-NEXT: movl 80(%ebp), %edx
; X86-SSE-NEXT: movl (%edx), %eax
-; X86-SSE-NEXT: addps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movntps %xmm0, (%esi)
-; X86-SSE-NEXT: paddq {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm2, (%esi)
-; X86-SSE-NEXT: addpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntpd %xmm1, (%esi)
-; X86-SSE-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm6
+; X86-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm6
; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm6, (%esi)
-; X86-SSE-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm5
+; X86-SSE-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm5
; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm5, (%esi)
-; X86-SSE-NEXT: paddb {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
+; X86-SSE-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm4, (%esi)
; X86-SSE-NEXT: addl (%edx), %eax
@@ -62,21 +62,21 @@ define i32 @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4
; X86-AVX-NEXT: movl 8(%ebp), %edx
; X86-AVX-NEXT: movl 80(%ebp), %esi
; X86-AVX-NEXT: movl (%esi), %eax
-; X86-AVX-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovntps %xmm0, (%edx)
-; X86-AVX-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm0
+; X86-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
-; X86-AVX-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
+; X86-AVX-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntpd %xmm0, (%edx)
-; X86-AVX-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm6, %xmm0
+; X86-AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm6, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
-; X86-AVX-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm5, %xmm0
+; X86-AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm5, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
-; X86-AVX-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %xmm4, %xmm0
+; X86-AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
; X86-AVX-NEXT: addl (%esi), %eax
@@ -92,21 +92,21 @@ define i32 @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4
; X64-SSE-LABEL: f:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl (%rcx), %eax
-; X64-SSE-NEXT: addps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: movntps %xmm0, (%rdi)
-; X64-SSE-NEXT: paddq {{.*}}(%rip), %xmm2
+; X64-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-SSE-NEXT: addl (%rcx), %eax
; X64-SSE-NEXT: movntdq %xmm2, (%rdi)
-; X64-SSE-NEXT: addpd {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: addl (%rcx), %eax
; X64-SSE-NEXT: movntpd %xmm1, (%rdi)
-; X64-SSE-NEXT: paddd {{.*}}(%rip), %xmm3
+; X64-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; X64-SSE-NEXT: addl (%rcx), %eax
; X64-SSE-NEXT: movntdq %xmm3, (%rdi)
-; X64-SSE-NEXT: paddw {{.*}}(%rip), %xmm4
+; X64-SSE-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; X64-SSE-NEXT: addl (%rcx), %eax
; X64-SSE-NEXT: movntdq %xmm4, (%rdi)
-; X64-SSE-NEXT: paddb {{.*}}(%rip), %xmm5
+; X64-SSE-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; X64-SSE-NEXT: addl (%rcx), %eax
; X64-SSE-NEXT: movntdq %xmm5, (%rdi)
; X64-SSE-NEXT: addl (%rcx), %eax
@@ -119,21 +119,21 @@ define i32 @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4
; X64-AVX-LABEL: f:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl (%rcx), %eax
-; X64-AVX-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovntps %xmm0, (%rdi)
-; X64-AVX-NEXT: vpaddq {{.*}}(%rip), %xmm2, %xmm0
+; X64-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; X64-AVX-NEXT: addl (%rcx), %eax
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
-; X64-AVX-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm0
+; X64-AVX-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; X64-AVX-NEXT: addl (%rcx), %eax
; X64-AVX-NEXT: vmovntpd %xmm0, (%rdi)
-; X64-AVX-NEXT: vpaddd {{.*}}(%rip), %xmm3, %xmm0
+; X64-AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm0
; X64-AVX-NEXT: addl (%rcx), %eax
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
-; X64-AVX-NEXT: vpaddw {{.*}}(%rip), %xmm4, %xmm0
+; X64-AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm0
; X64-AVX-NEXT: addl (%rcx), %eax
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
-; X64-AVX-NEXT: vpaddb {{.*}}(%rip), %xmm5, %xmm0
+; X64-AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm0
; X64-AVX-NEXT: addl (%rcx), %eax
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
; X64-AVX-NEXT: addl (%rcx), %eax
diff --git a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
index 637814b756c8e..ddd03846c12ab 100644
--- a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
+++ b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
@@ -81,7 +81,7 @@ define i1 @p3_scalar_shifted2_urem_by_const(i32 %x, i32 %y) {
define <4 x i1> @p4_vector_urem_by_const__splat(<4 x i32> %x, <4 x i32> %y) {
; SSE2-LABEL: p4_vector_urem_by_const__splat:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -93,16 +93,16 @@ define <4 x i1> @p4_vector_urem_by_const__splat(<4 x i32> %x, <4 x i32> %y) {
; SSE2-NEXT: psrld $1, %xmm0
; SSE2-NEXT: pslld $31, %xmm3
; SSE2-NEXT: por %xmm0, %xmm3
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: p4_vector_urem_by_const__splat:
; SSE4: # %bb.0:
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE4-NEXT: pmulld {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: psrld $1, %xmm0
; SSE4-NEXT: movdqa {{.*#+}} xmm1 = [715827882,715827882,715827882,715827882]
; SSE4-NEXT: pminud %xmm0, %xmm1
@@ -129,34 +129,34 @@ define <4 x i1> @p4_vector_urem_by_const__splat(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @p5_vector_urem_by_const__nonsplat(<4 x i32> %x, <4 x i32> %y) {
; SSE2-LABEL: p5_vector_urem_by_const__nonsplat:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,954437177]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm1, %xmm0
-; SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm2, %xmm1
-; SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,2,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE2-NEXT: por %xmm3, %xmm2
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm2
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: p5_vector_urem_by_const__nonsplat:
; SSE4: # %bb.0:
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE4-NEXT: pmulld {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; SSE4-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; SSE4-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE4-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -169,12 +169,12 @@ define <4 x i1> @p5_vector_urem_by_const__nonsplat(<4 x i32> %x, <4 x i32> %y) {
;
; AVX2-LABEL: p5_vector_urem_by_const__nonsplat:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
%t0 = and <4 x i32> %x, <i32 128, i32 2, i32 4, i32 8>
@@ -186,7 +186,7 @@ define <4 x i1> @p5_vector_urem_by_const__nonsplat(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @p6_vector_urem_by_const__nonsplat_undef0(<4 x i32> %x, <4 x i32> %y) {
; SSE2-LABEL: p6_vector_urem_by_const__nonsplat_undef0:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -198,16 +198,16 @@ define <4 x i1> @p6_vector_urem_by_const__nonsplat_undef0(<4 x i32> %x, <4 x i32
; SSE2-NEXT: psrld $1, %xmm0
; SSE2-NEXT: pslld $31, %xmm3
; SSE2-NEXT: por %xmm0, %xmm3
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: p6_vector_urem_by_const__nonsplat_undef0:
; SSE4: # %bb.0:
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE4-NEXT: pmulld {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: movdqa %xmm0, %xmm1
; SSE4-NEXT: psrld $1, %xmm1
; SSE4-NEXT: pslld $31, %xmm0
@@ -239,7 +239,7 @@ define <4 x i1> @p6_vector_urem_by_const__nonsplat_undef0(<4 x i32> %x, <4 x i32
define <4 x i1> @p7_vector_urem_by_const__nonsplat_undef2(<4 x i32> %x, <4 x i32> %y) {
; SSE2-LABEL: p7_vector_urem_by_const__nonsplat_undef2:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pmuludq %xmm1, %xmm2
@@ -249,7 +249,7 @@ define <4 x i1> @p7_vector_urem_by_const__nonsplat_undef2(<4 x i32> %x, <4 x i32
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; SSE2-NEXT: psrld $2, %xmm2
-; SSE2-NEXT: pmaddwd {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psubd %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
@@ -257,7 +257,7 @@ define <4 x i1> @p7_vector_urem_by_const__nonsplat_undef2(<4 x i32> %x, <4 x i32
;
; SSE4-LABEL: p7_vector_urem_by_const__nonsplat_undef2:
; SSE4: # %bb.0:
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE4-NEXT: movdqa {{.*#+}} xmm2 = [2863311531,2863311531,2863311531,2863311531]
; SSE4-NEXT: pmuludq %xmm2, %xmm1
@@ -265,7 +265,7 @@ define <4 x i1> @p7_vector_urem_by_const__nonsplat_undef2(<4 x i32> %x, <4 x i32
; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; SSE4-NEXT: psrld $2, %xmm2
-; SSE4-NEXT: pmaddwd {{.*}}(%rip), %xmm2
+; SSE4-NEXT: pmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE4-NEXT: psubd %xmm2, %xmm0
; SSE4-NEXT: pxor %xmm1, %xmm1
; SSE4-NEXT: pcmpeqd %xmm1, %xmm0
@@ -282,7 +282,7 @@ define <4 x i1> @p7_vector_urem_by_const__nonsplat_undef2(<4 x i32> %x, <4 x i32
; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
; AVX2-NEXT: vpsrld $2, %xmm1, %xmm1
-; AVX2-NEXT: vpmaddwd {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -296,7 +296,7 @@ define <4 x i1> @p7_vector_urem_by_const__nonsplat_undef2(<4 x i32> %x, <4 x i32
define <4 x i1> @p8_vector_urem_by_const__nonsplat_undef3(<4 x i32> %x, <4 x i32> %y) {
; SSE2-LABEL: p8_vector_urem_by_const__nonsplat_undef3:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pmuludq %xmm1, %xmm2
@@ -320,7 +320,7 @@ define <4 x i1> @p8_vector_urem_by_const__nonsplat_undef3(<4 x i32> %x, <4 x i32
;
; SSE4-LABEL: p8_vector_urem_by_const__nonsplat_undef3:
; SSE4: # %bb.0:
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE4-NEXT: movdqa {{.*#+}} xmm2 = [2863311531,2863311531,2863311531,2863311531]
; SSE4-NEXT: pmuludq %xmm2, %xmm1
@@ -328,7 +328,7 @@ define <4 x i1> @p8_vector_urem_by_const__nonsplat_undef3(<4 x i32> %x, <4 x i32
; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; SSE4-NEXT: psrld $2, %xmm2
-; SSE4-NEXT: pmulld {{.*}}(%rip), %xmm2
+; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE4-NEXT: psubd %xmm2, %xmm0
; SSE4-NEXT: pxor %xmm1, %xmm1
; SSE4-NEXT: pcmpeqd %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/packss.ll b/llvm/test/CodeGen/X86/packss.ll
index c395cf84ce34e..1505ed7e45320 100644
--- a/llvm/test/CodeGen/X86/packss.ll
+++ b/llvm/test/CodeGen/X86/packss.ll
@@ -121,28 +121,28 @@ define <8 x i16> @trunc_ashr_v4i32_icmp_v4i32(<4 x i32> %a, <4 x i32> %b) nounwi
; X86-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrad $31, %xmm0
-; X86-SSE-NEXT: pcmpgtd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: packssdw %xmm1, %xmm0
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsrad $31, %xmm0, %xmm0
-; X86-AVX-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-AVX-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; X86-AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: psrad $31, %xmm0
-; X64-SSE-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: packssdw %xmm1, %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpsrad $31, %xmm0, %xmm0
-; X64-AVX-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = ashr <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31>
diff --git a/llvm/test/CodeGen/X86/paddus.ll b/llvm/test/CodeGen/X86/paddus.ll
index 23024d5e68537..7dd676d87866e 100644
--- a/llvm/test/CodeGen/X86/paddus.ll
+++ b/llvm/test/CodeGen/X86/paddus.ll
@@ -51,12 +51,12 @@ define <16 x i8> @test1(<16 x i8> %x) {
define <16 x i8> @test2(<16 x i8> %x) {
; SSE-LABEL: test2:
; SSE: # %bb.0:
-; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test2:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <16 x i8> %x, <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>
%2 = icmp ugt <16 x i8> %x, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
@@ -67,12 +67,12 @@ define <16 x i8> @test2(<16 x i8> %x) {
define <16 x i8> @test3(<16 x i8> %x) {
; SSE-LABEL: test3:
; SSE: # %bb.0:
-; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test3:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <16 x i8> %x, <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>
%2 = icmp ugt <16 x i8> %x, <i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126>
@@ -83,12 +83,12 @@ define <16 x i8> @test3(<16 x i8> %x) {
define <16 x i8> @test4(<16 x i8> %x) {
; SSE-LABEL: test4:
; SSE: # %bb.0:
-; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test4:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <16 x i8> %x, <i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2>
%2 = icmp ugt <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -111,7 +111,7 @@ define <16 x i8> @test5(<16 x i8> %x) {
;
; AVX1-LABEL: test5:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpmaxub %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpcmpeqb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
@@ -121,7 +121,7 @@ define <16 x i8> @test5(<16 x i8> %x) {
;
; AVX2-LABEL: test5:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpmaxub %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpcmpeqb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
@@ -131,7 +131,7 @@ define <16 x i8> @test5(<16 x i8> %x) {
;
; AVX512-LABEL: test5:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512-NEXT: vpcmpltub %xmm0, %xmm1, %k1
; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovdqu8 %xmm0, %xmm1 {%k1}
@@ -146,12 +146,12 @@ define <16 x i8> @test5(<16 x i8> %x) {
define <16 x i8> @test6(<16 x i8> %x) {
; SSE-LABEL: test6:
; SSE: # %bb.0:
-; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test6:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <16 x i8> %x, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
%2 = icmp ugt <16 x i8> %x, <i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3>
@@ -227,12 +227,12 @@ define <32 x i8> @test8(<32 x i8> %x) {
;
; AVX2-LABEL: test8:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <32 x i8> %x, <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>
%2 = icmp ugt <32 x i8> %x, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
@@ -259,12 +259,12 @@ define <32 x i8> @test9(<32 x i8> %x) {
;
; AVX2-LABEL: test9:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test9:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <32 x i8> %x, <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>
%2 = icmp ugt <32 x i8> %x, <i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126>
@@ -291,12 +291,12 @@ define <32 x i8> @test10(<32 x i8> %x) {
;
; AVX2-LABEL: test10:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test10:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <32 x i8> %x, <i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2>
%2 = icmp ugt <32 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -324,7 +324,7 @@ define <32 x i8> @test11(<32 x i8> %x) {
;
; AVX1-LABEL: test11:
; AVX1: # %bb.0:
-; AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm1
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpmaxub %xmm2, %xmm3, %xmm2
@@ -340,7 +340,7 @@ define <32 x i8> @test11(<32 x i8> %x) {
;
; AVX2-LABEL: test11:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpmaxub %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpcmpeqb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
@@ -350,7 +350,7 @@ define <32 x i8> @test11(<32 x i8> %x) {
;
; AVX512-LABEL: test11:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm1
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512-NEXT: vpcmpltub %ymm0, %ymm1, %k1
; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512-NEXT: vmovdqu8 %ymm0, %ymm1 {%k1}
@@ -381,12 +381,12 @@ define <32 x i8> @test12(<32 x i8> %x) {
;
; AVX2-LABEL: test12:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test12:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <32 x i8> %x, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
%2 = icmp ugt <32 x i8> %x, <i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3>
@@ -494,7 +494,7 @@ define <64 x i8> @test14(<64 x i8> %x) {
;
; AVX512-LABEL: test14:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <64 x i8> %x, <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>
%2 = icmp ugt <64 x i8> %x, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
@@ -534,7 +534,7 @@ define <64 x i8> @test15(<64 x i8> %x) {
;
; AVX512-LABEL: test15:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <64 x i8> %x, <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>
%2 = icmp ugt <64 x i8> %x, <i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126>
@@ -574,7 +574,7 @@ define <64 x i8> @test16(<64 x i8> %x) {
;
; AVX512-LABEL: test16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <64 x i8> %x, <i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2>
%2 = icmp ugt <64 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -658,7 +658,7 @@ define <64 x i8> @test17(<64 x i8> %x) {
;
; AVX512-LABEL: test17:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxorq {{.*}}(%rip), %zmm0, %zmm1
+; AVX512-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
; AVX512-NEXT: vpcmpltub %zmm0, %zmm1, %k1
; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; AVX512-NEXT: vmovdqu8 %zmm0, %zmm1 {%k1}
@@ -702,7 +702,7 @@ define <64 x i8> @test18(<64 x i8> %x) {
;
; AVX512-LABEL: test18:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusb {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <64 x i8> %x, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
%2 = icmp ugt <64 x i8> %x, <i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3, i8 -3>
@@ -753,12 +753,12 @@ define <8 x i16> @test19(<8 x i16> %x) {
define <8 x i16> @test20(<8 x i16> %x) {
; SSE-LABEL: test20:
; SSE: # %bb.0:
-; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test20:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <8 x i16> %x, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>
%2 = icmp ugt <8 x i16> %x, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
@@ -769,12 +769,12 @@ define <8 x i16> @test20(<8 x i16> %x) {
define <8 x i16> @test21(<8 x i16> %x) {
; SSE-LABEL: test21:
; SSE: # %bb.0:
-; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test21:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <8 x i16> %x, <i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767>
%2 = icmp ugt <8 x i16> %x, <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>
@@ -785,12 +785,12 @@ define <8 x i16> @test21(<8 x i16> %x) {
define <8 x i16> @test22(<8 x i16> %x) {
; SSE-LABEL: test22:
; SSE: # %bb.0:
-; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test22:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <8 x i16> %x, <i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2>
%2 = icmp ugt <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -832,7 +832,7 @@ define <8 x i16> @test23(<8 x i16> %x) {
;
; AVX1-LABEL: test23:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpmaxuw %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpcmpeqw %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
@@ -842,7 +842,7 @@ define <8 x i16> @test23(<8 x i16> %x) {
;
; AVX2-LABEL: test23:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpmaxuw %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpcmpeqw %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
@@ -852,7 +852,7 @@ define <8 x i16> @test23(<8 x i16> %x) {
;
; AVX512-LABEL: test23:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512-NEXT: vpcmpltuw %xmm0, %xmm1, %k1
; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovdqu16 %xmm0, %xmm1 {%k1}
@@ -867,12 +867,12 @@ define <8 x i16> @test23(<8 x i16> %x) {
define <8 x i16> @test24(<8 x i16> %x) {
; SSE-LABEL: test24:
; SSE: # %bb.0:
-; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test24:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = add <8 x i16> %x, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
%2 = icmp ugt <8 x i16> %x, <i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3>
@@ -948,12 +948,12 @@ define <16 x i16> @test26(<16 x i16> %x) {
;
; AVX2-LABEL: test26:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test26:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <16 x i16> %x, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>
%2 = icmp ugt <16 x i16> %x, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
@@ -980,12 +980,12 @@ define <16 x i16> @test27(<16 x i16> %x) {
;
; AVX2-LABEL: test27:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test27:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <16 x i16> %x, <i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767>
%2 = icmp ugt <16 x i16> %x, <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>
@@ -1012,12 +1012,12 @@ define <16 x i16> @test28(<16 x i16> %x) {
;
; AVX2-LABEL: test28:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test28:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <16 x i16> %x, <i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2>
%2 = icmp ugt <16 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1077,7 +1077,7 @@ define <16 x i16> @test29(<16 x i16> %x) {
;
; AVX1-LABEL: test29:
; AVX1: # %bb.0:
-; AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm1
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpmaxuw %xmm2, %xmm3, %xmm2
@@ -1093,7 +1093,7 @@ define <16 x i16> @test29(<16 x i16> %x) {
;
; AVX2-LABEL: test29:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpmaxuw %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpcmpeqw %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
@@ -1103,7 +1103,7 @@ define <16 x i16> @test29(<16 x i16> %x) {
;
; AVX512-LABEL: test29:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm1
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512-NEXT: vpcmpltuw %ymm0, %ymm1, %k1
; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512-NEXT: vmovdqu16 %ymm0, %ymm1 {%k1}
@@ -1134,12 +1134,12 @@ define <16 x i16> @test30(<16 x i16> %x) {
;
; AVX2-LABEL: test30:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: test30:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = add <16 x i16> %x, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
%2 = icmp ugt <16 x i16> %x, <i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3>
@@ -1247,7 +1247,7 @@ define <32 x i16> @test32(<32 x i16> %x) {
;
; AVX512-LABEL: test32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <32 x i16> %x, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>
%2 = icmp ugt <32 x i16> %x, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
@@ -1287,7 +1287,7 @@ define <32 x i16> @test33(<32 x i16> %x) {
;
; AVX512-LABEL: test33:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <32 x i16> %x, <i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767>
%2 = icmp ugt <32 x i16> %x, <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>
@@ -1327,7 +1327,7 @@ define <32 x i16> @test34(<32 x i16> %x) {
;
; AVX512-LABEL: test34:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <32 x i16> %x, <i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2, i16 -2>
%2 = icmp ugt <32 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1467,7 +1467,7 @@ define <32 x i16> @test35(<32 x i16> %x) {
;
; AVX512-LABEL: test35:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxorq {{.*}}(%rip), %zmm0, %zmm1
+; AVX512-NEXT: vpxorq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
; AVX512-NEXT: vpcmpltuw %zmm0, %zmm1, %k1
; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; AVX512-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1}
@@ -1511,7 +1511,7 @@ define <32 x i16> @test36(<32 x i16> %x) {
;
; AVX512-LABEL: test36:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpaddusw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = add <32 x i16> %x, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
%2 = icmp ugt <32 x i16> %x, <i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3>
diff --git a/llvm/test/CodeGen/X86/peep-test-1.ll b/llvm/test/CodeGen/X86/peep-test-1.ll
index 7a356c1b361f1..2d72c54731683 100644
--- a/llvm/test/CodeGen/X86/peep-test-1.ll
+++ b/llvm/test/CodeGen/X86/peep-test-1.ll
@@ -10,7 +10,7 @@ define void @foo(i32 %n, double* nocapture %p) nounwind {
; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: fldl (%eax,%ecx,8)
-; CHECK-NEXT: fmull {{\.LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: fmull {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fstpl (%eax,%ecx,8)
; CHECK-NEXT: decl %ecx
; CHECK-NEXT: js .LBB0_1
diff --git a/llvm/test/CodeGen/X86/peephole-fold-movsd.ll b/llvm/test/CodeGen/X86/peephole-fold-movsd.ll
index bdff8541a50e5..ff99fd2d0caa7 100644
--- a/llvm/test/CodeGen/X86/peephole-fold-movsd.ll
+++ b/llvm/test/CodeGen/X86/peephole-fold-movsd.ll
@@ -16,12 +16,12 @@ define dso_local void @foo1(double %a.coerce0, double %a.coerce1, double %b.coer
; CHECK: # %bb.0:
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: movq %rsp, %rdi
-; CHECK-NEXT: callq foo3
+; CHECK-NEXT: callq foo3 at PLT
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movapd {{.*#+}} xmm1 = <1.0E+0,u>
; CHECK-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: addpd %xmm0, %xmm1
-; CHECK-NEXT: movapd %xmm1, {{.*}}(%rip)
+; CHECK-NEXT: movapd %xmm1, g(%rip)
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: retq
%1 = alloca <2 x double>, align 16
diff --git a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
index d12043f2c2f7e..6333c418aea5d 100644
--- a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
+++ b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
@@ -29,8 +29,8 @@ define i1 @plus_one() nounwind {
;
; CHECK64-LABEL: plus_one:
; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: movb {{.*}}(%rip), %al
-; CHECK64-NEXT: incl {{.*}}(%rip)
+; CHECK64-NEXT: movb M(%rip), %al
+; CHECK64-NEXT: incl L(%rip)
; CHECK64-NEXT: jne .LBB0_2
; CHECK64-NEXT: # %bb.1: # %entry
; CHECK64-NEXT: andb $8, %al
@@ -77,8 +77,8 @@ define i1 @plus_forty_two() nounwind {
;
; CHECK64-LABEL: plus_forty_two:
; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: movb {{.*}}(%rip), %al
-; CHECK64-NEXT: addl $42, {{.*}}(%rip)
+; CHECK64-NEXT: movb M(%rip), %al
+; CHECK64-NEXT: addl $42, L(%rip)
; CHECK64-NEXT: jne .LBB1_2
; CHECK64-NEXT: # %bb.1: # %entry
; CHECK64-NEXT: andb $8, %al
@@ -125,8 +125,8 @@ define i1 @minus_one() nounwind {
;
; CHECK64-LABEL: minus_one:
; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: movb {{.*}}(%rip), %al
-; CHECK64-NEXT: decl {{.*}}(%rip)
+; CHECK64-NEXT: movb M(%rip), %al
+; CHECK64-NEXT: decl L(%rip)
; CHECK64-NEXT: jne .LBB2_2
; CHECK64-NEXT: # %bb.1: # %entry
; CHECK64-NEXT: andb $8, %al
@@ -173,8 +173,8 @@ define i1 @minus_forty_two() nounwind {
;
; CHECK64-LABEL: minus_forty_two:
; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: movb {{.*}}(%rip), %al
-; CHECK64-NEXT: addl $-42, {{.*}}(%rip)
+; CHECK64-NEXT: movb M(%rip), %al
+; CHECK64-NEXT: addl $-42, L(%rip)
; CHECK64-NEXT: jne .LBB3_2
; CHECK64-NEXT: # %bb.1: # %entry
; CHECK64-NEXT: andb $8, %al
@@ -219,7 +219,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind {
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: pushl %edx
; CHECK32-NEXT: pushl %eax
-; CHECK32-NEXT: calll bar
+; CHECK32-NEXT: calll bar at PLT
; CHECK32-NEXT: addl $16, %esp
; CHECK32-NEXT: testb %bl, %bl
; CHECK32-NEXT: jne .LBB4_3
@@ -242,7 +242,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind {
; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi)
; CHECK64-NEXT: setne %bl
; CHECK64-NEXT: movq %rax, %rdi
-; CHECK64-NEXT: callq bar
+; CHECK64-NEXT: callq bar at PLT
; CHECK64-NEXT: testb %bl, %bl
; CHECK64-NEXT: jne .LBB4_2
; CHECK64-NEXT: # %bb.1: # %t
diff --git a/llvm/test/CodeGen/X86/pic-load-remat.ll b/llvm/test/CodeGen/X86/pic-load-remat.ll
index 81db544513f6e..8596e5699b280 100644
--- a/llvm/test/CodeGen/X86/pic-load-remat.ll
+++ b/llvm/test/CodeGen/X86/pic-load-remat.ll
@@ -9,8 +9,8 @@ define void @f() nounwind {
; CHECK-NEXT: popl %eax
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1]
-; CHECK-NEXT: psllw LCPI0_1-L0$pb(%eax), %xmm1
-; CHECK-NEXT: pavgw LCPI0_2-L0$pb(%eax), %xmm0
+; CHECK-NEXT: psllw {{\.?LCPI[0-9]+_[0-9]+}}-L0$pb(%eax), %xmm1
+; CHECK-NEXT: pavgw {{\.?LCPI[0-9]+_[0-9]+}}-L0$pb(%eax), %xmm0
; CHECK-NEXT: paddsw %xmm0, %xmm0
; CHECK-NEXT: paddw %xmm1, %xmm0
; CHECK-NEXT: .p2align 4, 0x90
diff --git a/llvm/test/CodeGen/X86/pmul.ll b/llvm/test/CodeGen/X86/pmul.ll
index 56476eea323ed..98a756afec88c 100644
--- a/llvm/test/CodeGen/X86/pmul.ll
+++ b/llvm/test/CodeGen/X86/pmul.ll
@@ -37,8 +37,8 @@ define <16 x i8> @mul_v16i8c(<16 x i8> %i) nounwind {
; AVX2-LABEL: mul_v16i8c:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper
@@ -47,7 +47,7 @@ define <16 x i8> @mul_v16i8c(<16 x i8> %i) nounwind {
; AVX512F-LABEL: mul_v16i8c:
; AVX512F: # %bb.0: # %entry
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: vzeroupper
@@ -56,7 +56,7 @@ define <16 x i8> @mul_v16i8c(<16 x i8> %i) nounwind {
; AVX512BW-LABEL: mul_v16i8c:
; AVX512BW: # %bb.0: # %entry
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512BW-NEXT: vzeroupper
@@ -69,12 +69,12 @@ entry:
define <8 x i16> @mul_v8i16c(<8 x i16> %i) nounwind {
; SSE-LABEL: mul_v8i16c:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: mul_v8i16c:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
entry:
%A = mul <8 x i16> %i, < i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117 >
@@ -95,7 +95,7 @@ define <4 x i32> @mul_v4i32c(<4 x i32> %i) nounwind {
;
; SSE41-LABEL: mul_v4i32c:
; SSE41: # %bb.0: # %entry
-; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX-LABEL: mul_v4i32c:
@@ -171,7 +171,7 @@ define <16 x i8> @mul_v16i8(<16 x i8> %i, <16 x i8> %j) nounwind {
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX2-NEXT: vpmullw %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper
@@ -281,7 +281,7 @@ define <4 x i32> @mul_v4i32spill(<4 x i32> %i, <4 x i32> %j) nounwind {
; SSE2-NEXT: subq $40, %rsp
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE2-NEXT: callq foo
+; SSE2-NEXT: callq foo at PLT
; SSE2-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
@@ -299,7 +299,7 @@ define <4 x i32> @mul_v4i32spill(<4 x i32> %i, <4 x i32> %j) nounwind {
; SSE41-NEXT: subq $40, %rsp
; SSE41-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE41-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE41-NEXT: callq foo
+; SSE41-NEXT: callq foo at PLT
; SSE41-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
; SSE41-NEXT: pmulld {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE41-NEXT: addq $40, %rsp
@@ -310,7 +310,7 @@ define <4 x i32> @mul_v4i32spill(<4 x i32> %i, <4 x i32> %j) nounwind {
; AVX-NEXT: subq $40, %rsp
; AVX-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: callq foo
+; AVX-NEXT: callq foo at PLT
; AVX-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
; AVX-NEXT: vpmulld {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; AVX-NEXT: addq $40, %rsp
@@ -328,7 +328,7 @@ define <2 x i64> @mul_v2i64spill(<2 x i64> %i, <2 x i64> %j) nounwind {
; SSE-NEXT: subq $40, %rsp
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: callq foo
+; SSE-NEXT: callq foo at PLT
; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: psrlq $32, %xmm2
@@ -349,7 +349,7 @@ define <2 x i64> @mul_v2i64spill(<2 x i64> %i, <2 x i64> %j) nounwind {
; AVX-NEXT: subq $40, %rsp
; AVX-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: callq foo
+; AVX-NEXT: callq foo at PLT
; AVX-NEXT: vmovdqa (%rsp), %xmm3 # 16-byte Reload
; AVX-NEXT: vpsrlq $32, %xmm3, %xmm0
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
@@ -443,7 +443,7 @@ define <32 x i8> @mul_v32i8c(<32 x i8> %i) nounwind {
; AVX512BW-LABEL: mul_v32i8c:
; AVX512BW: # %bb.0: # %entry
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: retq
entry:
@@ -461,7 +461,7 @@ define <16 x i16> @mul_v16i16c(<16 x i16> %i) nounwind {
;
; AVX-LABEL: mul_v16i16c:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
entry:
%A = mul <16 x i16> %i, < i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117 >
diff --git a/llvm/test/CodeGen/X86/pointer-vector.ll b/llvm/test/CodeGen/X86/pointer-vector.ll
index 04e2a2a350c45..86afcdf230bcc 100644
--- a/llvm/test/CodeGen/X86/pointer-vector.ll
+++ b/llvm/test/CodeGen/X86/pointer-vector.ll
@@ -133,7 +133,7 @@ define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
; CHECK-NEXT: movdqa (%ecx), %xmm0
; CHECK-NEXT: pcmpgtd (%eax), %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
-; CHECK-NEXT: blendvps %xmm0, {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; CHECK-NEXT: blendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
@@ -152,7 +152,7 @@ define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
; CHECK-NEXT: movdqa (%ecx), %xmm0
; CHECK-NEXT: pcmpeqd (%eax), %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
-; CHECK-NEXT: blendvps %xmm0, {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; CHECK-NEXT: blendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/popcnt.ll b/llvm/test/CodeGen/X86/popcnt.ll
index fc35ac4780714..09bab90813306 100644
--- a/llvm/test/CodeGen/X86/popcnt.ll
+++ b/llvm/test/CodeGen/X86/popcnt.ll
@@ -253,7 +253,7 @@ define i64 @cnt64(i64 %x) nounwind readnone {
; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $1, %xmm1
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -264,7 +264,7 @@ define i64 @cnt64(i64 %x) nounwind readnone {
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm1
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: psadbw %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
@@ -749,7 +749,7 @@ define i64 @cnt64_optsize(i64 %x) nounwind readnone optsize {
; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $1, %xmm1
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -760,7 +760,7 @@ define i64 @cnt64_optsize(i64 %x) nounwind readnone optsize {
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm1
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: psadbw %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
@@ -1178,7 +1178,7 @@ define i64 @cnt64_pgso(i64 %x) nounwind readnone !prof !14 {
; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $1, %xmm1
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1189,7 +1189,7 @@ define i64 @cnt64_pgso(i64 %x) nounwind readnone !prof !14 {
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm1
-; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: psadbw %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
diff --git a/llvm/test/CodeGen/X86/pow.75.ll b/llvm/test/CodeGen/X86/pow.75.ll
index 5f4e228945e22..9f5adb945ae62 100644
--- a/llvm/test/CodeGen/X86/pow.75.ll
+++ b/llvm/test/CodeGen/X86/pow.75.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -debug 2>&1 | FileCheck %s
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/X86/pow.ll b/llvm/test/CodeGen/X86/pow.ll
index a0b85cc811cbb..91c04be18c2b2 100644
--- a/llvm/test/CodeGen/X86/pow.ll
+++ b/llvm/test/CodeGen/X86/pow.ll
@@ -154,23 +154,23 @@ define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: callq powf
+; CHECK-NEXT: callq powf at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: callq powf
+; CHECK-NEXT: callq powf at PLT
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: callq powf
+; CHECK-NEXT: callq powf at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: callq powf
+; CHECK-NEXT: callq powf at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
@@ -188,12 +188,12 @@ define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwi
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, %xmm0
@@ -232,10 +232,10 @@ define x86_fp80 @pow_f80_one_third_fmf(x86_fp80 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fldt {{.*}}(%rip)
+; CHECK-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq powl
+; CHECK-NEXT: callq powl at PLT
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: retq
%one = uitofp i32 1 to x86_fp80
diff --git a/llvm/test/CodeGen/X86/pr13577.ll b/llvm/test/CodeGen/X86/pr13577.ll
index f70f6f7739d42..7511560d85f51 100644
--- a/llvm/test/CodeGen/X86/pr13577.ll
+++ b/llvm/test/CodeGen/X86/pr13577.ll
@@ -12,8 +12,8 @@ define x86_fp80 @foo(x86_fp80 %a) {
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt -{{[0-9]+}}(%rsp)
; CHECK-NEXT: testb $-128, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: flds {{.*}}(%rip)
-; CHECK-NEXT: flds {{.*}}(%rip)
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; CHECK-NEXT: fcmovne %st(1), %st
; CHECK-NEXT: fstp %st(1)
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr14161.ll b/llvm/test/CodeGen/X86/pr14161.ll
index d0ddcd64c216f..cbd24c702f033 100644
--- a/llvm/test/CodeGen/X86/pr14161.ll
+++ b/llvm/test/CodeGen/X86/pr14161.ll
@@ -7,7 +7,7 @@ define <2 x i16> @good(<4 x i32>*, <4 x i8>*) {
; CHECK-LABEL: good:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movdqa (%rdi), %xmm0
-; CHECK-NEXT: pminud {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
entry:
%2 = load <4 x i32>, <4 x i32>* %0, align 16
@@ -25,7 +25,7 @@ define <2 x i16> @bad(<4 x i32>*, <4 x i8>*) {
; CHECK-LABEL: bad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movdqa (%rdi), %xmm0
-; CHECK-NEXT: pminud {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr15309.ll b/llvm/test/CodeGen/X86/pr15309.ll
index 91dfdf5bdf0ba..7a47384830e42 100644
--- a/llvm/test/CodeGen/X86/pr15309.ll
+++ b/llvm/test/CodeGen/X86/pr15309.ll
@@ -19,10 +19,10 @@ define void @test_convert_float2_ulong2(<2 x i64>* nocapture %src, <2 x float>*
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: shrl $31, %ecx
; CHECK-NEXT: fildll (%esp)
-; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; CHECK-NEXT: shrl $31, %esi
; CHECK-NEXT: fildll {{[0-9]+}}(%esp)
-; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%esi,4)
+; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%esi,4)
; CHECK-NEXT: fstps 84(%eax)
; CHECK-NEXT: fstps 80(%eax)
; CHECK-NEXT: addl $20, %esp
diff --git a/llvm/test/CodeGen/X86/pr15981.ll b/llvm/test/CodeGen/X86/pr15981.ll
index 58007de36bfd7..f486d31edf969 100644
--- a/llvm/test/CodeGen/X86/pr15981.ll
+++ b/llvm/test/CodeGen/X86/pr15981.ll
@@ -43,12 +43,12 @@ define void @fn2() {
; X64-LABEL: fn2:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: decl {{.*}}(%rip)
+; X64-NEXT: decl a(%rip)
; X64-NEXT: je .LBB1_2
; X64-NEXT: # %bb.1:
-; X64-NEXT: movl {{.*}}(%rip), %eax
+; X64-NEXT: movl b(%rip), %eax
; X64-NEXT: .LBB1_2:
-; X64-NEXT: movl %eax, {{.*}}(%rip)
+; X64-NEXT: movl %eax, c(%rip)
; X64-NEXT: retq
%1 = load volatile i32, i32* @b, align 4
%2 = load i32, i32* @a, align 4
diff --git a/llvm/test/CodeGen/X86/pr21792.ll b/llvm/test/CodeGen/X86/pr21792.ll
index 67d64c09566b0..f7318615e6715 100644
--- a/llvm/test/CodeGen/X86/pr21792.ll
+++ b/llvm/test/CodeGen/X86/pr21792.ll
@@ -11,7 +11,7 @@ define void @func(<4 x float> %vx) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movd %xmm0, %r8d
; CHECK-NEXT: leaq stuff(%r8), %rdi
; CHECK-NEXT: pextrd $1, %xmm0, %eax
@@ -22,7 +22,7 @@ define void @func(<4 x float> %vx) {
; CHECK-NEXT: leaq stuff(%rcx), %rcx
; CHECK-NEXT: leaq stuff+8(%r8), %r8
; CHECK-NEXT: leaq stuff+8(%rax), %r9
-; CHECK-NEXT: callq toto
+; CHECK-NEXT: callq toto at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr22774.ll b/llvm/test/CodeGen/X86/pr22774.ll
index 8e60f984aa9f0..c994b7290fc6f 100644
--- a/llvm/test/CodeGen/X86/pr22774.ll
+++ b/llvm/test/CodeGen/X86/pr22774.ll
@@ -8,7 +8,7 @@ define dso_local i32 @_Z3foov() {
; CHECK-LABEL: _Z3foov:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: vmovaps %xmm0, {{.*}}(%rip)
+; CHECK-NEXT: vmovaps %xmm0, out(%rip)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr23103.ll b/llvm/test/CodeGen/X86/pr23103.ll
index 6b1788c345618..92be38a7a1a24 100644
--- a/llvm/test/CodeGen/X86/pr23103.ll
+++ b/llvm/test/CodeGen/X86/pr23103.ll
@@ -13,7 +13,7 @@ define <1 x double> @pr23103(<1 x double>* align 8 %Vp) {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/pr2326.ll b/llvm/test/CodeGen/X86/pr2326.ll
index 4b9cb35c00129..47767f362aa2d 100644
--- a/llvm/test/CodeGen/X86/pr2326.ll
+++ b/llvm/test/CodeGen/X86/pr2326.ll
@@ -12,7 +12,7 @@ define i32 @func_59(i32 %p_60) nounwind {
; CHECK-NEXT: sete %cl
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl %ecx
-; CHECK-NEXT: calll func_15
+; CHECK-NEXT: calll func_15 at PLT
entry:
%l_108 = alloca i32 ; <i32*> [#uses=2]
%tmp15 = load i32, i32* null, align 4 ; <i32> [#uses=1]
diff --git a/llvm/test/CodeGen/X86/pr23603.ll b/llvm/test/CodeGen/X86/pr23603.ll
index f92d368782194..9b82d50167ff3 100644
--- a/llvm/test/CodeGen/X86/pr23603.ll
+++ b/llvm/test/CodeGen/X86/pr23603.ll
@@ -12,7 +12,7 @@ define void @f(i32* %x, i32 %c32, i32* %y) nounwind {
; CHECK-NEXT: movq %rdx, %r14
; CHECK-NEXT: movl %esi, %ebp
; CHECK-NEXT: movl (%rdi), %ebx
-; CHECK-NEXT: callq free_v
+; CHECK-NEXT: callq free_v at PLT
; CHECK-NEXT: testl %ebp, %ebp
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %left
diff --git a/llvm/test/CodeGen/X86/pr2585.ll b/llvm/test/CodeGen/X86/pr2585.ll
index e8469255f23bd..a013fe86b63b0 100644
--- a/llvm/test/CodeGen/X86/pr2585.ll
+++ b/llvm/test/CodeGen/X86/pr2585.ll
@@ -19,7 +19,7 @@ define internal void @PR2585() {
; X64-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X64-NEXT: movq %xmm0, {{.*}}(%rip)
+; X64-NEXT: movq %xmm0, __unnamed_2(%rip)
; X64-NEXT: retq
load <4 x i32>, <4 x i32>* @0, align 16 ; <<4 x i32>>:1 [#uses=1]
bitcast <4 x i32> %1 to <8 x i16> ; <<8 x i16>>:2 [#uses=1]
diff --git a/llvm/test/CodeGen/X86/pr2656.ll b/llvm/test/CodeGen/X86/pr2656.ll
index d4ab0b4d074bb..8e3fdad86b392 100644
--- a/llvm/test/CodeGen/X86/pr2656.ll
+++ b/llvm/test/CodeGen/X86/pr2656.ll
@@ -56,7 +56,7 @@ define double @PR22371(double %x) {
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: andps LCPI1_0, %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movlps %xmm0, (%esp)
; CHECK-NEXT: fldl (%esp)
; CHECK-NEXT: addl $12, %esp
diff --git a/llvm/test/CodeGen/X86/pr27591.ll b/llvm/test/CodeGen/X86/pr27591.ll
index a925bb8dfd6a2..c3c15e7bac959 100644
--- a/llvm/test/CodeGen/X86/pr27591.ll
+++ b/llvm/test/CodeGen/X86/pr27591.ll
@@ -11,7 +11,7 @@ define void @test1(i32 %x) #0 {
; CHECK-NEXT: setne %al
; CHECK-NEXT: movzbl %al, %edi
; CHECK-NEXT: andl $1, %edi
-; CHECK-NEXT: callq callee1
+; CHECK-NEXT: callq callee1 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
entry:
@@ -29,7 +29,7 @@ define void @test2(i32 %x) #0 {
; CHECK-NEXT: movzbl %al, %edi
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: negl %edi
-; CHECK-NEXT: callq callee2
+; CHECK-NEXT: callq callee2 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr29112.ll b/llvm/test/CodeGen/X86/pr29112.ll
index 1cfa810f17325..135d763743f73 100644
--- a/llvm/test/CodeGen/X86/pr29112.ll
+++ b/llvm/test/CodeGen/X86/pr29112.ll
@@ -54,7 +54,7 @@ define <4 x float> @bar(<4 x float>* %a1p, <4 x float>* %a2p, <4 x float> %a3, <
; CHECK-NEXT: vmovaps %xmm10, (%rsp)
; CHECK-NEXT: vmovaps %xmm9, %xmm3
; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: vaddps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/pr30290.ll b/llvm/test/CodeGen/X86/pr30290.ll
index 5c0118a070186..34c9b5460e023 100644
--- a/llvm/test/CodeGen/X86/pr30290.ll
+++ b/llvm/test/CodeGen/X86/pr30290.ll
@@ -27,7 +27,7 @@ define void @foo(%struct.face* byval(%struct.face) nocapture align 8) local_unna
; CHECK-NEXT: vmovups %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: vmovups %xmm0, (%rsp)
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr30511.ll b/llvm/test/CodeGen/X86/pr30511.ll
index 6764656e3337c..088f3bfef8542 100644
--- a/llvm/test/CodeGen/X86/pr30511.ll
+++ b/llvm/test/CodeGen/X86/pr30511.ll
@@ -7,9 +7,9 @@ target triple = "x86_64-pc-linux-gnu"
define i64 @PR30511(<2 x double> %a) {
; CHECK-LABEL: PR30511:
; CHECK: # %bb.0:
-; CHECK-NEXT: addpd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: cvtdq2pd %xmm0, %xmm0
-; CHECK-NEXT: mulsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movq %xmm0, %rax
; CHECK-NEXT: retq
%1 = fadd <2 x double> %a, <double 0x4338000000000000, double 0x4338000000000000>
diff --git a/llvm/test/CodeGen/X86/pr31045.ll b/llvm/test/CodeGen/X86/pr31045.ll
index eaddcb792da1e..87204950258bd 100644
--- a/llvm/test/CodeGen/X86/pr31045.ll
+++ b/llvm/test/CodeGen/X86/pr31045.ll
@@ -18,17 +18,17 @@
define void @_Z1av() local_unnamed_addr #0 {
; CHECK-LABEL: _Z1av:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl struct_obj_3+{{.*}}(%rip), %eax
-; CHECK-NEXT: movzbl {{.*}}(%rip), %ecx
-; CHECK-NEXT: movzbl {{.*}}(%rip), %edx
+; CHECK-NEXT: movl struct_obj_3+8(%rip), %eax
+; CHECK-NEXT: movzbl var_46(%rip), %ecx
+; CHECK-NEXT: movzbl var_49(%rip), %edx
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: addl %eax, %eax
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: subl %edx, %eax
; CHECK-NEXT: notl %eax
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: movw %ax, struct_obj_12+{{.*}}(%rip)
-; CHECK-NEXT: movb $0, {{.*}}(%rip)
+; CHECK-NEXT: movw %ax, struct_obj_12+5(%rip)
+; CHECK-NEXT: movb $0, var_163(%rip)
; CHECK-NEXT: retq
entry:
%bf.load = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363, %struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363* @struct_obj_3, i64 0, i32 0, i32 2) to i32*), align 2
diff --git a/llvm/test/CodeGen/X86/pr31956.ll b/llvm/test/CodeGen/X86/pr31956.ll
index 50e98f689b2d5..3dc8a57b4753f 100644
--- a/llvm/test/CodeGen/X86/pr31956.ll
+++ b/llvm/test/CodeGen/X86/pr31956.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-scei-ps4"
define <4 x float> @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmovaps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: vmovaps G2(%rip), %xmm0
; CHECK-NEXT: vmovlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],mem[0,2]
; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
diff --git a/llvm/test/CodeGen/X86/pr32282.ll b/llvm/test/CodeGen/X86/pr32282.ll
index f8ef8fcaf8a85..562b322d3b119 100644
--- a/llvm/test/CodeGen/X86/pr32282.ll
+++ b/llvm/test/CodeGen/X86/pr32282.ll
@@ -36,7 +36,7 @@ define dso_local void @foo(i64 %x) nounwind {
; X64-LABEL: foo:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
-; X64-NEXT: movq {{.*}}(%rip), %rcx
+; X64-NEXT: movq d(%rip), %rcx
; X64-NEXT: movabsq $3013716102212485120, %rdx # imm = 0x29D2DED3DE400000
; X64-NEXT: andnq %rdx, %rcx, %rcx
; X64-NEXT: shrq $21, %rcx
diff --git a/llvm/test/CodeGen/X86/pr32284.ll b/llvm/test/CodeGen/X86/pr32284.ll
index 5e79ebf5d1a0e..867711810914b 100644
--- a/llvm/test/CodeGen/X86/pr32284.ll
+++ b/llvm/test/CodeGen/X86/pr32284.ll
@@ -37,7 +37,7 @@ define void @foo() {
;
; X64-LABEL: foo:
; X64: # %bb.0: # %entry
-; X64-NEXT: movzbl {{.*}}(%rip), %eax
+; X64-NEXT: movzbl c(%rip), %eax
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: testl %eax, %eax
; X64-NEXT: setne -{{[0-9]+}}(%rsp)
@@ -157,7 +157,7 @@ define void @f1() {
;
; X64-LABEL: f1:
; X64: # %bb.0: # %entry
-; X64-NEXT: movslq {{.*}}(%rip), %rax
+; X64-NEXT: movslq var_5(%rip), %rax
; X64-NEXT: movabsq $-8381627093, %rcx # imm = 0xFFFFFFFE0C6A852B
; X64-NEXT: cmpq %rcx, %rax
; X64-NEXT: setne -{{[0-9]+}}(%rsp)
@@ -171,8 +171,8 @@ define void @f1() {
; X64-NEXT: xorl %esi, %esi
; X64-NEXT: cmpq %rax, %rdx
; X64-NEXT: setg %sil
-; X64-NEXT: movq %rsi, {{.*}}(%rip)
-; X64-NEXT: movq %rcx, {{.*}}(%rip)
+; X64-NEXT: movq %rsi, var_57(%rip)
+; X64-NEXT: movq %rcx, _ZN8struct_210member_2_0E(%rip)
; X64-NEXT: retq
;
; X86-O0-LABEL: f1:
@@ -312,7 +312,7 @@ define void @f2() {
;
; X64-LABEL: f2:
; X64: # %bb.0: # %entry
-; X64-NEXT: movzbl {{.*}}(%rip), %eax
+; X64-NEXT: movzbl var_7(%rip), %eax
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: testl %eax, %eax
; X64-NEXT: sete %cl
@@ -444,17 +444,17 @@ define void @f3() #0 {
;
; X64-LABEL: f3:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl {{.*}}(%rip), %eax
+; X64-NEXT: movl var_13(%rip), %eax
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: testl %eax, %eax
; X64-NEXT: notl %eax
; X64-NEXT: sete %cl
-; X64-NEXT: movl {{.*}}(%rip), %edx
+; X64-NEXT: movl var_16(%rip), %edx
; X64-NEXT: xorl %eax, %edx
; X64-NEXT: andl %edx, %ecx
; X64-NEXT: orl %eax, %ecx
; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movl %eax, {{.*}}(%rip)
+; X64-NEXT: movl %eax, var_46(%rip)
; X64-NEXT: retq
;
; X86-O0-LABEL: f3:
diff --git a/llvm/test/CodeGen/X86/pr32329.ll b/llvm/test/CodeGen/X86/pr32329.ll
index 33e2ec16a18e9..ac5859fb2c7b1 100644
--- a/llvm/test/CodeGen/X86/pr32329.ll
+++ b/llvm/test/CodeGen/X86/pr32329.ll
@@ -68,13 +68,13 @@ define void @foo() local_unnamed_addr {
;
; X64-LABEL: foo:
; X64: # %bb.0: # %entry
-; X64-NEXT: movsbl {{.*}}(%rip), %r9d
-; X64-NEXT: movzwl {{.*}}(%rip), %r8d
-; X64-NEXT: movl {{.*}}(%rip), %ecx
+; X64-NEXT: movsbl var_27(%rip), %r9d
+; X64-NEXT: movzwl var_2(%rip), %r8d
+; X64-NEXT: movl var_310(%rip), %ecx
; X64-NEXT: imull %r9d, %ecx
-; X64-NEXT: addl {{.*}}(%rip), %ecx
+; X64-NEXT: addl var_24(%rip), %ecx
; X64-NEXT: movl $4194303, %esi # imm = 0x3FFFFF
-; X64-NEXT: andl {{.*}}(%rip), %esi
+; X64-NEXT: andl obj(%rip), %esi
; X64-NEXT: leal (%rsi,%rsi), %edi
; X64-NEXT: subl %r9d, %edi
; X64-NEXT: movl %edi, %edx
@@ -84,11 +84,11 @@ define void @foo() local_unnamed_addr {
; X64-NEXT: movl $9, %eax
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NEXT: shlq %cl, %rax
-; X64-NEXT: movq %rax, {{.*}}(%rip)
+; X64-NEXT: movq %rax, var_50(%rip)
; X64-NEXT: cmpl %esi, %edx
-; X64-NEXT: setge {{.*}}(%rip)
+; X64-NEXT: setge var_205(%rip)
; X64-NEXT: imull %r9d, %edi
-; X64-NEXT: movb %dil, {{.*}}(%rip)
+; X64-NEXT: movb %dil, var_218(%rip)
; X64-NEXT: retq
entry:
%bf.load = load i32, i32* bitcast (%struct.AA* @obj to i32*), align 8
diff --git a/llvm/test/CodeGen/X86/pr32345.ll b/llvm/test/CodeGen/X86/pr32345.ll
index fdfb427dcbe13..9b940d3275298 100644
--- a/llvm/test/CodeGen/X86/pr32345.ll
+++ b/llvm/test/CodeGen/X86/pr32345.ll
@@ -88,8 +88,8 @@ define void @foo() {
;
; X64-LABEL: foo:
; X64: # %bb.0: # %bb
-; X64-NEXT: movzwl {{.*}}(%rip), %ecx
-; X64-NEXT: movzwl {{.*}}(%rip), %eax
+; X64-NEXT: movzwl var_27(%rip), %ecx
+; X64-NEXT: movzwl var_22(%rip), %eax
; X64-NEXT: xorw %cx, %ax
; X64-NEXT: xorl %ecx, %eax
; X64-NEXT: movzwl %ax, %eax
diff --git a/llvm/test/CodeGen/X86/pr32368.ll b/llvm/test/CodeGen/X86/pr32368.ll
index 32dc482f1b9a1..c10bacea688aa 100644
--- a/llvm/test/CodeGen/X86/pr32368.ll
+++ b/llvm/test/CodeGen/X86/pr32368.ll
@@ -7,16 +7,16 @@
define <4 x float> @PR32368_128(<4 x float>) {
; SSE-LABEL: PR32368_128:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: addps %xmm0, %xmm0
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: PR32368_128:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: PR32368_128:
@@ -61,9 +61,9 @@ define <8 x float> @PR32368_256(<8 x float>) {
;
; AVX1-LABEL: PR32368_256:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: PR32368_256:
@@ -138,9 +138,9 @@ define <16 x float> @PR32368_512(<16 x float>) {
;
; AVX512-LABEL: PR32368_512:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-NEXT: vaddps %zmm0, %zmm0, %zmm0
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-NEXT: retq
%2 = bitcast <16 x float> %0 to <16 x i32>
%3 = and <16 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292>
diff --git a/llvm/test/CodeGen/X86/pr32420.ll b/llvm/test/CodeGen/X86/pr32420.ll
index 2775760e1b068..4f0ad9ab2332b 100644
--- a/llvm/test/CodeGen/X86/pr32420.ll
+++ b/llvm/test/CodeGen/X86/pr32420.ll
@@ -10,13 +10,13 @@ target triple = "x86_64-apple-macosx10.12.0"
define i32 @PR32420() {
; CHECK-LABEL: PR32420:
; CHECK: ## %bb.0:
-; CHECK-NEXT: movq _a@{{.*}}(%rip), %rcx
+; CHECK-NEXT: movq _a at GOTPCREL(%rip), %rcx
; CHECK-NEXT: movzwl (%rcx), %eax
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: shll $12, %edx
; CHECK-NEXT: movswl %dx, %edx
; CHECK-NEXT: shrl $12, %edx
-; CHECK-NEXT: movq _b@{{.*}}(%rip), %rsi
+; CHECK-NEXT: movq _b at GOTPCREL(%rip), %rsi
; CHECK-NEXT: orw (%rsi), %dx
; CHECK-NEXT: movl (%rcx), %ecx
; CHECK-NEXT: shll $12, %ecx
diff --git a/llvm/test/CodeGen/X86/pr32451.ll b/llvm/test/CodeGen/X86/pr32451.ll
index f12e85b9a177d..6b906a92ee0ec 100644
--- a/llvm/test/CodeGen/X86/pr32451.ll
+++ b/llvm/test/CodeGen/X86/pr32451.ll
@@ -13,9 +13,9 @@ define i8** @japi1_convert_690(i8**, i8***, i32) {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT: calll julia.gc_root_decl
+; CHECK-NEXT: calll julia.gc_root_decl at PLT
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT: calll jl_get_ptls_states
+; CHECK-NEXT: calll jl_get_ptls_states at PLT
; CHECK-NEXT: # kill: def $ecx killed $eax
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; CHECK-NEXT: movl 4(%eax), %eax
@@ -23,7 +23,7 @@ define i8** @japi1_convert_690(i8**, i8***, i32) {
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movl %eax, (%esp)
-; CHECK-NEXT: calll jl_box_int32
+; CHECK-NEXT: calll jl_box_int32 at PLT
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; CHECK-NEXT: movl %eax, (%ecx)
; CHECK-NEXT: addl $12, %esp
diff --git a/llvm/test/CodeGen/X86/pr32588.ll b/llvm/test/CodeGen/X86/pr32588.ll
index 223fd5dc3b887..9e6f0b2881d94 100644
--- a/llvm/test/CodeGen/X86/pr32588.ll
+++ b/llvm/test/CodeGen/X86/pr32588.ll
@@ -8,10 +8,10 @@
define void @fn1() {
; CHECK-LABEL: fn1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmpl $1, {{.*}}(%rip)
+; CHECK-NEXT: cmpl $1, c(%rip)
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, d(%rip)
; CHECK-NEXT: retq
%t0 = load i32, i32* @c, align 4
%tobool1 = icmp eq i32 %t0, 0
diff --git a/llvm/test/CodeGen/X86/pr32659.ll b/llvm/test/CodeGen/X86/pr32659.ll
index e60929b1afedd..009a58c665a26 100644
--- a/llvm/test/CodeGen/X86/pr32659.ll
+++ b/llvm/test/CodeGen/X86/pr32659.ll
@@ -27,7 +27,7 @@ define void @fn2() nounwind optsize {
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl $48, (%esp)
-; CHECK-NEXT: calll putchar
+; CHECK-NEXT: calll putchar at PLT
; CHECK-NEXT: movl h, %eax
; CHECK-NEXT: movl c, %ecx
; CHECK-NEXT: movl j, %edx
diff --git a/llvm/test/CodeGen/X86/pr33010.ll b/llvm/test/CodeGen/X86/pr33010.ll
index 0d8a4a494753c..4a837eea0637e 100644
--- a/llvm/test/CodeGen/X86/pr33010.ll
+++ b/llvm/test/CodeGen/X86/pr33010.ll
@@ -16,7 +16,7 @@ define i32 addrspace(1)* @test(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %w
; CHECK-NEXT: movl %edx, %ebx
; CHECK-NEXT: movq %rdi, (%rsp)
; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: callq f
+; CHECK-NEXT: callq f at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: je .LBB0_1
diff --git a/llvm/test/CodeGen/X86/pr33290.ll b/llvm/test/CodeGen/X86/pr33290.ll
index 457ba48b82c13..bd8e099006aed 100644
--- a/llvm/test/CodeGen/X86/pr33290.ll
+++ b/llvm/test/CodeGen/X86/pr33290.ll
@@ -21,16 +21,16 @@ define dso_local void @e() {
;
; X64-LABEL: e:
; X64: # %bb.0: # %entry
-; X64-NEXT: movq {{.*}}(%rip), %rax
+; X64-NEXT: movq b(%rip), %rax
; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_1: # %for.cond
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: movzbl {{.*}}(%rip), %ecx
+; X64-NEXT: movzbl c(%rip), %ecx
; X64-NEXT: addq $a, %rcx
; X64-NEXT: setb %dl
; X64-NEXT: addq $2, %rcx
; X64-NEXT: adcb $0, %dl
-; X64-NEXT: movb %dl, {{.*}}(%rip)
+; X64-NEXT: movb %dl, c(%rip)
; X64-NEXT: movl %ecx, (%rax)
; X64-NEXT: jmp .LBB0_1
entry:
diff --git a/llvm/test/CodeGen/X86/pr33828.ll b/llvm/test/CodeGen/X86/pr33828.ll
index 56737206246c3..9ae4243f59f51 100644
--- a/llvm/test/CodeGen/X86/pr33828.ll
+++ b/llvm/test/CodeGen/X86/pr33828.ll
@@ -16,7 +16,7 @@ define void @foo(i8 %a0) {
;
; X64-LABEL: foo:
; X64: # %bb.0: # %entry
-; X64-NEXT: movsbl {{.*}}(%rip), %eax
+; X64-NEXT: movsbl var_580(%rip), %eax
; X64-NEXT: testl $-536870913, %eax # imm = 0xDFFFFFFF
; X64-NEXT: jne .LBB0_1
; X64-NEXT: # %bb.2: # %if.end13
diff --git a/llvm/test/CodeGen/X86/pr33960.ll b/llvm/test/CodeGen/X86/pr33960.ll
index 582d2e9026981..dca01af427095 100644
--- a/llvm/test/CodeGen/X86/pr33960.ll
+++ b/llvm/test/CodeGen/X86/pr33960.ll
@@ -12,7 +12,7 @@ define void @PR33960() {
;
; X64-LABEL: PR33960:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl $-1, {{.*}}(%rip)
+; X64-NEXT: movl $-1, b(%rip)
; X64-NEXT: retq
entry:
%tmp = insertelement <4 x i32> <i32 undef, i32 -7, i32 -3, i32 undef>, i32 -2, i32 3
diff --git a/llvm/test/CodeGen/X86/pr34080-2.ll b/llvm/test/CodeGen/X86/pr34080-2.ll
index dee2885992473..ad7100284b044 100644
--- a/llvm/test/CodeGen/X86/pr34080-2.ll
+++ b/llvm/test/CodeGen/X86/pr34080-2.ll
@@ -48,8 +48,8 @@ define void @computeJD(%struct.DateTime*) nounwind {
; CHECK-NEXT: leal 257(%ecx,%edx), %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: fildl {{[0-9]+}}(%esp)
-; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
@@ -62,7 +62,7 @@ define void @computeJD(%struct.DateTime*) nounwind {
; CHECK-NEXT: imull $60000, 24(%ebx), %ecx # imm = 0xEA60
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: fldl 28(%ebx)
-; CHECK-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
diff --git a/llvm/test/CodeGen/X86/pr34080.ll b/llvm/test/CodeGen/X86/pr34080.ll
index 6c293cc8adaee..a8540aa0114e6 100644
--- a/llvm/test/CodeGen/X86/pr34080.ll
+++ b/llvm/test/CodeGen/X86/pr34080.ll
@@ -26,7 +26,7 @@ define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
; SSE2-NEXT: movsd %xmm0, -64(%rbp)
; SSE2-NEXT: movsd %xmm0, -32(%rbp)
; SSE2-NEXT: fsubl -32(%rbp)
-; SSE2-NEXT: flds {{.*}}(%rip)
+; SSE2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; SSE2-NEXT: fmul %st, %st(1)
; SSE2-NEXT: fnstcw -2(%rbp)
; SSE2-NEXT: movzwl -2(%rbp), %eax
@@ -65,7 +65,7 @@ define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
; SSE2-SCHEDULE-NEXT: movsd %xmm0, -64(%rbp)
; SSE2-SCHEDULE-NEXT: movsd %xmm0, -32(%rbp)
; SSE2-SCHEDULE-NEXT: fsubl -32(%rbp)
-; SSE2-SCHEDULE-NEXT: flds {{.*}}(%rip)
+; SSE2-SCHEDULE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; SSE2-SCHEDULE-NEXT: fmul %st, %st(1)
; SSE2-SCHEDULE-NEXT: fnstcw -2(%rbp)
; SSE2-SCHEDULE-NEXT: movzwl -2(%rbp), %eax
@@ -99,7 +99,7 @@ define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
; SSE3-NEXT: movsd %xmm0, -48(%rbp)
; SSE3-NEXT: movsd %xmm0, -24(%rbp)
; SSE3-NEXT: fsubl -24(%rbp)
-; SSE3-NEXT: flds {{.*}}(%rip)
+; SSE3-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; SSE3-NEXT: fmul %st, %st(1)
; SSE3-NEXT: fld %st(1)
; SSE3-NEXT: fisttpl -8(%rbp)
@@ -128,7 +128,7 @@ define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
; AVX-NEXT: vmovsd %xmm0, -48(%rbp)
; AVX-NEXT: vmovsd %xmm0, -24(%rbp)
; AVX-NEXT: fsubl -24(%rbp)
-; AVX-NEXT: flds {{.*}}(%rip)
+; AVX-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; AVX-NEXT: fmul %st, %st(1)
; AVX-NEXT: fld %st(1)
; AVX-NEXT: fisttpl -8(%rbp)
diff --git a/llvm/test/CodeGen/X86/pr34088.ll b/llvm/test/CodeGen/X86/pr34088.ll
index 6950e50dd7556..66a6b90782674 100644
--- a/llvm/test/CodeGen/X86/pr34088.ll
+++ b/llvm/test/CodeGen/X86/pr34088.ll
@@ -6,7 +6,7 @@
%struct.Buffer = type { i8*, i32 }
; This test checks that the load of store %2 is not dropped.
-;
+;
define i32 @pr34088() local_unnamed_addr {
; CHECK-LABEL: pr34088:
; CHECK: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/pr34137.ll b/llvm/test/CodeGen/X86/pr34137.ll
index f374515f1a439..650c9b8acb401 100644
--- a/llvm/test/CodeGen/X86/pr34137.ll
+++ b/llvm/test/CodeGen/X86/pr34137.ll
@@ -8,8 +8,8 @@
define void @pr34127() {
; CHECK-LABEL: pr34127:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
-; CHECK-NEXT: movzwl {{.*}}(%rip), %ecx
+; CHECK-NEXT: movzwl var_3(%rip), %eax
+; CHECK-NEXT: movzwl var_13(%rip), %ecx
; CHECK-NEXT: andl %eax, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: andl %eax, %ecx
@@ -17,7 +17,7 @@ define void @pr34127() {
; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: sete %dl
; CHECK-NEXT: andl %eax, %edx
-; CHECK-NEXT: movq %rdx, {{.*}}(%rip)
+; CHECK-NEXT: movq %rdx, var_212(%rip)
; CHECK-NEXT: movw $0, (%rax)
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr34177.ll b/llvm/test/CodeGen/X86/pr34177.ll
index 65e46f4a8b4c6..f74e07fedeef9 100644
--- a/llvm/test/CodeGen/X86/pr34177.ll
+++ b/llvm/test/CodeGen/X86/pr34177.ll
@@ -48,7 +48,7 @@ define void @test(<4 x i64> %a, <4 x x86_fp80> %b, <8 x x86_fp80>* %c) local_unn
;
; AVX512VL-LABEL: test:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpcmpeqq {{.*}}(%rip), %ymm0, %k0
+; AVX512VL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; AVX512VL-NEXT: kshiftrb $2, %k0, %k1
; AVX512VL-NEXT: kshiftrb $1, %k0, %k2
; AVX512VL-NEXT: kmovd %k0, %eax
diff --git a/llvm/test/CodeGen/X86/pr34271-1.ll b/llvm/test/CodeGen/X86/pr34271-1.ll
index d341ceb1c11e8..25ce12fa7cd58 100644
--- a/llvm/test/CodeGen/X86/pr34271-1.ll
+++ b/llvm/test/CodeGen/X86/pr34271-1.ll
@@ -4,7 +4,7 @@
define <16 x i16> @foo(<16 x i32> %i) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpminud {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; CHECK-NEXT: vpmovdw %zmm0, %ymm0
; CHECK-NEXT: retq
%x3 = icmp ult <16 x i32> %i, <i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009, i32 16843009>
diff --git a/llvm/test/CodeGen/X86/pr34271.ll b/llvm/test/CodeGen/X86/pr34271.ll
index d626f8f6bf9fd..49f6173197eff 100644
--- a/llvm/test/CodeGen/X86/pr34271.ll
+++ b/llvm/test/CodeGen/X86/pr34271.ll
@@ -7,7 +7,7 @@
define <4 x i32> @f(<4 x i32> %a) {
; CHECK-LABEL: f:
; CHECK: # %bb.0:
-; CHECK-NEXT: paddd .LCPI0_0(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%v = add nuw nsw <4 x i32> %a, <i32 16843009, i32 16843009, i32 16843009, i32 16843009>
ret <4 x i32> %v
diff --git a/llvm/test/CodeGen/X86/pr34292.ll b/llvm/test/CodeGen/X86/pr34292.ll
index 01f7d553b8640..604aa883aa51c 100644
--- a/llvm/test/CodeGen/X86/pr34292.ll
+++ b/llvm/test/CodeGen/X86/pr34292.ll
@@ -7,7 +7,7 @@
define void @sum_unroll(i64* nocapture readonly, i64* nocapture) {
; CHECK-LABEL: sum_unroll:
; CHECK: # %bb.0:
-; CHECK-NEXT: movb {{.*}}(%rip), %al
+; CHECK-NEXT: movb _ZL1c(%rip), %al
; CHECK-NEXT: movq (%rdi), %rcx
; CHECK-NEXT: addb $-1, %al
; CHECK-NEXT: adcq %rcx, (%rsi)
@@ -17,7 +17,7 @@ define void @sum_unroll(i64* nocapture readonly, i64* nocapture) {
; CHECK-NEXT: adcq %rax, 16(%rsi)
; CHECK-NEXT: movq 24(%rdi), %rax
; CHECK-NEXT: adcq %rax, 24(%rsi)
-; CHECK-NEXT: setb {{.*}}(%rip)
+; CHECK-NEXT: setb _ZL1c(%rip)
; CHECK-NEXT: retq
%3 = load i8, i8* @_ZL1c, align 1
%4 = load i64, i64* %0, align 8
diff --git a/llvm/test/CodeGen/X86/pr34381.ll b/llvm/test/CodeGen/X86/pr34381.ll
index fd91f75d6b31c..5edde575ed074 100644
--- a/llvm/test/CodeGen/X86/pr34381.ll
+++ b/llvm/test/CodeGen/X86/pr34381.ll
@@ -11,14 +11,14 @@
define void @_Z3foov() {
; CHECK-LABEL: _Z3foov:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movsbl {{.*}}(%rip), %eax
+; CHECK-NEXT: movsbl var_29(%rip), %eax
; CHECK-NEXT: negl %eax
; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: cmpl %eax, {{.*}}(%rip)
+; CHECK-NEXT: cmpl %eax, var_21(%rip)
; CHECK-NEXT: setb %cl
-; CHECK-NEXT: movl %ecx, {{.*}}(%rip)
-; CHECK-NEXT: movb {{.*}}(%rip), %al
-; CHECK-NEXT: movb %al, {{.*}}(%rip)
+; CHECK-NEXT: movl %ecx, var_390(%rip)
+; CHECK-NEXT: movb var_11(%rip), %al
+; CHECK-NEXT: movb %al, var_370(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i32, i32* @var_21, align 4
diff --git a/llvm/test/CodeGen/X86/pr34421.ll b/llvm/test/CodeGen/X86/pr34421.ll
index a21191246c231..81ac44b2bb7f3 100644
--- a/llvm/test/CodeGen/X86/pr34421.ll
+++ b/llvm/test/CodeGen/X86/pr34421.ll
@@ -15,7 +15,6 @@ define void @thread_selfcounts() noimplicitfloat noredzone nounwind {
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: ud2
-; X86-NEXT: ## -- End function
;
; X64-LABEL: thread_selfcounts:
; X64: ## %bb.0: ## %entry
@@ -25,7 +24,6 @@ define void @thread_selfcounts() noimplicitfloat noredzone nounwind {
; X64-NEXT: movq %rax, (%rsp)
; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; X64-NEXT: ud2
-; X64-NEXT: ## -- End function
entry:
%counts = alloca [2 x i64], align 16
%thread_counts = alloca [3 x i64], align 16
diff --git a/llvm/test/CodeGen/X86/pr34605.ll b/llvm/test/CodeGen/X86/pr34605.ll
index 2bd9c03be46c8..b4c10c4597e05 100644
--- a/llvm/test/CodeGen/X86/pr34605.ll
+++ b/llvm/test/CodeGen/X86/pr34605.ll
@@ -6,18 +6,18 @@ define void @pr34605(i8* nocapture %s, i32 %p) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: vpbroadcastd {{[0-9]+}}(%esp), %zmm0
-; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k0
-; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k1
+; CHECK-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %k0
+; CHECK-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %k1
; CHECK-NEXT: kunpckwd %k0, %k1, %k0
-; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k1
-; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k2
+; CHECK-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %k1
+; CHECK-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %k2
; CHECK-NEXT: kunpckwd %k1, %k2, %k1
; CHECK-NEXT: kunpckdq %k0, %k1, %k0
; CHECK-NEXT: movl $1, %ecx
; CHECK-NEXT: kmovd %ecx, %k1
; CHECK-NEXT: kmovd %k1, %k1
; CHECK-NEXT: kandq %k1, %k0, %k1
-; CHECK-NEXT: vmovdqu8 {{\.LCPI[0-9]+_[0-9]+}}, %zmm0 {%k1} {z}
+; CHECK-NEXT: vmovdqu8 {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0 {%k1} {z}
; CHECK-NEXT: vmovdqu64 %zmm0, (%eax)
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqu64 %zmm0, 64(%eax)
diff --git a/llvm/test/CodeGen/X86/pr34629.ll b/llvm/test/CodeGen/X86/pr34629.ll
index 16cf53a3e925b..bb647c19e97f1 100644
--- a/llvm/test/CodeGen/X86/pr34629.ll
+++ b/llvm/test/CodeGen/X86/pr34629.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-unknown-linux-gnu"
define dso_local void @c() local_unnamed_addr #0 {
; CHECK-LABEL: c:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq b(%rip), %rax
; CHECK-NEXT: leaq (%rax,%rax,4), %rcx
; CHECK-NEXT: negq %rcx
; CHECK-NEXT: leaq (%rax,%rax,8), %rax
@@ -19,7 +19,7 @@ define dso_local void @c() local_unnamed_addr #0 {
; CHECK-NEXT: testq %rax, %rcx
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: movb $0, {{.*}}(%rip)
+; CHECK-NEXT: movb $0, a(%rip)
; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr34634.ll b/llvm/test/CodeGen/X86/pr34634.ll
index 3825db7a303b3..5d8b60982bfb8 100644
--- a/llvm/test/CodeGen/X86/pr34634.ll
+++ b/llvm/test/CodeGen/X86/pr34634.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-unknown-linux-gnu"
define dso_local void @fn1() local_unnamed_addr #0 {
; CHECK-LABEL: fn1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movslq {{.*}}(%rip), %rax
+; CHECK-NEXT: movslq c(%rip), %rax
; CHECK-NEXT: leaq (%rax,%rax,4), %rcx
; CHECK-NEXT: leaq (,%rax,4), %rdx
; CHECK-NEXT: movl a(%rdx,%rcx,8), %ecx
@@ -34,7 +34,7 @@ entry:
define dso_local i32 @main() local_unnamed_addr #0 {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movslq {{.*}}(%rip), %rax
+; CHECK-NEXT: movslq c(%rip), %rax
; CHECK-NEXT: leaq (%rax,%rax,4), %rcx
; CHECK-NEXT: leaq (,%rax,4), %rdx
; CHECK-NEXT: movl a(%rdx,%rcx,8), %ecx
diff --git a/llvm/test/CodeGen/X86/pr34653.ll b/llvm/test/CodeGen/X86/pr34653.ll
index f341a9a6c6741..d46cd2091856e 100644
--- a/llvm/test/CodeGen/X86/pr34653.ll
+++ b/llvm/test/CodeGen/X86/pr34653.ll
@@ -14,7 +14,7 @@ define void @pr34653() {
; CHECK-NEXT: andq $-512, %rsp # imm = 0xFE00
; CHECK-NEXT: subq $1024, %rsp # imm = 0x400
; CHECK-NEXT: movq %rsp, %rdi
-; CHECK-NEXT: callq test
+; CHECK-NEXT: callq test at PLT
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
diff --git a/llvm/test/CodeGen/X86/pr35316.ll b/llvm/test/CodeGen/X86/pr35316.ll
index 2cb9733fbf8cc..47ae9ac857943 100644
--- a/llvm/test/CodeGen/X86/pr35316.ll
+++ b/llvm/test/CodeGen/X86/pr35316.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=CHECK
-; This tests for a cyclic dependencies in the generated DAG.
+; This tests for a cyclic dependencies in the generated DAG.
@c = external dso_local local_unnamed_addr global i32, align 4
@a = external dso_local local_unnamed_addr global i32, align 4
@@ -25,15 +25,15 @@ define void @foo() {
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, b(%rip)
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl {{.*}}(%rip)
+; CHECK-NEXT: idivl a(%rip)
; CHECK-NEXT: movl %eax, %ecx
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl c(%rip), %eax
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %esi
; CHECK-NEXT: andl %edi, %eax
diff --git a/llvm/test/CodeGen/X86/pr35443.ll b/llvm/test/CodeGen/X86/pr35443.ll
index d8d6e5113a1bb..4704471ad445d 100644
--- a/llvm/test/CodeGen/X86/pr35443.ll
+++ b/llvm/test/CodeGen/X86/pr35443.ll
@@ -8,11 +8,11 @@
define void @pr35443() {
; CHECK-LABEL: pr35443:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vpbroadcastb ac+{{.*}}(%rip), %xmm0
+; CHECK-NEXT: vpbroadcastb ac+4(%rip), %xmm0
; CHECK-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpsubq %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: vpmovqd %ymm0, ai3+{{.*}}(%rip)
+; CHECK-NEXT: vpmovqd %ymm0, ai3+16(%rip)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr35761.ll b/llvm/test/CodeGen/X86/pr35761.ll
index aaab027282a98..061250e1f153b 100644
--- a/llvm/test/CodeGen/X86/pr35761.ll
+++ b/llvm/test/CodeGen/X86/pr35761.ll
@@ -8,13 +8,13 @@
define dso_local void @PR35761(i32 %call) {
; CHECK-LABEL: PR35761:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzbl {{.*}}(%rip), %eax
+; CHECK-NEXT: movzbl x(%rip), %eax
; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: movzbl {{.*}}(%rip), %ecx
+; CHECK-NEXT: movzbl y(%rip), %ecx
; CHECK-NEXT: xorl $255, %ecx
; CHECK-NEXT: orl %eax, %ecx
-; CHECK-NEXT: movw %cx, {{.*}}(%rip)
-; CHECK-NEXT: movb $0, z+{{.*}}(%rip)
+; CHECK-NEXT: movw %cx, z(%rip)
+; CHECK-NEXT: movb $0, z+2(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i8, i8* @x, align 1
diff --git a/llvm/test/CodeGen/X86/pr35763.ll b/llvm/test/CodeGen/X86/pr35763.ll
index 6b67d04ad772f..8b3e91dc577ae 100644
--- a/llvm/test/CodeGen/X86/pr35763.ll
+++ b/llvm/test/CodeGen/X86/pr35763.ll
@@ -10,19 +10,19 @@
define dso_local void @PR35763() {
; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
-; CHECK-NEXT: orl z+{{.*}}(%rip), %eax
+; CHECK-NEXT: movl z(%rip), %eax
+; CHECK-NEXT: orl z+2(%rip), %eax
; CHECK-NEXT: movzwl %ax, %eax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movl z+{{.*}}(%rip), %eax
-; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx
+; CHECK-NEXT: movq %rax, tf_3_var_136(%rip)
+; CHECK-NEXT: movl z+6(%rip), %eax
+; CHECK-NEXT: movzbl z+10(%rip), %ecx
; CHECK-NEXT: shlq $32, %rcx
; CHECK-NEXT: orq %rax, %rcx
; CHECK-NEXT: movabsq $1090921758719, %rax # imm = 0xFE0000FFFF
; CHECK-NEXT: andq %rcx, %rax
-; CHECK-NEXT: movl %eax, z+{{.*}}(%rip)
+; CHECK-NEXT: movl %eax, z+6(%rip)
; CHECK-NEXT: shrq $32, %rax
-; CHECK-NEXT: movb %al, z+{{.*}}(%rip)
+; CHECK-NEXT: movb %al, z+10(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i16, i16* getelementptr inbounds (%struct.S, %struct.S* bitcast ({ i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] }* @z to %struct.S*), i32 0, i32 0), align 8
diff --git a/llvm/test/CodeGen/X86/pr35765.ll b/llvm/test/CodeGen/X86/pr35765.ll
index b421dcc6095e0..5ff34a005f53f 100644
--- a/llvm/test/CodeGen/X86/pr35765.ll
+++ b/llvm/test/CodeGen/X86/pr35765.ll
@@ -9,19 +9,19 @@
define dso_local void @PR35765() {
; CHECK-LABEL: PR35765:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movb {{.*}}(%rip), %cl
+; CHECK-NEXT: movb s1(%rip), %cl
; CHECK-NEXT: addb $-118, %cl
; CHECK-NEXT: movl $4, %eax
; CHECK-NEXT: shll %cl, %eax
-; CHECK-NEXT: movzwl {{.*}}(%rip), %ecx
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl x(%rip), %ecx
+; CHECK-NEXT: movzwl s2(%rip), %edx
; CHECK-NEXT: notl %edx
; CHECK-NEXT: orl $63488, %edx # imm = 0xF800
; CHECK-NEXT: movzwl %dx, %edx
; CHECK-NEXT: orl %ecx, %edx
; CHECK-NEXT: xorl %eax, %edx
; CHECK-NEXT: movslq %edx, %rax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
+; CHECK-NEXT: movq %rax, ll(%rip)
; CHECK-NEXT: retq
entry:
%bf.load.i = load i16, i16* bitcast ({ i8, i8 }* @s1 to i16*), align 2
diff --git a/llvm/test/CodeGen/X86/pr36312.ll b/llvm/test/CodeGen/X86/pr36312.ll
index 4481b734421b2..cffbe68aac4ef 100644
--- a/llvm/test/CodeGen/X86/pr36312.ll
+++ b/llvm/test/CodeGen/X86/pr36312.ll
@@ -12,13 +12,13 @@
define void @g() local_unnamed_addr #0 {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq d(%rip), %rax
; CHECK-NEXT: movl 4(%rax), %eax
; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: incl {{.*}}(%rip)
+; CHECK-NEXT: incl b(%rip)
; CHECK-NEXT: setne %cl
; CHECK-NEXT: addl %eax, %ecx
-; CHECK-NEXT: movl %ecx, {{.*}}(%rip)
+; CHECK-NEXT: movl %ecx, a(%rip)
; CHECK-NEXT: retq
entry:
%0 = load %struct.anon*, %struct.anon** @d, align 8
diff --git a/llvm/test/CodeGen/X86/pr36553.ll b/llvm/test/CodeGen/X86/pr36553.ll
index 827f80a3e07e1..b61ec81473081 100644
--- a/llvm/test/CodeGen/X86/pr36553.ll
+++ b/llvm/test/CodeGen/X86/pr36553.ll
@@ -8,7 +8,7 @@ define float @pr36553(float %a, float %b, float %c) nounwind {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq _fmaf
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr36865.ll b/llvm/test/CodeGen/X86/pr36865.ll
index 82b2e86695eac..a94a88f013302 100644
--- a/llvm/test/CodeGen/X86/pr36865.ll
+++ b/llvm/test/CodeGen/X86/pr36865.ll
@@ -9,7 +9,7 @@ define void @main() {
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
; CHECK-NEXT: movl $400, %edx # imm = 0x190
; CHECK-NEXT: xorl %esi, %esi
-; CHECK-NEXT: callq memset
+; CHECK-NEXT: callq memset at PLT
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl (%rax), %ecx
; CHECK-NEXT: addl 0, %eax
diff --git a/llvm/test/CodeGen/X86/pr37820.ll b/llvm/test/CodeGen/X86/pr37820.ll
index 1eff33946825c..711b20b29d5d0 100644
--- a/llvm/test/CodeGen/X86/pr37820.ll
+++ b/llvm/test/CodeGen/X86/pr37820.ll
@@ -10,8 +10,8 @@
define void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl a+{{.*}}(%rip), %eax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
+; CHECK-NEXT: movzwl a+6(%rip), %eax
+; CHECK-NEXT: movq %rax, b(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i64, i64* @a, align 8
diff --git a/llvm/test/CodeGen/X86/pr37826.ll b/llvm/test/CodeGen/X86/pr37826.ll
index bd31bf4d88d0d..c2b3e0bf6d8f2 100644
--- a/llvm/test/CodeGen/X86/pr37826.ll
+++ b/llvm/test/CodeGen/X86/pr37826.ll
@@ -13,10 +13,10 @@
define dso_local void @k(i32 %l) {
; CHECK-LABEL: k:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
-; CHECK-NEXT: orl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl e(%rip), %eax
+; CHECK-NEXT: orl f(%rip), %eax
; CHECK-NEXT: shrl $24, %eax
-; CHECK-NEXT: movb %al, f+{{.*}}(%rip)
+; CHECK-NEXT: movb %al, f+3(%rip)
; CHECK-NEXT: retq
%load = load i32, i32* @c, align 4
%load6 = load i32, i32* @f, align 4
@@ -45,10 +45,10 @@ define dso_local i32 @main() {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movl $1, %edi
; CHECK-NEXT: callq k
-; CHECK-NEXT: movl {{.*}}(%rip), %esi
+; CHECK-NEXT: movl f(%rip), %esi
; CHECK-NEXT: movl $.L.str.1, %edi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq printf
+; CHECK-NEXT: callq printf at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/pr37916.ll b/llvm/test/CodeGen/X86/pr37916.ll
index 270266b9bddbf..f97399ba35def 100644
--- a/llvm/test/CodeGen/X86/pr37916.ll
+++ b/llvm/test/CodeGen/X86/pr37916.ll
@@ -7,7 +7,8 @@
define void @fn1() local_unnamed_addr {
; CHECK-LABEL: fn1:
; CHECK: # %bb.0: # %entry
-; CHECK: .LBB0_1: # %if.end
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB0_1: # %if.end
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl a+4, %eax
; CHECK-NEXT: orl a, %eax
diff --git a/llvm/test/CodeGen/X86/pr38743.ll b/llvm/test/CodeGen/X86/pr38743.ll
index bb8cbb13f7bee..2ab06bb90fa8b 100644
--- a/llvm/test/CodeGen/X86/pr38743.ll
+++ b/llvm/test/CodeGen/X86/pr38743.ll
@@ -23,19 +23,19 @@ define void @pr38743(i32 %a0) #1 align 2 {
; CHECK-NEXT: decl %edi
; CHECK-NEXT: jmpq *.LJTI0_0(,%rdi,8)
; CHECK-NEXT: .LBB0_2: # %bb5
-; CHECK-NEXT: movzwl .str.17+{{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl .str.17+8(%rip), %eax
; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq .str.17(%rip), %rax
; CHECK-NEXT: jmp .LBB0_4
; CHECK-NEXT: .LBB0_1: # %bb2
-; CHECK-NEXT: movq .str.16+{{.*}}(%rip), %rax
+; CHECK-NEXT: movq .str.16+7(%rip), %rax
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq .str.16(%rip), %rax
; CHECK-NEXT: jmp .LBB0_4
; CHECK-NEXT: .LBB0_3: # %bb8
-; CHECK-NEXT: movq .str.18+{{.*}}(%rip), %rax
+; CHECK-NEXT: movq .str.18+6(%rip), %rax
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq .str.18(%rip), %rax
; CHECK-NEXT: .LBB0_4: # %bb12
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
diff --git a/llvm/test/CodeGen/X86/pr38803.ll b/llvm/test/CodeGen/X86/pr38803.ll
index a9f094a2ee6c7..53d31b70e902a 100644
--- a/llvm/test/CodeGen/X86/pr38803.ll
+++ b/llvm/test/CodeGen/X86/pr38803.ll
@@ -10,18 +10,18 @@ define dso_local float @_Z3fn2v() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq _Z1av
+; CHECK-NEXT: callq _Z1av at PLT
; CHECK-NEXT: # kill: def $al killed $al def $eax
; CHECK-NEXT: kmovd %eax, %k1
-; CHECK-NEXT: vmovss {{.*}}(%rip), %xmm0 {%k1} {z}
-; CHECK-NEXT: cmpl $0, {{.*}}(%rip)
+; CHECK-NEXT: vmovss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1} {z}
+; CHECK-NEXT: cmpl $0, c(%rip)
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: vcvtsi2ssl {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvtsi2ssl b(%rip), %xmm1, %xmm1
; CHECK-NEXT: kmovd %eax, %k1
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1}
-; CHECK-NEXT: vmovss %xmm1, {{.*}}(%rip)
+; CHECK-NEXT: vmovss %xmm1, d(%rip)
; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/pr38865-2.ll b/llvm/test/CodeGen/X86/pr38865-2.ll
index 5400e9c5955a0..e14d9668e870a 100644
--- a/llvm/test/CodeGen/X86/pr38865-2.ll
+++ b/llvm/test/CodeGen/X86/pr38865-2.ll
@@ -13,7 +13,7 @@ define void @_Z1bv(%struct.a* noalias sret(%struct.a) %agg.result) {
; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT: callq _Z1bv
+; CHECK-NEXT: callq _Z1bv at PLT
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/pr40529.ll b/llvm/test/CodeGen/X86/pr40529.ll
index 04a468d197955..a0ab4b5ffb635 100644
--- a/llvm/test/CodeGen/X86/pr40529.ll
+++ b/llvm/test/CodeGen/X86/pr40529.ll
@@ -15,7 +15,7 @@ define x86_fp80 @rem_pio2l_min(x86_fp80 %z) {
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fisubl -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: flds {{.*}}(%rip)
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; CHECK-NEXT: fmul %st, %st(1)
; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
diff --git a/llvm/test/CodeGen/X86/pr40539.ll b/llvm/test/CodeGen/X86/pr40539.ll
index 8f98a7a35fa28..85c329eafd1bb 100644
--- a/llvm/test/CodeGen/X86/pr40539.ll
+++ b/llvm/test/CodeGen/X86/pr40539.ll
@@ -41,7 +41,7 @@ define zeroext i1 @_Z8test_cosv() {
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: divss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; CHECK-NEXT: divss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: #APP
@@ -51,7 +51,7 @@ define zeroext i1 @_Z8test_cosv() {
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm0, %xmm1
; CHECK-NEXT: setae %cl
-; CHECK-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: setae %al
; CHECK-NEXT: andb %cl, %al
; CHECK-NEXT: addl $8, %esp
diff --git a/llvm/test/CodeGen/X86/pr40891.ll b/llvm/test/CodeGen/X86/pr40891.ll
index 1455f72e810aa..24f644683c286 100644
--- a/llvm/test/CodeGen/X86/pr40891.ll
+++ b/llvm/test/CodeGen/X86/pr40891.ll
@@ -7,7 +7,7 @@ define <8 x i32> @foo(<8 x i64> %x, <4 x i64> %y) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: vandps %ymm2, %ymm0, %ymm0
-; CHECK-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
+; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; CHECK-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm2[0,2],ymm0[4,6],ymm2[4,6]
diff --git a/llvm/test/CodeGen/X86/pr42064.ll b/llvm/test/CodeGen/X86/pr42064.ll
index 089895da18a1d..e76a3295201a0 100644
--- a/llvm/test/CodeGen/X86/pr42064.ll
+++ b/llvm/test/CodeGen/X86/pr42064.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-pc-windows-msvc19.11.0 -mattr=+avx,+cx16 | FileCheck %s
%struct.TestStruct = type { %union.Int128 }
diff --git a/llvm/test/CodeGen/X86/pr43157.ll b/llvm/test/CodeGen/X86/pr43157.ll
index 9510ed81bb353..2b333782f43a0 100644
--- a/llvm/test/CodeGen/X86/pr43157.ll
+++ b/llvm/test/CodeGen/X86/pr43157.ll
@@ -6,8 +6,8 @@ define void @foo(fp128 %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movaps {{.*}}(%rip), %xmm1
-; CHECK-NEXT: callq __multf3
+; CHECK-NEXT: movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: callq __multf3 at PLT
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/pr43509.ll b/llvm/test/CodeGen/X86/pr43509.ll
index 4243764d08cf7..e2c3affd952bb 100644
--- a/llvm/test/CodeGen/X86/pr43509.ll
+++ b/llvm/test/CodeGen/X86/pr43509.ll
@@ -4,11 +4,11 @@
define <8 x i8> @foo(<8 x float> %arg) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %bb
-; CHECK-NEXT: vcmpgtps {{.*}}(%rip){1to8}, %ymm0, %k0
+; CHECK-NEXT: vcmpgtps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k0
; CHECK-NEXT: vpmovm2b %k0, %xmm1
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpltps %ymm2, %ymm0, %k1
-; CHECK-NEXT: vmovdqu8 {{.*}}(%rip), %xmm0 {%k1} {z}
+; CHECK-NEXT: vmovdqu8 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1} {z}
; CHECK-NEXT: vpand %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr43529.ll b/llvm/test/CodeGen/X86/pr43529.ll
index afccf5e46d7c6..f0e860bd89da7 100644
--- a/llvm/test/CodeGen/X86/pr43529.ll
+++ b/llvm/test/CodeGen/X86/pr43529.ll
@@ -9,7 +9,7 @@ define i32 @a() nounwind {
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: subl $a, %eax
-; CHECK-NEXT: calll d
+; CHECK-NEXT: calll d at PLT
; CHECK-NEXT: cmpl $a, %esi
; CHECK-NEXT: jbe .LBB0_2
; CHECK-NEXT: .p2align 4, 0x90
diff --git a/llvm/test/CodeGen/X86/pr43952.ll b/llvm/test/CodeGen/X86/pr43952.ll
index 9c6b5113669aa..8e1425c281ccb 100644
--- a/llvm/test/CodeGen/X86/pr43952.ll
+++ b/llvm/test/CodeGen/X86/pr43952.ll
@@ -6,7 +6,7 @@ define void @x() {
; CHECK: ## %bb.0: ## %start
; CHECK-NEXT: ## InlineAsm Start
; CHECK-EMPTY:
-; CHECK-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1}
+; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k1}
; CHECK-EMPTY:
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr44140.ll b/llvm/test/CodeGen/X86/pr44140.ll
index 9e623ae5bceb5..68ac3663a4cd8 100644
--- a/llvm/test/CodeGen/X86/pr44140.ll
+++ b/llvm/test/CodeGen/X86/pr44140.ll
@@ -41,7 +41,7 @@ define i32 @main() {
; CHECK-NEXT: vmovups %ymm5, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovups %ymm4, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: callq opaque
+; CHECK-NEXT: callq opaque at PLT
; CHECK-NEXT: vmovaps %xmm6, {{[0-9]+}}(%rsp)
; CHECK-NEXT: testb %sil, %sil
; CHECK-NEXT: jne .LBB1_1
diff --git a/llvm/test/CodeGen/X86/pr44396.ll b/llvm/test/CodeGen/X86/pr44396.ll
index d42d7513a50a1..cd78d3e2298cb 100644
--- a/llvm/test/CodeGen/X86/pr44396.ll
+++ b/llvm/test/CodeGen/X86/pr44396.ll
@@ -21,7 +21,7 @@ define double @c() nounwind {
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: fildll (%esp)
-; CHECK-NEXT: fadds LCPI0_0(,%edx,4)
+; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%edx,4)
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldz
diff --git a/llvm/test/CodeGen/X86/pr44412.ll b/llvm/test/CodeGen/X86/pr44412.ll
index dbd0a4e6ea5c8..6c33666fb5c3a 100644
--- a/llvm/test/CodeGen/X86/pr44412.ll
+++ b/llvm/test/CodeGen/X86/pr44412.ll
@@ -13,7 +13,7 @@ define void @bar(i32 %0, i32 %1) nounwind {
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebx, %edi
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: addl $-1, %ebx
; CHECK-NEXT: jb .LBB0_2
; CHECK-NEXT: .LBB0_3:
@@ -45,7 +45,7 @@ define void @baz(i32 %0, i32 %1) nounwind {
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebx, %edi
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: addl $-1, %ebx
; CHECK-NEXT: jae .LBB1_2
; CHECK-NEXT: .LBB1_3:
diff --git a/llvm/test/CodeGen/X86/pr44749.ll b/llvm/test/CodeGen/X86/pr44749.ll
index 7f3db698ed69f..17cc431285f67 100644
--- a/llvm/test/CodeGen/X86/pr44749.ll
+++ b/llvm/test/CodeGen/X86/pr44749.ll
@@ -10,18 +10,18 @@ define i32 @a() {
; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: callq _b
; CHECK-NEXT: cvtsi2sd %eax, %xmm0
-; CHECK-NEXT: movq _calloc@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _calloc at GOTPCREL(%rip), %rax
; CHECK-NEXT: subq $-1, %rax
; CHECK-NEXT: setne %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movl %eax, %ecx
-; CHECK-NEXT: leaq {{.*}}(%rip), %rax
+; CHECK-NEXT: leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: ucomisd %xmm1, %xmm0
; CHECK-NEXT: setae %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movl %eax, %ecx
-; CHECK-NEXT: leaq {{.*}}(%rip), %rax
+; CHECK-NEXT: leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: cvttsd2si %xmm0, %eax
; CHECK-NEXT: popq %rcx
diff --git a/llvm/test/CodeGen/X86/pr45067.ll b/llvm/test/CodeGen/X86/pr45067.ll
index 1cdd53f8db357..1731213916981 100644
--- a/llvm/test/CodeGen/X86/pr45067.ll
+++ b/llvm/test/CodeGen/X86/pr45067.ll
@@ -8,7 +8,7 @@ define void @foo(<8 x i32>* %x, <8 x i1> %y) {
; CHECK: ## %bb.0:
; CHECK-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; CHECK-NEXT: movq _global@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _global at GOTPCREL(%rip), %rax
; CHECK-NEXT: vpgatherdd %ymm1, (%rax,%ymm2), %ymm3
; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; CHECK-NEXT: vpslld $31, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/pr45995.ll b/llvm/test/CodeGen/X86/pr45995.ll
index 693b488a55596..9b6275002092e 100644
--- a/llvm/test/CodeGen/X86/pr45995.ll
+++ b/llvm/test/CodeGen/X86/pr45995.ll
@@ -23,13 +23,13 @@ define void @extracter0([4 x <4 x i1>] %matrix) {
; CHECK-NEXT: mov ebx, edi
; CHECK-NEXT: and bl, 2
; CHECK-NEXT: shr bl
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, bl
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, r14b
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, bpl
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: pop rbx
; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: pop r14
@@ -93,21 +93,21 @@ define void @extracter1([4 x <4 x i1>] %matrix) {
; CHECK-NEXT: mov r14d, edi
; CHECK-NEXT: and r14b, 2
; CHECK-NEXT: shr r14b
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, r14b
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, bl
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, r12b
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: mov edi, ebp
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, r13b
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, r15b
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: movzx edi, byte ptr [rsp + 7] # 1-byte Folded Reload
-; CHECK-NEXT: call print_i1
+; CHECK-NEXT: call print_i1 at PLT
; CHECK-NEXT: add rsp, 8
; CHECK-NEXT: .cfi_def_cfa_offset 56
; CHECK-NEXT: pop rbx
diff --git a/llvm/test/CodeGen/X86/pr46527.ll b/llvm/test/CodeGen/X86/pr46527.ll
index 076d8137120f6..65f6d4d81b062 100644
--- a/llvm/test/CodeGen/X86/pr46527.ll
+++ b/llvm/test/CodeGen/X86/pr46527.ll
@@ -22,7 +22,7 @@ define void @f(<16 x i8>* %out, <16 x i8> %in, i1 %flag) {
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; CHECK-NEXT: paddb %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm1
-; CHECK-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}@GOTOFF(%eax), %xmm1
+; CHECK-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF(%eax), %xmm1
; CHECK-NEXT: movdqa %xmm1, (%ecx)
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/pr46585.ll b/llvm/test/CodeGen/X86/pr46585.ll
index 7bea63176d1bb..3700f13bbc4ed 100644
--- a/llvm/test/CodeGen/X86/pr46585.ll
+++ b/llvm/test/CodeGen/X86/pr46585.ll
@@ -11,7 +11,7 @@ define void @spam() local_unnamed_addr {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_2
; CHECK-NEXT: ## %bb.1: ## %bb9
-; CHECK-NEXT: movq _global.1@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _global.1 at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq $1, (%rax)
; CHECK-NEXT: LBB0_2: ## %bb8
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr47000.ll b/llvm/test/CodeGen/X86/pr47000.ll
index c2d9317a95ea6..5c77c48b37ba7 100755
--- a/llvm/test/CodeGen/X86/pr47000.ll
+++ b/llvm/test/CodeGen/X86/pr47000.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=pentium4 -O0 | FileCheck %s
target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128"
diff --git a/llvm/test/CodeGen/X86/pr47299.ll b/llvm/test/CodeGen/X86/pr47299.ll
index 93710b87751e0..d51c03c633478 100644
--- a/llvm/test/CodeGen/X86/pr47299.ll
+++ b/llvm/test/CodeGen/X86/pr47299.ll
@@ -13,7 +13,7 @@ define <7 x i1> @create_mask7(i64 %0) {
; CHECK: # %bb.0:
; CHECK-NEXT: mov rax, rdi
; CHECK-NEXT: vpbroadcastq zmm0, rsi
-; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kshiftrb k1, k0, 6
; CHECK-NEXT: kmovd r8d, k1
; CHECK-NEXT: kshiftrb k1, k0, 5
@@ -57,8 +57,8 @@ define <16 x i1> @create_mask16(i64 %0) {
; CHECK-LABEL: create_mask16:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastq zmm0, rdi
-; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k0, k1, k0
; CHECK-NEXT: vpmovm2b xmm0, k0
; CHECK-NEXT: vzeroupper
@@ -71,11 +71,11 @@ define <32 x i1> @create_mask32(i64 %0) {
; CHECK-LABEL: create_mask32:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastq zmm0, rdi
-; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k0, k1, k0
-; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k1, k1, k2
; CHECK-NEXT: kunpckwd k0, k1, k0
; CHECK-NEXT: vpmovm2b ymm0, k0
@@ -88,18 +88,18 @@ define <64 x i1> @create_mask64(i64 %0) {
; CHECK-LABEL: create_mask64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastq zmm0, rdi
-; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k0, k1, k0
-; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k1, k1, k2
-; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckwd k0, k1, k0
-; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k1, k1, k2
-; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleuq k3, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleuq k3, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k2, k3, k2
; CHECK-NEXT: kunpckwd k1, k2, k1
; CHECK-NEXT: kunpckdq k0, k1, k0
@@ -113,7 +113,7 @@ define <16 x i1> @create_mask16_i32(i32 %0) {
; CHECK-LABEL: create_mask16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastd zmm0, edi
-; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpmovm2b xmm0, k0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret
@@ -125,11 +125,11 @@ define <64 x i1> @create_mask64_i32(i32 %0) {
; CHECK-LABEL: create_mask64_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastd zmm0, edi
-; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
-; CHECK-NEXT: vpcmpnleud k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleud k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckwd k0, k1, k0
-; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
+; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckwd k1, k1, k2
; CHECK-NEXT: kunpckdq k0, k1, k0
; CHECK-NEXT: vpmovm2b zmm0, k0
diff --git a/llvm/test/CodeGen/X86/pr47482.ll b/llvm/test/CodeGen/X86/pr47482.ll
index d78b1aea0e466..f7f8d021dec74 100644
--- a/llvm/test/CodeGen/X86/pr47482.ll
+++ b/llvm/test/CodeGen/X86/pr47482.ll
@@ -7,7 +7,7 @@
define void @g(i32* %x, i32* %y, i32* %z) {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl a(%rip), %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: xorl %ecx, %ecx
@@ -19,7 +19,7 @@ define void @g(i32* %x, i32* %y, i32* %z) {
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: shll $8, %eax
-; CHECK-NEXT: bextrl %eax, {{.*}}(%rip), %eax
+; CHECK-NEXT: bextrl %eax, f(%rip), %eax
; CHECK-NEXT: orl %ecx, %eax
; CHECK-NEXT: movl %eax, (%rdx)
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr47517.ll b/llvm/test/CodeGen/X86/pr47517.ll
index afc27b49ab2a4..3e3f818842626 100644
--- a/llvm/test/CodeGen/X86/pr47517.ll
+++ b/llvm/test/CodeGen/X86/pr47517.ll
@@ -30,6 +30,11 @@ entry:
; To ensure negated result will not be removed when NegX=NegY and
; NegX is needed
define float @test2(float %x, float %y) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: retq
%add = fadd fast float %x, 750.0
%sub = fsub fast float %x, %add
%mul = fmul fast float %sub, %sub
diff --git a/llvm/test/CodeGen/X86/pr48215.ll b/llvm/test/CodeGen/X86/pr48215.ll
index 125bde728c3f8..6639696a114a8 100644
--- a/llvm/test/CodeGen/X86/pr48215.ll
+++ b/llvm/test/CodeGen/X86/pr48215.ll
@@ -52,8 +52,8 @@ define i32 @PR48215(i32 %a0, i32 %a1) {
; AVX512-NEXT: idivl %esi
; AVX512-NEXT: vpbroadcastd %eax, %ymm0
; AVX512-NEXT: vpbroadcastd %edx, %xmm1
-; AVX512-NEXT: vpcmpltd {{.*}}(%rip), %ymm0, %k0
-; AVX512-NEXT: vpcmpltd {{.*}}(%rip), %xmm1, %k1
+; AVX512-NEXT: vpcmpltd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
+; AVX512-NEXT: vpcmpltd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
; AVX512-NEXT: kmovw %k0, %eax
; AVX512-NEXT: movzbl %al, %ecx
; AVX512-NEXT: kmovw %k1, %eax
diff --git a/llvm/test/CodeGen/X86/pr49451.ll b/llvm/test/CodeGen/X86/pr49451.ll
index 396b92df3c0d9..2317f222fe1d6 100644
--- a/llvm/test/CodeGen/X86/pr49451.ll
+++ b/llvm/test/CodeGen/X86/pr49451.ll
@@ -47,9 +47,9 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind {
; X64-NEXT: # in Loop: Header=BB0_1 Depth=1
; X64-NEXT: testb %cl, %cl
; X64-NEXT: addl %esi, %edx
-; X64-NEXT: movw %dx, {{.*}}(%rip)
+; X64-NEXT: movw %dx, s_2(%rip)
; X64-NEXT: leal -23090(%rax), %edi
-; X64-NEXT: movw %di, {{.*}}(%rip)
+; X64-NEXT: movw %di, s_0(%rip)
; X64-NEXT: incq %rax
; X64-NEXT: leal -23091(%rax), %edi
; X64-NEXT: cmpw $73, %di
diff --git a/llvm/test/CodeGen/X86/pr50254.ll b/llvm/test/CodeGen/X86/pr50254.ll
index 1bb9bec330e0f..6f544f7c88760 100644
--- a/llvm/test/CodeGen/X86/pr50254.ll
+++ b/llvm/test/CodeGen/X86/pr50254.ll
@@ -18,12 +18,12 @@ define void @PR50254() {
;
; X64-LABEL: PR50254:
; X64: # %bb.0: # %entry
-; X64-NEXT: movswq {{.*}}(%rip), %rax
+; X64-NEXT: movswq d.e(%rip), %rax
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: testb %cl, %cl
; X64-NEXT: jne .LBB0_2
; X64-NEXT: # %bb.1: # %for.end
-; X64-NEXT: movw %ax, {{.*}}(%rip)
+; X64-NEXT: movw %ax, d.e(%rip)
; X64-NEXT: .LBB0_2: # %for.body.1
; X64-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr5145.ll b/llvm/test/CodeGen/X86/pr5145.ll
index e3658d87e895a..be1610a59a2bd 100644
--- a/llvm/test/CodeGen/X86/pr5145.ll
+++ b/llvm/test/CodeGen/X86/pr5145.ll
@@ -5,7 +5,7 @@
define void @atomic_maxmin_i8() {
; CHECK-LABEL: atomic_maxmin_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: movb {{.*}}(%rip), %al
+; CHECK-NEXT: movb sc8(%rip), %al
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -14,10 +14,10 @@ define void @atomic_maxmin_i8() {
; CHECK-NEXT: movl $5, %ecx
; CHECK-NEXT: cmovgl %eax, %ecx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, {{.*}}(%rip)
+; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
-; CHECK-NEXT: movb {{.*}}(%rip), %al
+; CHECK-NEXT: movb sc8(%rip), %al
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_3: # %atomicrmw.start2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -26,10 +26,10 @@ define void @atomic_maxmin_i8() {
; CHECK-NEXT: movl $6, %ecx
; CHECK-NEXT: cmovll %eax, %ecx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, {{.*}}(%rip)
+; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: # %bb.4: # %atomicrmw.end1
-; CHECK-NEXT: movb {{.*}}(%rip), %al
+; CHECK-NEXT: movb sc8(%rip), %al
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_5: # %atomicrmw.start8
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -38,10 +38,10 @@ define void @atomic_maxmin_i8() {
; CHECK-NEXT: movl $7, %ecx
; CHECK-NEXT: cmoval %eax, %ecx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, {{.*}}(%rip)
+; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_5
; CHECK-NEXT: # %bb.6: # %atomicrmw.end7
-; CHECK-NEXT: movb {{.*}}(%rip), %al
+; CHECK-NEXT: movb sc8(%rip), %al
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_7: # %atomicrmw.start14
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -50,7 +50,7 @@ define void @atomic_maxmin_i8() {
; CHECK-NEXT: movl $8, %ecx
; CHECK-NEXT: cmovbl %eax, %ecx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, {{.*}}(%rip)
+; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_7
; CHECK-NEXT: # %bb.8: # %atomicrmw.end13
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr9517.ll b/llvm/test/CodeGen/X86/pr9517.ll
index 6ff03683bbe08..182005c10e5be 100644
--- a/llvm/test/CodeGen/X86/pr9517.ll
+++ b/llvm/test/CodeGen/X86/pr9517.ll
@@ -7,11 +7,11 @@
define i16 @unify_through_trivial_asm() {
; CHECK-LABEL: unify_through_trivial_asm:
; CHECK: # %bb.0:
-; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl base(%rip), %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl base(%rip), %eax
; CHECK-NEXT: incl %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
@@ -22,15 +22,15 @@ define i16 @unify_through_trivial_asm() {
ret i16 %v
}
-; The asm call prevents the merging the loads here.
+; The asm call prevents the merging the loads here.
define i16 @unify_through_trival_asm_w_memory_clobber() {
; CHECK-LABEL: unify_through_trival_asm_w_memory_clobber:
; CHECK: # %bb.0:
-; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl base(%rip), %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl base(%rip), %eax
; CHECK-NEXT: incl %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
@@ -44,63 +44,63 @@ define i16 @unify_through_trival_asm_w_memory_clobber() {
define dso_local void @fulltest() local_unnamed_addr {
; CHECK-LABEL: fulltest:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $2, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $3, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $4, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $5, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $6, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $7, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
; CHECK-NEXT: #APP
; CHECK-NEXT: outb %al, %dx
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzwl base(%rip), %edx
; CHECK-NEXT: addl $16, %edx
; CHECK-NEXT: movb $8, %al
; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
diff --git a/llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll b/llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll
index 65e16fdfbf5c7..0655cc9c9f470 100644
--- a/llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll
+++ b/llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll
@@ -10,7 +10,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) {
; AVX256-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX256-NEXT: vplzcntd %ymm0, %ymm0
; AVX256-NEXT: vpmovdw %ymm0, %xmm0
-; AVX256-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
+; AVX256-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX256-NEXT: vzeroupper
; AVX256-NEXT: retq
;
@@ -19,7 +19,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) {
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VL-NEXT: vplzcntd %ymm0, %ymm0
; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VL-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
@@ -28,7 +28,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) {
; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512F-NEXT: vplzcntd %zmm0, %zmm0
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512F-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
%out = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %in, i1 false)
@@ -41,7 +41,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) {
; AVX256-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX256-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX256-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX256-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX256-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX256-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX256-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm3
; AVX256-NEXT: vpand %xmm3, %xmm2, %xmm2
@@ -54,7 +54,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) {
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512-NEXT: vplzcntd %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512-NEXT: vpsubb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpsubb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%out = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %in, i1 false)
@@ -82,7 +82,7 @@ define <16 x i16> @testv16i16(<16 x i16> %in) {
; AVX512-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512-NEXT: vplzcntd %zmm0, %zmm0
; AVX512-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %in, i1 false)
ret <16 x i16> %out
@@ -94,7 +94,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) {
; AVX256-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX256-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX256-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX256-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX256-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX256-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX256-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; AVX256-NEXT: vpand %ymm3, %ymm2, %ymm2
diff --git a/llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll b/llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll
index 8149d238097cf..abc75a76b8c7d 100644
--- a/llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll
+++ b/llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll
@@ -194,7 +194,7 @@ define <16 x i8> @testv16i1_zext_v16i8(<8 x i32>* %p, <8 x i32>* %q) {
; AVX512VL-NEXT: vmovdqa (%rsi), %ymm0
; AVX512VL-NEXT: vptestnmd %ymm0, %ymm0, %k1
; AVX512VL-NEXT: kunpckbw %k0, %k1, %k1
-; AVX512VL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
+; AVX512VL-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k1} {z}
; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
@@ -206,7 +206,7 @@ define <16 x i8> @testv16i1_zext_v16i8(<8 x i32>* %p, <8 x i32>* %q) {
; AVX512F-NEXT: vmovdqa (%rsi), %ymm0
; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k1
; AVX512F-NEXT: kunpckbw %k0, %k1, %k1
-; AVX512F-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
+; AVX512F-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll b/llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
index c3855ad8de5ec..992909228f96c 100644
--- a/llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
+++ b/llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
@@ -152,7 +152,7 @@ define <32 x i1> @shuf32i1_3_6_22_12_3_7_7_0_3_6_1_13_3_21_7_0_3_6_22_12_3_7_7_0
; AVX256VL-NEXT: vmovdqa32 %ymm0, %ymm2 {%k1} {z}
; AVX256VL-NEXT: vpmovdw %ymm2, %xmm2
; AVX256VL-NEXT: vpermq {{.*#+}} ymm2 = ymm2[1,1,1,1]
-; AVX256VL-NEXT: vpternlogq $220, {{.*}}(%rip), %ymm1, %ymm2
+; AVX256VL-NEXT: vpternlogq $220, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
; AVX256VL-NEXT: vpmovsxwd %xmm2, %ymm1
; AVX256VL-NEXT: vpslld $31, %ymm1, %ymm1
; AVX256VL-NEXT: vptestmd %ymm1, %ymm1, %k1
diff --git a/llvm/test/CodeGen/X86/prefer-avx256-mulo.ll b/llvm/test/CodeGen/X86/prefer-avx256-mulo.ll
index 968f75e96e013..7c49af06e117c 100644
--- a/llvm/test/CodeGen/X86/prefer-avx256-mulo.ll
+++ b/llvm/test/CodeGen/X86/prefer-avx256-mulo.ll
@@ -11,7 +11,7 @@ define <16 x i1> @smulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) noun
; AVX256-NEXT: vpsrlw $8, %ymm0, %ymm1
; AVX256-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX256-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX256-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX256-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX256-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX256-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
; AVX256-NEXT: vpxor %xmm2, %xmm2, %xmm2
@@ -75,7 +75,7 @@ define <16 x i1> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) noun
; AVX256-NEXT: vptestmd %ymm2, %ymm2, %k1
; AVX256-NEXT: vpmovsxbd %xmm1, %ymm1
; AVX256-NEXT: vptestmd %ymm1, %ymm1, %k2
-; AVX256-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX256-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX256-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX256-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX256-NEXT: vmovdqa %xmm0, (%rdi)
diff --git a/llvm/test/CodeGen/X86/prefer-avx256-trunc.ll b/llvm/test/CodeGen/X86/prefer-avx256-trunc.ll
index 2219a302a23fb..3fbf694278df0 100644
--- a/llvm/test/CodeGen/X86/prefer-avx256-trunc.ll
+++ b/llvm/test/CodeGen/X86/prefer-avx256-trunc.ll
@@ -11,7 +11,7 @@
define <16 x i8> @testv16i16_trunc_v16i8(<16 x i16> %x) {
; AVX256NOBW-LABEL: testv16i16_trunc_v16i8:
; AVX256NOBW: # %bb.0:
-; AVX256NOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX256NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX256NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX256NOBW-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX256NOBW-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll b/llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
index 04e1a257d18b3..3b811f40f1fdb 100644
--- a/llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
+++ b/llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
@@ -18,24 +18,24 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) {
; AVX256BW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
; AVX256BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX256BW-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX256BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX256BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX256BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX256BW-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX256BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX256BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX256BW-NEXT: retq
;
; AVX512BW-LABEL: test_div7_32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: retq
%res = udiv <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %res
diff --git a/llvm/test/CodeGen/X86/promote-cmp.ll b/llvm/test/CodeGen/X86/promote-cmp.ll
index 37450df80941e..8cb33e9433a8d 100644
--- a/llvm/test/CodeGen/X86/promote-cmp.ll
+++ b/llvm/test/CodeGen/X86/promote-cmp.ll
@@ -35,7 +35,7 @@ define <4 x i64> @PR45808(<4 x i64> %0, <4 x i64> %1) {
; SSE2-NEXT: pandn %xmm3, %xmm4
; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,1,1,3]
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psllq $63, %xmm3
; SSE2-NEXT: psrad $31, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
@@ -70,14 +70,14 @@ define <4 x i64> @PR45808(<4 x i64> %0, <4 x i64> %1) {
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
-; AVX1-NEXT: vxorpd {{.*}}(%rip), %ymm2, %ymm2
+; AVX1-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: PR45808:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpxor {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
%3 = icmp sgt <4 x i64> %0, %1
diff --git a/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll b/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll
index e0370534239be..6a009ec0efed7 100644
--- a/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll
+++ b/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll
@@ -7,23 +7,6 @@
; X86TargetLowering::EmitLoweredSelect.
;
define double @foo1(float %p1, double %p2, double %p3) nounwind {
-; CHECK-LABEL: foo1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorps %xmm3, %xmm3
-; CHECK-NEXT: ucomiss %xmm3, %xmm0
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: jae .LBB0_1
-; CHECK-NEXT: # %bb.2: # %entry
-; CHECK-NEXT: addsd %xmm2, %xmm0
-; CHECK-NEXT: jmp .LBB0_3
-; CHECK-NEXT: .LBB0_1:
-; CHECK-NEXT: addsd %xmm0, %xmm1
-; CHECK-NEXT: movapd %xmm1, %xmm0
-; CHECK-NEXT: movapd %xmm1, %xmm2
-; CHECK-NEXT: .LBB0_3: # %entry
-; CHECK-NEXT: subsd %xmm1, %xmm0
-; CHECK-NEXT: addsd %xmm2, %xmm0
-; CHECK-NEXT: retq
entry:
%c1 = fcmp oge float %p1, 0.000000e+00
%d0 = fadd double %p2, 1.25e0
@@ -178,13 +161,13 @@ define double @foo6(float %p1, double %p2, double %p3) nounwind {
; CHECK-NEXT: # %bb.2: # %select.false
; CHECK-NEXT: addsd %xmm2, %xmm0
; CHECK-NEXT: .LBB5_3: # %select.end
-; CHECK-NEXT: ucomiss {{.*}}(%rip), %xmm3
+; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-NEXT: movapd %xmm0, %xmm4
; CHECK-NEXT: jae .LBB5_5
; CHECK-NEXT: # %bb.4: # %select.false2
; CHECK-NEXT: movapd %xmm1, %xmm4
; CHECK-NEXT: .LBB5_5: # %select.end1
-; CHECK-NEXT: ucomiss {{.*}}(%rip), %xmm3
+; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-NEXT: movapd %xmm4, %xmm1
; CHECK-NEXT: jae .LBB5_7
; CHECK-NEXT: # %bb.6: # %select.false4
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 3cc9120c90480..f53b06eff0559 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -77,10 +77,10 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
; CHECK-NEXT: callq _memset
; CHECK-NEXT: LBB0_8: ## %while.body.preheader
; CHECK-NEXT: imulq $1040, %rbx, %rax ## imm = 0x410
-; CHECK-NEXT: movq _syBuf@{{.*}}(%rip), %rcx
+; CHECK-NEXT: movq _syBuf at GOTPCREL(%rip), %rcx
; CHECK-NEXT: leaq 8(%rcx,%rax), %rdx
; CHECK-NEXT: movl $1, %r15d
-; CHECK-NEXT: movq _syCTRO@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _syCTRO at GOTPCREL(%rip), %rax
; CHECK-NEXT: movb $1, %cl
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_9: ## %do.body
@@ -96,8 +96,8 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
; CHECK-NEXT: jne LBB0_11
; CHECK-NEXT: ## %bb.12: ## %while.body200.preheader
; CHECK-NEXT: xorl %r12d, %r12d
-; CHECK-NEXT: leaq {{.*}}(%rip), %rdx
-; CHECK-NEXT: leaq {{.*}}(%rip), %rbx
+; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx
+; CHECK-NEXT: leaq LJTI0_1(%rip), %rbx
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: xorl %r14d, %r14d
; CHECK-NEXT: jmp LBB0_13
@@ -223,7 +223,7 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
; CHECK-NEXT: je LBB0_38
; CHECK-NEXT: ## %bb.37: ## %if.then532
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: movq _SyFgets.yank@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _SyFgets.yank at GOTPCREL(%rip), %rax
; CHECK-NEXT: movb $0, (%rax)
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_38: ## %for.cond534
@@ -236,7 +236,7 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
; CHECK-NEXT: testb %r12b, %r12b
; CHECK-NEXT: movb $0, (%rbp)
; CHECK-NEXT: movl %r13d, %r14d
-; CHECK-NEXT: leaq {{.*}}(%rip), %rdx
+; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx
; CHECK-NEXT: jmp LBB0_21
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_42: ## %while.cond864
@@ -268,7 +268,7 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
; CHECK-NEXT: movl $1, %edx
; CHECK-NEXT: callq _write
; CHECK-NEXT: subq %rbp, %rbx
-; CHECK-NEXT: movq _syHistory@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _syHistory at GOTPCREL(%rip), %rax
; CHECK-NEXT: leaq 8189(%rbx,%rax), %rax
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_49: ## %for.body1723
diff --git a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
index ae520e4ebd8e4..376cf86f0695a 100644
--- a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
+++ b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
@@ -39,15 +39,15 @@ define dso_local i32 @test() nounwind uwtable ssp {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movq {{.*}}(%rip), %rsi
+; CHECK-NEXT: movq c(%rip), %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: decq %rsi
-; CHECK-NEXT: movq %rsi, {{.*}}(%rip)
+; CHECK-NEXT: movq %rsi, c(%rip)
; CHECK-NEXT: setne %al
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, a(%rip)
; CHECK-NEXT: movl $.L.str, %edi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq printf
+; CHECK-NEXT: callq printf at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -68,15 +68,15 @@ define dso_local i32 @test2() nounwind uwtable ssp {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movq {{.*}}(%rip), %rsi
+; CHECK-NEXT: movq c(%rip), %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addq $-1, %rsi
; CHECK-NEXT: setb %al
-; CHECK-NEXT: movq %rsi, {{.*}}(%rip)
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movq %rsi, c(%rip)
+; CHECK-NEXT: movl %eax, a(%rip)
; CHECK-NEXT: movl $.L.str, %edi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq printf
+; CHECK-NEXT: callq printf at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -231,7 +231,7 @@ return:
define dso_local void @test3() nounwind ssp {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq foo(%rip), %rax
; CHECK-NEXT: decq 16(%rax)
; CHECK-NEXT: je .LBB5_2
; CHECK-NEXT: # %bb.1: # %if.end
@@ -269,12 +269,12 @@ define dso_local void @test4() nounwind uwtable ssp {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: decl {{.*}}(%rip)
+; CHECK-NEXT: decl y(%rip)
; CHECK-NEXT: je .LBB6_2
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl x(%rip), %eax
; CHECK-NEXT: .LBB6_2: # %entry
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, z(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i32, i32* @x, align 4
diff --git a/llvm/test/CodeGen/X86/recip-fastmath2.ll b/llvm/test/CodeGen/X86/recip-fastmath2.ll
index 370ec157a4a1f..00fb23cc05812 100644
--- a/llvm/test/CodeGen/X86/recip-fastmath2.ll
+++ b/llvm/test/CodeGen/X86/recip-fastmath2.ll
@@ -16,13 +16,13 @@ define float @f32_no_step_2(float %x) #3 {
; SSE-LABEL: f32_no_step_2:
; SSE: # %bb.0:
; SSE-NEXT: rcpss %xmm0, %xmm0
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: f32_no_step_2:
; AVX: # %bb.0:
; AVX-NEXT: vrcpss %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%div = fdiv fast float 1234.0, %x
ret float %div
@@ -147,7 +147,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; AVX-RECIP-NEXT: vsubss %xmm0, %xmm2, %xmm0
; AVX-RECIP-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX-RECIP-NEXT: vaddss %xmm0, %xmm1, %xmm0
-; AVX-RECIP-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; AVX-RECIP-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-RECIP-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX-RECIP-NEXT: retq
;
@@ -156,7 +156,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; FMA-RECIP-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; FMA-RECIP-NEXT: vfmsub213ss {{.*#+}} xmm0 = (xmm1 * xmm0) - mem
; FMA-RECIP-NEXT: vfnmadd132ss {{.*#+}} xmm0 = -(xmm0 * xmm1) + xmm1
-; FMA-RECIP-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; FMA-RECIP-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; FMA-RECIP-NEXT: vmulss %xmm0, %xmm1, %xmm0
; FMA-RECIP-NEXT: retq
;
@@ -165,7 +165,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; BDVER2-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; BDVER2-NEXT: vfmsubss {{.*#+}} xmm0 = (xmm0 * xmm1) - mem
; BDVER2-NEXT: vfnmaddss {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm1
-; BDVER2-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; BDVER2-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; BDVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BDVER2-NEXT: retq
;
@@ -177,7 +177,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; BTVER2-NEXT: vsubss %xmm0, %xmm2, %xmm0
; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddss %xmm0, %xmm1, %xmm0
-; BTVER2-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; BTVER2-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq
;
@@ -189,7 +189,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddss %xmm0, %xmm1, %xmm0
-; SANDY-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; SANDY-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq
;
@@ -198,7 +198,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; HASWELL-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; HASWELL-NEXT: vfmsub213ss {{.*#+}} xmm0 = (xmm1 * xmm0) - mem
; HASWELL-NEXT: vfnmadd132ss {{.*#+}} xmm0 = -(xmm0 * xmm1) + xmm1
-; HASWELL-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; HASWELL-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; HASWELL-NEXT: vmulss %xmm0, %xmm1, %xmm0
; HASWELL-NEXT: retq
;
@@ -210,7 +210,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; HASWELL-NO-FMA-NEXT: vsubss %xmm0, %xmm2, %xmm0
; HASWELL-NO-FMA-NEXT: vmulss %xmm0, %xmm1, %xmm0
; HASWELL-NO-FMA-NEXT: vaddss %xmm0, %xmm1, %xmm0
-; HASWELL-NO-FMA-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; HASWELL-NO-FMA-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; HASWELL-NO-FMA-NEXT: vmulss %xmm0, %xmm1, %xmm0
; HASWELL-NO-FMA-NEXT: retq
;
@@ -219,7 +219,7 @@ define float @f32_one_step_2_divs(float %x) #1 {
; AVX512-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vfmsub213ss {{.*#+}} xmm0 = (xmm1 * xmm0) - mem
; AVX512-NEXT: vfnmadd132ss {{.*#+}} xmm0 = -(xmm0 * xmm1) + xmm1
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX512-NEXT: retq
%div = fdiv fast float 3456.0, %x
@@ -480,7 +480,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; AVX-RECIP-NEXT: vsubps %xmm0, %xmm2, %xmm0
; AVX-RECIP-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX-RECIP-NEXT: vaddps %xmm0, %xmm1, %xmm0
-; AVX-RECIP-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
+; AVX-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-RECIP-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX-RECIP-NEXT: retq
;
@@ -489,7 +489,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; FMA-RECIP-NEXT: vrcpps %xmm0, %xmm1
; FMA-RECIP-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - mem
; FMA-RECIP-NEXT: vfnmadd132ps {{.*#+}} xmm0 = -(xmm0 * xmm1) + xmm1
-; FMA-RECIP-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
+; FMA-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; FMA-RECIP-NEXT: vmulps %xmm0, %xmm1, %xmm0
; FMA-RECIP-NEXT: retq
;
@@ -498,7 +498,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; BDVER2-NEXT: vrcpps %xmm0, %xmm1
; BDVER2-NEXT: vfmsubps {{.*#+}} xmm0 = (xmm0 * xmm1) - mem
; BDVER2-NEXT: vfnmaddps {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm1
-; BDVER2-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
+; BDVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; BDVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BDVER2-NEXT: retq
;
@@ -510,7 +510,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; BTVER2-NEXT: vsubps %xmm0, %xmm2, %xmm0
; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0
-; BTVER2-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
+; BTVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq
;
@@ -522,7 +522,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddps %xmm0, %xmm1, %xmm0
-; SANDY-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
+; SANDY-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq
;
@@ -532,7 +532,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; HASWELL-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; HASWELL-NEXT: vfmsub231ps {{.*#+}} xmm2 = (xmm1 * xmm0) - xmm2
; HASWELL-NEXT: vfnmadd132ps {{.*#+}} xmm2 = -(xmm2 * xmm1) + xmm1
-; HASWELL-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm0
+; HASWELL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; HASWELL-NEXT: vmulps %xmm2, %xmm0, %xmm0
; HASWELL-NEXT: retq
;
@@ -544,7 +544,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; HASWELL-NO-FMA-NEXT: vsubps %xmm0, %xmm2, %xmm0
; HASWELL-NO-FMA-NEXT: vmulps %xmm0, %xmm1, %xmm0
; HASWELL-NO-FMA-NEXT: vaddps %xmm0, %xmm1, %xmm0
-; HASWELL-NO-FMA-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
+; HASWELL-NO-FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; HASWELL-NO-FMA-NEXT: vmulps %xmm0, %xmm1, %xmm0
; HASWELL-NO-FMA-NEXT: retq
;
@@ -554,7 +554,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; KNL-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; KNL-NEXT: vfmsub231ps {{.*#+}} xmm2 = (xmm1 * xmm0) - xmm2
; KNL-NEXT: vfnmadd132ps {{.*#+}} xmm2 = -(xmm2 * xmm1) + xmm1
-; KNL-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm0
+; KNL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; KNL-NEXT: vmulps %xmm2, %xmm0, %xmm0
; KNL-NEXT: retq
;
@@ -563,7 +563,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
; SKX-NEXT: vrcpps %xmm0, %xmm1
; SKX-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - mem
; SKX-NEXT: vfnmadd132ps {{.*#+}} xmm0 = -(xmm0 * xmm1) + xmm1
-; SKX-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
+; SKX-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; SKX-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SKX-NEXT: retq
%div = fdiv fast <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, %x
@@ -842,7 +842,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; AVX-RECIP-NEXT: vsubps %ymm0, %ymm2, %ymm0
; AVX-RECIP-NEXT: vmulps %ymm0, %ymm1, %ymm0
; AVX-RECIP-NEXT: vaddps %ymm0, %ymm1, %ymm0
-; AVX-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
+; AVX-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX-RECIP-NEXT: vmulps %ymm0, %ymm1, %ymm0
; AVX-RECIP-NEXT: retq
;
@@ -851,7 +851,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; FMA-RECIP-NEXT: vrcpps %ymm0, %ymm1
; FMA-RECIP-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) - mem
; FMA-RECIP-NEXT: vfnmadd132ps {{.*#+}} ymm0 = -(ymm0 * ymm1) + ymm1
-; FMA-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
+; FMA-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; FMA-RECIP-NEXT: vmulps %ymm0, %ymm1, %ymm0
; FMA-RECIP-NEXT: retq
;
@@ -860,7 +860,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; BDVER2-NEXT: vrcpps %ymm0, %ymm1
; BDVER2-NEXT: vfmsubps {{.*#+}} ymm0 = (ymm0 * ymm1) - mem
; BDVER2-NEXT: vfnmaddps {{.*#+}} ymm0 = -(ymm1 * ymm0) + ymm1
-; BDVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
+; BDVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; BDVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
; BDVER2-NEXT: retq
;
@@ -872,7 +872,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; BTVER2-NEXT: vsubps %ymm0, %ymm2, %ymm0
; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0
-; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
+; BTVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: retq
;
@@ -884,7 +884,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; SANDY-NEXT: vsubps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0
-; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
+; SANDY-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: retq
;
@@ -894,7 +894,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; HASWELL-NEXT: vfmsub231ps {{.*#+}} ymm2 = (ymm1 * ymm0) - ymm2
; HASWELL-NEXT: vfnmadd132ps {{.*#+}} ymm2 = -(ymm2 * ymm1) + ymm1
-; HASWELL-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm0
+; HASWELL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0
; HASWELL-NEXT: vmulps %ymm2, %ymm0, %ymm0
; HASWELL-NEXT: retq
;
@@ -906,7 +906,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; HASWELL-NO-FMA-NEXT: vsubps %ymm0, %ymm2, %ymm0
; HASWELL-NO-FMA-NEXT: vmulps %ymm0, %ymm1, %ymm0
; HASWELL-NO-FMA-NEXT: vaddps %ymm0, %ymm1, %ymm0
-; HASWELL-NO-FMA-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
+; HASWELL-NO-FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; HASWELL-NO-FMA-NEXT: vmulps %ymm0, %ymm1, %ymm0
; HASWELL-NO-FMA-NEXT: retq
;
@@ -916,7 +916,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; KNL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; KNL-NEXT: vfmsub231ps {{.*#+}} ymm2 = (ymm1 * ymm0) - ymm2
; KNL-NEXT: vfnmadd132ps {{.*#+}} ymm2 = -(ymm2 * ymm1) + ymm1
-; KNL-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm0
+; KNL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0
; KNL-NEXT: vmulps %ymm2, %ymm0, %ymm0
; KNL-NEXT: retq
;
@@ -925,7 +925,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
; SKX-NEXT: vrcpps %ymm0, %ymm1
; SKX-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) - mem
; SKX-NEXT: vfnmadd132ps {{.*#+}} ymm0 = -(ymm0 * ymm1) + ymm1
-; SKX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
+; SKX-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; SKX-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SKX-NEXT: retq
%div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
@@ -1101,15 +1101,15 @@ define <8 x float> @v8f32_no_step2(<8 x float> %x) #3 {
; SSE-LABEL: v8f32_no_step2:
; SSE: # %bb.0:
; SSE-NEXT: rcpps %xmm0, %xmm0
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: rcpps %xmm1, %xmm1
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm1
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: v8f32_no_step2:
; AVX: # %bb.0:
; AVX-NEXT: vrcpps %ymm0, %ymm0
-; AVX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq
%div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
ret <8 x float> %div
@@ -1336,8 +1336,8 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; AVX-RECIP-NEXT: vsubps %ymm1, %ymm3, %ymm1
; AVX-RECIP-NEXT: vmulps %ymm1, %ymm2, %ymm1
; AVX-RECIP-NEXT: vaddps %ymm1, %ymm2, %ymm1
-; AVX-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
-; AVX-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
+; AVX-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
+; AVX-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; AVX-RECIP-NEXT: vmulps %ymm0, %ymm3, %ymm0
; AVX-RECIP-NEXT: vmulps %ymm1, %ymm2, %ymm1
; AVX-RECIP-NEXT: retq
@@ -1351,8 +1351,8 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; FMA-RECIP-NEXT: vrcpps %ymm1, %ymm2
; FMA-RECIP-NEXT: vfmsub213ps {{.*#+}} ymm1 = (ymm2 * ymm1) - ymm3
; FMA-RECIP-NEXT: vfnmadd132ps {{.*#+}} ymm1 = -(ymm1 * ymm2) + ymm2
-; FMA-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
-; FMA-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
+; FMA-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
+; FMA-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; FMA-RECIP-NEXT: vmulps %ymm0, %ymm3, %ymm0
; FMA-RECIP-NEXT: vmulps %ymm1, %ymm2, %ymm1
; FMA-RECIP-NEXT: retq
@@ -1365,9 +1365,9 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; BDVER2-NEXT: vfnmaddps {{.*#+}} ymm0 = -(ymm2 * ymm0) + ymm2
; BDVER2-NEXT: vrcpps %ymm1, %ymm2
; BDVER2-NEXT: vfmsubps {{.*#+}} ymm1 = (ymm1 * ymm2) - ymm3
-; BDVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
+; BDVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; BDVER2-NEXT: vfnmaddps {{.*#+}} ymm1 = -(ymm2 * ymm1) + ymm2
-; BDVER2-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
+; BDVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
; BDVER2-NEXT: vmulps %ymm0, %ymm3, %ymm0
; BDVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
; BDVER2-NEXT: retq
@@ -1383,10 +1383,10 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; BTVER2-NEXT: vrcpps %ymm1, %ymm2
; BTVER2-NEXT: vmulps %ymm2, %ymm1, %ymm1
; BTVER2-NEXT: vsubps %ymm1, %ymm3, %ymm1
-; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
+; BTVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
; BTVER2-NEXT: vaddps %ymm1, %ymm2, %ymm1
-; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
+; BTVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
; BTVER2-NEXT: vmulps %ymm0, %ymm3, %ymm0
; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
; BTVER2-NEXT: retq
@@ -1404,8 +1404,8 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; SANDY-NEXT: vsubps %ymm1, %ymm3, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm4, %ymm1
; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1
-; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
-; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
+; SANDY-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
+; SANDY-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; SANDY-NEXT: vmulps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: vmulps %ymm1, %ymm2, %ymm1
; SANDY-NEXT: retq
@@ -1419,8 +1419,8 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; HASWELL-NEXT: vrcpps %ymm1, %ymm2
; HASWELL-NEXT: vfmsub213ps {{.*#+}} ymm1 = (ymm2 * ymm1) - ymm3
; HASWELL-NEXT: vfnmadd132ps {{.*#+}} ymm1 = -(ymm1 * ymm2) + ymm2
-; HASWELL-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
-; HASWELL-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
+; HASWELL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
+; HASWELL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; HASWELL-NEXT: vmulps %ymm0, %ymm3, %ymm0
; HASWELL-NEXT: vmulps %ymm1, %ymm2, %ymm1
; HASWELL-NEXT: retq
@@ -1438,8 +1438,8 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; HASWELL-NO-FMA-NEXT: vsubps %ymm1, %ymm3, %ymm1
; HASWELL-NO-FMA-NEXT: vmulps %ymm1, %ymm4, %ymm1
; HASWELL-NO-FMA-NEXT: vaddps %ymm1, %ymm4, %ymm1
-; HASWELL-NO-FMA-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
-; HASWELL-NO-FMA-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
+; HASWELL-NO-FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
+; HASWELL-NO-FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; HASWELL-NO-FMA-NEXT: vmulps %ymm0, %ymm3, %ymm0
; HASWELL-NO-FMA-NEXT: vmulps %ymm1, %ymm2, %ymm1
; HASWELL-NO-FMA-NEXT: retq
@@ -1449,7 +1449,7 @@ define <16 x float> @v16f32_one_step_2_divs(<16 x float> %x) #1 {
; AVX512-NEXT: vrcp14ps %zmm0, %zmm1
; AVX512-NEXT: vfmsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) - mem
; AVX512-NEXT: vfnmadd132ps {{.*#+}} zmm0 = -(zmm0 * zmm1) + zmm1
-; AVX512-NEXT: vmulps {{.*}}(%rip), %zmm0, %zmm1
+; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
; AVX512-NEXT: vmulps %zmm0, %zmm1, %zmm0
; AVX512-NEXT: retq
%div = fdiv fast <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, %x
@@ -1767,75 +1767,75 @@ define <16 x float> @v16f32_no_step2(<16 x float> %x) #3 {
; SSE-LABEL: v16f32_no_step2:
; SSE: # %bb.0:
; SSE-NEXT: rcpps %xmm0, %xmm0
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: rcpps %xmm1, %xmm1
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm1
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: rcpps %xmm2, %xmm2
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm2
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: rcpps %xmm3, %xmm3
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm3
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE-NEXT: retq
;
; AVX-RECIP-LABEL: v16f32_no_step2:
; AVX-RECIP: # %bb.0:
; AVX-RECIP-NEXT: vrcpps %ymm0, %ymm0
-; AVX-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-RECIP-NEXT: vrcpps %ymm1, %ymm1
-; AVX-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; AVX-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX-RECIP-NEXT: retq
;
; FMA-RECIP-LABEL: v16f32_no_step2:
; FMA-RECIP: # %bb.0:
; FMA-RECIP-NEXT: vrcpps %ymm0, %ymm0
-; FMA-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
+; FMA-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; FMA-RECIP-NEXT: vrcpps %ymm1, %ymm1
-; FMA-RECIP-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; FMA-RECIP-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; FMA-RECIP-NEXT: retq
;
; BDVER2-LABEL: v16f32_no_step2:
; BDVER2: # %bb.0:
; BDVER2-NEXT: vrcpps %ymm0, %ymm0
; BDVER2-NEXT: vrcpps %ymm1, %ymm1
-; BDVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
-; BDVER2-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; BDVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; BDVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; BDVER2-NEXT: retq
;
; BTVER2-LABEL: v16f32_no_step2:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vrcpps %ymm0, %ymm0
; BTVER2-NEXT: vrcpps %ymm1, %ymm1
-; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
-; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; BTVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; BTVER2-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; BTVER2-NEXT: retq
;
; SANDY-LABEL: v16f32_no_step2:
; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm0
; SANDY-NEXT: vrcpps %ymm1, %ymm1
-; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
-; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; SANDY-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; SANDY-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; SANDY-NEXT: retq
;
; HASWELL-LABEL: v16f32_no_step2:
; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %ymm0, %ymm0
; HASWELL-NEXT: vrcpps %ymm1, %ymm1
-; HASWELL-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
-; HASWELL-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; HASWELL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; HASWELL-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; HASWELL-NEXT: retq
;
; HASWELL-NO-FMA-LABEL: v16f32_no_step2:
; HASWELL-NO-FMA: # %bb.0:
; HASWELL-NO-FMA-NEXT: vrcpps %ymm0, %ymm0
; HASWELL-NO-FMA-NEXT: vrcpps %ymm1, %ymm1
-; HASWELL-NO-FMA-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
-; HASWELL-NO-FMA-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; HASWELL-NO-FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; HASWELL-NO-FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; HASWELL-NO-FMA-NEXT: retq
;
; AVX512-LABEL: v16f32_no_step2:
; AVX512: # %bb.0:
; AVX512-NEXT: vrcp14ps %zmm0, %zmm0
-; AVX512-NEXT: vmulps {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%div = fdiv fast <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, %x
ret <16 x float> %div
diff --git a/llvm/test/CodeGen/X86/remat-constant.ll b/llvm/test/CodeGen/X86/remat-constant.ll
index ca56ac79268eb..ae4809723703a 100644
--- a/llvm/test/CodeGen/X86/remat-constant.ll
+++ b/llvm/test/CodeGen/X86/remat-constant.ll
@@ -11,11 +11,11 @@ define void @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
%f = load float, float* @a
diff --git a/llvm/test/CodeGen/X86/ret-mmx.ll b/llvm/test/CodeGen/X86/ret-mmx.ll
index 8c2ded4ebb362..42cdc56981136 100644
--- a/llvm/test/CodeGen/X86/ret-mmx.ll
+++ b/llvm/test/CodeGen/X86/ret-mmx.ll
@@ -9,7 +9,7 @@ define void @t1() nounwind {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq _return_v1di
-; CHECK-NEXT: movq _g_v1di@{{.*}}(%rip), %rcx
+; CHECK-NEXT: movq _g_v1di at GOTPCREL(%rip), %rcx
; CHECK-NEXT: movq %rax, (%rcx)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/reverse_branches.ll b/llvm/test/CodeGen/X86/reverse_branches.ll
index 7a9ff8452d1d2..9e95e5af76dfb 100644
--- a/llvm/test/CodeGen/X86/reverse_branches.ll
+++ b/llvm/test/CodeGen/X86/reverse_branches.ll
@@ -30,7 +30,7 @@ define i32 @test_branches_order() uwtable ssp {
; CHECK-NEXT: .cfi_offset %r14, -32
; CHECK-NEXT: .cfi_offset %r15, -24
; CHECK-NEXT: .cfi_offset %rbp, -16
-; CHECK-NEXT: movq ___stack_chk_guard@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq ___stack_chk_guard at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %r12d, %r12d
@@ -70,7 +70,7 @@ define i32 @test_branches_order() uwtable ssp {
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: jmp LBB0_5
; CHECK-NEXT: LBB0_7: ## %for.end11
-; CHECK-NEXT: leaq {{.*}}(%rip), %rdi
+; CHECK-NEXT: leaq L_.str2(%rip), %rdi
; CHECK-NEXT: callq _puts
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movq %rsp, %rcx
@@ -121,14 +121,14 @@ define i32 @test_branches_order() uwtable ssp {
; CHECK-NEXT: incq %rbp
; CHECK-NEXT: jne LBB0_12
; CHECK-NEXT: LBB0_5: ## %if.then
-; CHECK-NEXT: leaq {{.*}}(%rip), %rdi
+; CHECK-NEXT: leaq L_str4(%rip), %rdi
; CHECK-NEXT: callq _puts
; CHECK-NEXT: movl $1, %edi
; CHECK-NEXT: callq _exit
; CHECK-NEXT: LBB0_16: ## %for.end40
-; CHECK-NEXT: leaq {{.*}}(%rip), %rdi
+; CHECK-NEXT: leaq L_.str3(%rip), %rdi
; CHECK-NEXT: callq _puts
-; CHECK-NEXT: movq ___stack_chk_guard@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq ___stack_chk_guard at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: jne LBB0_18
diff --git a/llvm/test/CodeGen/X86/rotate_vec.ll b/llvm/test/CodeGen/X86/rotate_vec.ll
index fbaf2d0f09141..7e4e8515f0b3b 100644
--- a/llvm/test/CodeGen/X86/rotate_vec.ll
+++ b/llvm/test/CodeGen/X86/rotate_vec.ll
@@ -22,12 +22,12 @@ define <4 x i32> @rot_v4i32_splat(<4 x i32> %x) {
define <4 x i32> @rot_v4i32_non_splat(<4 x i32> %x) {
; XOP-LABEL: rot_v4i32_non_splat:
; XOP: # %bb.0:
-; XOP-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
;
; AVX512-LABEL: rot_v4i32_non_splat:
; AVX512: # %bb.0:
-; AVX512-NEXT: vprolvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
%2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
@@ -39,13 +39,13 @@ define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) {
; XOP-LABEL: rot_v4i32_splat_2masks:
; XOP: # %bb.0:
; XOP-NEXT: vprotd $31, %xmm0, %xmm0
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
;
; AVX512-LABEL: rot_v4i32_splat_2masks:
; AVX512: # %bb.0:
; AVX512-NEXT: vprold $31, %xmm0, %xmm0
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
%2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
@@ -59,14 +59,14 @@ define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) {
define <4 x i32> @rot_v4i32_non_splat_2masks(<4 x i32> %x) {
; XOP-LABEL: rot_v4i32_non_splat_2masks:
; XOP: # %bb.0:
-; XOP-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
;
; AVX512-LABEL: rot_v4i32_non_splat_2masks:
; AVX512: # %bb.0:
-; AVX512-NEXT: vprolvd {{.*}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
%2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
@@ -110,23 +110,23 @@ define <4 x i32> @rot_v4i32_allsignbits(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @rot_v4i32_mask_ashr0(<4 x i32> %a0) {
; XOPAVX1-LABEL: rot_v4i32_mask_ashr0:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: vpshad {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX1-NEXT: vpshad {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX1-NEXT: vprotd $1, %xmm0, %xmm0
-; XOPAVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: rot_v4i32_mask_ashr0:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX2-NEXT: vprotd $1, %xmm0, %xmm0
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX2-NEXT: retq
;
; AVX512-LABEL: rot_v4i32_mask_ashr0:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vprold $1, %xmm0, %xmm0
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 28>
%2 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %1, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
@@ -141,7 +141,7 @@ define <4 x i32> @rot_v4i32_mask_ashr1(<4 x i32> %a0) {
; XOPAVX1-NEXT: vpsrad $25, %xmm0, %xmm0
; XOPAVX1-NEXT: vprotd $1, %xmm0, %xmm0
; XOPAVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; XOPAVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: rot_v4i32_mask_ashr1:
@@ -149,7 +149,7 @@ define <4 x i32> @rot_v4i32_mask_ashr1(<4 x i32> %a0) {
; XOPAVX2-NEXT: vpsrad $25, %xmm0, %xmm0
; XOPAVX2-NEXT: vprotd $1, %xmm0, %xmm0
; XOPAVX2-NEXT: vpbroadcastd %xmm0, %xmm0
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX2-NEXT: retq
;
; AVX512-LABEL: rot_v4i32_mask_ashr1:
@@ -157,7 +157,7 @@ define <4 x i32> @rot_v4i32_mask_ashr1(<4 x i32> %a0) {
; AVX512-NEXT: vpsrad $25, %xmm0, %xmm0
; AVX512-NEXT: vprold $1, %xmm0, %xmm0
; AVX512-NEXT: vpbroadcastd %xmm0, %xmm0
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 28>
%2 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %1, <4 x i32> %1, <4 x i32> <i32 1, i32 2, i32 3, i32 4>)
diff --git a/llvm/test/CodeGen/X86/rtm.ll b/llvm/test/CodeGen/X86/rtm.ll
index ed964409f710a..265e3bc0a6b9b 100644
--- a/llvm/test/CodeGen/X86/rtm.ll
+++ b/llvm/test/CodeGen/X86/rtm.ll
@@ -13,8 +13,9 @@ define i32 @test_xbegin() nounwind uwtable {
; X86-NEXT: xbegin .LBB0_2
; X86-NEXT: # %bb.1: # %entry
; X86-NEXT: movl $-1, %eax
-; X86: .LBB0_2: # %entry
-; X86-NEXT: # XABORT DEF
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_2: # %entry
+; X86-NEXT: # XABORT DEF
; X86-NEXT: retl
;
; X64-LABEL: test_xbegin:
@@ -22,8 +23,9 @@ define i32 @test_xbegin() nounwind uwtable {
; X64-NEXT: xbegin .LBB0_2
; X64-NEXT: # %bb.1: # %entry
; X64-NEXT: movl $-1, %eax
-; X64: .LBB0_2: # %entry
-; X64-NEXT: # XABORT DEF
+; X64-NEXT: retq
+; X64-NEXT: .LBB0_2: # %entry
+; X64-NEXT: # XABORT DEF
; X64-NEXT: retq
entry:
%0 = tail call i32 @llvm.x86.xbegin() nounwind
@@ -64,7 +66,7 @@ define void @f2(i32 %x) nounwind uwtable {
; X86-LABEL: f2:
; X86: # %bb.0: # %entry
; X86-NEXT: xabort $1
-; X86-NEXT: calll f1
+; X86-NEXT: calll f1 at PLT
; X86-NEXT: retl
;
; X64-LABEL: f2:
@@ -73,7 +75,7 @@ define void @f2(i32 %x) nounwind uwtable {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; X64-NEXT: xabort $1
-; X64-NEXT: callq f1
+; X64-NEXT: callq f1 at PLT
; X64-NEXT: popq %rax
; X64-NEXT: .cfi_def_cfa_offset 8
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/sad.ll b/llvm/test/CodeGen/X86/sad.ll
index bf04403694e16..4e537368799f0 100644
--- a/llvm/test/CodeGen/X86/sad.ll
+++ b/llvm/test/CodeGen/X86/sad.ll
@@ -986,7 +986,7 @@ define dso_local i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %ar
; SSE2-NEXT: movdqu (%rcx), %xmm2
; SSE2-NEXT: psadbw %xmm0, %xmm2
; SSE2-NEXT: paddd %xmm1, %xmm2
-; SSE2-NEXT: paddd {{.*}}(%rip), %xmm2
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
; SSE2-NEXT: paddd %xmm2, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
@@ -1001,7 +1001,7 @@ define dso_local i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %ar
; AVX-NEXT: vmovdqu (%rdx), %xmm1
; AVX-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
diff --git a/llvm/test/CodeGen/X86/sadd_sat.ll b/llvm/test/CodeGen/X86/sadd_sat.ll
index 5674511d3a4ab..6f16bd15c0e74 100644
--- a/llvm/test/CodeGen/X86/sadd_sat.ll
+++ b/llvm/test/CodeGen/X86/sadd_sat.ll
@@ -236,7 +236,7 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: pcmpgtd %xmm1, %xmm0
; X64-NEXT: pxor %xmm3, %xmm0
; X64-NEXT: movdqa %xmm1, %xmm3
-; X64-NEXT: pandn {{.*}}(%rip), %xmm3
+; X64-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; X64-NEXT: pcmpgtd %xmm1, %xmm2
; X64-NEXT: psrld $1, %xmm2
; X64-NEXT: por %xmm3, %xmm2
diff --git a/llvm/test/CodeGen/X86/sadd_sat_vec.ll b/llvm/test/CodeGen/X86/sadd_sat_vec.ll
index 2a913393b094d..cc1d94c9c4870 100644
--- a/llvm/test/CodeGen/X86/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/X86/sadd_sat_vec.ll
@@ -510,7 +510,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; SSE-NEXT: pand %xmm2, %xmm0
; SSE-NEXT: paddsb %xmm1, %xmm0
; SSE-NEXT: psrlw $4, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: psubb %xmm1, %xmm0
@@ -525,7 +525,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpaddsb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -540,7 +540,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpaddsb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -555,7 +555,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX512F-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX512F-NEXT: vpaddsb %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX512F-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -571,7 +571,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX512BW-NEXT: vpaddsb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
-; AVX512BW-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512BW-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: retq
%z = call <16 x i4> @llvm.sadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
@@ -604,7 +604,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm3
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: psrld $1, %xmm2
; SSE2-NEXT: por %xmm3, %xmm2
@@ -622,7 +622,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm0
; SSSE3-NEXT: movdqa %xmm1, %xmm3
-; SSSE3-NEXT: pandn {{.*}}(%rip), %xmm3
+; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
; SSSE3-NEXT: psrld $1, %xmm2
; SSSE3-NEXT: por %xmm3, %xmm2
@@ -638,7 +638,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; SSE41-NEXT: paddd %xmm1, %xmm3
; SSE41-NEXT: movaps {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm0
-; SSE41-NEXT: blendvps %xmm0, {{.*}}(%rip), %xmm4
+; SSE41-NEXT: blendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: pcmpgtd %xmm3, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
@@ -650,7 +650,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmovaps {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
-; AVX1-NEXT: vblendvps %xmm2, {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vblendvps %xmm0, %xmm3, %xmm2, %xmm0
@@ -687,7 +687,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtd %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vpbroadcastd {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648]
-; AVX512BW-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
@@ -705,7 +705,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm3
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: psrld $1, %xmm2
; SSE2-NEXT: por %xmm3, %xmm2
@@ -723,7 +723,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm0
; SSSE3-NEXT: movdqa %xmm1, %xmm3
-; SSSE3-NEXT: pandn {{.*}}(%rip), %xmm3
+; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
; SSSE3-NEXT: psrld $1, %xmm2
; SSSE3-NEXT: por %xmm3, %xmm2
@@ -739,7 +739,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE41-NEXT: paddd %xmm1, %xmm3
; SSE41-NEXT: movaps {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm0
-; SSE41-NEXT: blendvps %xmm0, {{.*}}(%rip), %xmm4
+; SSE41-NEXT: blendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: pcmpgtd %xmm3, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
@@ -751,7 +751,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmovaps {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
-; AVX1-NEXT: vblendvps %xmm2, {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vblendvps %xmm0, %xmm3, %xmm2, %xmm0
@@ -788,7 +788,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtd %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vpbroadcastd {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648]
-; AVX512BW-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
@@ -897,7 +897,7 @@ define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm4, %ymm5
; AVX1-NEXT: vmovaps {{.*#+}} ymm6 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX1-NEXT: vblendvps %ymm5, {{.*}}(%rip), %ymm6, %ymm6
+; AVX1-NEXT: vblendvps %ymm5, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6
; AVX1-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpcmpgtd %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
@@ -936,7 +936,7 @@ define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtd %ymm1, %ymm2, %k2
; AVX512BW-NEXT: vpbroadcastd {{.*#+}} ymm0 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX512BW-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k2}
; AVX512BW-NEXT: vmovdqa32 %ymm0, %ymm1 {%k1}
; AVX512BW-NEXT: vmovdqa %ymm1, %ymm0
; AVX512BW-NEXT: retq
@@ -1168,7 +1168,7 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
; AVX512-NEXT: kxorw %k1, %k0, %k1
; AVX512-NEXT: vpcmpgtd %zmm1, %zmm2, %k2
; AVX512-NEXT: vpbroadcastd {{.*#+}} zmm0 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX512-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k2}
+; AVX512-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k2}
; AVX512-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; AVX512-NEXT: vmovdqa64 %zmm1, %zmm0
; AVX512-NEXT: retq
@@ -1200,9 +1200,9 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: pandn %xmm0, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pcmpgtd %xmm3, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
@@ -1231,9 +1231,9 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSSE3-NEXT: movdqa %xmm4, %xmm1
; SSSE3-NEXT: pandn %xmm0, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; SSSE3-NEXT: pandn {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm2
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm2
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSSE3-NEXT: por %xmm2, %xmm0
; SSSE3-NEXT: pand %xmm4, %xmm0
; SSSE3-NEXT: por %xmm1, %xmm0
@@ -1256,7 +1256,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE41-NEXT: pxor %xmm1, %xmm3
; SSE41-NEXT: movapd {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; SSE41-NEXT: movdqa %xmm2, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, {{.*}}(%rip), %xmm1
+; SSE41-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm0
@@ -1266,7 +1266,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmovapd {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
-; AVX1-NEXT: vblendvpd %xmm2, {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vblendvpd %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vblendvpd %xmm0, %xmm3, %xmm2, %xmm0
@@ -1276,7 +1276,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm2
; AVX2-NEXT: vmovapd {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
-; AVX2-NEXT: vblendvpd %xmm2, {{.*}}(%rip), %xmm3, %xmm3
+; AVX2-NEXT: vblendvpd %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vblendvpd %xmm0, %xmm3, %xmm2, %xmm0
@@ -1286,7 +1286,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpaddq %xmm1, %xmm0, %xmm2
; AVX512F-NEXT: vmovapd {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
-; AVX512F-NEXT: vblendvpd %xmm2, {{.*}}(%rip), %xmm3, %xmm3
+; AVX512F-NEXT: vblendvpd %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512F-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0
; AVX512F-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: vblendvpd %xmm0, %xmm3, %xmm2, %xmm0
@@ -1301,7 +1301,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
-; AVX512BW-NEXT: vmovdqa64 {{.*}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
@@ -1478,7 +1478,7 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm4, %ymm5
; AVX1-NEXT: vmovapd {{.*#+}} ymm6 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX1-NEXT: vblendvpd %ymm5, {{.*}}(%rip), %ymm6, %ymm6
+; AVX1-NEXT: vblendvpd %ymm5, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
@@ -1517,7 +1517,7 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %ymm1, %ymm2, %k2
; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm0 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX512BW-NEXT: vpbroadcastq {{.*}}(%rip), %ymm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %ymm0, %ymm1 {%k1}
; AVX512BW-NEXT: vmovdqa %ymm1, %ymm0
; AVX512BW-NEXT: retq
@@ -1881,7 +1881,7 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; AVX512-NEXT: kxorw %k1, %k0, %k1
; AVX512-NEXT: vpcmpgtq %zmm1, %zmm2, %k2
; AVX512-NEXT: vpbroadcastq {{.*#+}} zmm0 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX512-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k2}
+; AVX512-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k2}
; AVX512-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; AVX512-NEXT: vmovdqa64 %zmm1, %zmm0
; AVX512-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/sandybridge-loads.ll b/llvm/test/CodeGen/X86/sandybridge-loads.ll
index 60043baa381cd..529fbc68cb1f4 100644
--- a/llvm/test/CodeGen/X86/sandybridge-loads.ll
+++ b/llvm/test/CodeGen/X86/sandybridge-loads.ll
@@ -11,7 +11,7 @@ define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi
; CHECK-NEXT: vmovaps (%rdx), %ymm2
; CHECK-NEXT: vcmpltps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rax)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/sar_fold64.ll b/llvm/test/CodeGen/X86/sar_fold64.ll
index f597efc99b7de..4165da9171f6a 100644
--- a/llvm/test/CodeGen/X86/sar_fold64.ll
+++ b/llvm/test/CodeGen/X86/sar_fold64.ll
@@ -72,7 +72,7 @@ define i8 @all_sign_bit_ashr(i8 %x) {
define <4 x i32> @all_sign_bit_ashr_vec0(<4 x i32> %x) {
; SSE-LABEL: all_sign_bit_ashr_vec0:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: psubd %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
@@ -80,7 +80,7 @@ define <4 x i32> @all_sign_bit_ashr_vec0(<4 x i32> %x) {
;
; AVX1-LABEL: all_sign_bit_ashr_vec0:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
@@ -101,7 +101,7 @@ define <4 x i32> @all_sign_bit_ashr_vec0(<4 x i32> %x) {
define <4 x i32> @all_sign_bit_ashr_vec1(<4 x i32> %x) {
; SSE-LABEL: all_sign_bit_ashr_vec1:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,0,0]
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: psubd %xmm1, %xmm0
@@ -109,7 +109,7 @@ define <4 x i32> @all_sign_bit_ashr_vec1(<4 x i32> %x) {
;
; AVX1-LABEL: all_sign_bit_ashr_vec1:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
@@ -133,14 +133,14 @@ define <4 x i32> @all_sign_bit_ashr_vec1(<4 x i32> %x) {
define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) {
; SSE-LABEL: all_sign_bit_ashr_vec2:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: all_sign_bit_ashr_vec2:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -161,7 +161,7 @@ define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) {
define <4 x i32> @all_sign_bit_ashr_vec3(<4 x i32> %x) {
; SSE-LABEL: all_sign_bit_ashr_vec3:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,0,0]
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
; SSE-NEXT: paddd %xmm1, %xmm0
@@ -169,7 +169,7 @@ define <4 x i32> @all_sign_bit_ashr_vec3(<4 x i32> %x) {
;
; AVX1-LABEL: all_sign_bit_ashr_vec3:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/sat-add.ll b/llvm/test/CodeGen/X86/sat-add.ll
index 149f3cea0b7ec..8aeeff5939e4b 100644
--- a/llvm/test/CodeGen/X86/sat-add.ll
+++ b/llvm/test/CodeGen/X86/sat-add.ll
@@ -364,14 +364,14 @@ define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {
define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
; SSE-LABEL: unsigned_sat_constant_v16i8_using_min:
; SSE: # %bb.0:
-; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
-; SSE-NEXT: paddb {{.*}}(%rip), %xmm0
+; SSE-NEXT: pminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v16i8_using_min:
; AVX: # %bb.0:
-; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
@@ -382,12 +382,12 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
; SSE-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
; SSE: # %bb.0:
-; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
%c = icmp ugt <16 x i8> %x, %a
@@ -398,12 +398,12 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
; SSE-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
; SSE: # %bb.0:
-; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
%c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
@@ -415,21 +415,21 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
; SSE2-LABEL: unsigned_sat_constant_v8i16_using_min:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
-; SSE2-NEXT: psubusw {{.*}}(%rip), %xmm1
+; SSE2-NEXT: psubusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubw %xmm1, %xmm0
-; SSE2-NEXT: paddw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: unsigned_sat_constant_v8i16_using_min:
; SSE4: # %bb.0:
-; SSE4-NEXT: pminuw {{.*}}(%rip), %xmm0
-; SSE4-NEXT: paddw {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v8i16_using_min:
; AVX: # %bb.0:
-; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
@@ -440,12 +440,12 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
; SSE-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
; SSE: # %bb.0:
-; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
%c = icmp ugt <8 x i16> %x, %a
@@ -456,12 +456,12 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
; SSE-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
; SSE: # %bb.0:
-; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
%c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
@@ -477,15 +477,15 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483605,2147483605,2147483605,2147483605]
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: por %xmm2, %xmm0
-; SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_min:
; SSE4: # %bb.0:
-; SSE4-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: retq
;
; AVX2-LABEL: unsigned_sat_constant_v4i32_using_min:
@@ -498,8 +498,8 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v4i32_using_min:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; AVX512-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-NEXT: retq
%c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
%s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43>
@@ -521,8 +521,8 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
;
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
; SSE4: # %bb.0:
-; SSE4-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: retq
;
; AVX2-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
@@ -535,8 +535,8 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; AVX512-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
%c = icmp ugt <4 x i32> %x, %a
@@ -549,15 +549,15 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42]
; SSE2-NEXT: paddd %xmm0, %xmm1
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
; SSE4: # %bb.0:
-; SSE4-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: retq
;
; AVX2-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
@@ -570,8 +570,8 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; AVX512-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
%c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
@@ -584,21 +584,21 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat(<4 x i32
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [43,44,45,46]
; SSE2-NEXT: paddd %xmm0, %xmm1
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat:
; SSE4: # %bb.0:
-; SSE4-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat:
; AVX: # %bb.0:
-; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%a = add <4 x i32> %x, <i32 43, i32 44, i32 45, i32 46>
%c = icmp ugt <4 x i32> %x, <i32 -44, i32 -45, i32 -46, i32 -47>
@@ -621,9 +621,9 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm0
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: por %xmm2, %xmm0
-; SSE2-NEXT: paddq {{.*}}(%rip), %xmm0
+; SSE2-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: unsigned_sat_constant_v2i64_using_min:
@@ -640,7 +640,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
-; SSE41-NEXT: paddq {{.*}}(%rip), %xmm2
+; SSE41-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
@@ -653,24 +653,24 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775765,9223372036854775765]
; SSE42-NEXT: pcmpgtq %xmm3, %xmm0
; SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2
-; SSE42-NEXT: paddq {{.*}}(%rip), %xmm2
+; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE42-NEXT: movdqa %xmm2, %xmm0
; SSE42-NEXT: retq
;
; AVX2-LABEL: unsigned_sat_constant_v2i64_using_min:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovapd {{.*#+}} xmm1 = [18446744073709551573,18446744073709551573]
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm2
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775765,9223372036854775765]
; AVX2-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_min:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>
%s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>
@@ -720,7 +720,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; SSE42-NEXT: movdqa %xmm0, %xmm1
; SSE42-NEXT: pxor %xmm2, %xmm1
-; SSE42-NEXT: paddq {{.*}}(%rip), %xmm0
+; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE42-NEXT: pxor %xmm0, %xmm2
; SSE42-NEXT: pcmpgtq %xmm2, %xmm1
; SSE42-NEXT: por %xmm0, %xmm1
@@ -731,7 +731,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm2
-; AVX2-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm1
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
@@ -739,8 +739,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, %a
@@ -753,7 +753,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [42,42]
; SSE2-NEXT: paddq %xmm0, %xmm1
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372034707292117,9223372034707292117]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pcmpgtd %xmm2, %xmm3
@@ -770,7 +770,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [42,42]
; SSE41-NEXT: paddq %xmm0, %xmm1
-; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372034707292117,9223372034707292117]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: pcmpgtd %xmm2, %xmm3
@@ -788,7 +788,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; SSE42-NEXT: movdqa %xmm0, %xmm1
; SSE42-NEXT: pxor %xmm2, %xmm1
-; SSE42-NEXT: paddq {{.*}}(%rip), %xmm0
+; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE42-NEXT: pxor %xmm0, %xmm2
; SSE42-NEXT: pcmpgtq %xmm2, %xmm1
; SSE42-NEXT: por %xmm0, %xmm1
@@ -799,7 +799,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm2
-; AVX2-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm1
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
@@ -807,8 +807,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
@@ -965,8 +965,8 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: paddw %xmm1, %xmm2
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pcmpgtw %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq
@@ -1102,8 +1102,8 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: paddd %xmm1, %xmm2
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq
@@ -1210,8 +1210,8 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_min(<2 x i64> %x, <2 x i64>
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm3
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm4
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm4
; AVX2-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm3
; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
@@ -1304,8 +1304,8 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: paddq %xmm1, %xmm2
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pcmpgtd %xmm1, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
@@ -1321,8 +1321,8 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: paddq %xmm1, %xmm2
-; SSE41-NEXT: pxor {{.*}}(%rip), %xmm1
-; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: pcmpgtd %xmm1, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
@@ -1338,8 +1338,8 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
; SSE42: # %bb.0:
; SSE42-NEXT: movdqa %xmm0, %xmm2
; SSE42-NEXT: paddq %xmm1, %xmm2
-; SSE42-NEXT: pxor {{.*}}(%rip), %xmm1
-; SSE42-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE42-NEXT: pcmpgtq %xmm1, %xmm0
; SSE42-NEXT: por %xmm2, %xmm0
; SSE42-NEXT: retq
@@ -1347,8 +1347,8 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
; AVX2-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval:
; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm2
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX2-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/scalar-fp-to-i32.ll b/llvm/test/CodeGen/X86/scalar-fp-to-i32.ll
index 7d910031d0d89..99c158420dbef 100644
--- a/llvm/test/CodeGen/X86/scalar-fp-to-i32.ll
+++ b/llvm/test/CodeGen/X86/scalar-fp-to-i32.ll
@@ -724,7 +724,7 @@ define i32 @t_to_u32(fp128 %a) nounwind {
; X64-AVX512-LIN-LABEL: t_to_u32:
; X64-AVX512-LIN: # %bb.0:
; X64-AVX512-LIN-NEXT: pushq %rax
-; X64-AVX512-LIN-NEXT: callq __fixunstfsi
+; X64-AVX512-LIN-NEXT: callq __fixunstfsi at PLT
; X64-AVX512-LIN-NEXT: popq %rcx
; X64-AVX512-LIN-NEXT: retq
;
@@ -759,7 +759,7 @@ define i32 @t_to_u32(fp128 %a) nounwind {
; X64-SSE-LIN-LABEL: t_to_u32:
; X64-SSE-LIN: # %bb.0:
; X64-SSE-LIN-NEXT: pushq %rax
-; X64-SSE-LIN-NEXT: callq __fixunstfsi
+; X64-SSE-LIN-NEXT: callq __fixunstfsi at PLT
; X64-SSE-LIN-NEXT: popq %rcx
; X64-SSE-LIN-NEXT: retq
;
@@ -816,7 +816,7 @@ define i32 @t_to_s32(fp128 %a) nounwind {
; X64-AVX512-LIN-LABEL: t_to_s32:
; X64-AVX512-LIN: # %bb.0:
; X64-AVX512-LIN-NEXT: pushq %rax
-; X64-AVX512-LIN-NEXT: callq __fixtfsi
+; X64-AVX512-LIN-NEXT: callq __fixtfsi at PLT
; X64-AVX512-LIN-NEXT: popq %rcx
; X64-AVX512-LIN-NEXT: retq
;
@@ -851,7 +851,7 @@ define i32 @t_to_s32(fp128 %a) nounwind {
; X64-SSE-LIN-LABEL: t_to_s32:
; X64-SSE-LIN: # %bb.0:
; X64-SSE-LIN-NEXT: pushq %rax
-; X64-SSE-LIN-NEXT: callq __fixtfsi
+; X64-SSE-LIN-NEXT: callq __fixtfsi at PLT
; X64-SSE-LIN-NEXT: popq %rcx
; X64-SSE-LIN-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll b/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
index f4d08960be0a3..5bed83322fcb8 100644
--- a/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
+++ b/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
@@ -267,7 +267,7 @@ define i64 @f_to_u64(float %a) nounwind {
; X87-LIN: # %bb.0:
; X87-LIN-NEXT: subl $20, %esp
; X87-LIN-NEXT: flds {{[0-9]+}}(%esp)
-; X87-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-LIN-NEXT: fucom %st(1)
; X87-LIN-NEXT: fnstsw %ax
; X87-LIN-NEXT: xorl %edx, %edx
@@ -691,7 +691,7 @@ define i64 @d_to_u64(double %a) nounwind {
; X87-LIN: # %bb.0:
; X87-LIN-NEXT: subl $20, %esp
; X87-LIN-NEXT: fldl {{[0-9]+}}(%esp)
-; X87-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-LIN-NEXT: fucom %st(1)
; X87-LIN-NEXT: fnstsw %ax
; X87-LIN-NEXT: xorl %edx, %edx
@@ -914,7 +914,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X86-AVX512-LIN: # %bb.0:
; X86-AVX512-LIN-NEXT: subl $12, %esp
; X86-AVX512-LIN-NEXT: fldt {{[0-9]+}}(%esp)
-; X86-AVX512-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-AVX512-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-AVX512-LIN-NEXT: xorl %edx, %edx
; X86-AVX512-LIN-NEXT: fucomi %st(1), %st
; X86-AVX512-LIN-NEXT: fldz
@@ -933,7 +933,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X64-AVX512-WIN: # %bb.0:
; X64-AVX512-WIN-NEXT: pushq %rax
; X64-AVX512-WIN-NEXT: fldt (%rcx)
-; X64-AVX512-WIN-NEXT: flds __real@{{.*}}(%rip)
+; X64-AVX512-WIN-NEXT: flds __real at 5f000000(%rip)
; X64-AVX512-WIN-NEXT: xorl %eax, %eax
; X64-AVX512-WIN-NEXT: fucomi %st(1), %st
; X64-AVX512-WIN-NEXT: fldz
@@ -950,7 +950,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X64-AVX512-LIN-LABEL: x_to_u64:
; X64-AVX512-LIN: # %bb.0:
; X64-AVX512-LIN-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-AVX512-LIN-NEXT: flds {{.*}}(%rip)
+; X64-AVX512-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-AVX512-LIN-NEXT: xorl %eax, %eax
; X64-AVX512-LIN-NEXT: fucomi %st(1), %st
; X64-AVX512-LIN-NEXT: fldz
@@ -990,7 +990,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X86-SSE3-LIN: # %bb.0:
; X86-SSE3-LIN-NEXT: subl $12, %esp
; X86-SSE3-LIN-NEXT: fldt {{[0-9]+}}(%esp)
-; X86-SSE3-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE3-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE3-LIN-NEXT: xorl %edx, %edx
; X86-SSE3-LIN-NEXT: fucomi %st(1), %st
; X86-SSE3-LIN-NEXT: fldz
@@ -1009,7 +1009,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X64-SSE3-WIN: # %bb.0:
; X64-SSE3-WIN-NEXT: pushq %rax
; X64-SSE3-WIN-NEXT: fldt (%rcx)
-; X64-SSE3-WIN-NEXT: flds __real@{{.*}}(%rip)
+; X64-SSE3-WIN-NEXT: flds __real at 5f000000(%rip)
; X64-SSE3-WIN-NEXT: xorl %eax, %eax
; X64-SSE3-WIN-NEXT: fucomi %st(1), %st
; X64-SSE3-WIN-NEXT: fldz
@@ -1026,7 +1026,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X64-SSE3-LIN-LABEL: x_to_u64:
; X64-SSE3-LIN: # %bb.0:
; X64-SSE3-LIN-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-SSE3-LIN-NEXT: flds {{.*}}(%rip)
+; X64-SSE3-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-SSE3-LIN-NEXT: xorl %eax, %eax
; X64-SSE3-LIN-NEXT: fucomi %st(1), %st
; X64-SSE3-LIN-NEXT: fldz
@@ -1072,7 +1072,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X86-SSE2-LIN: # %bb.0:
; X86-SSE2-LIN-NEXT: subl $20, %esp
; X86-SSE2-LIN-NEXT: fldt {{[0-9]+}}(%esp)
-; X86-SSE2-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X86-SSE2-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE2-LIN-NEXT: xorl %edx, %edx
; X86-SSE2-LIN-NEXT: fucomi %st(1), %st
; X86-SSE2-LIN-NEXT: setbe %dl
@@ -1097,7 +1097,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X64-SSE2-WIN: # %bb.0:
; X64-SSE2-WIN-NEXT: subq $16, %rsp
; X64-SSE2-WIN-NEXT: fldt (%rcx)
-; X64-SSE2-WIN-NEXT: flds __real@{{.*}}(%rip)
+; X64-SSE2-WIN-NEXT: flds __real at 5f000000(%rip)
; X64-SSE2-WIN-NEXT: xorl %eax, %eax
; X64-SSE2-WIN-NEXT: fucomi %st(1), %st
; X64-SSE2-WIN-NEXT: setbe %al
@@ -1120,7 +1120,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X64-SSE2-LIN-LABEL: x_to_u64:
; X64-SSE2-LIN: # %bb.0:
; X64-SSE2-LIN-NEXT: fldt {{[0-9]+}}(%rsp)
-; X64-SSE2-LIN-NEXT: flds {{.*}}(%rip)
+; X64-SSE2-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-SSE2-LIN-NEXT: xorl %eax, %eax
; X64-SSE2-LIN-NEXT: fucomi %st(1), %st
; X64-SSE2-LIN-NEXT: setbe %al
@@ -1180,7 +1180,7 @@ define i64 @x_to_u64(x86_fp80 %a) nounwind {
; X87-LIN: # %bb.0:
; X87-LIN-NEXT: subl $20, %esp
; X87-LIN-NEXT: fldt {{[0-9]+}}(%esp)
-; X87-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; X87-LIN-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X87-LIN-NEXT: fucom %st(1)
; X87-LIN-NEXT: fnstsw %ax
; X87-LIN-NEXT: xorl %edx, %edx
diff --git a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
index eedf744f15925..979b440fc7a8b 100644
--- a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
@@ -33,8 +33,8 @@ define float @u32_to_f(i32 %a) nounwind {
; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %eax
; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2_32-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE2_32-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2_32-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2_32-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: cvtsd2ss %xmm0, %xmm0
; SSE2_32-NEXT: movss %xmm0, (%esp)
; SSE2_32-NEXT: flds (%esp)
@@ -147,8 +147,8 @@ define double @u32_to_d(i32 %a) nounwind {
; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2_32-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE2_32-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2_32-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2_32-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movsd %xmm0, (%esp)
; SSE2_32-NEXT: fldl (%esp)
; SSE2_32-NEXT: movl %ebp, %esp
@@ -333,7 +333,7 @@ define float @u64_to_f(i64 %a) nounwind {
; AVX512F_32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: shrl $31, %eax
; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX512F_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX512F_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX512F_32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512F_32-NEXT: vmovss %xmm0, (%esp)
@@ -353,7 +353,7 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE2_32-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE2_32-NEXT: shrl $31, %eax
; SSE2_32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE2_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE2_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE2_32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2_32-NEXT: movss %xmm0, (%esp)
@@ -392,7 +392,7 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE1_32-NEXT: movss %xmm0, (%esp)
@@ -413,7 +413,7 @@ define float @u64_to_f(i64 %a) nounwind {
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
-; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp
@@ -652,7 +652,7 @@ define double @u64_to_d(i64 %a) nounwind {
; AVX512F_32-NEXT: subl $8, %esp
; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F_32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
-; AVX512F_32-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX512F_32-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512F_32-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512F_32-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; AVX512F_32-NEXT: vmovsd %xmm0, (%esp)
@@ -669,7 +669,7 @@ define double @u64_to_d(i64 %a) nounwind {
; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
-; SSE2_32-NEXT: subpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2_32-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movapd %xmm0, %xmm1
; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2_32-NEXT: addsd %xmm0, %xmm1
@@ -683,7 +683,7 @@ define double @u64_to_d(i64 %a) nounwind {
; SSE2_64: # %bb.0:
; SSE2_64-NEXT: movq %rdi, %xmm1
; SSE2_64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
-; SSE2_64-NEXT: subpd {{.*}}(%rip), %xmm1
+; SSE2_64-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2_64-NEXT: movapd %xmm1, %xmm0
; SSE2_64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2_64-NEXT: addsd %xmm1, %xmm0
@@ -701,7 +701,7 @@ define double @u64_to_d(i64 %a) nounwind {
; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll (%esp)
-; SSE1_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp
@@ -720,7 +720,7 @@ define double @u64_to_d(i64 %a) nounwind {
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
-; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp
@@ -774,7 +774,7 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; AVX512F_32-NEXT: subl $8, %esp
; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F_32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
-; AVX512F_32-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX512F_32-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512F_32-NEXT: vhaddpd %xmm0, %xmm0, %xmm0
; AVX512F_32-NEXT: vmovlpd %xmm0, (%esp)
; AVX512F_32-NEXT: fldl (%esp)
@@ -790,7 +790,7 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
-; SSE2_32-NEXT: subpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE2_32-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movapd %xmm0, %xmm1
; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2_32-NEXT: addsd %xmm0, %xmm1
@@ -804,7 +804,7 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; SSE2_64: # %bb.0:
; SSE2_64-NEXT: movq %rdi, %xmm1
; SSE2_64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
-; SSE2_64-NEXT: subpd {{.*}}(%rip), %xmm1
+; SSE2_64-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2_64-NEXT: movapd %xmm1, %xmm0
; SSE2_64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2_64-NEXT: addsd %xmm1, %xmm0
@@ -822,7 +822,7 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll (%esp)
-; SSE1_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp
@@ -841,7 +841,7 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
-; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp
@@ -1076,7 +1076,7 @@ define x86_fp80 @u64_to_x(i64 %a) nounwind {
; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: shrl $31, %ecx
; CHECK32-NEXT: fildll (%esp)
-; CHECK32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; CHECK32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp
; CHECK32-NEXT: retl
@@ -1088,7 +1088,7 @@ define x86_fp80 @u64_to_x(i64 %a) nounwind {
; CHECK64-NEXT: testq %rdi, %rdi
; CHECK64-NEXT: sets %al
; CHECK64-NEXT: fildll -{{[0-9]+}}(%rsp)
-; CHECK64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rax,4)
+; CHECK64-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%rax,4)
; CHECK64-NEXT: retq
%r = uitofp i64 %a to x86_fp80
ret x86_fp80 %r
diff --git a/llvm/test/CodeGen/X86/scalarize-fp.ll b/llvm/test/CodeGen/X86/scalarize-fp.ll
index d7955319507f1..562fc91eed443 100644
--- a/llvm/test/CodeGen/X86/scalarize-fp.ll
+++ b/llvm/test/CodeGen/X86/scalarize-fp.ll
@@ -5,12 +5,12 @@
define <4 x float> @fadd_op1_constant_v4f32(float %x) nounwind {
; SSE-LABEL: fadd_op1_constant_v4f32:
; SSE: # %bb.0:
-; SSE-NEXT: addss {{.*}}(%rip), %xmm0
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fadd_op1_constant_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%v = insertelement <4 x float> undef, float %x, i32 0
%b = fadd <4 x float> %v, <float 42.0, float undef, float undef, float undef>
@@ -21,13 +21,13 @@ define <4 x float> @load_fadd_op1_constant_v4f32(float* %p) nounwind {
; SSE-LABEL: load_fadd_op1_constant_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-NEXT: addss {{.*}}(%rip), %xmm0
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: load_fadd_op1_constant_v4f32:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load float, float* %p
%v = insertelement <4 x float> undef, float %x, i32 0
@@ -74,12 +74,12 @@ define <4 x float> @load_fsub_op0_constant_v4f32(float* %p) nounwind {
define <4 x float> @fmul_op1_constant_v4f32(float %x) nounwind {
; SSE-LABEL: fmul_op1_constant_v4f32:
; SSE: # %bb.0:
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fmul_op1_constant_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%v = insertelement <4 x float> undef, float %x, i32 0
%b = fmul <4 x float> %v, <float 42.0, float undef, float undef, float undef>
@@ -90,13 +90,13 @@ define <4 x float> @load_fmul_op1_constant_v4f32(float* %p) nounwind {
; SSE-LABEL: load_fmul_op1_constant_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: load_fmul_op1_constant_v4f32:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load float, float* %p
%v = insertelement <4 x float> undef, float %x, i32 0
@@ -107,12 +107,12 @@ define <4 x float> @load_fmul_op1_constant_v4f32(float* %p) nounwind {
define <4 x float> @fdiv_op1_constant_v4f32(float %x) nounwind {
; SSE-LABEL: fdiv_op1_constant_v4f32:
; SSE: # %bb.0:
-; SSE-NEXT: divss {{.*}}(%rip), %xmm0
+; SSE-NEXT: divss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fdiv_op1_constant_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vdivss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vdivss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%v = insertelement <4 x float> undef, float %x, i32 0
%b = fdiv <4 x float> %v, <float 42.0, float undef, float undef, float undef>
@@ -123,13 +123,13 @@ define <4 x float> @load_fdiv_op1_constant_v4f32(float* %p) nounwind {
; SSE-LABEL: load_fdiv_op1_constant_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-NEXT: divss {{.*}}(%rip), %xmm0
+; SSE-NEXT: divss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: load_fdiv_op1_constant_v4f32:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vdivss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vdivss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load float, float* %p
%v = insertelement <4 x float> undef, float %x, i32 0
@@ -176,12 +176,12 @@ define <4 x float> @load_fdiv_op0_constant_v4f32(float* %p) nounwind {
define <4 x double> @fadd_op1_constant_v4f64(double %x) nounwind {
; SSE-LABEL: fadd_op1_constant_v4f64:
; SSE: # %bb.0:
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fadd_op1_constant_v4f64:
; AVX: # %bb.0:
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%v = insertelement <4 x double> undef, double %x, i32 0
%b = fadd <4 x double> %v, <double 42.0, double undef, double undef, double undef>
@@ -192,13 +192,13 @@ define <4 x double> @load_fadd_op1_constant_v4f64(double* %p) nounwind {
; SSE-LABEL: load_fadd_op1_constant_v4f64:
; SSE: # %bb.0:
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: load_fadd_op1_constant_v4f64:
; AVX: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load double, double* %p
%v = insertelement <4 x double> undef, double %x, i32 0
@@ -245,12 +245,12 @@ define <4 x double> @load_fsub_op0_constant_v4f64(double* %p) nounwind {
define <4 x double> @fmul_op1_constant_v4f64(double %x) nounwind {
; SSE-LABEL: fmul_op1_constant_v4f64:
; SSE: # %bb.0:
-; SSE-NEXT: mulsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fmul_op1_constant_v4f64:
; AVX: # %bb.0:
-; AVX-NEXT: vmulsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%v = insertelement <4 x double> undef, double %x, i32 0
%b = fmul <4 x double> %v, <double 42.0, double undef, double undef, double undef>
@@ -261,13 +261,13 @@ define <4 x double> @load_fmul_op1_constant_v4f64(double* %p) nounwind {
; SSE-LABEL: load_fmul_op1_constant_v4f64:
; SSE: # %bb.0:
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: mulsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: load_fmul_op1_constant_v4f64:
; AVX: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vmulsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load double, double* %p
%v = insertelement <4 x double> undef, double %x, i32 0
@@ -278,12 +278,12 @@ define <4 x double> @load_fmul_op1_constant_v4f64(double* %p) nounwind {
define <4 x double> @fdiv_op1_constant_v4f64(double %x) nounwind {
; SSE-LABEL: fdiv_op1_constant_v4f64:
; SSE: # %bb.0:
-; SSE-NEXT: divsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fdiv_op1_constant_v4f64:
; AVX: # %bb.0:
-; AVX-NEXT: vdivsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%v = insertelement <4 x double> undef, double %x, i32 0
%b = fdiv <4 x double> %v, <double 42.0, double undef, double undef, double undef>
@@ -294,13 +294,13 @@ define <4 x double> @load_fdiv_op1_constant_v4f64(double* %p) nounwind {
; SSE-LABEL: load_fdiv_op1_constant_v4f64:
; SSE: # %bb.0:
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: divsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: load_fdiv_op1_constant_v4f64:
; AVX: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vdivsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%x = load double, double* %p
%v = insertelement <4 x double> undef, double %x, i32 0
@@ -507,13 +507,13 @@ define <2 x i64> @add_splat_splat_v2i64(<2 x i64> %vx, <2 x i64> %vy) {
define <2 x double> @fadd_splat_const_op1_v2f64(<2 x double> %vx) {
; SSE-LABEL: fadd_splat_const_op1_v2f64:
; SSE: # %bb.0:
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: fadd_splat_const_op1_v2f64:
; AVX: # %bb.0:
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; AVX-NEXT: retq
%splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> zeroinitializer
@@ -548,13 +548,13 @@ define <4 x double> @fsub_const_op0_splat_v4f64(double %x) {
define <4 x float> @fmul_splat_const_op1_v4f32(<4 x float> %vx, <4 x float> %vy) {
; SSE-LABEL: fmul_splat_const_op1_v4f32:
; SSE: # %bb.0:
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: fmul_splat_const_op1_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX-NEXT: retq
%splatx = shufflevector <4 x float> %vx, <4 x float> undef, <4 x i32> zeroinitializer
@@ -683,13 +683,13 @@ define <8 x float> @splat0_fdiv_v8f32(<8 x float> %vx, <8 x float> %vy) {
define <2 x double> @splat0_fadd_const_op1_v2f64(<2 x double> %vx) {
; SSE-LABEL: splat0_fadd_const_op1_v2f64:
; SSE: # %bb.0:
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: splat0_fadd_const_op1_v2f64:
; AVX: # %bb.0:
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; AVX-NEXT: retq
%b = fadd <2 x double> %vx, <double 42.0, double 12.0>
@@ -722,13 +722,13 @@ define <4 x double> @splat0_fsub_const_op0_v4f64(double %x) {
define <4 x float> @splat0_fmul_const_op1_v4f32(<4 x float> %vx) {
; SSE-LABEL: splat0_fmul_const_op1_v4f32:
; SSE: # %bb.0:
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: splat0_fmul_const_op1_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX-NEXT: retq
%b = fmul fast <4 x float> %vx, <float 6.0, float -1.0, float 1.0, float 7.0>
diff --git a/llvm/test/CodeGen/X86/sdiv-exact.ll b/llvm/test/CodeGen/X86/sdiv-exact.ll
index 3c238d7f1bff5..af8462d449ef0 100644
--- a/llvm/test/CodeGen/X86/sdiv-exact.ll
+++ b/llvm/test/CodeGen/X86/sdiv-exact.ll
@@ -96,8 +96,8 @@ define <4 x i32> @test5(<4 x i32> %x) {
;
; X64-LABEL: test5:
; X64: # %bb.0:
-; X64-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%div = sdiv exact <4 x i32> %x, <i32 24, i32 24, i32 25, i32 25>
ret <4 x i32> %div
@@ -124,8 +124,8 @@ define <4 x i32> @test6(<4 x i32> %x) {
;
; X64-LABEL: test6:
; X64: # %bb.0:
-; X64-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%div = sdiv exact <4 x i32> %x, <i32 24, i32 24, i32 26, i32 26>
ret <4 x i32> %div
@@ -146,7 +146,7 @@ define <4 x i32> @test7(<4 x i32> %x) {
;
; X64-LABEL: test7:
; X64: # %bb.0:
-; X64-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%div = sdiv exact <4 x i32> %x, <i32 25, i32 25, i32 27, i32 27>
ret <4 x i32> %div
@@ -171,8 +171,8 @@ define <4 x i32> @test8(<4 x i32> %x) {
;
; X64-LABEL: test8:
; X64: # %bb.0:
-; X64-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%div = sdiv exact <4 x i32> %x, <i32 1, i32 1, i32 24, i32 24>
ret <4 x i32> %div
diff --git a/llvm/test/CodeGen/X86/select-of-fp-constants.ll b/llvm/test/CodeGen/X86/select-of-fp-constants.ll
index 934f0f8b9465e..9f4510ff1964d 100644
--- a/llvm/test/CodeGen/X86/select-of-fp-constants.ll
+++ b/llvm/test/CodeGen/X86/select-of-fp-constants.ll
@@ -16,7 +16,7 @@ define float @icmp_select_fp_constants(i32 %x) nounwind readnone {
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: sete %al
-; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: retl
;
; X64-SSE-LABEL: icmp_select_fp_constants:
@@ -46,7 +46,7 @@ define float @fcmp_select_fp_constants(float %x) nounwind readnone {
; X86-SSE-NEXT: cmpneqss {{[0-9]+}}(%esp), %xmm0
; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: andl $1, %eax
-; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: retl
;
; X86-AVX2-LABEL: fcmp_select_fp_constants:
@@ -55,20 +55,20 @@ define float @fcmp_select_fp_constants(float %x) nounwind readnone {
; X86-AVX2-NEXT: vcmpneqss {{[0-9]+}}(%esp), %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
; X86-AVX2-NEXT: andl $1, %eax
-; X86-AVX2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-AVX2-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-AVX2-NEXT: retl
;
; X86-AVX512F-LABEL: fcmp_select_fp_constants:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-AVX512F-NEXT: vcmpneqss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %k0
+; X86-AVX512F-NEXT: vcmpneqss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %k0
; X86-AVX512F-NEXT: kmovw %k0, %eax
-; X86-AVX512F-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-AVX512F-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-AVX512F-NEXT: retl
;
; X64-SSE-LABEL: fcmp_select_fp_constants:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: cmpneqss {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: cmpneqss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $1, %eax
; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -76,7 +76,7 @@ define float @fcmp_select_fp_constants(float %x) nounwind readnone {
;
; X64-AVX2-LABEL: fcmp_select_fp_constants:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vcmpneqss {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vcmpneqss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X64-AVX2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X64-AVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
@@ -84,9 +84,9 @@ define float @fcmp_select_fp_constants(float %x) nounwind readnone {
;
; X64-AVX512F-LABEL: fcmp_select_fp_constants:
; X64-AVX512F: # %bb.0:
-; X64-AVX512F-NEXT: vcmpneqss {{.*}}(%rip), %xmm0, %k1
+; X64-AVX512F-NEXT: vcmpneqss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; X64-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-AVX512F-NEXT: vmovss {{.*}}(%rip), %xmm0 {%k1}
+; X64-AVX512F-NEXT: vmovss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1}
; X64-AVX512F-NEXT: retq
%c = fcmp une float %x, -4.0
%r = select i1 %c, float 42.0, float 23.0
diff --git a/llvm/test/CodeGen/X86/select-sra.ll b/llvm/test/CodeGen/X86/select-sra.ll
index 4d984aab06bd1..2a3f8a125e4a1 100644
--- a/llvm/test/CodeGen/X86/select-sra.ll
+++ b/llvm/test/CodeGen/X86/select-sra.ll
@@ -56,7 +56,7 @@ define <16 x i8> @isnonneg_v16i8(<16 x i8> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pcmpgtb %xmm0, %xmm1
-; CHECK-NEXT: por {{.*}}(%rip), %xmm1
+; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq
%cond = icmp sgt <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
@@ -68,7 +68,7 @@ define <8 x i16> @isnonneg_v8i16(<8 x i16> %x) {
; CHECK-LABEL: isnonneg_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: psraw $15, %xmm0
-; CHECK-NEXT: por {{.*}}(%rip), %xmm0
+; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cond = icmp sgt <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%r = select <8 x i1> %cond, <8 x i16> <i16 1, i16 542, i16 542, i16 542, i16 542, i16 542, i16 542, i16 1>, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
@@ -79,7 +79,7 @@ define <4 x i32> @isnonneg_v4i32(<4 x i32> %x) {
; CHECK-LABEL: isnonneg_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
-; CHECK-NEXT: por {{.*}}(%rip), %xmm0
+; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cond = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%r = select <4 x i1> %cond, <4 x i32> <i32 0, i32 42, i32 -42, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -91,7 +91,7 @@ define <2 x i64> @isnonneg_v2i64(<2 x i64> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; CHECK-NEXT: por {{.*}}(%rip), %xmm0
+; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cond = icmp sgt <2 x i64> %x, <i64 -1, i64 -1>
%r = select <2 x i1> %cond, <2 x i64> <i64 2342342, i64 12>, <2 x i64> <i64 -1, i64 -1>
@@ -153,7 +153,7 @@ define <16 x i8> @isneg_v16i8(<16 x i8> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pcmpgtb %xmm0, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq
%cond = icmp slt <16 x i8> %x, zeroinitializer
@@ -165,7 +165,7 @@ define <8 x i16> @isneg_v8i16(<8 x i16> %x) {
; CHECK-LABEL: isneg_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: psraw $15, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cond = icmp slt <8 x i16> %x, zeroinitializer
%r = select <8 x i1> %cond, <8 x i16> <i16 1, i16 542, i16 542, i16 542, i16 542, i16 542, i16 542, i16 1>, <8 x i16> zeroinitializer
@@ -176,7 +176,7 @@ define <4 x i32> @isneg_v4i32(<4 x i32> %x) {
; CHECK-LABEL: isneg_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cond = icmp slt <4 x i32> %x, zeroinitializer
%r = select <4 x i1> %cond, <4 x i32> <i32 0, i32 42, i32 -42, i32 1>, <4 x i32> zeroinitializer
@@ -188,7 +188,7 @@ define <2 x i64> @isneg_v2i64(<2 x i64> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cond = icmp slt <2 x i64> %x, zeroinitializer
%r = select <2 x i1> %cond, <2 x i64> <i64 2342342, i64 12>, <2 x i64> zeroinitializer
diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll
index 34c7911220c42..1ef10c894a019 100644
--- a/llvm/test/CodeGen/X86/select.ll
+++ b/llvm/test/CodeGen/X86/select.ll
@@ -137,14 +137,14 @@ define float @test3(i32 %x) nounwind readnone {
; GENERIC-NEXT: xorl %eax, %eax
; GENERIC-NEXT: testl %edi, %edi
; GENERIC-NEXT: sete %al
-; GENERIC-NEXT: leaq {{.*}}(%rip), %rcx
+; GENERIC-NEXT: leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rcx
; GENERIC-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; GENERIC-NEXT: retq
;
; ATOM-LABEL: test3:
; ATOM: ## %bb.0: ## %entry
; ATOM-NEXT: xorl %eax, %eax
-; ATOM-NEXT: leaq {{.*}}(%rip), %rcx
+; ATOM-NEXT: leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rcx
; ATOM-NEXT: testl %edi, %edi
; ATOM-NEXT: sete %al
; ATOM-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -155,7 +155,7 @@ define float @test3(i32 %x) nounwind readnone {
; ATHLON-NEXT: xorl %eax, %eax
; ATHLON-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; ATHLON-NEXT: sete %al
-; ATHLON-NEXT: flds LCPI2_0(,%eax,4)
+; ATHLON-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; ATHLON-NEXT: retl
;
; MCU-LABEL: test3:
@@ -163,7 +163,7 @@ define float @test3(i32 %x) nounwind readnone {
; MCU-NEXT: xorl %ecx, %ecx
; MCU-NEXT: testl %eax, %eax
; MCU-NEXT: sete %cl
-; MCU-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
+; MCU-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; MCU-NEXT: retl
entry:
%0 = icmp eq i32 %x, 0
@@ -185,7 +185,7 @@ define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly {
; ATHLON: ## %bb.0: ## %entry
; ATHLON-NEXT: movl {{[0-9]+}}(%esp), %eax
; ATHLON-NEXT: fldl {{[0-9]+}}(%esp)
-; ATHLON-NEXT: flds LCPI3_0
+; ATHLON-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; ATHLON-NEXT: xorl %ecx, %ecx
; ATHLON-NEXT: fucompi %st(1), %st
; ATHLON-NEXT: fstp %st(0)
@@ -197,7 +197,7 @@ define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly {
; MCU: # %bb.0: # %entry
; MCU-NEXT: movl %eax, %ecx
; MCU-NEXT: fldl {{[0-9]+}}(%esp)
-; MCU-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; MCU-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; MCU-NEXT: fucompp
; MCU-NEXT: fnstsw %ax
; MCU-NEXT: xorl %edx, %edx
@@ -394,14 +394,14 @@ define x86_fp80 @test7(i32 %tmp8) nounwind {
; GENERIC-NEXT: testl %edi, %edi
; GENERIC-NEXT: setns %al
; GENERIC-NEXT: shlq $4, %rax
-; GENERIC-NEXT: leaq {{.*}}(%rip), %rcx
+; GENERIC-NEXT: leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rcx
; GENERIC-NEXT: fldt (%rax,%rcx)
; GENERIC-NEXT: retq
;
; ATOM-LABEL: test7:
; ATOM: ## %bb.0:
; ATOM-NEXT: xorl %eax, %eax
-; ATOM-NEXT: leaq {{.*}}(%rip), %rcx
+; ATOM-NEXT: leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rcx
; ATOM-NEXT: testl %edi, %edi
; ATOM-NEXT: setns %al
; ATOM-NEXT: shlq $4, %rax
@@ -414,7 +414,7 @@ define x86_fp80 @test7(i32 %tmp8) nounwind {
; ATHLON-NEXT: notl %eax
; ATHLON-NEXT: shrl $27, %eax
; ATHLON-NEXT: andl $-16, %eax
-; ATHLON-NEXT: fldt LCPI6_0(%eax)
+; ATHLON-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%eax)
; ATHLON-NEXT: retl
;
; MCU-LABEL: test7:
@@ -422,7 +422,7 @@ define x86_fp80 @test7(i32 %tmp8) nounwind {
; MCU-NEXT: notl %eax
; MCU-NEXT: shrl $27, %eax
; MCU-NEXT: andl $-16, %eax
-; MCU-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}(%eax)
+; MCU-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%eax)
; MCU-NEXT: retl
%tmp9 = icmp sgt i32 %tmp8, -1
%retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
diff --git a/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll b/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
index 8e8e1e806f43e..c1e182460c08f 100644
--- a/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
@@ -204,7 +204,7 @@ define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
; ANY-LABEL: sel_shift_bool_v16i8:
; ANY: # %bb.0:
; ANY-NEXT: psllw $7, %xmm0
-; ANY-NEXT: pand {{.*}}(%rip), %xmm0
+; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: retq
%shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer
ret <16 x i8> %shl
@@ -213,7 +213,7 @@ define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
; ANY-LABEL: sel_shift_bool_v8i16:
; ANY: # %bb.0:
-; ANY-NEXT: pand {{.*}}(%rip), %xmm0
+; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: psllw $7, %xmm0
; ANY-NEXT: retq
%shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer
@@ -223,7 +223,7 @@ define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
; ANY-LABEL: sel_shift_bool_v4i32:
; ANY: # %bb.0:
-; ANY-NEXT: pand {{.*}}(%rip), %xmm0
+; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: pslld $6, %xmm0
; ANY-NEXT: retq
%shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer
@@ -233,7 +233,7 @@ define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {
; ANY-LABEL: sel_shift_bool_v2i64:
; ANY: # %bb.0:
-; ANY-NEXT: pand {{.*}}(%rip), %xmm0
+; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: psllq $16, %xmm0
; ANY-NEXT: retq
%shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer
diff --git a/llvm/test/CodeGen/X86/semantic-interposition-asm.ll b/llvm/test/CodeGen/X86/semantic-interposition-asm.ll
index 89e001c8261d7..cf81f71db5fa0 100644
--- a/llvm/test/CodeGen/X86/semantic-interposition-asm.ll
+++ b/llvm/test/CodeGen/X86/semantic-interposition-asm.ll
@@ -51,18 +51,18 @@ entry:
define i64 @test_fun() nounwind {
; STATIC-LABEL: test_fun:
; STATIC: # %bb.0: # %entry
-; STATIC-NEXT: movq fun1@{{.*}}(%rip), %rax
+; STATIC-NEXT: movq fun1 at GOTPCREL(%rip), %rax
; STATIC-NEXT: #APP
-; STATIC-NEXT: movq {{.*}}(%rip), %rax
+; STATIC-NEXT: movq fun0(%rip), %rax
; STATIC-NEXT: movq (%rax), %rax
; STATIC-NEXT: #NO_APP
; STATIC-NEXT: retq
;
; CHECK-LABEL: test_fun:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq fun1@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq fun1 at GOTPCREL(%rip), %rax
; CHECK-NEXT: #APP
-; CHECK-NEXT: movq .Lfun0${{.*}}(%rip), %rax
+; CHECK-NEXT: movq .Lfun0$local(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/setcc-lowering.ll b/llvm/test/CodeGen/X86/setcc-lowering.ll
index c91b0f2ebb246..fae9602eaaafa 100644
--- a/llvm/test/CodeGen/X86/setcc-lowering.ll
+++ b/llvm/test/CodeGen/X86/setcc-lowering.ll
@@ -9,20 +9,20 @@
define <8 x i16> @pr25080(<8 x i32> %a) {
; AVX-LABEL: pr25080:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
; KNL-32-LABEL: pr25080:
; KNL-32: # %bb.0: # %entry
; KNL-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; KNL-32-NEXT: vptestnmd {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %k0
+; KNL-32-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %k0
; KNL-32-NEXT: movb $15, %al
; KNL-32-NEXT: kmovw %eax, %k1
; KNL-32-NEXT: korw %k1, %k0, %k1
diff --git a/llvm/test/CodeGen/X86/setcc-narrowing.ll b/llvm/test/CodeGen/X86/setcc-narrowing.ll
index 52f143f8b3237..42883fc05cc0d 100644
--- a/llvm/test/CodeGen/X86/setcc-narrowing.ll
+++ b/llvm/test/CodeGen/X86/setcc-narrowing.ll
@@ -11,7 +11,6 @@ define i32 @t1() nounwind ssp {
; CHECK-NEXT: cmpl $0, _t1.global
; CHECK-NEXT: setne %al
; CHECK-NEXT: retl
-; CHECK-NEXT: ## -- End function
entry:
%0 = load i64, i64* @t1.global, align 8
%and = and i64 4294967295, %0
diff --git a/llvm/test/CodeGen/X86/setcc.ll b/llvm/test/CodeGen/X86/setcc.ll
index 6ae7e5cbb701c..3a386da4503ee 100644
--- a/llvm/test/CodeGen/X86/setcc.ll
+++ b/llvm/test/CodeGen/X86/setcc.ll
@@ -46,7 +46,7 @@ define i64 @t3(i64 %x) nounwind readnone ssp {
define i32 @t4(i32 %a) {
; CHECK-LABEL: t4:
; CHECK: ## %bb.0:
-; CHECK-NEXT: movq _v4@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _v4 at GOTPCREL(%rip), %rax
; CHECK-NEXT: cmpl $1, (%rax)
; CHECK-NEXT: movw $1, %ax
; CHECK-NEXT: adcw $0, %ax
diff --git a/llvm/test/CodeGen/X86/shadow-stack.ll b/llvm/test/CodeGen/X86/shadow-stack.ll
index 7316ad80cda7e..a0ad65e4e5f66 100644
--- a/llvm/test/CodeGen/X86/shadow-stack.ll
+++ b/llvm/test/CodeGen/X86/shadow-stack.ll
@@ -36,7 +36,7 @@ define i32 @bar(i32 %i) local_unnamed_addr {
; X86_64-NEXT: pushq %rbp
; X86_64-NEXT: .cfi_def_cfa_offset 16
; X86_64-NEXT: .cfi_offset %rbp, -16
-; X86_64-NEXT: movq _buf@{{.*}}(%rip), %rax
+; X86_64-NEXT: movq _buf at GOTPCREL(%rip), %rax
; X86_64-NEXT: movq (%rax), %rax
; X86_64-NEXT: xorl %edx, %edx
; X86_64-NEXT: rdsspq %rdx
@@ -129,11 +129,11 @@ define i32 @foo(i32 %i) local_unnamed_addr {
; X86_64-NEXT: .cfi_offset %r15, -24
; X86_64-NEXT: ## kill: def $edi killed $edi def $rdi
; X86_64-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
-; X86_64-NEXT: movq _buf@{{.*}}(%rip), %rax
+; X86_64-NEXT: movq _buf at GOTPCREL(%rip), %rax
; X86_64-NEXT: movq (%rax), %rax
; X86_64-NEXT: movq %rbp, (%rax)
; X86_64-NEXT: movq %rsp, 16(%rax)
-; X86_64-NEXT: leaq {{.*}}(%rip), %rcx
+; X86_64-NEXT: leaq LBB1_4(%rip), %rcx
; X86_64-NEXT: movq %rcx, 8(%rax)
; X86_64-NEXT: xorq %rcx, %rcx
; X86_64-NEXT: rdsspq %rcx
diff --git a/llvm/test/CodeGen/X86/shift-and.ll b/llvm/test/CodeGen/X86/shift-and.ll
index 00dc6358ed0b3..98df415dfcecb 100644
--- a/llvm/test/CodeGen/X86/shift-and.ll
+++ b/llvm/test/CodeGen/X86/shift-and.ll
@@ -55,7 +55,7 @@ define void @t3(i16 %t) nounwind {
; X64: # %bb.0:
; X64-NEXT: movl %edi, %ecx
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
-; X64-NEXT: sarw %cl, {{.*}}(%rip)
+; X64-NEXT: sarw %cl, X(%rip)
; X64-NEXT: retq
%shamt = and i16 %t, 31
%tmp = load i16, i16* @X
diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll
index b40754b823006..e1f6f3e82fda5 100644
--- a/llvm/test/CodeGen/X86/shift-combine.ll
+++ b/llvm/test/CodeGen/X86/shift-combine.ll
@@ -227,7 +227,7 @@ define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) nounwind {
; X64-LABEL: ashr_add_shl_v4i8:
; X64: # %bb.0:
; X64-NEXT: pslld $24, %xmm0
-; X64-NEXT: paddd {{.*}}(%rip), %xmm0
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: psrad $24, %xmm0
; X64-NEXT: retq
%conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>
diff --git a/llvm/test/CodeGen/X86/shift-logic.ll b/llvm/test/CodeGen/X86/shift-logic.ll
index 12e2328f7ce87..35572fecc72bb 100644
--- a/llvm/test/CodeGen/X86/shift-logic.ll
+++ b/llvm/test/CodeGen/X86/shift-logic.ll
@@ -90,12 +90,12 @@ define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: ashr_and:
; CHECK: # %bb.0:
; CHECK-NEXT: psrlw $2, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: psubb %xmm2, %xmm1
; CHECK-NEXT: psrlw $5, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: psubb %xmm2, %xmm0
diff --git a/llvm/test/CodeGen/X86/shift-parts.ll b/llvm/test/CodeGen/X86/shift-parts.ll
index e33faed8a3ed6..99400e8ee0580 100644
--- a/llvm/test/CodeGen/X86/shift-parts.ll
+++ b/llvm/test/CodeGen/X86/shift-parts.ll
@@ -9,8 +9,8 @@
define i32 @int87(i32 %uint64p_8, i1 %cond) nounwind {
; CHECK-LABEL: int87:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq g_144+{{.*}}(%rip), %rax
-; CHECK-NEXT: movq g_144+{{.*}}(%rip), %rcx
+; CHECK-NEXT: movq g_144+24(%rip), %rax
+; CHECK-NEXT: movq g_144+16(%rip), %rcx
; CHECK-NEXT: movzbl %sil, %edx
; CHECK-NEXT: shll $6, %edx
; CHECK-NEXT: .p2align 4, 0x90
diff --git a/llvm/test/CodeGen/X86/shift-pcmp.ll b/llvm/test/CodeGen/X86/shift-pcmp.ll
index e3ca10353cd71..11e9a05484734 100644
--- a/llvm/test/CodeGen/X86/shift-pcmp.ll
+++ b/llvm/test/CodeGen/X86/shift-pcmp.ll
@@ -6,13 +6,13 @@ define <8 x i16> @foo(<8 x i16> %a, <8 x i16> %b) {
; SSE-LABEL: foo:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqw %xmm1, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: foo:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%icmp = icmp eq <8 x i16> %a, %b
%zext = zext <8 x i1> %icmp to <8 x i16>
@@ -25,13 +25,13 @@ define <8 x i16> @bar(<8 x i16> %a, <8 x i16> %b) {
; SSE-LABEL: bar:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqw %xmm1, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: bar:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%icmp = icmp eq <8 x i16> %a, %b
%zext = zext <8 x i1> %icmp to <8 x i16>
diff --git a/llvm/test/CodeGen/X86/shift_minsize.ll b/llvm/test/CodeGen/X86/shift_minsize.ll
index 548c2d37707a3..51e62612be3c2 100644
--- a/llvm/test/CodeGen/X86/shift_minsize.ll
+++ b/llvm/test/CodeGen/X86/shift_minsize.ll
@@ -15,6 +15,13 @@ define i64 @f0(i64 %val, i64 %amt) minsize optsize {
; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
; CHECK-NEXT: shlq %cl, %rax
; CHECK-NEXT: retq
+;
+; CHECK-WIN-LABEL: f0:
+; CHECK-WIN: # %bb.0:
+; CHECK-WIN-NEXT: movq %rcx, %rax
+; CHECK-WIN-NEXT: movl %edx, %ecx
+; CHECK-WIN-NEXT: shlq %cl, %rax
+; CHECK-WIN-NEXT: retq
%res = shl i64 %val, %amt
ret i64 %res
}
@@ -28,6 +35,14 @@ define i32 @f1(i64 %x, i64 %y) minsize optsize {
; CHECK-NEXT: shlq %cl, %rax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
+;
+; CHECK-WIN-LABEL: f1:
+; CHECK-WIN: # %bb.0:
+; CHECK-WIN-NEXT: movq %rcx, %rax
+; CHECK-WIN-NEXT: movl %edx, %ecx
+; CHECK-WIN-NEXT: shlq %cl, %rax
+; CHECK-WIN-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-WIN-NEXT: retq
%a = shl i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
@@ -42,6 +57,14 @@ define i32 @f2(i64 %x, i64 %y) minsize optsize {
; CHECK-NEXT: sarq %cl, %rax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
+;
+; CHECK-WIN-LABEL: f2:
+; CHECK-WIN: # %bb.0:
+; CHECK-WIN-NEXT: movq %rcx, %rax
+; CHECK-WIN-NEXT: movl %edx, %ecx
+; CHECK-WIN-NEXT: sarq %cl, %rax
+; CHECK-WIN-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-WIN-NEXT: retq
%a = ashr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
@@ -56,6 +79,14 @@ define i32 @f3(i64 %x, i64 %y) minsize optsize {
; CHECK-NEXT: shrq %cl, %rax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
+;
+; CHECK-WIN-LABEL: f3:
+; CHECK-WIN: # %bb.0:
+; CHECK-WIN-NEXT: movq %rcx, %rax
+; CHECK-WIN-NEXT: movl %edx, %ecx
+; CHECK-WIN-NEXT: shrq %cl, %rax
+; CHECK-WIN-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-WIN-NEXT: retq
%a = lshr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
@@ -67,10 +98,22 @@ define dso_local { i64, i64 } @shl128(i64 %x.coerce0, i64 %x.coerce1, i8 signext
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movzbl %dl, %edx
-; CHECK-NEXT: callq __ashlti3
+; CHECK-NEXT: callq __ashlti3 at PLT
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
+;
+; CHECK-WIN-LABEL: shl128:
+; CHECK-WIN: # %bb.0: # %entry
+; CHECK-WIN-NEXT: movq %rcx, %r9
+; CHECK-WIN-NEXT: movl %r8d, %ecx
+; CHECK-WIN-NEXT: shldq %cl, %r9, %rdx
+; CHECK-WIN-NEXT: shlq %cl, %r9
+; CHECK-WIN-NEXT: xorl %eax, %eax
+; CHECK-WIN-NEXT: testb $64, %r8b
+; CHECK-WIN-NEXT: cmovneq %r9, %rdx
+; CHECK-WIN-NEXT: cmoveq %r9, %rax
+; CHECK-WIN-NEXT: retq
entry:
%x.sroa.2.0.insert.ext = zext i64 %x.coerce1 to i128
%x.sroa.2.0.insert.shift = shl nuw i128 %x.sroa.2.0.insert.ext, 64
@@ -92,10 +135,23 @@ define dso_local { i64, i64 } @ashr128(i64 %x.coerce0, i64 %x.coerce1, i8 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq __ashrti3
+; CHECK-NEXT: callq __ashrti3 at PLT
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
+;
+; CHECK-WIN-LABEL: ashr128:
+; CHECK-WIN: # %bb.0: # %entry
+; CHECK-WIN-NEXT: movq %rcx, %rax
+; CHECK-WIN-NEXT: movl %r8d, %ecx
+; CHECK-WIN-NEXT: shrdq %cl, %rdx, %rax
+; CHECK-WIN-NEXT: movq %rdx, %r9
+; CHECK-WIN-NEXT: sarq %cl, %r9
+; CHECK-WIN-NEXT: sarq $63, %rdx
+; CHECK-WIN-NEXT: testb $64, %r8b
+; CHECK-WIN-NEXT: cmovneq %r9, %rax
+; CHECK-WIN-NEXT: cmoveq %r9, %rdx
+; CHECK-WIN-NEXT: retq
entry:
%x.sroa.2.0.insert.ext = zext i64 %x.coerce1 to i128
%x.sroa.2.0.insert.shift = shl nuw i128 %x.sroa.2.0.insert.ext, 64
@@ -118,10 +174,22 @@ define dso_local { i64, i64 } @lshr128(i64 %x.coerce0, i64 %x.coerce1, i8 signex
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movzbl %dl, %edx
-; CHECK-NEXT: callq __lshrti3
+; CHECK-NEXT: callq __lshrti3 at PLT
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
+;
+; CHECK-WIN-LABEL: lshr128:
+; CHECK-WIN: # %bb.0: # %entry
+; CHECK-WIN-NEXT: movq %rcx, %rax
+; CHECK-WIN-NEXT: movl %r8d, %ecx
+; CHECK-WIN-NEXT: shrdq %cl, %rdx, %rax
+; CHECK-WIN-NEXT: shrq %cl, %rdx
+; CHECK-WIN-NEXT: xorl %ecx, %ecx
+; CHECK-WIN-NEXT: testb $64, %r8b
+; CHECK-WIN-NEXT: cmovneq %rdx, %rax
+; CHECK-WIN-NEXT: cmovneq %rcx, %rdx
+; CHECK-WIN-NEXT: retq
entry:
%x.sroa.2.0.insert.ext = zext i64 %x.coerce1 to i128
%x.sroa.2.0.insert.shift = shl nuw i128 %x.sroa.2.0.insert.ext, 64
diff --git a/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll b/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
index 08f89d26302a9..301c26ee2a529 100644
--- a/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
+++ b/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
@@ -21,7 +21,7 @@ define i32 @PR29058(i8 %x, i32 %y) {
; CHECK-NEXT: orb %dl, %cl
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: shll %cl, %eax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
+; CHECK-NEXT: movq %rax, structMember(%rip)
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
index ede2b2440a4fb..f2eea75ada236 100644
--- a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
+++ b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
@@ -98,9 +98,9 @@ lor.end: ; preds = %lor.rhs, %entry
define dso_local void @test5(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzbl x+{{.*}}(%rip), %eax
+; CHECK-NEXT: movzbl x+6(%rip), %eax
; CHECK-NEXT: shll $16, %eax
-; CHECK-NEXT: movzwl x+{{.*}}(%rip), %ecx
+; CHECK-NEXT: movzwl x+4(%rip), %ecx
; CHECK-NEXT: orl %eax, %ecx
; CHECK-NEXT: cmpl $1, %ecx
; CHECK-NEXT: jne bar # TAILCALL
diff --git a/llvm/test/CodeGen/X86/shrink-compare.ll b/llvm/test/CodeGen/X86/shrink-compare.ll
index 5da8e4015f629..313368b4af761 100644
--- a/llvm/test/CodeGen/X86/shrink-compare.ll
+++ b/llvm/test/CodeGen/X86/shrink-compare.ll
@@ -98,9 +98,9 @@ lor.end: ; preds = %lor.rhs, %entry
define dso_local void @test5(i32 %X) nounwind minsize {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzbl x+{{.*}}(%rip), %eax
+; CHECK-NEXT: movzbl x+6(%rip), %eax
; CHECK-NEXT: shll $16, %eax
-; CHECK-NEXT: movzwl x+{{.*}}(%rip), %ecx
+; CHECK-NEXT: movzwl x+4(%rip), %ecx
; CHECK-NEXT: orl %eax, %ecx
; CHECK-NEXT: cmpl $1, %ecx
; CHECK-NEXT: jne bar # TAILCALL
diff --git a/llvm/test/CodeGen/X86/shrink-const.ll b/llvm/test/CodeGen/X86/shrink-const.ll
index 981e6b15022f8..1f4929c517081 100644
--- a/llvm/test/CodeGen/X86/shrink-const.ll
+++ b/llvm/test/CodeGen/X86/shrink-const.ll
@@ -7,14 +7,14 @@ define <4 x i32> @sext_vector_constants(<4 x i32> %a0) {
; SSE-LABEL: sext_vector_constants:
; SSE: # %bb.0:
; SSE-NEXT: psrld $9, %xmm0
-; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pslld $26, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sext_vector_constants:
; AVX: # %bb.0:
; AVX-NEXT: vpsrld $9, %xmm0, %xmm0
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpslld $26, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = lshr <4 x i32> %a0, <i32 9, i32 9, i32 9, i32 9>
diff --git a/llvm/test/CodeGen/X86/shrink-fp-const1.ll b/llvm/test/CodeGen/X86/shrink-fp-const1.ll
index b633cc23bcea5..25fe46ba837b1 100644
--- a/llvm/test/CodeGen/X86/shrink-fp-const1.ll
+++ b/llvm/test/CodeGen/X86/shrink-fp-const1.ll
@@ -5,7 +5,7 @@
define double @foo(double %x) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
-; CHECK-NEXT: mulsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul double %x, 5.000000e-01
ret double %y
diff --git a/llvm/test/CodeGen/X86/shrink-fp-const2.ll b/llvm/test/CodeGen/X86/shrink-fp-const2.ll
index 01d799b589825..8a2a3e3f185e6 100644
--- a/llvm/test/CodeGen/X86/shrink-fp-const2.ll
+++ b/llvm/test/CodeGen/X86/shrink-fp-const2.ll
@@ -4,7 +4,7 @@
define x86_fp80 @test2() nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: retl
entry:
ret x86_fp80 0xK3FFFC000000000000000
diff --git a/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll b/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll
index b806203136f3a..96960b77a2097 100644
--- a/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll
+++ b/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll
@@ -13,7 +13,7 @@ define void @fn1() nounwind uwtable {
; CHECK-NEXT: callq ___chkstk_ms
; CHECK-NEXT: subq %rax, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 4144
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl a(%rip), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %select.true.sink
@@ -24,7 +24,7 @@ define void @fn1() nounwind uwtable {
; CHECK-NEXT: shrq $32, %rax
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: .LBB0_2: # %select.end
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, b(%rip)
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: # kill: def $ecx killed $ecx killed $rcx
; CHECK-NEXT: callq fn2
diff --git a/llvm/test/CodeGen/X86/shrink_vmul.ll b/llvm/test/CodeGen/X86/shrink_vmul.ll
index 177d1206c9608..c27181ca7f1de 100644
--- a/llvm/test/CodeGen/X86/shrink_vmul.ll
+++ b/llvm/test/CodeGen/X86/shrink_vmul.ll
@@ -55,7 +55,7 @@ define void @mul_2xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-SSE-LABEL: mul_2xi8:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rdx), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: movzwl (%rsi,%rdx), %ecx
@@ -70,7 +70,7 @@ define void @mul_2xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX-LABEL: mul_2xi8:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rdx), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
@@ -138,7 +138,7 @@ define void @mul_4xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-SSE-LABEL: mul_4xi8:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pxor %xmm2, %xmm2
@@ -151,7 +151,7 @@ define void @mul_4xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX-LABEL: mul_4xi8:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X64-AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X64-AVX-NEXT: vpmaddwd %xmm0, %xmm1, %xmm0
@@ -237,7 +237,7 @@ define void @mul_8xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-SSE-LABEL: mul_8xi8:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X64-SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; X64-SSE-NEXT: pxor %xmm2, %xmm2
@@ -253,7 +253,7 @@ define void @mul_8xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX1-LABEL: mul_8xi8:
; X64-AVX1: # %bb.0: # %entry
-; X64-AVX1-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX1-NEXT: movq c(%rip), %rax
; X64-AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X64-AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X64-AVX1-NEXT: vpmovzxbd {{.*#+}} xmm2 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
@@ -266,7 +266,7 @@ define void @mul_8xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX2-LABEL: mul_8xi8:
; X64-AVX2: # %bb.0: # %entry
-; X64-AVX2-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX2-NEXT: movq c(%rip), %rax
; X64-AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; X64-AVX2-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; X64-AVX2-NEXT: vpmaddwd %ymm0, %ymm1, %ymm0
@@ -375,7 +375,7 @@ define void @mul_16xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-SSE-LABEL: mul_16xi8:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movdqu (%rdi,%rdx), %xmm0
; X64-SSE-NEXT: movdqu (%rsi,%rdx), %xmm1
; X64-SSE-NEXT: pxor %xmm2, %xmm2
@@ -401,7 +401,7 @@ define void @mul_16xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX1-LABEL: mul_16xi8:
; X64-AVX1: # %bb.0: # %entry
-; X64-AVX1-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX1-NEXT: movq c(%rip), %rax
; X64-AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X64-AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X64-AVX1-NEXT: vpmovzxbd {{.*#+}} xmm2 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
@@ -422,7 +422,7 @@ define void @mul_16xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX2-LABEL: mul_16xi8:
; X64-AVX2: # %bb.0: # %entry
-; X64-AVX2-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX2-NEXT: movq c(%rip), %rax
; X64-AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; X64-AVX2-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; X64-AVX2-NEXT: vpmovzxbd {{.*#+}} ymm2 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
@@ -492,7 +492,7 @@ define void @mul_2xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-SSE-LABEL: mul_2xi16:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movdqa %xmm1, %xmm2
@@ -504,7 +504,7 @@ define void @mul_2xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX-LABEL: mul_2xi16:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; X64-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -569,7 +569,7 @@ define void @mul_4xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-SSE-LABEL: mul_4xi16:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X64-SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; X64-SSE-NEXT: movdqa %xmm1, %xmm2
@@ -581,7 +581,7 @@ define void @mul_4xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX-LABEL: mul_4xi16:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm0
@@ -666,7 +666,7 @@ define void @mul_8xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-SSE-LABEL: mul_8xi16:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movdqu (%rdi,%rdx), %xmm0
; X64-SSE-NEXT: movdqu (%rsi,%rdx), %xmm1
; X64-SSE-NEXT: movdqa %xmm1, %xmm2
@@ -681,7 +681,7 @@ define void @mul_8xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX1-LABEL: mul_8xi16:
; X64-AVX1: # %bb.0: # %entry
-; X64-AVX1-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX1-NEXT: movq c(%rip), %rax
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
@@ -694,7 +694,7 @@ define void @mul_8xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
;
; X64-AVX2-LABEL: mul_8xi16:
; X64-AVX2: # %bb.0: # %entry
-; X64-AVX2-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX2-NEXT: movq c(%rip), %rax
; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; X64-AVX2-NEXT: vpmulld %ymm0, %ymm1, %ymm0
@@ -802,7 +802,7 @@ define void @mul_16xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i6
;
; X64-SSE-LABEL: mul_16xi16:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movdqu (%rdi,%rdx), %xmm0
; X64-SSE-NEXT: movdqu 16(%rdi,%rdx), %xmm1
; X64-SSE-NEXT: movdqu (%rsi,%rdx), %xmm2
@@ -827,7 +827,7 @@ define void @mul_16xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i6
;
; X64-AVX1-LABEL: mul_16xi16:
; X64-AVX1: # %bb.0: # %entry
-; X64-AVX1-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX1-NEXT: movq c(%rip), %rax
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
@@ -848,7 +848,7 @@ define void @mul_16xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i6
;
; X64-AVX2-LABEL: mul_16xi16:
; X64-AVX2: # %bb.0: # %entry
-; X64-AVX2-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX2-NEXT: movq c(%rip), %rax
; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
@@ -925,7 +925,7 @@ define void @mul_2xi8_sext(i8* nocapture readonly %a, i8* nocapture readonly %b,
;
; X64-SSE-LABEL: mul_2xi8_sext:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rdx), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: movzwl (%rsi,%rdx), %ecx
@@ -942,7 +942,7 @@ define void @mul_2xi8_sext(i8* nocapture readonly %a, i8* nocapture readonly %b,
;
; X64-AVX-LABEL: mul_2xi8_sext:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rdx), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
@@ -1019,7 +1019,7 @@ define void @mul_2xi8_sext_zext(i8* nocapture readonly %a, i8* nocapture readonl
;
; X64-SSE-LABEL: mul_2xi8_sext_zext:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rdx), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: movzwl (%rsi,%rdx), %ecx
@@ -1037,7 +1037,7 @@ define void @mul_2xi8_sext_zext(i8* nocapture readonly %a, i8* nocapture readonl
;
; X64-AVX-LABEL: mul_2xi8_sext_zext:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rdx), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
@@ -1106,7 +1106,7 @@ define void @mul_2xi16_sext(i8* nocapture readonly %a, i8* nocapture readonly %b
;
; X64-SSE-LABEL: mul_2xi16_sext:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movdqa %xmm1, %xmm2
@@ -1118,7 +1118,7 @@ define void @mul_2xi16_sext(i8* nocapture readonly %a, i8* nocapture readonly %b
;
; X64-AVX-LABEL: mul_2xi16_sext:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
; X64-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -1190,7 +1190,7 @@ define void @mul_2xi16_sext_zext(i8* nocapture readonly %a, i8* nocapture readon
;
; X64-SSE-LABEL: mul_2xi16_sext_zext:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X64-SSE-NEXT: psrad $16, %xmm0
@@ -1207,7 +1207,7 @@ define void @mul_2xi16_sext_zext(i8* nocapture readonly %a, i8* nocapture readon
;
; X64-AVX-LABEL: mul_2xi16_sext_zext:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
; X64-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -1316,7 +1316,7 @@ define void @mul_16xi16_sext(i8* nocapture readonly %a, i8* nocapture readonly %
;
; X64-SSE-LABEL: mul_16xi16_sext:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movdqu (%rdi,%rdx), %xmm0
; X64-SSE-NEXT: movdqu 16(%rdi,%rdx), %xmm1
; X64-SSE-NEXT: movdqu (%rsi,%rdx), %xmm2
@@ -1341,7 +1341,7 @@ define void @mul_16xi16_sext(i8* nocapture readonly %a, i8* nocapture readonly %
;
; X64-AVX1-LABEL: mul_16xi16_sext:
; X64-AVX1: # %bb.0: # %entry
-; X64-AVX1-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX1-NEXT: movq c(%rip), %rax
; X64-AVX1-NEXT: vpmovsxwd 24(%rdi,%rdx), %xmm0
; X64-AVX1-NEXT: vpmovsxwd 16(%rdi,%rdx), %xmm1
; X64-AVX1-NEXT: vpmovsxwd 8(%rdi,%rdx), %xmm2
@@ -1362,7 +1362,7 @@ define void @mul_16xi16_sext(i8* nocapture readonly %a, i8* nocapture readonly %
;
; X64-AVX2-LABEL: mul_16xi16_sext:
; X64-AVX2: # %bb.0: # %entry
-; X64-AVX2-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX2-NEXT: movq c(%rip), %rax
; X64-AVX2-NEXT: vpmovsxwd 16(%rdi,%rdx), %ymm0
; X64-AVX2-NEXT: vpmovsxwd (%rdi,%rdx), %ymm1
; X64-AVX2-NEXT: vpmovsxwd 16(%rsi,%rdx), %ymm2
@@ -1406,7 +1406,7 @@ define void @mul_2xi8_varconst1(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X86-SSE-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmaddwd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl
;
@@ -1418,29 +1418,29 @@ define void @mul_2xi8_varconst1(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X86-AVX-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi8_varconst1:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm1
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X64-SSE-NEXT: pmaddwd {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_2xi8_varconst1:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X64-AVX-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1471,7 +1471,7 @@ define void @mul_2xi8_varconst2(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-NEXT: movd %ecx, %xmm0
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
@@ -1485,18 +1485,18 @@ define void @mul_2xi8_varconst2(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi8_varconst2:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X64-SSE-NEXT: psraw $8, %xmm0
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X64-SSE-NEXT: psrad $16, %xmm0
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
@@ -1504,11 +1504,11 @@ define void @mul_2xi8_varconst2(i8* nocapture readonly %a, i64 %index) {
;
; X64-AVX-LABEL: mul_2xi8_varconst2:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1540,7 +1540,7 @@ define void @mul_2xi8_varconst3(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X86-SSE-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmaddwd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl
;
@@ -1552,29 +1552,29 @@ define void @mul_2xi8_varconst3(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X86-AVX-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi8_varconst3:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm1
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X64-SSE-NEXT: pmaddwd {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_2xi8_varconst3:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X64-AVX-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1621,13 +1621,13 @@ define void @mul_2xi8_varconst4(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi8_varconst4:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm1
@@ -1642,11 +1642,11 @@ define void @mul_2xi8_varconst4(i8* nocapture readonly %a, i64 %index) {
;
; X64-AVX-LABEL: mul_2xi8_varconst4:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1693,13 +1693,13 @@ define void @mul_2xi8_varconst5(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi8_varconst5:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
@@ -1714,11 +1714,11 @@ define void @mul_2xi8_varconst5(i8* nocapture readonly %a, i64 %index) {
;
; X64-AVX-LABEL: mul_2xi8_varconst5:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1765,13 +1765,13 @@ define void @mul_2xi8_varconst6(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi8_varconst6:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
@@ -1786,11 +1786,11 @@ define void @mul_2xi8_varconst6(i8* nocapture readonly %a, i64 %index) {
;
; X64-AVX-LABEL: mul_2xi8_varconst6:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-AVX-NEXT: vmovd %ecx, %xmm0
; X64-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1833,13 +1833,13 @@ define void @mul_2xi16_varconst1(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi16_varconst1:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,65535,u,u,u,u,u,u>
; X64-SSE-NEXT: movdqa %xmm0, %xmm2
@@ -1851,10 +1851,10 @@ define void @mul_2xi16_varconst1(i8* nocapture readonly %a, i64 %index) {
;
; X64-AVX-LABEL: mul_2xi16_varconst1:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1897,13 +1897,13 @@ define void @mul_2xi16_varconst2(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi16_varconst2:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <32768,32767,u,u,u,u,u,u>
; X64-SSE-NEXT: movdqa %xmm0, %xmm2
@@ -1915,10 +1915,10 @@ define void @mul_2xi16_varconst2(i8* nocapture readonly %a, i64 %index) {
;
; X64-AVX-LABEL: mul_2xi16_varconst2:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -1947,7 +1947,7 @@ define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: psrld $16, %xmm0
-; X86-SSE-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psllq $32, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl
@@ -1959,26 +1959,26 @@ define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi16_varconst3:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: psrld $16, %xmm0
-; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: psllq $32, %xmm0
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_2xi16_varconst3:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
@@ -2009,7 +2009,7 @@ define void @mul_2xi16_varconst4(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; X86-SSE-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psllq $32, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl
@@ -2021,28 +2021,28 @@ define void @mul_2xi16_varconst4(i8* nocapture readonly %a, i64 %index) {
; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
-; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: mul_2xi16_varconst4:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
+; X64-SSE-NEXT: movq c(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X64-SSE-NEXT: psrad $16, %xmm0
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: psllq $32, %xmm0
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_2xi16_varconst4:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
+; X64-AVX-NEXT: movq c(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
; X64-AVX-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll b/llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
index f36248d740598..ea6f1c597b698 100644
--- a/llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
+++ b/llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
@@ -155,7 +155,7 @@ define void @shuffle_v16i8_to_v4i8_2(<16 x i8>* %L, <4 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v4i8_2:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,1,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
@@ -464,7 +464,7 @@ define void @shuffle_v16i8_to_v2i8_2(<16 x i8>* %L, <2 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v2i8_2:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,3,2,3,4,5,6,7]
; SSE2-NEXT: packuswb %xmm0, %xmm0
@@ -543,7 +543,7 @@ define void @shuffle_v16i8_to_v2i8_4(<16 x i8>* %L, <2 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v2i8_4:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[2,0,2,3,4,5,6,7]
; SSE2-NEXT: packuswb %xmm0, %xmm0
@@ -622,7 +622,7 @@ define void @shuffle_v16i8_to_v2i8_6(<16 x i8>* %L, <2 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v2i8_6:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,1,2,3,4,5,6,7]
; SSE2-NEXT: packuswb %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
index c807eff7efe19..d02a1baf416d3 100644
--- a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
+++ b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
@@ -23,7 +23,7 @@ define void @shuffle_v16i8_to_v8i8(<16 x i8>* %L, <8 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v8i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: movq %xmm0, (%rsi)
; SSE2-NEXT: retq
@@ -78,7 +78,7 @@ define void @trunc_v8i16_to_v8i8(<16 x i8>* %L, <8 x i8>* %S) nounwind {
; SSE2-LABEL: trunc_v8i16_to_v8i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: movq %xmm0, (%rsi)
; SSE2-NEXT: retq
@@ -310,7 +310,7 @@ define void @shuffle_v16i8_to_v4i8(<16 x i8>* %L, <4 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v4i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: movd %xmm0, (%rsi)
@@ -365,7 +365,7 @@ define void @trunc_v4i32_to_v4i8(<16 x i8>* %L, <4 x i8>* %S) nounwind {
; SSE2-LABEL: trunc_v4i32_to_v4i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: movd %xmm0, (%rsi)
@@ -542,7 +542,7 @@ define void @shuffle_v16i8_to_v2i8(<16 x i8>* %L, <2 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v2i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
@@ -599,7 +599,7 @@ define void @trunc_v2i64_to_v2i8(<16 x i8>* %L, <2 x i8>* %S) nounwind {
; SSE2-LABEL: trunc_v2i64_to_v2i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/sibcall.ll b/llvm/test/CodeGen/X86/sibcall.ll
index 0effa4551e58b..1859efb98f346 100644
--- a/llvm/test/CodeGen/X86/sibcall.ll
+++ b/llvm/test/CodeGen/X86/sibcall.ll
@@ -706,7 +706,7 @@ define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret(%struct
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp)
-; X86-NEXT: calll f_sret
+; X86-NEXT: calll f_sret at PLT
; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $8, %esp
; X86-NEXT: popl %esi
@@ -716,7 +716,7 @@ define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret(%struct
; X64: # %bb.0:
; X64-NEXT: pushq %rbx
; X64-NEXT: movq %rdi, %rbx
-; X64-NEXT: callq f_sret
+; X64-NEXT: callq f_sret at PLT
; X64-NEXT: movq %rbx, %rax
; X64-NEXT: popq %rbx
; X64-NEXT: retq
@@ -725,7 +725,7 @@ define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret(%struct
; X32: # %bb.0:
; X32-NEXT: pushq %rbx
; X32-NEXT: movq %rdi, %rbx
-; X32-NEXT: callq f_sret
+; X32-NEXT: callq f_sret at PLT
; X32-NEXT: movl %ebx, %eax
; X32-NEXT: popq %rbx
; X32-NEXT: retq
@@ -778,7 +778,7 @@ define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret(%struc
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %edx, (%esp)
; X86-NEXT: movl %eax, %edx
-; X86-NEXT: calll f_sret
+; X86-NEXT: calll f_sret at PLT
; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $8, %esp
; X86-NEXT: popl %esi
@@ -791,7 +791,7 @@ define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret(%struc
; X64-NEXT: movq %rdi, %rbx
; X64-NEXT: movl %edx, %esi
; X64-NEXT: movl %eax, %edx
-; X64-NEXT: callq f_sret
+; X64-NEXT: callq f_sret at PLT
; X64-NEXT: movq %rbx, %rax
; X64-NEXT: popq %rbx
; X64-NEXT: retq
@@ -803,7 +803,7 @@ define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret(%struc
; X32-NEXT: movq %rdi, %rbx
; X32-NEXT: movl %edx, %esi
; X32-NEXT: movl %eax, %edx
-; X32-NEXT: callq f_sret
+; X32-NEXT: callq f_sret at PLT
; X32-NEXT: movl %ebx, %eax
; X32-NEXT: popq %rbx
; X32-NEXT: retq
@@ -890,7 +890,7 @@ define fastcc void @t21_sret_to_sret_arg_mismatch(%struct.foo* noalias sret(%str
; X86-NEXT: pushl %esi
; X86-NEXT: subl $8, %esp
; X86-NEXT: movl %ecx, %esi
-; X86-NEXT: calll ret_struct
+; X86-NEXT: calll ret_struct at PLT
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: calll t21_f_sret
; X86-NEXT: movl %esi, %eax
@@ -902,7 +902,7 @@ define fastcc void @t21_sret_to_sret_arg_mismatch(%struct.foo* noalias sret(%str
; X64: # %bb.0:
; X64-NEXT: pushq %rbx
; X64-NEXT: movq %rdi, %rbx
-; X64-NEXT: callq ret_struct
+; X64-NEXT: callq ret_struct at PLT
; X64-NEXT: movq %rax, %rdi
; X64-NEXT: callq t21_f_sret
; X64-NEXT: movq %rbx, %rax
@@ -913,7 +913,7 @@ define fastcc void @t21_sret_to_sret_arg_mismatch(%struct.foo* noalias sret(%str
; X32: # %bb.0:
; X32-NEXT: pushq %rbx
; X32-NEXT: movq %rdi, %rbx
-; X32-NEXT: callq ret_struct
+; X32-NEXT: callq ret_struct at PLT
; X32-NEXT: movl %eax, %edi
; X32-NEXT: callq t21_f_sret
; X32-NEXT: movl %ebx, %eax
@@ -932,7 +932,7 @@ define fastcc void @t21_sret_to_sret_structs_mismatch(%struct.foo* noalias sret(
; X86-NEXT: pushl %eax
; X86-NEXT: movl %edx, %esi
; X86-NEXT: movl %ecx, %edi
-; X86-NEXT: calll ret_struct
+; X86-NEXT: calll ret_struct at PLT
; X86-NEXT: movl %esi, %ecx
; X86-NEXT: movl %eax, %edx
; X86-NEXT: calll t21_f_sret2
@@ -949,7 +949,7 @@ define fastcc void @t21_sret_to_sret_structs_mismatch(%struct.foo* noalias sret(
; X64-NEXT: pushq %rax
; X64-NEXT: movq %rsi, %rbx
; X64-NEXT: movq %rdi, %r14
-; X64-NEXT: callq ret_struct
+; X64-NEXT: callq ret_struct at PLT
; X64-NEXT: movq %rbx, %rdi
; X64-NEXT: movq %rax, %rsi
; X64-NEXT: callq t21_f_sret2
@@ -966,7 +966,7 @@ define fastcc void @t21_sret_to_sret_structs_mismatch(%struct.foo* noalias sret(
; X32-NEXT: pushq %rax
; X32-NEXT: movq %rsi, %rbx
; X32-NEXT: movq %rdi, %r14
-; X32-NEXT: callq ret_struct
+; X32-NEXT: callq ret_struct at PLT
; X32-NEXT: movl %eax, %esi
; X32-NEXT: movq %rbx, %rdi
; X32-NEXT: callq t21_f_sret2
@@ -1023,21 +1023,21 @@ define ccc void @t22_non_sret_to_sret(%struct.foo* %agg.result) nounwind {
; X86-NEXT: subl $12, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp)
-; X86-NEXT: calll t22_f_sret
+; X86-NEXT: calll t22_f_sret at PLT
; X86-NEXT: addl $8, %esp
; X86-NEXT: retl
;
; X64-LABEL: t22_non_sret_to_sret:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
-; X64-NEXT: callq t22_f_sret
+; X64-NEXT: callq t22_f_sret at PLT
; X64-NEXT: popq %rax
; X64-NEXT: retq
;
; X32-LABEL: t22_non_sret_to_sret:
; X32: # %bb.0:
; X32-NEXT: pushq %rax
-; X32-NEXT: callq t22_f_sret
+; X32-NEXT: callq t22_f_sret at PLT
; X32-NEXT: popq %rax
; X32-NEXT: retq
tail call ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind
diff --git a/llvm/test/CodeGen/X86/signbit-shift.ll b/llvm/test/CodeGen/X86/signbit-shift.ll
index 45a2becb283a3..3db4e25577251 100644
--- a/llvm/test/CodeGen/X86/signbit-shift.ll
+++ b/llvm/test/CodeGen/X86/signbit-shift.ll
@@ -100,7 +100,7 @@ define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = sext <4 x i1> %c to <4 x i32>
@@ -113,7 +113,7 @@ define <4 x i32> @add_sext_ifpos_vec_nonsplat(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = sext <4 x i1> %c to <4 x i32>
@@ -224,7 +224,7 @@ define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_lshr_not_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
@@ -236,7 +236,7 @@ define <4 x i32> @add_lshr_not_vec_nonsplat(<4 x i32> %x) {
; CHECK-LABEL: add_lshr_not_vec_nonsplat:
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
@@ -261,7 +261,7 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: sub_lshr_not_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: psrld $31, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
@@ -273,7 +273,7 @@ define <4 x i32> @sub_lshr_not_vec_nonsplat(<4 x i32> %x) {
; CHECK-LABEL: sub_lshr_not_vec_nonsplat:
; CHECK: # %bb.0:
; CHECK-NEXT: psrld $31, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
@@ -321,7 +321,7 @@ define <4 x i32> @sub_const_op_lshr_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: sub_const_op_lshr_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
@@ -332,7 +332,7 @@ define <4 x i32> @sub_const_op_lshr_vec_nonsplat(<4 x i32> %x) {
; CHECK-LABEL: sub_const_op_lshr_vec_nonsplat:
; CHECK: # %bb.0:
; CHECK-NEXT: psrad $31, %xmm0
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %sh
diff --git a/llvm/test/CodeGen/X86/sink-addsub-of-const.ll b/llvm/test/CodeGen/X86/sink-addsub-of-const.ll
index 75241d9ea1b5d..9f08cc4cba32c 100644
--- a/llvm/test/CodeGen/X86/sink-addsub-of-const.ll
+++ b/llvm/test/CodeGen/X86/sink-addsub-of-const.ll
@@ -261,13 +261,13 @@ define <4 x i32> @vec_sink_add_of_const_to_add0(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_add0:
; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0
-; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_add_of_const_to_add0:
; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0
-; X64-NEXT: paddd {{.*}}(%rip), %xmm0
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
%r = add <4 x i32> %t0, %b
@@ -277,13 +277,13 @@ define <4 x i32> @vec_sink_add_of_const_to_add1(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_add1:
; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0
-; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_add_of_const_to_add1:
; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0
-; X64-NEXT: paddd {{.*}}(%rip), %xmm0
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
%r = add <4 x i32> %b, %t0
@@ -297,13 +297,13 @@ define <4 x i32> @vec_sink_sub_of_const_to_add0(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_add0:
; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0
-; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_sub_of_const_to_add0:
; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0
-; X64-NEXT: psubd {{.*}}(%rip), %xmm0
+; X64-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46>
%r = add <4 x i32> %t0, %b
@@ -313,13 +313,13 @@ define <4 x i32> @vec_sink_sub_of_const_to_add1(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_add1:
; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0
-; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_sub_of_const_to_add1:
; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0
-; X64-NEXT: psubd {{.*}}(%rip), %xmm0
+; X64-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46>
%r = add <4 x i32> %b, %t0
@@ -333,14 +333,14 @@ define <4 x i32> @vec_sink_sub_from_const_to_add0(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_from_const_to_add0:
; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1
-; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_sub_from_const_to_add0:
; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1
-; X64-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
@@ -351,14 +351,14 @@ define <4 x i32> @vec_sink_sub_from_const_to_add1(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_from_const_to_add1:
; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1
-; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_sub_from_const_to_add1:
; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1
-; X64-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
@@ -373,13 +373,13 @@ define <4 x i32> @vec_sink_add_of_const_to_sub(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_sub:
; X32: # %bb.0:
; X32-NEXT: psubd %xmm1, %xmm0
-; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_add_of_const_to_sub:
; X64: # %bb.0:
; X64-NEXT: psubd %xmm1, %xmm0
-; X64-NEXT: paddd {{.*}}(%rip), %xmm0
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
%r = sub <4 x i32> %t0, %b
@@ -389,14 +389,14 @@ define <4 x i32> @vec_sink_add_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_sub2:
; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1
-; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_add_of_const_to_sub2:
; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1
-; X64-NEXT: psubd {{.*}}(%rip), %xmm1
+; X64-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
@@ -411,13 +411,13 @@ define <4 x i32> @vec_sink_sub_of_const_to_sub(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_sub:
; X32: # %bb.0:
; X32-NEXT: psubd %xmm1, %xmm0
-; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_sub_of_const_to_sub:
; X64: # %bb.0:
; X64-NEXT: psubd %xmm1, %xmm0
-; X64-NEXT: psubd {{.*}}(%rip), %xmm0
+; X64-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46>
%r = sub <4 x i32> %t0, %b
@@ -427,14 +427,14 @@ define <4 x i32> @vec_sink_sub_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_sub2:
; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1
-; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_sub_of_const_to_sub2:
; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1
-; X64-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
%t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46>
@@ -461,13 +461,13 @@ define <4 x i32> @vec_sink_sub_from_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_from_const_to_sub2:
; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0
-; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: vec_sink_sub_from_const_to_sub2:
; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0
-; X64-NEXT: psubd {{.*}}(%rip), %xmm0
+; X64-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
%r = sub <4 x i32> %b, %t0
diff --git a/llvm/test/CodeGen/X86/small-byval-memcpy.ll b/llvm/test/CodeGen/X86/small-byval-memcpy.ll
index 12498123e3ac3..0d63fd4cf9d95 100644
--- a/llvm/test/CodeGen/X86/small-byval-memcpy.ll
+++ b/llvm/test/CodeGen/X86/small-byval-memcpy.ll
@@ -23,8 +23,8 @@ define void @copy16bytes(i8* nocapture %a, i8* nocapture readonly %b) {
;
; BDVER2-LABEL: copy16bytes:
; BDVER2: ## %bb.0:
-; BDVER2-NEXT: movups (%rsi), %xmm0
-; BDVER2-NEXT: movups %xmm0, (%rdi)
+; BDVER2-NEXT: vmovups (%rsi), %xmm0
+; BDVER2-NEXT: vmovups %xmm0, (%rdi)
; BDVER2-NEXT: retq
;
; BTVER2-LABEL: copy16bytes:
diff --git a/llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll b/llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll
index cf33a4a20524b..f2b0a6e186305 100644
--- a/llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll
+++ b/llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll
@@ -18,11 +18,11 @@ define fp128 @TestSelect(fp128 %a, fp128 %b) {
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq __gttf2
+; CHECK-NEXT: callq __gttf2 at PLT
; CHECK-NEXT: movl %eax, %ebx
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq __subtf3
+; CHECK-NEXT: callq __subtf3 at PLT
; CHECK-NEXT: testl %ebx, %ebx
; CHECK-NEXT: jg .LBB0_2
; CHECK-NEXT: # %bb.1:
@@ -42,7 +42,7 @@ define fp128 @TestSelect(fp128 %a, fp128 %b) {
define fp128 @TestFabs(fp128 %a) {
; CHECK-LABEL: TestFabs:
; CHECK: # %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%res = call fp128 @llvm.fabs.f128(fp128 %a)
ret fp128 %res
@@ -51,8 +51,8 @@ define fp128 @TestFabs(fp128 %a) {
define fp128 @TestCopysign(fp128 %a, fp128 %b) {
; CHECK-LABEL: TestCopysign:
; CHECK: # %bb.0:
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
-; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: orps %xmm1, %xmm0
; CHECK-NEXT: retq
%res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %b)
@@ -65,8 +65,8 @@ define fp128 @TestFneg(fp128 %a) {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: callq __multf3
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: callq __multf3 at PLT
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
index a7a26ed27ce32..b29400a1b9c3c 100644
--- a/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
@@ -19,7 +19,7 @@ define i32 @test_calls_and_rets(i32 *%ptr) nounwind {
; X64-NOPIC-NEXT: sarq $63, %rax
; X64-NOPIC-NEXT: shlq $47, %rax
; X64-NOPIC-NEXT: orq %rax, %rsp
-; X64-NOPIC-NEXT: callq f
+; X64-NOPIC-NEXT: callq f at PLT
; X64-NOPIC-NEXT: .Lslh_ret_addr0:
; X64-NOPIC-NEXT: movq %rsp, %rax
; X64-NOPIC-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -29,7 +29,7 @@ define i32 @test_calls_and_rets(i32 *%ptr) nounwind {
; X64-NOPIC-NEXT: movl (%rbx), %ebp
; X64-NOPIC-NEXT: shlq $47, %rax
; X64-NOPIC-NEXT: orq %rax, %rsp
-; X64-NOPIC-NEXT: callq f
+; X64-NOPIC-NEXT: callq f at PLT
; X64-NOPIC-NEXT: .Lslh_ret_addr1:
; X64-NOPIC-NEXT: movq %rsp, %rcx
; X64-NOPIC-NEXT: movq -{{[0-9]+}}(%rsp), %rax
@@ -57,7 +57,7 @@ define i32 @test_calls_and_rets(i32 *%ptr) nounwind {
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT: callq f
+; X64-NOPIC-MCM-NEXT: callq f at PLT
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr0:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -68,7 +68,7 @@ define i32 @test_calls_and_rets(i32 *%ptr) nounwind {
; X64-NOPIC-MCM-NEXT: movl (%rbx), %ebp
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT: callq f
+; X64-NOPIC-MCM-NEXT: callq f at PLT
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr1:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rcx
; X64-NOPIC-MCM-NEXT: movq -{{[0-9]+}}(%rsp), %rax
@@ -149,7 +149,7 @@ define i32 @test_calls_and_rets_noredzone(i32 *%ptr) nounwind noredzone {
; X64-NOPIC-NEXT: shlq $47, %rax
; X64-NOPIC-NEXT: orq %rax, %rsp
; X64-NOPIC-NEXT: movq $.Lslh_ret_addr2, %rbp
-; X64-NOPIC-NEXT: callq f
+; X64-NOPIC-NEXT: callq f at PLT
; X64-NOPIC-NEXT: .Lslh_ret_addr2:
; X64-NOPIC-NEXT: movq %rsp, %rax
; X64-NOPIC-NEXT: sarq $63, %rax
@@ -159,7 +159,7 @@ define i32 @test_calls_and_rets_noredzone(i32 *%ptr) nounwind noredzone {
; X64-NOPIC-NEXT: shlq $47, %rax
; X64-NOPIC-NEXT: orq %rax, %rsp
; X64-NOPIC-NEXT: movq $.Lslh_ret_addr3, %r15
-; X64-NOPIC-NEXT: callq f
+; X64-NOPIC-NEXT: callq f at PLT
; X64-NOPIC-NEXT: .Lslh_ret_addr3:
; X64-NOPIC-NEXT: movq %rsp, %rcx
; X64-NOPIC-NEXT: sarq $63, %rcx
@@ -191,7 +191,7 @@ define i32 @test_calls_and_rets_noredzone(i32 *%ptr) nounwind noredzone {
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr2(%rip), %rbp
-; X64-NOPIC-MCM-NEXT: callq f
+; X64-NOPIC-MCM-NEXT: callq f at PLT
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr2:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
@@ -202,7 +202,7 @@ define i32 @test_calls_and_rets_noredzone(i32 *%ptr) nounwind noredzone {
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr3(%rip), %r15
-; X64-NOPIC-MCM-NEXT: callq f
+; X64-NOPIC-MCM-NEXT: callq f at PLT
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr3:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rcx
; X64-NOPIC-MCM-NEXT: sarq $63, %rcx
@@ -296,7 +296,7 @@ define i32 @test_call_setjmp(i32 *%ptr) nounwind {
; X64-NOPIC-NEXT: movq %r14, %rdi
; X64-NOPIC-NEXT: orq %rax, %rsp
; X64-NOPIC-NEXT: movq $.Lslh_ret_addr4, %rbp
-; X64-NOPIC-NEXT: callq setjmp
+; X64-NOPIC-NEXT: callq setjmp at PLT
; X64-NOPIC-NEXT: .Lslh_ret_addr4:
; X64-NOPIC-NEXT: movq %rsp, %rax
; X64-NOPIC-NEXT: sarq $63, %rax
@@ -309,7 +309,7 @@ define i32 @test_call_setjmp(i32 *%ptr) nounwind {
; X64-NOPIC-NEXT: movl %r12d, %esi
; X64-NOPIC-NEXT: orq %rax, %rsp
; X64-NOPIC-NEXT: movq $.Lslh_ret_addr5, %r13
-; X64-NOPIC-NEXT: callq sigsetjmp
+; X64-NOPIC-NEXT: callq sigsetjmp at PLT
; X64-NOPIC-NEXT: .Lslh_ret_addr5:
; X64-NOPIC-NEXT: movq %rsp, %rax
; X64-NOPIC-NEXT: sarq $63, %rax
@@ -322,7 +322,7 @@ define i32 @test_call_setjmp(i32 *%ptr) nounwind {
; X64-NOPIC-NEXT: movl %r12d, %edx
; X64-NOPIC-NEXT: orq %rax, %rsp
; X64-NOPIC-NEXT: movq $.Lslh_ret_addr6, %r14
-; X64-NOPIC-NEXT: callq __sigsetjmp
+; X64-NOPIC-NEXT: callq __sigsetjmp at PLT
; X64-NOPIC-NEXT: .Lslh_ret_addr6:
; X64-NOPIC-NEXT: movq %rsp, %rax
; X64-NOPIC-NEXT: sarq $63, %rax
@@ -361,7 +361,7 @@ define i32 @test_call_setjmp(i32 *%ptr) nounwind {
; X64-NOPIC-MCM-NEXT: movq %r14, %rdi
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr4(%rip), %rbp
-; X64-NOPIC-MCM-NEXT: callq setjmp
+; X64-NOPIC-MCM-NEXT: callq setjmp at PLT
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr4:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
@@ -375,7 +375,7 @@ define i32 @test_call_setjmp(i32 *%ptr) nounwind {
; X64-NOPIC-MCM-NEXT: movl %r12d, %esi
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr5(%rip), %r13
-; X64-NOPIC-MCM-NEXT: callq sigsetjmp
+; X64-NOPIC-MCM-NEXT: callq sigsetjmp at PLT
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr5:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
@@ -389,7 +389,7 @@ define i32 @test_call_setjmp(i32 *%ptr) nounwind {
; X64-NOPIC-MCM-NEXT: movl %r12d, %edx
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr6(%rip), %r14
-; X64-NOPIC-MCM-NEXT: callq __sigsetjmp
+; X64-NOPIC-MCM-NEXT: callq __sigsetjmp at PLT
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr6:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
index cb3ce4e52538b..7d0dff9dcca4d 100644
--- a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
@@ -58,7 +58,7 @@ define dso_local i32 @test_indirect_call(i32 ()** %ptr) nounwind {
; X64-PIC-NEXT: movq %rsp, %rcx
; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
; X64-PIC-NEXT: sarq $63, %rcx
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .Lslh_ret_addr0(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rbx, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -139,7 +139,7 @@ define dso_local i32 @test_indirect_call_global() nounwind {
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq $-1, %rbx
; X64-NEXT: sarq $63, %rax
-; X64-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
+; X64-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
; X64-NEXT: movq (%rcx), %rcx
; X64-NEXT: orq %rax, %rcx
; X64-NEXT: shlq $47, %rax
@@ -162,7 +162,7 @@ define dso_local i32 @test_indirect_call_global() nounwind {
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: movq $-1, %rbx
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
+; X64-PIC-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
; X64-PIC-NEXT: movq (%rcx), %rcx
; X64-PIC-NEXT: orq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rax
@@ -172,7 +172,7 @@ define dso_local i32 @test_indirect_call_global() nounwind {
; X64-PIC-NEXT: movq %rsp, %rcx
; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
; X64-PIC-NEXT: sarq $63, %rcx
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .Lslh_ret_addr1(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rbx, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -186,7 +186,7 @@ define dso_local i32 @test_indirect_call_global() nounwind {
; X64-RETPOLINE-NEXT: movq %rsp, %rax
; X64-RETPOLINE-NEXT: movq $-1, %rbx
; X64-RETPOLINE-NEXT: sarq $63, %rax
-; X64-RETPOLINE-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
+; X64-RETPOLINE-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
; X64-RETPOLINE-NEXT: movq (%rcx), %r11
; X64-RETPOLINE-NEXT: orq %rax, %r11
; X64-RETPOLINE-NEXT: shlq $47, %rax
@@ -214,7 +214,7 @@ define dso_local i32 @test_indirect_tail_call_global() nounwind {
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: sarq $63, %rax
-; X64-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
+; X64-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
; X64-NEXT: movq (%rcx), %rcx
; X64-NEXT: orq %rax, %rcx
; X64-NEXT: shlq $47, %rax
@@ -226,7 +226,7 @@ define dso_local i32 @test_indirect_tail_call_global() nounwind {
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: movq $-1, %rcx
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
+; X64-PIC-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
; X64-PIC-NEXT: movq (%rcx), %rcx
; X64-PIC-NEXT: orq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rax
@@ -238,7 +238,7 @@ define dso_local i32 @test_indirect_tail_call_global() nounwind {
; X64-RETPOLINE-NEXT: movq %rsp, %rax
; X64-RETPOLINE-NEXT: movq $-1, %rcx
; X64-RETPOLINE-NEXT: sarq $63, %rax
-; X64-RETPOLINE-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
+; X64-RETPOLINE-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
; X64-RETPOLINE-NEXT: movq (%rcx), %r11
; X64-RETPOLINE-NEXT: orq %rax, %r11
; X64-RETPOLINE-NEXT: shlq $47, %rax
@@ -302,7 +302,7 @@ define dso_local i32 @test_indirectbr(i8** %ptr) nounwind {
; X64-PIC-NEXT: jmpq *%rdx
; X64-PIC-NEXT: .LBB4_1: # Block address taken
; X64-PIC-NEXT: # %bb0
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB4_1(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -311,7 +311,7 @@ define dso_local i32 @test_indirectbr(i8** %ptr) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .LBB4_3: # Block address taken
; X64-PIC-NEXT: # %bb2
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB4_3(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -320,7 +320,7 @@ define dso_local i32 @test_indirectbr(i8** %ptr) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .LBB4_4: # Block address taken
; X64-PIC-NEXT: # %bb3
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB4_4(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -329,7 +329,7 @@ define dso_local i32 @test_indirectbr(i8** %ptr) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .LBB4_2: # Block address taken
; X64-PIC-NEXT: # %bb1
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB4_2(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -411,7 +411,7 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-PIC-NEXT: jmpq *%rdx
; X64-PIC-NEXT: .Ltmp0: # Block address taken
; X64-PIC-NEXT: .LBB5_1: # %bb0
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB5_1(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -420,7 +420,7 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .Ltmp1: # Block address taken
; X64-PIC-NEXT: .LBB5_3: # %bb2
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB5_3(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -429,7 +429,7 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .Ltmp2: # Block address taken
; X64-PIC-NEXT: .LBB5_4: # %bb3
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB5_4(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -438,7 +438,7 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .Ltmp3: # Block address taken
; X64-PIC-NEXT: .LBB5_2: # %bb1
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB5_2(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -575,14 +575,14 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
; X64-PIC-NEXT: # %bb.1: # %entry
; X64-PIC-NEXT: cmovaq %rax, %rcx
; X64-PIC-NEXT: movl %edi, %edx
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LJTI6_0(%rip), %rsi
; X64-PIC-NEXT: movslq (%rsi,%rdx,4), %rdx
; X64-PIC-NEXT: addq %rsi, %rdx
; X64-PIC-NEXT: orq %rcx, %rdx
; X64-PIC-NEXT: jmpq *%rdx
; X64-PIC-NEXT: .LBB6_3: # Block address taken
; X64-PIC-NEXT: # %bb1
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB6_3(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -597,7 +597,7 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .LBB6_4: # Block address taken
; X64-PIC-NEXT: # %bb2
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB6_4(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -606,7 +606,7 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .LBB6_5: # Block address taken
; X64-PIC-NEXT: # %bb3
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB6_5(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -615,7 +615,7 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .LBB6_6: # Block address taken
; X64-PIC-NEXT: # %bb5
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB6_6(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -764,7 +764,7 @@ define dso_local i32 @test_switch_jumptable_fallthrough(i32 %idx, i32* %a.ptr, i
; X64-PIC-NEXT: cmovaq %r10, %r9
; X64-PIC-NEXT: xorl %eax, %eax
; X64-PIC-NEXT: movl %edi, %esi
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdi
+; X64-PIC-NEXT: leaq .LJTI7_0(%rip), %rdi
; X64-PIC-NEXT: movslq (%rdi,%rsi,4), %rsi
; X64-PIC-NEXT: addq %rdi, %rsi
; X64-PIC-NEXT: orq %r9, %rsi
@@ -773,34 +773,34 @@ define dso_local i32 @test_switch_jumptable_fallthrough(i32 %idx, i32* %a.ptr, i
; X64-PIC-NEXT: cmovbeq %r10, %r9
; X64-PIC-NEXT: movl (%rsi), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB7_3(%rip), %rsi
; X64-PIC-NEXT: .LBB7_3: # Block address taken
; X64-PIC-NEXT: # %bb1
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdi
+; X64-PIC-NEXT: leaq .LBB7_3(%rip), %rdi
; X64-PIC-NEXT: cmpq %rdi, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: addl (%rdx), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB7_4(%rip), %rsi
; X64-PIC-NEXT: .LBB7_4: # Block address taken
; X64-PIC-NEXT: # %bb2
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdx
+; X64-PIC-NEXT: leaq .LBB7_4(%rip), %rdx
; X64-PIC-NEXT: cmpq %rdx, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: addl (%rcx), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB7_5(%rip), %rsi
; X64-PIC-NEXT: .LBB7_5: # Block address taken
; X64-PIC-NEXT: # %bb3
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx
+; X64-PIC-NEXT: leaq .LBB7_5(%rip), %rcx
; X64-PIC-NEXT: cmpq %rcx, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: addl (%r8), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .LBB7_6(%rip), %rsi
; X64-PIC-NEXT: .LBB7_6: # Block address taken
; X64-PIC-NEXT: # %bb4
-; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx
+; X64-PIC-NEXT: leaq .LBB7_6(%rip), %rcx
; X64-PIC-NEXT: cmpq %rcx, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: shlq $47, %r9
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening.ll b/llvm/test/CodeGen/X86/speculative-load-hardening.ll
index c20964fcdaca2..a686833119280 100644
--- a/llvm/test/CodeGen/X86/speculative-load-hardening.ll
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening.ll
@@ -89,7 +89,7 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %ptr
; X64-NEXT: shlq $47, %rax
; X64-NEXT: # kill: def $edi killed $edi killed $rdi
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq leak
+; X64-NEXT: callq leak at PLT
; X64-NEXT: .Lslh_ret_addr0:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -138,7 +138,7 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %ptr
; X64-LFENCE-NEXT: movq (%r9), %r14
; X64-LFENCE-NEXT: addl (%r14), %esi
; X64-LFENCE-NEXT: # kill: def $edi killed $edi killed $rdi
-; X64-LFENCE-NEXT: callq leak
+; X64-LFENCE-NEXT: callq leak at PLT
; X64-LFENCE-NEXT: .LBB1_5: # %merge
; X64-LFENCE-NEXT: movslq (%r14), %rax
; X64-LFENCE-NEXT: movl $0, (%rbx,%rax,4)
@@ -225,7 +225,7 @@ define void @test_basic_loop(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2) nounwind sp
; X64-NEXT: movl (%rdx,%rcx,4), %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr1:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -271,7 +271,7 @@ define void @test_basic_loop(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2) nounwind sp
; X64-LFENCE-NEXT: lfence
; X64-LFENCE-NEXT: movslq (%r15), %rax
; X64-LFENCE-NEXT: movl (%r14,%rax,4), %edi
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: incl %ebx
; X64-LFENCE-NEXT: cmpl %ebp, %ebx
; X64-LFENCE-NEXT: jl .LBB2_2
@@ -343,7 +343,7 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %pt
; X64-NEXT: movl (%rdx,%rcx,4), %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr2:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -372,7 +372,7 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %pt
; X64-NEXT: movl (%rdx,%rcx,4), %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr3:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -436,7 +436,7 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %pt
; X64-LFENCE-NEXT: lfence
; X64-LFENCE-NEXT: movslq (%rbx), %rax
; X64-LFENCE-NEXT: movl (%r14,%rax,4), %edi
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: incl %r12d
; X64-LFENCE-NEXT: cmpl %r15d, %r12d
; X64-LFENCE-NEXT: jge .LBB3_6
@@ -457,7 +457,7 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %pt
; X64-LFENCE-NEXT: lfence
; X64-LFENCE-NEXT: movslq (%rbx), %rax
; X64-LFENCE-NEXT: movl (%r14,%rax,4), %edi
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: incl %ebp
; X64-LFENCE-NEXT: cmpl %r13d, %ebp
; X64-LFENCE-NEXT: jl .LBB3_4
@@ -501,142 +501,6 @@ declare i8* @__cxa_allocate_exception(i64) local_unnamed_addr
declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr
define void @test_basic_eh(i32 %a, i32* %ptr1, i32* %ptr2) speculative_load_hardening personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
-; X64-LABEL: test_basic_eh:
-; X64: # %bb.0: # %entry
-; X64-NEXT: pushq %rbp
-; X64-NEXT: .cfi_def_cfa_offset 16
-; X64-NEXT: pushq %r15
-; X64-NEXT: .cfi_def_cfa_offset 24
-; X64-NEXT: pushq %r14
-; X64-NEXT: .cfi_def_cfa_offset 32
-; X64-NEXT: pushq %rbx
-; X64-NEXT: .cfi_def_cfa_offset 40
-; X64-NEXT: pushq %rax
-; X64-NEXT: .cfi_def_cfa_offset 48
-; X64-NEXT: .cfi_offset %rbx, -40
-; X64-NEXT: .cfi_offset %r14, -32
-; X64-NEXT: .cfi_offset %r15, -24
-; X64-NEXT: .cfi_offset %rbp, -16
-; X64-NEXT: movq %rsp, %rax
-; X64-NEXT: movq $-1, %r15
-; X64-NEXT: sarq $63, %rax
-; X64-NEXT: cmpl $41, %edi
-; X64-NEXT: jg .LBB4_1
-; X64-NEXT: # %bb.2: # %thrower
-; X64-NEXT: movq %rdx, %r14
-; X64-NEXT: movq %rsi, %rbx
-; X64-NEXT: cmovgq %r15, %rax
-; X64-NEXT: movslq %edi, %rcx
-; X64-NEXT: movl (%rsi,%rcx,4), %ebp
-; X64-NEXT: orl %eax, %ebp
-; X64-NEXT: movl $4, %edi
-; X64-NEXT: shlq $47, %rax
-; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq __cxa_allocate_exception
-; X64-NEXT: .Lslh_ret_addr4:
-; X64-NEXT: movq %rsp, %rcx
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
-; X64-NEXT: sarq $63, %rcx
-; X64-NEXT: cmpq $.Lslh_ret_addr4, %rdx
-; X64-NEXT: cmovneq %r15, %rcx
-; X64-NEXT: movl %ebp, (%rax)
-; X64-NEXT: .Ltmp0:
-; X64-NEXT: shlq $47, %rcx
-; X64-NEXT: movq %rax, %rdi
-; X64-NEXT: xorl %esi, %esi
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: orq %rcx, %rsp
-; X64-NEXT: callq __cxa_throw
-; X64-NEXT: .Lslh_ret_addr5:
-; X64-NEXT: movq %rsp, %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
-; X64-NEXT: sarq $63, %rax
-; X64-NEXT: cmpq $.Lslh_ret_addr5, %rcx
-; X64-NEXT: cmovneq %r15, %rax
-; X64-NEXT: .Ltmp1:
-; X64-NEXT: jmp .LBB4_3
-; X64-NEXT: .LBB4_1:
-; X64-NEXT: cmovleq %r15, %rax
-; X64-NEXT: .LBB4_3: # %exit
-; X64-NEXT: shlq $47, %rax
-; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: addq $8, %rsp
-; X64-NEXT: .cfi_def_cfa_offset 40
-; X64-NEXT: popq %rbx
-; X64-NEXT: .cfi_def_cfa_offset 32
-; X64-NEXT: popq %r14
-; X64-NEXT: .cfi_def_cfa_offset 24
-; X64-NEXT: popq %r15
-; X64-NEXT: .cfi_def_cfa_offset 16
-; X64-NEXT: popq %rbp
-; X64-NEXT: .cfi_def_cfa_offset 8
-; X64-NEXT: retq
-; X64-NEXT: .LBB4_4: # %lpad
-; X64-NEXT: .cfi_def_cfa_offset 48
-; X64-NEXT: .Ltmp2:
-; X64-NEXT: movq %rsp, %rcx
-; X64-NEXT: sarq $63, %rcx
-; X64-NEXT: movl (%rax), %eax
-; X64-NEXT: addl (%rbx), %eax
-; X64-NEXT: cltq
-; X64-NEXT: orq %rcx, %rax
-; X64-NEXT: movl (%r14,%rax,4), %edi
-; X64-NEXT: orl %ecx, %edi
-; X64-NEXT: shlq $47, %rcx
-; X64-NEXT: orq %rcx, %rsp
-; X64-NEXT: callq sink
-; X64-NEXT: .Lslh_ret_addr6:
-; X64-NEXT: movq %rsp, %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
-; X64-NEXT: sarq $63, %rax
-; X64-NEXT: cmpq $.Lslh_ret_addr6, %rcx
-; X64-NEXT: cmovneq %r15, %rax
-;
-; X64-LFENCE-LABEL: test_basic_eh:
-; X64-LFENCE: # %bb.0: # %entry
-; X64-LFENCE-NEXT: pushq %rbp
-; X64-LFENCE-NEXT: .cfi_def_cfa_offset 16
-; X64-LFENCE-NEXT: pushq %r14
-; X64-LFENCE-NEXT: .cfi_def_cfa_offset 24
-; X64-LFENCE-NEXT: pushq %rbx
-; X64-LFENCE-NEXT: .cfi_def_cfa_offset 32
-; X64-LFENCE-NEXT: .cfi_offset %rbx, -32
-; X64-LFENCE-NEXT: .cfi_offset %r14, -24
-; X64-LFENCE-NEXT: .cfi_offset %rbp, -16
-; X64-LFENCE-NEXT: cmpl $41, %edi
-; X64-LFENCE-NEXT: jg .LBB4_2
-; X64-LFENCE-NEXT: # %bb.1: # %thrower
-; X64-LFENCE-NEXT: movq %rdx, %r14
-; X64-LFENCE-NEXT: movq %rsi, %rbx
-; X64-LFENCE-NEXT: lfence
-; X64-LFENCE-NEXT: movslq %edi, %rax
-; X64-LFENCE-NEXT: movl (%rsi,%rax,4), %ebp
-; X64-LFENCE-NEXT: movl $4, %edi
-; X64-LFENCE-NEXT: callq __cxa_allocate_exception
-; X64-LFENCE-NEXT: movl %ebp, (%rax)
-; X64-LFENCE-NEXT: .Ltmp0:
-; X64-LFENCE-NEXT: movq %rax, %rdi
-; X64-LFENCE-NEXT: xorl %esi, %esi
-; X64-LFENCE-NEXT: xorl %edx, %edx
-; X64-LFENCE-NEXT: callq __cxa_throw
-; X64-LFENCE-NEXT: .Ltmp1:
-; X64-LFENCE-NEXT: .LBB4_2: # %exit
-; X64-LFENCE-NEXT: lfence
-; X64-LFENCE-NEXT: popq %rbx
-; X64-LFENCE-NEXT: .cfi_def_cfa_offset 24
-; X64-LFENCE-NEXT: popq %r14
-; X64-LFENCE-NEXT: .cfi_def_cfa_offset 16
-; X64-LFENCE-NEXT: popq %rbp
-; X64-LFENCE-NEXT: .cfi_def_cfa_offset 8
-; X64-LFENCE-NEXT: retq
-; X64-LFENCE-NEXT: .LBB4_3: # %lpad
-; X64-LFENCE-NEXT: .cfi_def_cfa_offset 32
-; X64-LFENCE-NEXT: .Ltmp2:
-; X64-LFENCE-NEXT: movl (%rax), %eax
-; X64-LFENCE-NEXT: addl (%rbx), %eax
-; X64-LFENCE-NEXT: cltq
-; X64-LFENCE-NEXT: movl (%r14,%rax,4), %edi
-; X64-LFENCE-NEXT: callq sink
entry:
%a.cmp = icmp slt i32 %a, 42
br i1 %a.cmp, label %thrower, label %exit
@@ -690,7 +554,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_float
+; X64-NEXT: callq sink_float at PLT
; X64-NEXT: .Lslh_ret_addr7:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -701,7 +565,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_double
+; X64-NEXT: callq sink_double at PLT
; X64-NEXT: .Lslh_ret_addr8:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -712,7 +576,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: cvtsd2ss %xmm0, %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_float
+; X64-NEXT: callq sink_float at PLT
; X64-NEXT: .Lslh_ret_addr9:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -723,7 +587,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: cvtss2sd %xmm0, %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_double
+; X64-NEXT: callq sink_double at PLT
; X64-NEXT: .Lslh_ret_addr10:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -735,7 +599,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: cvtsi2ssl (%r14), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_float
+; X64-NEXT: callq sink_float at PLT
; X64-NEXT: .Lslh_ret_addr11:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -747,7 +611,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: cvtsi2sdq (%r15), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_double
+; X64-NEXT: callq sink_double at PLT
; X64-NEXT: .Lslh_ret_addr12:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -758,7 +622,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: cvtsi2ssq (%r15), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_float
+; X64-NEXT: callq sink_float at PLT
; X64-NEXT: .Lslh_ret_addr13:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -769,7 +633,7 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-NEXT: cvtsi2sdl (%r14), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_double
+; X64-NEXT: callq sink_double at PLT
; X64-NEXT: .Lslh_ret_addr14:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -797,27 +661,27 @@ define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64p
; X64-LFENCE-NEXT: movq %rsi, %rbx
; X64-LFENCE-NEXT: movq %rdi, %r12
; X64-LFENCE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-LFENCE-NEXT: callq sink_float
+; X64-LFENCE-NEXT: callq sink_float at PLT
; X64-LFENCE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X64-LFENCE-NEXT: callq sink_double
+; X64-LFENCE-NEXT: callq sink_double at PLT
; X64-LFENCE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X64-LFENCE-NEXT: cvtsd2ss %xmm0, %xmm0
-; X64-LFENCE-NEXT: callq sink_float
+; X64-LFENCE-NEXT: callq sink_float at PLT
; X64-LFENCE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-LFENCE-NEXT: cvtss2sd %xmm0, %xmm0
-; X64-LFENCE-NEXT: callq sink_double
+; X64-LFENCE-NEXT: callq sink_double at PLT
; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
; X64-LFENCE-NEXT: cvtsi2ssl (%r14), %xmm0
-; X64-LFENCE-NEXT: callq sink_float
+; X64-LFENCE-NEXT: callq sink_float at PLT
; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
; X64-LFENCE-NEXT: cvtsi2sdq (%r15), %xmm0
-; X64-LFENCE-NEXT: callq sink_double
+; X64-LFENCE-NEXT: callq sink_double at PLT
; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
; X64-LFENCE-NEXT: cvtsi2ssq (%r15), %xmm0
-; X64-LFENCE-NEXT: callq sink_float
+; X64-LFENCE-NEXT: callq sink_float at PLT
; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
; X64-LFENCE-NEXT: cvtsi2sdl (%r14), %xmm0
-; X64-LFENCE-NEXT: callq sink_double
+; X64-LFENCE-NEXT: callq sink_double at PLT
; X64-LFENCE-NEXT: addq $8, %rsp
; X64-LFENCE-NEXT: popq %rbx
; X64-LFENCE-NEXT: popq %r12
@@ -880,7 +744,7 @@ define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16
; X64-NEXT: movaps (%rdi), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_v4f32
+; X64-NEXT: callq sink_v4f32 at PLT
; X64-NEXT: .Lslh_ret_addr15:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -891,7 +755,7 @@ define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16
; X64-NEXT: movaps (%rbx), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_v2f64
+; X64-NEXT: callq sink_v2f64 at PLT
; X64-NEXT: .Lslh_ret_addr16:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -902,7 +766,7 @@ define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16
; X64-NEXT: movaps (%r13), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_v16i8
+; X64-NEXT: callq sink_v16i8 at PLT
; X64-NEXT: .Lslh_ret_addr17:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -913,7 +777,7 @@ define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16
; X64-NEXT: movaps (%r12), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_v8i16
+; X64-NEXT: callq sink_v8i16 at PLT
; X64-NEXT: .Lslh_ret_addr18:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -924,7 +788,7 @@ define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16
; X64-NEXT: movaps (%r15), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_v4i32
+; X64-NEXT: callq sink_v4i32 at PLT
; X64-NEXT: .Lslh_ret_addr19:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -935,7 +799,7 @@ define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16
; X64-NEXT: movaps (%r14), %xmm0
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink_v2i64
+; X64-NEXT: callq sink_v2i64 at PLT
; X64-NEXT: .Lslh_ret_addr20:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -966,17 +830,17 @@ define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16
; X64-LFENCE-NEXT: movq %rdx, %r13
; X64-LFENCE-NEXT: movq %rsi, %rbx
; X64-LFENCE-NEXT: movaps (%rdi), %xmm0
-; X64-LFENCE-NEXT: callq sink_v4f32
+; X64-LFENCE-NEXT: callq sink_v4f32 at PLT
; X64-LFENCE-NEXT: movaps (%rbx), %xmm0
-; X64-LFENCE-NEXT: callq sink_v2f64
+; X64-LFENCE-NEXT: callq sink_v2f64 at PLT
; X64-LFENCE-NEXT: movaps (%r13), %xmm0
-; X64-LFENCE-NEXT: callq sink_v16i8
+; X64-LFENCE-NEXT: callq sink_v16i8 at PLT
; X64-LFENCE-NEXT: movaps (%r12), %xmm0
-; X64-LFENCE-NEXT: callq sink_v8i16
+; X64-LFENCE-NEXT: callq sink_v8i16 at PLT
; X64-LFENCE-NEXT: movaps (%r15), %xmm0
-; X64-LFENCE-NEXT: callq sink_v4i32
+; X64-LFENCE-NEXT: callq sink_v4i32 at PLT
; X64-LFENCE-NEXT: movaps (%r14), %xmm0
-; X64-LFENCE-NEXT: callq sink_v2i64
+; X64-LFENCE-NEXT: callq sink_v2i64 at PLT
; X64-LFENCE-NEXT: popq %rbx
; X64-LFENCE-NEXT: popq %r12
; X64-LFENCE-NEXT: popq %r13
@@ -1016,7 +880,7 @@ define void @test_deferred_hardening(i32* %ptr1, i32* %ptr2, i32 %x) nounwind sp
; X64-NEXT: orl %eax, %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr21:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -1029,7 +893,7 @@ define void @test_deferred_hardening(i32* %ptr1, i32* %ptr2, i32 %x) nounwind sp
; X64-NEXT: orl %eax, %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr22:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -1041,7 +905,7 @@ define void @test_deferred_hardening(i32* %ptr1, i32* %ptr2, i32 %x) nounwind sp
; X64-NEXT: orl %eax, %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr23:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -1055,7 +919,7 @@ define void @test_deferred_hardening(i32* %ptr1, i32* %ptr2, i32 %x) nounwind sp
; X64-NEXT: orl %eax, %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr24:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -1069,7 +933,7 @@ define void @test_deferred_hardening(i32* %ptr1, i32* %ptr2, i32 %x) nounwind sp
; X64-NEXT: orl %eax, %edi
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
-; X64-NEXT: callq sink
+; X64-NEXT: callq sink at PLT
; X64-NEXT: .Lslh_ret_addr25:
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
@@ -1093,24 +957,24 @@ define void @test_deferred_hardening(i32* %ptr1, i32* %ptr2, i32 %x) nounwind sp
; X64-LFENCE-NEXT: movl (%rdi), %edi
; X64-LFENCE-NEXT: incl %edi
; X64-LFENCE-NEXT: imull %edx, %edi
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: movl (%rbx), %eax
; X64-LFENCE-NEXT: movl (%r14), %ecx
; X64-LFENCE-NEXT: leal 1(%rax,%rcx), %edi
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: movl (%rbx), %edi
; X64-LFENCE-NEXT: shll $7, %edi
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: movswl (%rbx), %edi
; X64-LFENCE-NEXT: shrl $7, %edi
; X64-LFENCE-NEXT: notl %edi
; X64-LFENCE-NEXT: orl $-65536, %edi # imm = 0xFFFF0000
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: movzwl (%rbx), %eax
; X64-LFENCE-NEXT: rolw $9, %ax
; X64-LFENCE-NEXT: movswl %ax, %edi
; X64-LFENCE-NEXT: negl %edi
-; X64-LFENCE-NEXT: callq sink
+; X64-LFENCE-NEXT: callq sink at PLT
; X64-LFENCE-NEXT: addq $8, %rsp
; X64-LFENCE-NEXT: popq %rbx
; X64-LFENCE-NEXT: popq %r14
diff --git a/llvm/test/CodeGen/X86/splat-for-size.ll b/llvm/test/CodeGen/X86/splat-for-size.ll
index 55e1470226ed6..97977f8823c89 100644
--- a/llvm/test/CodeGen/X86/splat-for-size.ll
+++ b/llvm/test/CodeGen/X86/splat-for-size.ll
@@ -242,7 +242,7 @@ define <8 x i32> @splat_v8i32_pgso(<8 x i32> %x) !prof !14 {
define <8 x i16> @splat_v8i16(<8 x i16> %x) #1 {
; AVX-LABEL: splat_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX2-LABEL: splat_v8i16:
@@ -257,7 +257,7 @@ define <8 x i16> @splat_v8i16(<8 x i16> %x) #1 {
define <8 x i16> @splat_v8i16_pgso(<8 x i16> %x) !prof !14 {
; AVX-LABEL: splat_v8i16_pgso:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX2-LABEL: splat_v8i16_pgso:
@@ -312,7 +312,7 @@ define <16 x i16> @splat_v16i16_pgso(<16 x i16> %x) !prof !14 {
define <16 x i8> @splat_v16i8(<16 x i8> %x) #1 {
; AVX-LABEL: splat_v16i8:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX2-LABEL: splat_v16i8:
@@ -327,7 +327,7 @@ define <16 x i8> @splat_v16i8(<16 x i8> %x) #1 {
define <16 x i8> @splat_v16i8_pgso(<16 x i8> %x) !prof !14 {
; AVX-LABEL: splat_v16i8_pgso:
; AVX: # %bb.0:
-; AVX-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX2-LABEL: splat_v16i8_pgso:
@@ -400,7 +400,7 @@ define <8 x i64> @pr23259() #1 {
;
; AVX2-LABEL: pr23259:
; AVX2: # %bb.0: # %entry
-; AVX2-NEXT: vmovdqa {{.*}}(%rip), %ymm0
+; AVX2-NEXT: vmovdqa A(%rip), %ymm0
; AVX2-NEXT: pushq $1
; AVX2-NEXT: .cfi_adjust_cfa_offset 8
; AVX2-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll b/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll
index 441d0ce99ec81..0e69e14d95f02 100644
--- a/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll
+++ b/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; rdar://6647639
diff --git a/llvm/test/CodeGen/X86/split-vector-rem.ll b/llvm/test/CodeGen/X86/split-vector-rem.ll
index ba8f57b2aaa01..e292e128d9bfa 100644
--- a/llvm/test/CodeGen/X86/split-vector-rem.ll
+++ b/llvm/test/CodeGen/X86/split-vector-rem.ll
@@ -147,25 +147,25 @@ define <8 x float> @qux(<8 x float> %t, <8 x float> %u) {
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: movaps %xmm2, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm2[3,3]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
@@ -175,25 +175,25 @@ define <8 x float> @qux(<8 x float> %t, <8 x float> %u) {
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
index 4c8e50468fd7c..377b1cfbdfa92 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
@@ -13,10 +13,10 @@ define float @f32_no_daz(float %f) #0 {
; NHM-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; NHM-NEXT: mulss %xmm2, %xmm3
; NHM-NEXT: mulss %xmm1, %xmm2
-; NHM-NEXT: addss {{.*}}(%rip), %xmm2
-; NHM-NEXT: andps {{.*}}(%rip), %xmm0
+; NHM-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; NHM-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NHM-NEXT: mulss %xmm3, %xmm2
-; NHM-NEXT: cmpltss {{.*}}(%rip), %xmm0
+; NHM-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NHM-NEXT: andnps %xmm2, %xmm0
; NHM-NEXT: retq
;
@@ -37,8 +37,8 @@ define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 {
; NHM-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; NHM-NEXT: mulps %xmm1, %xmm3
; NHM-NEXT: mulps %xmm2, %xmm1
-; NHM-NEXT: addps {{.*}}(%rip), %xmm1
-; NHM-NEXT: andps {{.*}}(%rip), %xmm0
+; NHM-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; NHM-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NHM-NEXT: mulps %xmm3, %xmm1
; NHM-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; NHM-NEXT: cmpleps %xmm0, %xmm2
@@ -50,10 +50,10 @@ define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 {
; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %xmm0, %xmm1
; SNB-NEXT: vmulps %xmm1, %xmm0, %xmm2
-; SNB-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3
+; SNB-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; SNB-NEXT: vmulps %xmm1, %xmm2, %xmm1
-; SNB-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
-; SNB-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; SNB-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; SNB-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SNB-NEXT: vmulps %xmm1, %xmm3, %xmm1
; SNB-NEXT: vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; SNB-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
@@ -120,10 +120,10 @@ define <8 x float> @v8f32_no_daz(<8 x float> %f) #0 {
; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %ymm0, %ymm1
; SNB-NEXT: vmulps %ymm1, %ymm0, %ymm2
-; SNB-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm3
+; SNB-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; SNB-NEXT: vmulps %ymm1, %ymm2, %ymm1
-; SNB-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm1
-; SNB-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; SNB-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; SNB-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; SNB-NEXT: vmulps %ymm1, %ymm3, %ymm1
; SNB-NEXT: vmovaps {{.*#+}} ymm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; SNB-NEXT: vcmpleps %ymm0, %ymm2, %ymm0
@@ -165,7 +165,7 @@ define float @f32_daz(float %f) #1 {
; NHM-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; NHM-NEXT: mulss %xmm2, %xmm3
; NHM-NEXT: mulss %xmm1, %xmm2
-; NHM-NEXT: addss {{.*}}(%rip), %xmm2
+; NHM-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; NHM-NEXT: mulss %xmm3, %xmm2
; NHM-NEXT: xorps %xmm1, %xmm1
; NHM-NEXT: cmpeqss %xmm1, %xmm0
@@ -189,7 +189,7 @@ define <4 x float> @v4f32_daz(<4 x float> %f) #1 {
; NHM-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; NHM-NEXT: mulps %xmm2, %xmm3
; NHM-NEXT: mulps %xmm1, %xmm2
-; NHM-NEXT: addps {{.*}}(%rip), %xmm2
+; NHM-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; NHM-NEXT: mulps %xmm3, %xmm2
; NHM-NEXT: xorps %xmm1, %xmm1
; NHM-NEXT: cmpneqps %xmm1, %xmm0
@@ -200,9 +200,9 @@ define <4 x float> @v4f32_daz(<4 x float> %f) #1 {
; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %xmm0, %xmm1
; SNB-NEXT: vmulps %xmm1, %xmm0, %xmm2
-; SNB-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3
+; SNB-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; SNB-NEXT: vmulps %xmm1, %xmm2, %xmm1
-; SNB-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
+; SNB-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; SNB-NEXT: vmulps %xmm1, %xmm3, %xmm1
; SNB-NEXT: vxorps %xmm2, %xmm2, %xmm2
; SNB-NEXT: vcmpneqps %xmm2, %xmm0, %xmm0
@@ -262,9 +262,9 @@ define <8 x float> @v8f32_daz(<8 x float> %f) #1 {
; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %ymm0, %ymm1
; SNB-NEXT: vmulps %ymm1, %ymm0, %ymm2
-; SNB-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm3
+; SNB-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; SNB-NEXT: vmulps %ymm1, %ymm2, %ymm1
-; SNB-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm1
+; SNB-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; SNB-NEXT: vmulps %ymm1, %ymm3, %ymm1
; SNB-NEXT: vxorps %xmm2, %xmm2, %xmm2
; SNB-NEXT: vcmpneqps %ymm2, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath.ll b/llvm/test/CodeGen/X86/sqrt-fastmath.ll
index a49d550b21f76..228665240735b 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath.ll
@@ -84,10 +84,10 @@ define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: mulss %xmm2, %xmm3
; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: addss {{.*}}(%rip), %xmm2
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulss %xmm3, %xmm2
-; SSE-NEXT: cmpltss {{.*}}(%rip), %xmm0
+; SSE-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: andnps %xmm2, %xmm0
; SSE-NEXT: retq
;
@@ -96,11 +96,11 @@ define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -109,11 +109,11 @@ define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm0
-; AVX512-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %k1
+; AVX512-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
; AVX512-NEXT: vmovaps %xmm1, %xmm0
@@ -145,7 +145,7 @@ define float @finite_f32_estimate_daz_ninf(float %f) #4 {
; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: mulss %xmm2, %xmm3
; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: addss {{.*}}(%rip), %xmm2
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: mulss %xmm3, %xmm2
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cmpeqss %xmm1, %xmm0
@@ -157,8 +157,8 @@ define float @finite_f32_estimate_daz_ninf(float %f) #4 {
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0
@@ -170,7 +170,7 @@ define float @finite_f32_estimate_daz_ninf(float %f) #4 {
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vcmpeqss %xmm2, %xmm0, %k1
@@ -228,10 +228,10 @@ define float @sqrtf_check_denorms_ninf(float %x) #3 {
; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: mulss %xmm2, %xmm3
; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: addss {{.*}}(%rip), %xmm2
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulss %xmm3, %xmm2
-; SSE-NEXT: cmpltss {{.*}}(%rip), %xmm0
+; SSE-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: andnps %xmm2, %xmm0
; SSE-NEXT: retq
;
@@ -240,11 +240,11 @@ define float @sqrtf_check_denorms_ninf(float %x) #3 {
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -253,11 +253,11 @@ define float @sqrtf_check_denorms_ninf(float %x) #3 {
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm0
-; AVX512-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %k1
+; AVX512-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
; AVX512-NEXT: vmovaps %xmm1, %xmm0
@@ -289,8 +289,8 @@ define <4 x float> @sqrt_v4f32_check_denorms_ninf(<4 x float> %x) #3 {
; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; SSE-NEXT: mulps %xmm1, %xmm3
; SSE-NEXT: mulps %xmm2, %xmm1
-; SSE-NEXT: addps {{.*}}(%rip), %xmm1
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulps %xmm3, %xmm1
; SSE-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; SSE-NEXT: cmpleps %xmm0, %xmm2
@@ -302,10 +302,10 @@ define <4 x float> @sqrt_v4f32_check_denorms_ninf(<4 x float> %x) #3 {
; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtps %xmm0, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm2
-; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulps %xmm1, %xmm3, %xmm1
; AVX1-NEXT: vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; AVX1-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
@@ -356,8 +356,8 @@ define float @f32_estimate(float %x) #1 {
; SSE-NEXT: rsqrtss %xmm0, %xmm1
; SSE-NEXT: mulss %xmm1, %xmm0
; SSE-NEXT: mulss %xmm1, %xmm0
-; SSE-NEXT: addss {{.*}}(%rip), %xmm0
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm1
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: mulss %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -366,8 +366,8 @@ define float @f32_estimate(float %x) #1 {
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -376,7 +376,7 @@ define float @f32_estimate(float %x) #1 {
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + mem
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX512-NEXT: retq
%sqrt = tail call float @llvm.sqrt.f32(float %x)
@@ -416,8 +416,8 @@ define <4 x float> @v4f32_estimate(<4 x float> %x) #1 {
; SSE-NEXT: rsqrtps %xmm0, %xmm1
; SSE-NEXT: mulps %xmm1, %xmm0
; SSE-NEXT: mulps %xmm1, %xmm0
-; SSE-NEXT: addps {{.*}}(%rip), %xmm0
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm1
+; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: mulps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -426,8 +426,8 @@ define <4 x float> @v4f32_estimate(<4 x float> %x) #1 {
; AVX1-NEXT: vrsqrtps %xmm0, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -499,8 +499,8 @@ define <8 x float> @v8f32_estimate(<8 x float> %x) #1 {
; AVX1-NEXT: vrsqrtps %ymm0, %ymm1
; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vmulps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -611,7 +611,7 @@ define <16 x float> @v16f32_estimate(<16 x float> %x) #1 {
; AVX512-NEXT: vrsqrt14ps %zmm0, %zmm1
; AVX512-NEXT: vmulps %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + mem
-; AVX512-NEXT: vmulps {{.*}}(%rip){1to16}, %zmm1, %zmm1
+; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1
; AVX512-NEXT: vmulps %zmm0, %zmm1, %zmm0
; AVX512-NEXT: retq
%sqrt = tail call <16 x float> @llvm.sqrt.v16f32(<16 x float> %x)
@@ -630,8 +630,8 @@ define float @div_sqrt_fabs_f32(float %x, float %y, float %z) {
; SSE-NEXT: rsqrtss %xmm1, %xmm2
; SSE-NEXT: mulss %xmm2, %xmm1
; SSE-NEXT: mulss %xmm2, %xmm1
-; SSE-NEXT: addss {{.*}}(%rip), %xmm1
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm2
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: mulss %xmm0, %xmm2
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm0
@@ -644,8 +644,8 @@ define float @div_sqrt_fabs_f32(float %x, float %y, float %z) {
; AVX1-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmulss %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
@@ -657,7 +657,7 @@ define float @div_sqrt_fabs_f32(float %x, float %y, float %z) {
; AVX512-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vmulss %xmm0, %xmm2, %xmm0
; AVX512-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX512-NEXT: retq
@@ -678,8 +678,8 @@ define <4 x float> @div_sqrt_fabs_v4f32(<4 x float> %x, <4 x float> %y, <4 x flo
; SSE-NEXT: rsqrtps %xmm1, %xmm2
; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: mulps %xmm2, %xmm1
-; SSE-NEXT: addps {{.*}}(%rip), %xmm1
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm2
+; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: mulps %xmm1, %xmm2
; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: retq
@@ -691,8 +691,8 @@ define <4 x float> @div_sqrt_fabs_v4f32(<4 x float> %x, <4 x float> %y, <4 x flo
; AVX1-NEXT: vrsqrtps %xmm1, %xmm2
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -728,10 +728,10 @@ define <4 x float> @div_sqrt_fabs_v4f32_fmf(<4 x float> %x, <4 x float> %y, <4 x
; SSE-NEXT: rsqrtps %xmm2, %xmm3
; SSE-NEXT: mulps %xmm3, %xmm2
; SSE-NEXT: mulps %xmm3, %xmm2
-; SSE-NEXT: addps {{.*}}(%rip), %xmm2
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm3
+; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE-NEXT: mulps %xmm2, %xmm3
-; SSE-NEXT: andps {{.*}}(%rip), %xmm1
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: divps %xmm1, %xmm3
; SSE-NEXT: mulps %xmm3, %xmm0
; SSE-NEXT: retq
@@ -741,10 +741,10 @@ define <4 x float> @div_sqrt_fabs_v4f32_fmf(<4 x float> %x, <4 x float> %y, <4 x
; AVX1-NEXT: vrsqrtps %xmm2, %xmm3
; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2
-; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vmulps %xmm2, %xmm3, %xmm2
-; AVX1-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vdivps %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -777,7 +777,7 @@ define double @div_sqrt_fabs_f64(double %x, double %y, double %z) {
; SSE-LABEL: div_sqrt_fabs_f64:
; SSE: # %bb.0:
; SSE-NEXT: sqrtsd %xmm2, %xmm2
-; SSE-NEXT: andpd {{.*}}(%rip), %xmm1
+; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm1
; SSE-NEXT: divsd %xmm1, %xmm0
; SSE-NEXT: retq
@@ -785,7 +785,7 @@ define double @div_sqrt_fabs_f64(double %x, double %y, double %z) {
; AVX-LABEL: div_sqrt_fabs_f64:
; AVX: # %bb.0:
; AVX-NEXT: vsqrtsd %xmm2, %xmm2, %xmm2
-; AVX-NEXT: vandpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vmulsd %xmm1, %xmm2, %xmm1
; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
@@ -811,8 +811,8 @@ define float @div_sqrt_f32(float %x, float %y) {
; SSE-NEXT: rsqrtss %xmm2, %xmm1
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: addss {{.*}}(%rip), %xmm2
-; SSE-NEXT: mulss {{.*}}(%rip), %xmm1
+; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: mulss %xmm0, %xmm1
; SSE-NEXT: mulss %xmm2, %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
@@ -825,8 +825,8 @@ define float @div_sqrt_f32(float %x, float %y) {
; AVX1-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmulss %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
@@ -838,7 +838,7 @@ define float @div_sqrt_f32(float %x, float %y) {
; AVX512-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vmulss %xmm0, %xmm2, %xmm0
; AVX512-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX512-NEXT: retq
@@ -862,8 +862,8 @@ define <4 x float> @div_sqrt_v4f32(<4 x float> %x, <4 x float> %y) {
; SSE-NEXT: rsqrtps %xmm2, %xmm1
; SSE-NEXT: mulps %xmm1, %xmm2
; SSE-NEXT: mulps %xmm1, %xmm2
-; SSE-NEXT: addps {{.*}}(%rip), %xmm2
-; SSE-NEXT: mulps {{.*}}(%rip), %xmm1
+; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: mulps %xmm1, %xmm0
; SSE-NEXT: retq
@@ -875,8 +875,8 @@ define <4 x float> @div_sqrt_v4f32(<4 x float> %x, <4 x float> %y) {
; AVX1-NEXT: vrsqrtps %xmm1, %xmm2
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
index 166bf345d89b1..2febbbdc4c16d 100644
--- a/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
@@ -206,8 +206,8 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; SSE2-NEXT: addq %rcx, %rax
; SSE2-NEXT: movq %rax, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2
-; SSE2-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
-; SSE2-NEXT: pcmpeqd {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,2]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,3]
@@ -261,10 +261,10 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; SSE41-NEXT: addq %rcx, %rax
; SSE41-NEXT: movq %rax, %xmm2
; SSE41-NEXT: pand %xmm1, %xmm2
-; SSE41-NEXT: pcmpeqq {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
; SSE41-NEXT: pxor %xmm1, %xmm0
-; SSE41-NEXT: pcmpeqq {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: pextrb $0, %xmm0, %eax
; SSE41-NEXT: pextrb $8, %xmm0, %edx
@@ -313,12 +313,12 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; AVX1-NEXT: addq %rcx, %rax
; AVX1-NEXT: vmovq %rax, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpextrb $0, %xmm0, %eax
; AVX1-NEXT: vpextrb $8, %xmm0, %edx
@@ -370,7 +370,7 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [8589934591,8589934591,8589934591,8589934591]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqq {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
@@ -422,8 +422,8 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; AVX512VL-NEXT: addq %rcx, %rax
; AVX512VL-NEXT: vmovq %rax, %xmm1
; AVX512VL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm0, %ymm0
-; AVX512VL-NEXT: vpcmpneqq {{.*}}(%rip), %ymm0, %k0
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vpcmpneqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; AVX512VL-NEXT: kshiftrw $1, %k0, %k1
; AVX512VL-NEXT: kmovw %k1, %edx
; AVX512VL-NEXT: kshiftrw $2, %k0, %k1
diff --git a/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
index 1a15175fa7a66..0ebe0f996bfcb 100644
--- a/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
@@ -17,7 +17,7 @@ define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -30,17 +30,17 @@ define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_even:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -59,8 +59,8 @@ define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -69,29 +69,29 @@ define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -114,16 +114,16 @@ define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_allones_eq:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,858993458,4294967295,858993458]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -132,9 +132,9 @@ define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_odd_allones_eq:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -145,16 +145,16 @@ define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [429496729,429496729,429496729,429496729]
; CHECK-AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_allones_eq:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -173,29 +173,29 @@ define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_allones_ne:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,858993458,4294967295,858993458]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
-; CHECK-SSE41-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: retq
;
; CHECK-AVX1-LABEL: test_srem_odd_allones_ne:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpandn {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_allones_ne:
@@ -204,7 +204,7 @@ define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [429496729,429496729,429496729,429496729]
; CHECK-AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
; CHECK-AVX2-NEXT: vpandn %xmm1, %xmm0, %xmm0
@@ -212,11 +212,11 @@ define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_srem_odd_allones_ne:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpandnd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpandnd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
%srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
%cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
@@ -235,20 +235,20 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: pslld $31, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_allones_eq:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pslld $31, %xmm0
@@ -261,12 +261,12 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_allones_eq:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -280,17 +280,17 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_even_allones_eq:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -309,20 +309,20 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: pslld $31, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_allones_ne:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pslld $31, %xmm0
@@ -330,19 +330,19 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,306783378,4294967295,306783378]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
-; CHECK-SSE41-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: retq
;
; CHECK-AVX1-LABEL: test_srem_even_allones_ne:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpandn {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_even_allones_ne:
@@ -354,7 +354,7 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
; CHECK-AVX2-NEXT: vpandn %xmm1, %xmm0, %xmm0
@@ -362,12 +362,12 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_srem_even_allones_ne:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpandnd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpandnd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
%cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
@@ -387,7 +387,7 @@ define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -400,17 +400,17 @@ define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_even_allones_eq:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -429,8 +429,8 @@ define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -439,29 +439,29 @@ define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even_allones_eq:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even_allones_eq:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -481,7 +481,7 @@ define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -494,8 +494,8 @@ define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -503,8 +503,8 @@ define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -516,15 +516,15 @@ define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,306783378,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm2, %xmm0
; CHECK-SSE41-NEXT: pcmpeqd %xmm2, %xmm0
-; CHECK-SSE41-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: retq
;
; CHECK-AVX1-LABEL: test_srem_odd_even_allones_ne:
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -533,19 +533,19 @@ define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpandn {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even_allones_ne:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
; CHECK-AVX2-NEXT: vpandn %xmm1, %xmm0, %xmm0
@@ -553,12 +553,12 @@ define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even_allones_ne:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpandnd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpandnd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
%srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
%cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
@@ -573,12 +573,12 @@ define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_srem_odd_poweroftwo:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = <1,u,268435456,u>
; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
@@ -591,18 +591,18 @@ define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm2, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pandn %xmm4, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_poweroftwo:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -616,39 +616,39 @@ define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_odd_poweroftwo:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -663,12 +663,12 @@ define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_srem_even_poweroftwo:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = <2147483648,u,268435456,u>
; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
@@ -682,17 +682,17 @@ define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_poweroftwo:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -706,39 +706,39 @@ define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_poweroftwo:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_even_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_even_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -760,7 +760,7 @@ define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,268435456,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -773,17 +773,17 @@ define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_even_poweroftwo:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,268435456,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -802,8 +802,8 @@ define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,268435456,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -812,29 +812,29 @@ define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -857,16 +857,16 @@ define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,858993458,4294967295,858993458]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -875,9 +875,9 @@ define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_odd_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -888,16 +888,16 @@ define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [429496729,429496729,429496729,429496729]
; CHECK-AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -918,20 +918,20 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: pslld $31, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pslld $31, %xmm0
@@ -944,12 +944,12 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -963,17 +963,17 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_even_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -995,7 +995,7 @@ define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -1008,17 +1008,17 @@ define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_even_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1037,8 +1037,8 @@ define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1047,29 +1047,29 @@ define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1090,14 +1090,14 @@ define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pand %xmm0, %xmm2
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,2,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm3
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm3, %xmm0
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
@@ -1111,8 +1111,8 @@ define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
; CHECK-SSE41-NEXT: pand %xmm0, %xmm2
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm2
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,858993458,0,858993458]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -1123,11 +1123,11 @@ define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX1-LABEL: test_srem_odd_INT_MIN:
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm2, %xmm1
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -1139,9 +1139,9 @@ define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
; CHECK-AVX2-NEXT: vpand %xmm2, %xmm0, %xmm2
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm2, %xmm1
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -1150,11 +1150,11 @@ define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-LABEL: test_srem_odd_INT_MIN:
; CHECK-AVX512VL: # %bb.0:
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm2
+; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm2, %xmm1
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -1174,10 +1174,10 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = <2147483648,u,2,u>
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,3,2,3]
@@ -1191,10 +1191,10 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm3
; CHECK-SSE2-NEXT: pxor %xmm5, %xmm3
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-SSE2-NEXT: pxor %xmm3, %xmm1
-; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
@@ -1210,8 +1210,8 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm3 = [306783378,306783378,0,306783378]
; CHECK-SSE41-NEXT: paddd %xmm3, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm4
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm2
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,2,2]
@@ -1219,7 +1219,7 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: por %xmm5, %xmm4
; CHECK-SSE41-NEXT: pminud %xmm4, %xmm3
; CHECK-SSE41-NEXT: pcmpeqd %xmm4, %xmm3
-; CHECK-SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: psrld $31, %xmm0
@@ -1228,12 +1228,12 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX1-LABEL: test_srem_even_INT_MIN:
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [306783378,306783378,0,306783378]
; CHECK-AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm4, %xmm4
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm2, %xmm2
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,0,2,2]
@@ -1241,7 +1241,7 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpor %xmm5, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpminud %xmm3, %xmm2, %xmm3
; CHECK-AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
-; CHECK-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -1250,11 +1250,11 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX2-LABEL: test_srem_even_INT_MIN:
; CHECK-AVX2: # %bb.0:
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [306783378,306783378,0,306783378]
; CHECK-AVX2-NEXT: vpaddd %xmm3, %xmm2, %xmm2
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm2, %xmm4
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm2, %xmm2
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm4
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; CHECK-AVX2-NEXT: vpor %xmm4, %xmm2, %xmm2
; CHECK-AVX2-NEXT: vpminud %xmm3, %xmm2, %xmm3
; CHECK-AVX2-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
@@ -1268,13 +1268,13 @@ define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-LABEL: test_srem_even_INT_MIN:
; CHECK-AVX512VL: # %bb.0:
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [306783378,306783378,0,306783378]
; CHECK-AVX512VL-NEXT: vpaddd %xmm3, %xmm2, %xmm2
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm2, %xmm2
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; CHECK-AVX512VL-NEXT: vpminud %xmm3, %xmm2, %xmm3
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
-; CHECK-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0,1],xmm0[2],xmm2[3]
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -1299,7 +1299,7 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,2,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
@@ -1312,11 +1312,11 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm5, %xmm3
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-SSE2-NEXT: pxor %xmm3, %xmm1
-; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
@@ -1331,7 +1331,7 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm4 = [3435973837,3067833783,1,3264175145]
; CHECK-SSE41-NEXT: pmulld %xmm0, %xmm4
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm4
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm3, %xmm5
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm4
@@ -1343,7 +1343,7 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [858993458,306783378,0,42949672]
; CHECK-SSE41-NEXT: pminud %xmm3, %xmm2
; CHECK-SSE41-NEXT: pcmpeqd %xmm3, %xmm2
-; CHECK-SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5],xmm2[6,7]
; CHECK-SSE41-NEXT: psrld $31, %xmm0
@@ -1354,8 +1354,8 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,2147483648,2,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm4
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm4, %xmm4
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm4
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm5, %xmm3
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm4, %xmm2
@@ -1364,9 +1364,9 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
; CHECK-AVX1-NEXT: vpor %xmm4, %xmm2, %xmm2
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm2, %xmm3
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; CHECK-AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
-; CHECK-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -1375,12 +1375,12 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX2-LABEL: test_srem_odd_even_INT_MIN:
; CHECK-AVX2: # %bb.0:
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm2, %xmm2
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm2, %xmm3
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm2, %xmm2
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; CHECK-AVX2-NEXT: vpor %xmm3, %xmm2, %xmm2
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm2, %xmm3
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
; CHECK-AVX2-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2147483647,2147483647,2147483647,2147483647]
; CHECK-AVX2-NEXT: vpand %xmm3, %xmm0, %xmm0
@@ -1392,12 +1392,12 @@ define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-LABEL: test_srem_odd_even_INT_MIN:
; CHECK-AVX512VL: # %bb.0:
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm2
+; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm2, %xmm1
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -1422,7 +1422,7 @@ define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = <1,u,268435456,u>
; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
@@ -1435,18 +1435,18 @@ define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm2, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pandn %xmm4, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -1460,39 +1460,39 @@ define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_odd_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_allones_and_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_allones_and_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1514,7 +1514,7 @@ define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,1,268435456,2147483648]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -1527,17 +1527,17 @@ define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,1,268435456,2147483648]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1556,8 +1556,8 @@ define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2147483648,1,268435456,2147483648]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1566,29 +1566,29 @@ define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_even_allones_and_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_even_allones_and_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1610,7 +1610,7 @@ define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,1,268435456,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -1623,17 +1623,17 @@ define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_even_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,268435456,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1652,8 +1652,8 @@ define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,268435456,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1662,29 +1662,29 @@ define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even_allones_and_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even_allones_and_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1707,16 +1707,16 @@ define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_allones_and_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,4294967295,4294967295,858993458]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -1725,9 +1725,9 @@ define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_odd_allones_and_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -1738,16 +1738,16 @@ define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [429496729,429496729,429496729,429496729]
; CHECK-AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_allones_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1768,20 +1768,20 @@ define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: pslld $31, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_allones_and_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pslld $31, %xmm0
@@ -1794,12 +1794,12 @@ define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_allones_and_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -1813,17 +1813,17 @@ define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_even_allones_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1845,7 +1845,7 @@ define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,1,1,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -1858,17 +1858,17 @@ define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_even_allones_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1887,8 +1887,8 @@ define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1897,29 +1897,29 @@ define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even_allones_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even_allones_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1943,7 +1943,7 @@ define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,268435456,1,1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -1956,17 +1956,17 @@ define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,268435456,1,1]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1985,8 +1985,8 @@ define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,268435456,1,1]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1995,29 +1995,29 @@ define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -2039,7 +2039,7 @@ define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,268435456,1,2147483648]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -2052,17 +2052,17 @@ define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,268435456,1,2147483648]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -2081,8 +2081,8 @@ define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2147483648,268435456,1,2147483648]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -2091,29 +2091,29 @@ define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_even_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_even_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -2135,7 +2135,7 @@ define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,268435456,1,1073741824]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -2148,17 +2148,17 @@ define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_even_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,268435456,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -2177,8 +2177,8 @@ define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,268435456,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -2187,29 +2187,29 @@ define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_even_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_even_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -2226,25 +2226,25 @@ define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nou
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: psrlq $32, %xmm0
@@ -2257,36 +2257,36 @@ define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nou
;
; CHECK-AVX1-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -2301,25 +2301,25 @@ define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) no
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: psrlq $32, %xmm0
@@ -2332,36 +2332,36 @@ define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) no
;
; CHECK-AVX1-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll b/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll
index e8c0b947baa18..4aa45ecde8736 100644
--- a/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll
@@ -16,16 +16,16 @@ define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_25:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [171798690,171798690,171798690,171798690]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -34,9 +34,9 @@ define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_odd_25:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -55,9 +55,9 @@ define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_srem_odd_25:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -78,20 +78,20 @@ define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: pslld $30, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_100:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $2, %xmm1
; CHECK-SSE41-NEXT: pslld $30, %xmm0
@@ -104,12 +104,12 @@ define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_100:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $30, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -131,10 +131,10 @@ define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_srem_even_100:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $2, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -157,16 +157,16 @@ define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_odd_neg25:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [171798690,171798690,171798690,171798690]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -175,9 +175,9 @@ define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_odd_neg25:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -196,9 +196,9 @@ define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_srem_odd_neg25:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -219,20 +219,20 @@ define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: pslld $30, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_srem_even_neg100:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $2, %xmm1
; CHECK-SSE41-NEXT: pslld $30, %xmm0
@@ -245,12 +245,12 @@ define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_neg100:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $30, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -272,10 +272,10 @@ define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_srem_even_neg100:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $2, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -333,7 +333,7 @@ define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: psrld $31, %xmm1
; CHECK-SSE41-NEXT: psrad $3, %xmm2
; CHECK-SSE41-NEXT: paddd %xmm1, %xmm2
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -351,7 +351,7 @@ define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpsrld $31, %xmm1, %xmm2
; CHECK-AVX1-NEXT: vpsrad $3, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -388,7 +388,7 @@ define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm1, %xmm2
; CHECK-AVX512VL-NEXT: vpsrad $3, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -444,7 +444,7 @@ define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: psrld $31, %xmm1
; CHECK-SSE41-NEXT: psrad $5, %xmm2
; CHECK-SSE41-NEXT: paddd %xmm1, %xmm2
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -462,7 +462,7 @@ define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpsrld $31, %xmm1, %xmm2
; CHECK-AVX1-NEXT: vpsrad $5, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -499,7 +499,7 @@ define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm1, %xmm2
; CHECK-AVX512VL-NEXT: vpsrad $5, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -564,7 +564,7 @@ define <4 x i32> @test_srem_pow2(<4 x i32> %X) nounwind {
; CHECK-SSE-NEXT: psrad $31, %xmm1
; CHECK-SSE-NEXT: psrld $28, %xmm1
; CHECK-SSE-NEXT: paddd %xmm0, %xmm1
-; CHECK-SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE-NEXT: pcmpeqd %xmm1, %xmm0
@@ -576,7 +576,7 @@ define <4 x i32> @test_srem_pow2(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpsrld $28, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; CHECK-AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -601,7 +601,7 @@ define <4 x i32> @test_srem_pow2(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpsrad $31, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpsrld $28, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; CHECK-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -621,7 +621,7 @@ define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-SSE-NEXT: psrad $31, %xmm1
; CHECK-SSE-NEXT: psrld $1, %xmm1
; CHECK-SSE-NEXT: paddd %xmm0, %xmm1
-; CHECK-SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE-NEXT: pcmpeqd %xmm1, %xmm0
@@ -633,7 +633,7 @@ define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; CHECK-AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -658,7 +658,7 @@ define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpsrad $31, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; CHECK-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index 8b9b794a3cc9e..c07c20d8f414a 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -118,18 +118,18 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; SSE-NEXT: psrlw $15, %xmm2
; SSE-NEXT: psraw $6, %xmm1
; SSE-NEXT: paddw %xmm2, %xmm1
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fold_srem_vec_2:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpaddw %xmm0, %xmm1, %xmm1
; AVX-NEXT: vpsrlw $15, %xmm1, %xmm2
; AVX-NEXT: vpsraw $6, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
@@ -156,12 +156,12 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
;
; AVX-LABEL: combine_srem_sdiv:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpaddw %xmm0, %xmm1, %xmm1
; AVX-NEXT: vpsrlw $15, %xmm1, %xmm2
; AVX-NEXT: vpsraw $6, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm2
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; AVX-NEXT: vpsubw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/sse-fcopysign.ll b/llvm/test/CodeGen/X86/sse-fcopysign.ll
index 896516c272543..ebc35b2843cc0 100644
--- a/llvm/test/CodeGen/X86/sse-fcopysign.ll
+++ b/llvm/test/CodeGen/X86/sse-fcopysign.ll
@@ -65,9 +65,9 @@ define float @int1(float %a, float %b) nounwind {
; X32: # %bb.0:
; X32-NEXT: pushl %eax
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: orps %xmm0, %xmm1
; X32-NEXT: movss %xmm1, (%esp)
; X32-NEXT: flds (%esp)
@@ -76,8 +76,8 @@ define float @int1(float %a, float %b) nounwind {
;
; X64-LABEL: int1:
; X64: # %bb.0:
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
-; X64-NEXT: andps {{.*}}(%rip), %xmm1
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: orps %xmm1, %xmm0
; X64-NEXT: retq
%tmp = tail call float @llvm.copysign.f32( float %b, float %a )
@@ -94,9 +94,9 @@ define double @int2(double %a, float %b, float %c) nounwind {
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: addss 20(%ebp), %xmm0
; X32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
-; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: cvtss2sd %xmm0, %xmm0
-; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: orps %xmm1, %xmm0
; X32-NEXT: movlps %xmm0, (%esp)
; X32-NEXT: fldl (%esp)
@@ -108,8 +108,8 @@ define double @int2(double %a, float %b, float %c) nounwind {
; X64: # %bb.0:
; X64-NEXT: addss %xmm2, %xmm1
; X64-NEXT: cvtss2sd %xmm1, %xmm1
-; X64-NEXT: andps {{.*}}(%rip), %xmm1
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: orps %xmm1, %xmm0
; X64-NEXT: retq
%tmp1 = fadd float %b, %c
diff --git a/llvm/test/CodeGen/X86/sse-load-ret.ll b/llvm/test/CodeGen/X86/sse-load-ret.ll
index 510c9e2bd8bac..d6aba9c19a327 100644
--- a/llvm/test/CodeGen/X86/sse-load-ret.ll
+++ b/llvm/test/CodeGen/X86/sse-load-ret.ll
@@ -14,7 +14,7 @@ define double @test1(double* %P) {
define double @test2() {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
-; CHECK-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: retl
ret double 1.234560e+03
}
diff --git a/llvm/test/CodeGen/X86/sse-minmax.ll b/llvm/test/CodeGen/X86/sse-minmax.ll
index 0f703d6954407..d2edde17d2b5e 100644
--- a/llvm/test/CodeGen/X86/sse-minmax.ll
+++ b/llvm/test/CodeGen/X86/sse-minmax.ll
@@ -674,7 +674,7 @@ define double @ule_inverse_x(double %x) {
define double @ogt_y(double %x) {
; ALL-LABEL: ogt_y:
; ALL: # %bb.0:
-; ALL-NEXT: maxsd {{.*}}(%rip), %xmm0
+; ALL-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ALL-NEXT: retq
%c = fcmp ogt double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -684,7 +684,7 @@ define double @ogt_y(double %x) {
define double @olt_y(double %x) {
; ALL-LABEL: olt_y:
; ALL: # %bb.0:
-; ALL-NEXT: minsd {{.*}}(%rip), %xmm0
+; ALL-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ALL-NEXT: retq
%c = fcmp olt double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -701,7 +701,7 @@ define double @ogt_inverse_y(double %x) {
;
; UNSAFE-LABEL: ogt_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: ogt_inverse_y:
@@ -725,7 +725,7 @@ define double @olt_inverse_y(double %x) {
;
; UNSAFE-LABEL: olt_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: olt_inverse_y:
@@ -752,7 +752,7 @@ define double @oge_y(double %x) {
;
; RELAX-LABEL: oge_y:
; RELAX: # %bb.0:
-; RELAX-NEXT: maxsd {{.*}}(%rip), %xmm0
+; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; RELAX-NEXT: retq
%c = fcmp oge double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -773,7 +773,7 @@ define double @ole_y(double %x) {
;
; RELAX-LABEL: ole_y:
; RELAX: # %bb.0:
-; RELAX-NEXT: minsd {{.*}}(%rip), %xmm0
+; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; RELAX-NEXT: retq
%c = fcmp ole double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -794,7 +794,7 @@ define double @oge_inverse_y(double %x) {
;
; UNSAFE-LABEL: oge_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: oge_inverse_y:
@@ -822,7 +822,7 @@ define double @ole_inverse_y(double %x) {
;
; UNSAFE-LABEL: ole_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: ole_inverse_y:
@@ -850,7 +850,7 @@ define double @ugt_y(double %x) {
;
; RELAX-LABEL: ugt_y:
; RELAX: # %bb.0:
-; RELAX-NEXT: maxsd {{.*}}(%rip), %xmm0
+; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; RELAX-NEXT: retq
%c = fcmp ugt double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -870,7 +870,7 @@ define double @ult_y(double %x) {
;
; RELAX-LABEL: ult_y:
; RELAX: # %bb.0:
-; RELAX-NEXT: minsd {{.*}}(%rip), %xmm0
+; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; RELAX-NEXT: retq
%c = fcmp ult double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -891,7 +891,7 @@ define double @ugt_inverse_y(double %x) {
;
; UNSAFE-LABEL: ugt_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: ugt_inverse_y:
@@ -919,7 +919,7 @@ define double @ult_inverse_y(double %x) {
;
; UNSAFE-LABEL: ult_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: ult_inverse_y:
@@ -943,7 +943,7 @@ define double @uge_y(double %x) {
;
; RELAX-LABEL: uge_y:
; RELAX: # %bb.0:
-; RELAX-NEXT: maxsd {{.*}}(%rip), %xmm0
+; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; RELAX-NEXT: retq
%c = fcmp uge double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -960,7 +960,7 @@ define double @ule_y(double %x) {
;
; RELAX-LABEL: ule_y:
; RELAX: # %bb.0:
-; RELAX-NEXT: minsd {{.*}}(%rip), %xmm0
+; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; RELAX-NEXT: retq
%c = fcmp ule double %x, -0.000000e+00
%d = select i1 %c, double %x, double -0.000000e+00
@@ -970,12 +970,12 @@ define double @ule_y(double %x) {
define double @uge_inverse_y(double %x) {
; STRICT-LABEL: uge_inverse_y:
; STRICT: # %bb.0:
-; STRICT-NEXT: minsd {{.*}}(%rip), %xmm0
+; STRICT-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; STRICT-NEXT: retq
;
; UNSAFE-LABEL: uge_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: uge_inverse_y:
@@ -992,12 +992,12 @@ define double @uge_inverse_y(double %x) {
define double @ule_inverse_y(double %x) {
; STRICT-LABEL: ule_inverse_y:
; STRICT: # %bb.0:
-; STRICT-NEXT: maxsd {{.*}}(%rip), %xmm0
+; STRICT-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; STRICT-NEXT: retq
;
; UNSAFE-LABEL: ule_inverse_y:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: ule_inverse_y:
@@ -1023,7 +1023,7 @@ define double @clampTo3k_a(double %x) {
;
; UNSAFE-LABEL: clampTo3k_a:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_a:
@@ -1040,12 +1040,12 @@ define double @clampTo3k_a(double %x) {
define double @clampTo3k_b(double %x) {
; STRICT-LABEL: clampTo3k_b:
; STRICT: # %bb.0:
-; STRICT-NEXT: minsd {{.*}}(%rip), %xmm0
+; STRICT-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; STRICT-NEXT: retq
;
; UNSAFE-LABEL: clampTo3k_b:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_b:
@@ -1069,7 +1069,7 @@ define double @clampTo3k_c(double %x) {
;
; UNSAFE-LABEL: clampTo3k_c:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_c:
@@ -1086,12 +1086,12 @@ define double @clampTo3k_c(double %x) {
define double @clampTo3k_d(double %x) {
; STRICT-LABEL: clampTo3k_d:
; STRICT: # %bb.0:
-; STRICT-NEXT: maxsd {{.*}}(%rip), %xmm0
+; STRICT-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; STRICT-NEXT: retq
;
; UNSAFE-LABEL: clampTo3k_d:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_d:
@@ -1115,7 +1115,7 @@ define double @clampTo3k_e(double %x) {
;
; UNSAFE-LABEL: clampTo3k_e:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_e:
@@ -1132,12 +1132,12 @@ define double @clampTo3k_e(double %x) {
define double @clampTo3k_f(double %x) {
; STRICT-LABEL: clampTo3k_f:
; STRICT: # %bb.0:
-; STRICT-NEXT: maxsd {{.*}}(%rip), %xmm0
+; STRICT-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; STRICT-NEXT: retq
;
; UNSAFE-LABEL: clampTo3k_f:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: maxsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_f:
@@ -1161,7 +1161,7 @@ define double @clampTo3k_g(double %x) {
;
; UNSAFE-LABEL: clampTo3k_g:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_g:
@@ -1178,12 +1178,12 @@ define double @clampTo3k_g(double %x) {
define double @clampTo3k_h(double %x) {
; STRICT-LABEL: clampTo3k_h:
; STRICT: # %bb.0:
-; STRICT-NEXT: minsd {{.*}}(%rip), %xmm0
+; STRICT-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; STRICT-NEXT: retq
;
; UNSAFE-LABEL: clampTo3k_h:
; UNSAFE: # %bb.0:
-; UNSAFE-NEXT: minsd {{.*}}(%rip), %xmm0
+; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; UNSAFE-NEXT: retq
;
; FINITE-LABEL: clampTo3k_h:
diff --git a/llvm/test/CodeGen/X86/sse-varargs.ll b/llvm/test/CodeGen/X86/sse-varargs.ll
index 6f13dfb1df4cd..074a53a1ae715 100644
--- a/llvm/test/CodeGen/X86/sse-varargs.ll
+++ b/llvm/test/CodeGen/X86/sse-varargs.ll
@@ -10,7 +10,7 @@ define i32 @t() nounwind {
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [10,11,12,13]
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $1, (%esp)
-; CHECK-NEXT: calll foo
+; CHECK-NEXT: calll foo at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
diff --git a/llvm/test/CodeGen/X86/sse1-fcopysign.ll b/llvm/test/CodeGen/X86/sse1-fcopysign.ll
index 28c7a3b80a03c..3f4c1b52a2a45 100644
--- a/llvm/test/CodeGen/X86/sse1-fcopysign.ll
+++ b/llvm/test/CodeGen/X86/sse1-fcopysign.ll
@@ -7,7 +7,7 @@ define float @f32_pos(float %a, float %b) nounwind {
; X86: # %bb.0:
; X86-NEXT: pushl %eax
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movss %xmm0, (%esp)
; X86-NEXT: flds (%esp)
; X86-NEXT: popl %eax
@@ -15,7 +15,7 @@ define float @f32_pos(float %a, float %b) nounwind {
;
; X64-LABEL: f32_pos:
; X64: # %bb.0:
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%tmp = tail call float @llvm.copysign.f32(float %a, float 1.0)
ret float %tmp
@@ -26,7 +26,7 @@ define float @f32_neg(float %a, float %b) nounwind {
; X86: # %bb.0:
; X86-NEXT: pushl %eax
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movss %xmm0, (%esp)
; X86-NEXT: flds (%esp)
; X86-NEXT: popl %eax
@@ -34,7 +34,7 @@ define float @f32_neg(float %a, float %b) nounwind {
;
; X64-LABEL: f32_neg:
; X64: # %bb.0:
-; X64-NEXT: orps {{.*}}(%rip), %xmm0
+; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%tmp = tail call float @llvm.copysign.f32(float %a, float -1.0)
ret float %tmp
@@ -43,12 +43,12 @@ define float @f32_neg(float %a, float %b) nounwind {
define <4 x float> @v4f32_pos(<4 x float> %a, <4 x float> %b) nounwind {
; X86-LABEL: v4f32_pos:
; X86: # %bb.0:
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: v4f32_pos:
; X64: # %bb.0:
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)
ret <4 x float> %tmp
@@ -57,12 +57,12 @@ define <4 x float> @v4f32_pos(<4 x float> %a, <4 x float> %b) nounwind {
define <4 x float> @v4f32_neg(<4 x float> %a, <4 x float> %b) nounwind {
; X86-LABEL: v4f32_neg:
; X86: # %bb.0:
-; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: v4f32_neg:
; X64: # %bb.0:
-; X64-NEXT: orps {{.*}}(%rip), %xmm0
+; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>)
ret <4 x float> %tmp
@@ -72,15 +72,15 @@ define <4 x float> @v4f32_const_mag(<4 x float> %a, <4 x float> %b) nounwind {
; X86-LABEL: v4f32_const_mag:
; X86: # %bb.0:
; X86-NEXT: movaps %xmm1, %xmm0
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: v4f32_const_mag:
; X64: # %bb.0:
; X64-NEXT: movaps %xmm1, %xmm0
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
-; X64-NEXT: orps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> %b )
ret <4 x float> %tmp
diff --git a/llvm/test/CodeGen/X86/sse1.ll b/llvm/test/CodeGen/X86/sse1.ll
index 7a5654c6ab1de..4485d611ef1b4 100644
--- a/llvm/test/CodeGen/X86/sse1.ll
+++ b/llvm/test/CodeGen/X86/sse1.ll
@@ -180,7 +180,7 @@ define <4 x i32> @PR30512(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X86-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; X86-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-NEXT: movaps %xmm2, (%eax)
; X86-NEXT: addl $16, %esp
; X86-NEXT: popl %esi
@@ -218,7 +218,7 @@ define <4 x i32> @PR30512(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; X64-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; X64-NEXT: andps {{.*}}(%rip), %xmm2
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-NEXT: movaps %xmm2, (%rax)
; X64-NEXT: retq
%cmp = icmp eq <4 x i32> %x, %y
@@ -238,12 +238,12 @@ define <4 x i32> @PR30512(<4 x i32> %x, <4 x i32> %y) nounwind {
define <2 x float> @PR31672() #0 {
; X86-LABEL: PR31672:
; X86: # %bb.0:
-; X86-NEXT: sqrtps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: sqrtps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: PR31672:
; X64: # %bb.0:
-; X64-NEXT: sqrtps {{.*}}(%rip), %xmm0
+; X64-NEXT: sqrtps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%t0 = call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> <float 42.0, float 3.0>)
ret <2 x float> %t0
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
index 863b04e8bc49b..7156ce288b91a 100644
--- a/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
@@ -329,8 +329,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-SSE-NEXT: xorpd %xmm1, %xmm1 ## encoding: [0x66,0x0f,0x57,0xc9]
-; X86-SSE-NEXT: movhpd LCPI11_0, %xmm1 ## encoding: [0x66,0x0f,0x16,0x0d,A,A,A,A]
-; X86-SSE-NEXT: ## fixup A - offset: 4, value: LCPI11_0, kind: FK_Data_4
+; X86-SSE-NEXT: movhpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 ## encoding: [0x66,0x0f,0x16,0x0d,A,A,A,A]
+; X86-SSE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-SSE-NEXT: ## xmm1 = xmm1[0],mem[0]
; X86-SSE-NEXT: addpd %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x58,0xc8]
; X86-SSE-NEXT: movupd %xmm1, (%eax) ## encoding: [0x66,0x0f,0x11,0x08]
@@ -340,8 +340,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x57,0xc9]
-; X86-AVX1-NEXT: vmovhpd LCPI11_0, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI11_0, kind: FK_Data_4
+; X86-AVX1-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X86-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX1-NEXT: ## xmm1 = xmm1[0],mem[0]
; X86-AVX1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x58,0xc1]
; X86-AVX1-NEXT: vmovupd %xmm0, (%eax) ## encoding: [0xc5,0xf9,0x11,0x00]
@@ -351,8 +351,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X86-AVX512: ## %bb.0:
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9]
-; X86-AVX512-NEXT: vmovhpd LCPI11_0, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI11_0, kind: FK_Data_4
+; X86-AVX512-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512-NEXT: ## xmm1 = xmm1[0],mem[0]
; X86-AVX512-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1]
; X86-AVX512-NEXT: vmovupd %xmm0, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x00]
@@ -361,8 +361,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X64-SSE-LABEL: test_x86_sse2_storeu_pd:
; X64-SSE: ## %bb.0:
; X64-SSE-NEXT: xorpd %xmm1, %xmm1 ## encoding: [0x66,0x0f,0x57,0xc9]
-; X64-SSE-NEXT: movhpd {{.*}}(%rip), %xmm1 ## encoding: [0x66,0x0f,0x16,0x0d,A,A,A,A]
-; X64-SSE-NEXT: ## fixup A - offset: 4, value: LCPI11_0-4, kind: reloc_riprel_4byte
+; X64-SSE-NEXT: movhpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ## encoding: [0x66,0x0f,0x16,0x0d,A,A,A,A]
+; X64-SSE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: ## xmm1 = xmm1[0],mem[0]
; X64-SSE-NEXT: addpd %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x58,0xc8]
; X64-SSE-NEXT: movupd %xmm1, (%rdi) ## encoding: [0x66,0x0f,0x11,0x0f]
@@ -371,8 +371,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X64-AVX1-LABEL: test_x86_sse2_storeu_pd:
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x57,0xc9]
-; X64-AVX1-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI11_0-4, kind: reloc_riprel_4byte
+; X64-AVX1-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X64-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX1-NEXT: ## xmm1 = xmm1[0],mem[0]
; X64-AVX1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x58,0xc1]
; X64-AVX1-NEXT: vmovupd %xmm0, (%rdi) ## encoding: [0xc5,0xf9,0x11,0x07]
@@ -381,8 +381,8 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; X64-AVX512-LABEL: test_x86_sse2_storeu_pd:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9]
-; X64-AVX512-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
-; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI11_0-4, kind: reloc_riprel_4byte
+; X64-AVX512-NEXT: vmovhpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
+; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512-NEXT: ## xmm1 = xmm1[0],mem[0]
; X64-AVX512-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1]
; X64-AVX512-NEXT: vmovupd %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x07]
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
index c25d4618903a9..b10a7fda51f27 100644
--- a/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
@@ -768,42 +768,42 @@ define <8 x i16> @test_x86_sse2_packssdw_128_fold() {
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X86-SSE-NEXT: ## fixup A - offset: 3, value: LCPI30_0, kind: FK_Data_4
+; X86-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-SSE-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX1-LABEL: test_x86_sse2_packssdw_128_fold:
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI30_0, kind: FK_Data_4
+; X86-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX1-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512-LABEL: test_x86_sse2_packssdw_128_fold:
; X86-AVX512: ## %bb.0:
-; X86-AVX512-NEXT: vmovaps LCPI30_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,32767,32767,65535,32768]
+; X86-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,32767,32767,65535,32768]
; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI30_0, kind: FK_Data_4
+; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse2_packssdw_128_fold:
; X64-SSE: ## %bb.0:
; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X64-SSE-NEXT: ## fixup A - offset: 3, value: LCPI30_0-4, kind: reloc_riprel_4byte
+; X64-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX1-LABEL: test_x86_sse2_packssdw_128_fold:
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI30_0-4, kind: reloc_riprel_4byte
+; X64-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX1-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512-LABEL: test_x86_sse2_packssdw_128_fold:
; X64-AVX512: ## %bb.0:
-; X64-AVX512-NEXT: vmovaps {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,32767,32767,65535,32768]
+; X64-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,32767,32767,65535,32768]
; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI30_0-4, kind: reloc_riprel_4byte
+; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)
ret <8 x i16> %res
@@ -836,42 +836,42 @@ define <16 x i8> @test_x86_sse2_packsswb_128_fold() {
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X86-SSE-NEXT: ## fixup A - offset: 3, value: LCPI32_0, kind: FK_Data_4
+; X86-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-SSE-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX1-LABEL: test_x86_sse2_packsswb_128_fold:
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI32_0, kind: FK_Data_4
+; X86-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX1-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512-LABEL: test_x86_sse2_packsswb_128_fold:
; X86-AVX512: ## %bb.0:
-; X86-AVX512-NEXT: vmovaps LCPI32_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X86-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI32_0, kind: FK_Data_4
+; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse2_packsswb_128_fold:
; X64-SSE: ## %bb.0:
; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X64-SSE-NEXT: ## fixup A - offset: 3, value: LCPI32_0-4, kind: reloc_riprel_4byte
+; X64-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX1-LABEL: test_x86_sse2_packsswb_128_fold:
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI32_0-4, kind: reloc_riprel_4byte
+; X64-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX1-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512-LABEL: test_x86_sse2_packsswb_128_fold:
; X64-AVX512: ## %bb.0:
-; X64-AVX512-NEXT: vmovaps {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X64-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI32_0-4, kind: reloc_riprel_4byte
+; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)
ret <16 x i8> %res
@@ -904,42 +904,42 @@ define <16 x i8> @test_x86_sse2_packuswb_128_fold() {
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X86-SSE-NEXT: ## fixup A - offset: 3, value: LCPI34_0, kind: FK_Data_4
+; X86-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-SSE-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX1-LABEL: test_x86_sse2_packuswb_128_fold:
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI34_0, kind: FK_Data_4
+; X86-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX1-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512-LABEL: test_x86_sse2_packuswb_128_fold:
; X86-AVX512: ## %bb.0:
-; X86-AVX512-NEXT: vmovaps LCPI34_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X86-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI34_0, kind: FK_Data_4
+; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse2_packuswb_128_fold:
; X64-SSE: ## %bb.0:
; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X64-SSE-NEXT: ## fixup A - offset: 3, value: LCPI34_0-4, kind: reloc_riprel_4byte
+; X64-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX1-LABEL: test_x86_sse2_packuswb_128_fold:
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI34_0-4, kind: reloc_riprel_4byte
+; X64-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX1-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512-LABEL: test_x86_sse2_packuswb_128_fold:
; X64-AVX512: ## %bb.0:
-; X64-AVX512-NEXT: vmovaps {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X64-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI34_0-4, kind: reloc_riprel_4byte
+; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)
ret <16 x i8> %res
diff --git a/llvm/test/CodeGen/X86/sse2.ll b/llvm/test/CodeGen/X86/sse2.ll
index 49aefe0ec5e9a..7bdab502c18f8 100644
--- a/llvm/test/CodeGen/X86/sse2.ll
+++ b/llvm/test/CodeGen/X86/sse2.ll
@@ -284,12 +284,12 @@ define <2 x i64> @test8() nounwind {
;
; X64-SSE-LABEL: test8:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: movups {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: movups x(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test8:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vmovups {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vmovups x(%rip), %xmm0
; X64-AVX-NEXT: retq
%tmp = load i32, i32* getelementptr ([4 x i32], [4 x i32]* @x, i32 0, i32 0) ; <i32> [#uses=1]
%tmp3 = load i32, i32* getelementptr ([4 x i32], [4 x i32]* @x, i32 0, i32 1) ; <i32> [#uses=1]
@@ -675,7 +675,7 @@ define <2 x i64> @test_insert_64_zext(<2 x i64> %i) {
define <4 x i32> @PR19721(<4 x i32> %i) {
; X86-SSE-LABEL: PR19721:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; AVX-LABEL: PR19721:
@@ -686,7 +686,7 @@ define <4 x i32> @PR19721(<4 x i32> %i) {
;
; X64-SSE-LABEL: PR19721:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
%bc = bitcast <4 x i32> %i to i128
%insert = and i128 %bc, -4294967296
diff --git a/llvm/test/CodeGen/X86/sse3.ll b/llvm/test/CodeGen/X86/sse3.ll
index 7a82e68122081..5fa5792905709 100644
--- a/llvm/test/CodeGen/X86/sse3.ll
+++ b/llvm/test/CodeGen/X86/sse3.ll
@@ -266,7 +266,7 @@ define void @t10() nounwind {
; X64-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X64-NEXT: movq %xmm0, {{.*}}(%rip)
+; X64-NEXT: movq %xmm0, g2(%rip)
; X64-NEXT: retq
load <4 x i32>, <4 x i32>* @g1, align 16
bitcast <4 x i32> %1 to <8 x i16>
@@ -397,13 +397,13 @@ define <4 x i32> @t17() nounwind {
; X86-LABEL: t17:
; X86: # %bb.0: # %entry
; X86-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1]
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: t17:
; X64: # %bb.0: # %entry
; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1]
-; X64-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
entry:
%tmp1 = load <4 x float>, <4 x float>* undef, align 16
diff --git a/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll b/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
index 3a78ec5d6f6df..3218916ddc285 100644
--- a/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
@@ -143,42 +143,42 @@ define <8 x i16> @test_x86_sse41_packusdw_fold() {
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X86-SSE-NEXT: ## fixup A - offset: 3, value: LCPI7_0, kind: FK_Data_4
+; X86-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-SSE-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX1-LABEL: test_x86_sse41_packusdw_fold:
; X86-AVX1: ## %bb.0:
; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI7_0, kind: FK_Data_4
+; X86-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX1-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512-LABEL: test_x86_sse41_packusdw_fold:
; X86-AVX512: ## %bb.0:
-; X86-AVX512-NEXT: vmovaps LCPI7_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,65535,65535,0,0]
+; X86-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,65535,65535,0,0]
; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI7_0, kind: FK_Data_4
+; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse41_packusdw_fold:
; X64-SSE: ## %bb.0:
; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X64-SSE-NEXT: ## fixup A - offset: 3, value: LCPI7_0-4, kind: reloc_riprel_4byte
+; X64-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX1-LABEL: test_x86_sse41_packusdw_fold:
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI7_0-4, kind: reloc_riprel_4byte
+; X64-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX1-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512-LABEL: test_x86_sse41_packusdw_fold:
; X64-AVX512: ## %bb.0:
-; X64-AVX512-NEXT: vmovaps {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,65535,65535,0,0]
+; X64-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,65535,65535,0,0]
; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI7_0-4, kind: reloc_riprel_4byte
+; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)
ret <8 x i16> %res
diff --git a/llvm/test/CodeGen/X86/sse41.ll b/llvm/test/CodeGen/X86/sse41.ll
index ec690f13fc40d..17aae3373c5ec 100644
--- a/llvm/test/CodeGen/X86/sse41.ll
+++ b/llvm/test/CodeGen/X86/sse41.ll
@@ -103,7 +103,7 @@ define <2 x i64> @pmovzxbq_1() nounwind {
;
; X64-SSE-LABEL: pmovzxbq_1:
; X64-SSE: ## %bb.0: ## %entry
-; X64-SSE-NEXT: movq _g16@{{.*}}(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
+; X64-SSE-NEXT: movq _g16 at GOTPCREL(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
; X64-SSE-NEXT: ## fixup A - offset: 3, value: _g16 at GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
; X64-SSE-NEXT: pmovzxbq (%rax), %xmm0 ## encoding: [0x66,0x0f,0x38,0x32,0x00]
; X64-SSE-NEXT: ## xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
@@ -111,7 +111,7 @@ define <2 x i64> @pmovzxbq_1() nounwind {
;
; X64-AVX1-LABEL: pmovzxbq_1:
; X64-AVX1: ## %bb.0: ## %entry
-; X64-AVX1-NEXT: movq _g16@{{.*}}(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
+; X64-AVX1-NEXT: movq _g16 at GOTPCREL(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
; X64-AVX1-NEXT: ## fixup A - offset: 3, value: _g16 at GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
; X64-AVX1-NEXT: vpmovzxbq (%rax), %xmm0 ## encoding: [0xc4,0xe2,0x79,0x32,0x00]
; X64-AVX1-NEXT: ## xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
@@ -119,7 +119,7 @@ define <2 x i64> @pmovzxbq_1() nounwind {
;
; X64-AVX512-LABEL: pmovzxbq_1:
; X64-AVX512: ## %bb.0: ## %entry
-; X64-AVX512-NEXT: movq _g16@{{.*}}(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
+; X64-AVX512-NEXT: movq _g16 at GOTPCREL(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
; X64-AVX512-NEXT: ## fixup A - offset: 3, value: _g16 at GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
; X64-AVX512-NEXT: vpmovzxbq (%rax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x32,0x00]
; X64-AVX512-NEXT: ## xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
@@ -184,8 +184,8 @@ define float @ext_1(<4 x float> %v) nounwind {
; X86-SSE-NEXT: pushl %eax ## encoding: [0x50]
; X86-SSE-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; X86-SSE-NEXT: ## xmm0 = xmm0[3,3,3,3]
-; X86-SSE-NEXT: addss LCPI5_0, %xmm0 ## encoding: [0xf3,0x0f,0x58,0x05,A,A,A,A]
-; X86-SSE-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
+; X86-SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## encoding: [0xf3,0x0f,0x58,0x05,A,A,A,A]
+; X86-SSE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-SSE-NEXT: movss %xmm0, (%esp) ## encoding: [0xf3,0x0f,0x11,0x04,0x24]
; X86-SSE-NEXT: flds (%esp) ## encoding: [0xd9,0x04,0x24]
; X86-SSE-NEXT: popl %eax ## encoding: [0x58]
@@ -196,8 +196,8 @@ define float @ext_1(<4 x float> %v) nounwind {
; X86-AVX1-NEXT: pushl %eax ## encoding: [0x50]
; X86-AVX1-NEXT: vpermilps $255, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x04,0xc0,0xff]
; X86-AVX1-NEXT: ## xmm0 = xmm0[3,3,3,3]
-; X86-AVX1-NEXT: vaddss LCPI5_0, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
-; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
+; X86-AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
+; X86-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX1-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; X86-AVX1-NEXT: flds (%esp) ## encoding: [0xd9,0x04,0x24]
; X86-AVX1-NEXT: popl %eax ## encoding: [0x58]
@@ -208,8 +208,8 @@ define float @ext_1(<4 x float> %v) nounwind {
; X86-AVX512-NEXT: pushl %eax ## encoding: [0x50]
; X86-AVX512-NEXT: vpermilps $255, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x04,0xc0,0xff]
; X86-AVX512-NEXT: ## xmm0 = xmm0[3,3,3,3]
-; X86-AVX512-NEXT: vaddss LCPI5_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
-; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
+; X86-AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
+; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512-NEXT: vmovss %xmm0, (%esp) ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x11,0x04,0x24]
; X86-AVX512-NEXT: flds (%esp) ## encoding: [0xd9,0x04,0x24]
; X86-AVX512-NEXT: popl %eax ## encoding: [0x58]
@@ -219,24 +219,24 @@ define float @ext_1(<4 x float> %v) nounwind {
; X64-SSE: ## %bb.0:
; X64-SSE-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; X64-SSE-NEXT: ## xmm0 = xmm0[3,3,3,3]
-; X64-SSE-NEXT: addss {{.*}}(%rip), %xmm0 ## encoding: [0xf3,0x0f,0x58,0x05,A,A,A,A]
-; X64-SSE-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
+; X64-SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ## encoding: [0xf3,0x0f,0x58,0x05,A,A,A,A]
+; X64-SSE-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX1-LABEL: ext_1:
; X64-AVX1: ## %bb.0:
; X64-AVX1-NEXT: vpermilps $255, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x04,0xc0,0xff]
; X64-AVX1-NEXT: ## xmm0 = xmm0[3,3,3,3]
-; X64-AVX1-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
-; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
+; X64-AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
+; X64-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX1-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512-LABEL: ext_1:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vpermilps $255, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x04,0xc0,0xff]
; X64-AVX512-NEXT: ## xmm0 = xmm0[3,3,3,3]
-; X64-AVX512-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
-; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
+; X64-AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x58,0x05,A,A,A,A]
+; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%s = extractelement <4 x float> %v, i32 3
%t = fadd float %s, 1.0
diff --git a/llvm/test/CodeGen/X86/ssub_sat.ll b/llvm/test/CodeGen/X86/ssub_sat.ll
index 4198904ab170c..0a72b8a01b612 100644
--- a/llvm/test/CodeGen/X86/ssub_sat.ll
+++ b/llvm/test/CodeGen/X86/ssub_sat.ll
@@ -219,7 +219,7 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: pcmpgtd %xmm3, %xmm0
; X64-NEXT: pxor %xmm1, %xmm0
; X64-NEXT: movdqa %xmm3, %xmm1
-; X64-NEXT: pandn {{.*}}(%rip), %xmm1
+; X64-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: pcmpgtd %xmm3, %xmm2
; X64-NEXT: psrld $1, %xmm2
; X64-NEXT: por %xmm2, %xmm1
diff --git a/llvm/test/CodeGen/X86/ssub_sat_vec.ll b/llvm/test/CodeGen/X86/ssub_sat_vec.ll
index 7787d898ac4f1..0ae0cb5b557e2 100644
--- a/llvm/test/CodeGen/X86/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/X86/ssub_sat_vec.ll
@@ -506,7 +506,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; SSE-NEXT: pand %xmm2, %xmm0
; SSE-NEXT: psubsb %xmm1, %xmm0
; SSE-NEXT: psrlw $4, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: psubb %xmm1, %xmm0
@@ -521,7 +521,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpsubsb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -536,7 +536,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpsubsb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -551,7 +551,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX512F-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX512F-NEXT: vpsubsb %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX512F-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -567,7 +567,7 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; AVX512BW-NEXT: vpsubsb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
-; AVX512BW-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512BW-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: retq
%z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
@@ -577,31 +577,31 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; SSE-LABEL: v16i1:
; SSE: # %bb.0:
-; SSE-NEXT: xorps {{.*}}(%rip), %xmm1
+; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: andps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: v16i1:
; AVX1: # %bb.0:
-; AVX1-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: v16i1:
; AVX2: # %bb.0:
-; AVX2-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v16i1:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: v16i1:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpternlogq $96, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512BW-NEXT: vpternlogq $96, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512BW-NEXT: retq
%z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z
@@ -619,7 +619,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; SSE2-NEXT: pcmpgtd %xmm3, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm1
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pcmpgtd %xmm3, %xmm2
; SSE2-NEXT: psrld $1, %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
@@ -637,7 +637,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm0
; SSSE3-NEXT: pxor %xmm1, %xmm0
; SSSE3-NEXT: movdqa %xmm3, %xmm1
-; SSSE3-NEXT: pandn {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm2
; SSSE3-NEXT: psrld $1, %xmm2
; SSSE3-NEXT: por %xmm2, %xmm1
@@ -657,7 +657,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: movaps {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm0
-; SSE41-NEXT: blendvps %xmm0, {{.*}}(%rip), %xmm1
+; SSE41-NEXT: blendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm3
; SSE41-NEXT: movaps %xmm3, %xmm0
@@ -671,7 +671,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vmovaps {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
-; AVX1-NEXT: vblendvps %xmm1, {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vblendvps %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -710,7 +710,7 @@ define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtd %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vpbroadcastd {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648]
-; AVX512BW-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
@@ -728,7 +728,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-NEXT: pcmpgtd %xmm3, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm1
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pcmpgtd %xmm3, %xmm2
; SSE2-NEXT: psrld $1, %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
@@ -746,7 +746,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm0
; SSSE3-NEXT: pxor %xmm1, %xmm0
; SSSE3-NEXT: movdqa %xmm3, %xmm1
-; SSSE3-NEXT: pandn {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm2
; SSSE3-NEXT: psrld $1, %xmm2
; SSSE3-NEXT: por %xmm2, %xmm1
@@ -766,7 +766,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: movaps {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm0
-; SSE41-NEXT: blendvps %xmm0, {{.*}}(%rip), %xmm1
+; SSE41-NEXT: blendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm3
; SSE41-NEXT: movaps %xmm3, %xmm0
@@ -780,7 +780,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vmovaps {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
-; AVX1-NEXT: vblendvps %xmm1, {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vblendvps %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -819,7 +819,7 @@ define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtd %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vpbroadcastd {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648]
-; AVX512BW-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
@@ -939,7 +939,7 @@ define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; AVX1-NEXT: vxorps %ymm0, %ymm3, %ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX1-NEXT: vblendvps %ymm1, {{.*}}(%rip), %ymm2, %ymm2
+; AVX1-NEXT: vblendvps %ymm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX1-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -978,7 +978,7 @@ define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtd %ymm1, %ymm2, %k2
; AVX512BW-NEXT: vpbroadcastd {{.*#+}} ymm0 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX512BW-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k2}
; AVX512BW-NEXT: vmovdqa32 %ymm0, %ymm1 {%k1}
; AVX512BW-NEXT: vmovdqa %ymm1, %ymm0
; AVX512BW-NEXT: retq
@@ -1224,7 +1224,7 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
; AVX512-NEXT: kxorw %k1, %k0, %k1
; AVX512-NEXT: vpcmpgtd %zmm1, %zmm2, %k2
; AVX512-NEXT: vpbroadcastd {{.*#+}} zmm0 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX512-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k2}
+; AVX512-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k2}
; AVX512-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; AVX512-NEXT: vmovdqa64 %zmm1, %zmm0
; AVX512-NEXT: retq
@@ -1262,10 +1262,10 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: pandn %xmm0, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
@@ -1300,10 +1300,10 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSSE3-NEXT: movdqa %xmm2, %xmm1
; SSSE3-NEXT: pandn %xmm0, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; SSSE3-NEXT: pandn {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: pxor %xmm4, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm4
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm4
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSSE3-NEXT: por %xmm4, %xmm0
; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: por %xmm1, %xmm0
@@ -1334,7 +1334,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE41-NEXT: pxor %xmm4, %xmm3
; SSE41-NEXT: movapd {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; SSE41-NEXT: movdqa %xmm2, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, {{.*}}(%rip), %xmm1
+; SSE41-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm0
@@ -1348,7 +1348,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vmovapd {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
-; AVX1-NEXT: vblendvpd %xmm1, {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vblendvpd %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -1360,7 +1360,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vmovapd {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
-; AVX2-NEXT: vblendvpd %xmm1, {{.*}}(%rip), %xmm2, %xmm2
+; AVX2-NEXT: vblendvpd %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
; AVX2-NEXT: retq
;
@@ -1372,7 +1372,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512F-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpxor %xmm0, %xmm2, %xmm0
; AVX512F-NEXT: vmovapd {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
-; AVX512F-NEXT: vblendvpd %xmm1, {{.*}}(%rip), %xmm2, %xmm2
+; AVX512F-NEXT: vblendvpd %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512F-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
; AVX512F-NEXT: retq
;
@@ -1385,7 +1385,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
-; AVX512BW-NEXT: vmovdqa64 {{.*}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
@@ -1611,7 +1611,7 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; AVX1-NEXT: vxorpd %ymm0, %ymm3, %ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vmovapd {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX1-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm2, %ymm2
+; AVX1-NEXT: vblendvpd %ymm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX1-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -1650,7 +1650,7 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %ymm1, %ymm2, %k2
; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm0 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX512BW-NEXT: vpbroadcastq {{.*}}(%rip), %ymm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %ymm0, %ymm1 {%k1}
; AVX512BW-NEXT: vmovdqa %ymm1, %ymm0
; AVX512BW-NEXT: retq
@@ -2103,7 +2103,7 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; AVX512-NEXT: kxorw %k1, %k0, %k1
; AVX512-NEXT: vpcmpgtq %zmm1, %zmm2, %k2
; AVX512-NEXT: vpbroadcastq {{.*#+}} zmm0 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX512-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k2}
+; AVX512-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0 {%k2}
; AVX512-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; AVX512-NEXT: vmovdqa64 %zmm1, %zmm0
; AVX512-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/stack-folding-int-avx2.ll b/llvm/test/CodeGen/X86/stack-folding-int-avx2.ll
index 38d87beb58cc5..e7302ea1d5351 100644
--- a/llvm/test/CodeGen/X86/stack-folding-int-avx2.ll
+++ b/llvm/test/CodeGen/X86/stack-folding-int-avx2.ll
@@ -90,7 +90,7 @@ define <8 x i32> @stack_fold_inserti128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -361,7 +361,7 @@ define <32 x i8> @stack_fold_pand(<32 x i8> %a0, <32 x i8> %a1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpand {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
-; CHECK-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = and <32 x i8> %a0, %a1
@@ -378,7 +378,7 @@ define <32 x i8> @stack_fold_pandn(<32 x i8> %a0, <32 x i8> %a1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpandn {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
-; CHECK-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = xor <32 x i8> %a0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
@@ -454,7 +454,7 @@ define <8 x i32> @stack_fold_pblendd_ymm(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpblendd $7, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = mem[0,1,2],ymm0[3,4,5,6,7]
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 8, i32 9, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -529,7 +529,7 @@ define <4 x i32> @stack_fold_pbroadcastd(<4 x i32> %a0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpbroadcastd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -546,7 +546,7 @@ define <8 x i32> @stack_fold_pbroadcastd_ymm(<4 x i32> %a0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpbroadcastd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 16-byte Folded Reload
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <4 x i32> %a0, <4 x i32> undef, <8 x i32> zeroinitializer
@@ -563,7 +563,7 @@ define <2 x i64> @stack_fold_pbroadcastq(<2 x i64> %a0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpbroadcastq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -580,7 +580,7 @@ define <4 x i64> @stack_fold_pbroadcastq_ymm(<2 x i64> %a0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpbroadcastq {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 16-byte Folded Reload
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> zeroinitializer
@@ -746,7 +746,7 @@ define <8 x i32> @stack_fold_perm2i128(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vperm2i128 $33, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = ymm0[2,3],mem[0,1]
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
@@ -763,7 +763,7 @@ define <8 x i32> @stack_fold_permd(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpermd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a1, <8 x i32> %a0)
@@ -816,7 +816,7 @@ define <4 x i64> @stack_fold_permq(<4 x i64> %a0) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpermq $235, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = mem[3,2,2,3]
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 2, i32 3>
@@ -1424,7 +1424,7 @@ define <32 x i8> @stack_fold_por(<32 x i8> %a0, <32 x i8> %a1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpor {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
-; CHECK-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = or <32 x i8> %a0, %a1
@@ -1472,7 +1472,7 @@ define <8 x i32> @stack_fold_pshufd(<8 x i32> %a0) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpshufd $27, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = mem[3,2,1,0,7,6,5,4]
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -1966,7 +1966,7 @@ define <8 x i32> @stack_fold_punpckhdq(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpunpckhdq {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7]
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
@@ -1984,7 +1984,7 @@ define <4 x i64> @stack_fold_punpckhqdq(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpunpckhqdq {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = ymm0[1],mem[1],ymm0[3],mem[3]
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
@@ -2032,7 +2032,7 @@ define <8 x i32> @stack_fold_punpckldq(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpunpckldq {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5]
-; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
@@ -2050,7 +2050,7 @@ define <4 x i64> @stack_fold_punpcklqdq(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
; CHECK-NEXT: # ymm0 = ymm0[0],mem[0],ymm0[2],mem[2]
-; CHECK-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
@@ -2082,7 +2082,7 @@ define <32 x i8> @stack_fold_pxor(<32 x i8> %a0, <32 x i8> %a1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vpxor {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload
-; CHECK-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
%2 = xor <32 x i8> %a0, %a1
diff --git a/llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll b/llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
index ccc4b34ae930f..89ff110dc5184 100644
--- a/llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
+++ b/llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
@@ -15,14 +15,14 @@ define dso_local i32 @main(i32 %argc, i8** %argv, ...) #0 {
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: subq $320, %rsp ## imm = 0x140
-; CHECK-NEXT: movq ___security_cookie@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq ___security_cookie at GOTPCREL(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: movq %rax, -8(%rbp)
; CHECK-NEXT: movl %ecx, -276(%rbp)
; CHECK-NEXT: movq %rdx, -288(%rbp)
; CHECK-NEXT: movslq -276(%rbp), %rax
; CHECK-NEXT: movb $1, -272(%rbp,%rax)
-; CHECK-NEXT: leaq {{.*}}(%rip), %rcx
+; CHECK-NEXT: leaq L_.str(%rip), %rcx
; CHECK-NEXT: callq _printf
; CHECK-NEXT: movq -8(%rbp), %rcx
; CHECK-NEXT: callq ___security_check_cookie
diff --git a/llvm/test/CodeGen/X86/statepoint-allocas.ll b/llvm/test/CodeGen/X86/statepoint-allocas.ll
index abbd3e0a40e96..8e929d9a8f9d9 100644
--- a/llvm/test/CodeGen/X86/statepoint-allocas.ll
+++ b/llvm/test/CodeGen/X86/statepoint-allocas.ll
@@ -17,7 +17,7 @@ define i32 addrspace(1)* @test(i32 addrspace(1)* %ptr) gc "statepoint-example" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: movq (%rsp), %rax
; CHECK-NEXT: popq %rcx
@@ -38,7 +38,7 @@ define i32 addrspace(1)* @test2(i32 addrspace(1)* %ptr) gc "statepoint-example"
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
diff --git a/llvm/test/CodeGen/X86/statepoint-call-lowering.ll b/llvm/test/CodeGen/X86/statepoint-call-lowering.ll
index a371db4c0bb69..4cb683f7a2882 100644
--- a/llvm/test/CodeGen/X86/statepoint-call-lowering.ll
+++ b/llvm/test/CodeGen/X86/statepoint-call-lowering.ll
@@ -20,7 +20,7 @@ define i1 @test_i1_return() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -38,7 +38,7 @@ define i32 @test_i32_return() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq return_i32
+; CHECK-NEXT: callq return_i32 at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -54,7 +54,7 @@ define i32* @test_i32ptr_return() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq return_i32ptr
+; CHECK-NEXT: callq return_i32ptr at PLT
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -70,7 +70,7 @@ define float @test_float_return() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq return_float
+; CHECK-NEXT: callq return_float at PLT
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -86,7 +86,7 @@ define %struct @test_struct_return() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq return_struct
+; CHECK-NEXT: callq return_struct at PLT
; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -103,7 +103,7 @@ define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp5:
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -123,7 +123,7 @@ define void @test_void_vararg() gc "statepoint-example" {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movl $42, %edi
; CHECK-NEXT: movl $43, %esi
-; CHECK-NEXT: callq varargf
+; CHECK-NEXT: callq varargf at PLT
; CHECK-NEXT: .Ltmp6:
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -168,14 +168,14 @@ define i1 @test_cross_bb(i32 addrspace(1)* %a, i1 %external_cond) gc "statepoint
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movl %esi, %ebp
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp8:
; CHECK-NEXT: testb $1, %bpl
; CHECK-NEXT: je .LBB8_2
; CHECK-NEXT: # %bb.1: # %left
; CHECK-NEXT: movl %eax, %ebx
; CHECK-NEXT: movq (%rsp), %rdi
-; CHECK-NEXT: callq consume
+; CHECK-NEXT: callq consume at PLT
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: jmp .LBB8_3
; CHECK-NEXT: .LBB8_2: # %right
@@ -225,7 +225,7 @@ define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-exampl
; CHECK-NEXT: .cfi_adjust_cfa_offset 8
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: .cfi_adjust_cfa_offset 8
-; CHECK-NEXT: callq consume_attributes
+; CHECK-NEXT: callq consume_attributes at PLT
; CHECK-NEXT: .Ltmp9:
; CHECK-NEXT: addq $32, %rsp
; CHECK-NEXT: .cfi_adjust_cfa_offset -32
diff --git a/llvm/test/CodeGen/X86/statepoint-duplicates-export.ll b/llvm/test/CodeGen/X86/statepoint-duplicates-export.ll
index baf9d6fda9a86..b30b40da65eaa 100644
--- a/llvm/test/CodeGen/X86/statepoint-duplicates-export.ll
+++ b/llvm/test/CodeGen/X86/statepoint-duplicates-export.ll
@@ -16,9 +16,9 @@ define i1 @test() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp0:
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: popq %rcx
@@ -47,9 +47,9 @@ define i1 @test2(i32 addrspace(1)* %arg) gc "statepoint-example" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp2:
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: cmpq $0, (%rsp)
; CHECK-NEXT: sete %al
diff --git a/llvm/test/CodeGen/X86/statepoint-gc-live.ll b/llvm/test/CodeGen/X86/statepoint-gc-live.ll
index fbbd320ad3ca7..ef5740a16832b 100644
--- a/llvm/test/CodeGen/X86/statepoint-gc-live.ll
+++ b/llvm/test/CodeGen/X86/statepoint-gc-live.ll
@@ -11,7 +11,7 @@ define void @test_empty() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -26,7 +26,7 @@ define void @test_dead(i8 addrspace(1)* %p) gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -42,7 +42,7 @@ define i8 addrspace(1)* @test_one(i8 addrspace(1)* %p) gc "statepoint-example" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: movq (%rsp), %rax
; CHECK-NEXT: popq %rcx
@@ -62,7 +62,7 @@ define i8 addrspace(1)* @test_one_derived(i8 addrspace(1)* %p) gc "statepoint-ex
; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: addq $8, %rdi
; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: addq $24, %rsp
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke.ll b/llvm/test/CodeGen/X86/statepoint-invoke.ll
index 4b59cbed31c6d..6e9076bcd5235 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke.ll
+++ b/llvm/test/CodeGen/X86/statepoint-invoke.ll
@@ -9,28 +9,6 @@ declare i64 addrspace(1)* @"some_other_call"(i64 addrspace(1)*)
declare i32 @"personality_function"()
define i64 addrspace(1)* @test_basic(i64 addrspace(1)* %obj,
-; CHECK-LABEL: test_basic:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: .Ltmp0:
-; CHECK-NEXT: callq some_call
-; CHECK-NEXT: .Ltmp3:
-; CHECK-NEXT: .Ltmp1:
-; CHECK-NEXT: # %bb.1: # %invoke_safepoint_normal_dest
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB0_2: # %exceptional_return
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: .Ltmp2:
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
i64 addrspace(1)* %obj1)
gc "statepoint-example" personality i32 ()* @"personality_function" {
entry:
@@ -59,26 +37,6 @@ exceptional_return:
; CHECK: .p2align 4
define i64 addrspace(1)* @test_result(i64 addrspace(1)* %obj,
-; CHECK-LABEL: test_result:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: .Ltmp4:
-; CHECK-NEXT: callq some_other_call
-; CHECK-NEXT: .Ltmp7:
-; CHECK-NEXT: .Ltmp5:
-; CHECK-NEXT: # %bb.1: # %normal_return
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB1_2: # %exceptional_return
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp6:
-; CHECK-NEXT: movq (%rsp), %rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
i64 addrspace(1)* %obj1)
gc "statepoint-example" personality i32 ()* @personality_function {
entry:
@@ -102,57 +60,6 @@ exceptional_return:
; CHECK: .p2align 4
define i64 addrspace(1)* @test_same_val(i1 %cond, i64 addrspace(1)* %val1, i64 addrspace(1)* %val2, i64 addrspace(1)* %val3)
-; CHECK-LABEL: test_same_val:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: subq $16, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: movl %edi, %ebx
-; CHECK-NEXT: testb $1, %bl
-; CHECK-NEXT: je .LBB2_3
-; CHECK-NEXT: # %bb.1: # %left
-; CHECK-NEXT: movq %rsi, (%rsp)
-; CHECK-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: .Ltmp11:
-; CHECK-NEXT: movq %rsi, %rdi
-; CHECK-NEXT: callq some_call
-; CHECK-NEXT: .Ltmp14:
-; CHECK-NEXT: .Ltmp12:
-; CHECK-NEXT: # %bb.2: # %left.relocs
-; CHECK-NEXT: movq (%rsp), %rax
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; CHECK-NEXT: jmp .LBB2_5
-; CHECK-NEXT: .LBB2_3: # %right
-; CHECK-NEXT: movq %rdx, (%rsp)
-; CHECK-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: .Ltmp8:
-; CHECK-NEXT: movq %rsi, %rdi
-; CHECK-NEXT: callq some_call
-; CHECK-NEXT: .Ltmp15:
-; CHECK-NEXT: .Ltmp9:
-; CHECK-NEXT: # %bb.4: # %right.relocs
-; CHECK-NEXT: movq (%rsp), %rcx
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: .LBB2_5: # %normal_return
-; CHECK-NEXT: testb $1, %bl
-; CHECK-NEXT: cmoveq %rcx, %rax
-; CHECK-NEXT: .LBB2_6: # %normal_return
-; CHECK-NEXT: addq $16, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: popq %rbx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB2_9: # %exceptional_return.right
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: .Ltmp10:
-; CHECK-NEXT: movq (%rsp), %rax
-; CHECK-NEXT: jmp .LBB2_6
-; CHECK-NEXT: .LBB2_7: # %exceptional_return.left
-; CHECK-NEXT: .Ltmp13:
-; CHECK-NEXT: movq (%rsp), %rax
-; CHECK-NEXT: jmp .LBB2_6
gc "statepoint-example" personality i32 ()* @"personality_function" {
entry:
br i1 %cond, label %left, label %right
@@ -195,23 +102,6 @@ exceptional_return.right:
}
define i64 addrspace(1)* @test_null_undef(i64 addrspace(1)* %val1)
-; CHECK-LABEL: test_null_undef:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp16:
-; CHECK-NEXT: callq some_call
-; CHECK-NEXT: .Ltmp19:
-; CHECK-NEXT: .Ltmp17:
-; CHECK-NEXT: .LBB3_1: # %normal_return
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB3_2: # %exceptional_return
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp18:
-; CHECK-NEXT: jmp .LBB3_1
gc "statepoint-example" personality i32 ()* @"personality_function" {
entry:
%sp1 = invoke token (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @some_call, i32 1, i32 0, i64 addrspace(1)* %val1, i32 0, i32 0) ["gc-live"(i64 addrspace(1)* null, i64 addrspace(1)* undef)]
@@ -231,26 +121,6 @@ exceptional_return:
}
define i64 addrspace(1)* @test_alloca_and_const(i64 addrspace(1)* %val1)
-; CHECK-LABEL: test_alloca_and_const:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp20:
-; CHECK-NEXT: callq some_call
-; CHECK-NEXT: .Ltmp23:
-; CHECK-NEXT: .Ltmp21:
-; CHECK-NEXT: # %bb.1: # %normal_return
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB4_2: # %exceptional_return
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp22:
-; CHECK-NEXT: movl $15, %eax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
gc "statepoint-example" personality i32 ()* @"personality_function" {
entry:
%a = alloca i32
diff --git a/llvm/test/CodeGen/X86/statepoint-live-in-remat.ll b/llvm/test/CodeGen/X86/statepoint-live-in-remat.ll
index 4b09ad2dfe622..02f57f85fc6a7 100644
--- a/llvm/test/CodeGen/X86/statepoint-live-in-remat.ll
+++ b/llvm/test/CodeGen/X86/statepoint-live-in-remat.ll
@@ -77,9 +77,6 @@ define void @test(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
-
-; Re-materialization happened.
-
; CHECK-NEXT: movabsq $_bar, %r13
; CHECK-NEXT: callq *%r13 ## 96-byte Folded Reload
; CHECK-NEXT: Ltmp0:
@@ -92,6 +89,9 @@ define void @test(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
+; Re-materialization happened.
+
+
; This is a call to hoist the loading of the target of the call for statepoint.
call void @bar()
br label %entry
diff --git a/llvm/test/CodeGen/X86/statepoint-live-in.ll b/llvm/test/CodeGen/X86/statepoint-live-in.ll
index d2c6f7abbf3e7..c684837e9a8c0 100644
--- a/llvm/test/CodeGen/X86/statepoint-live-in.ll
+++ b/llvm/test/CodeGen/X86/statepoint-live-in.ll
@@ -589,7 +589,7 @@ define void @addr_func() gc "statepoint-example" {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movq _bar@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _bar at GOTPCREL(%rip), %rax
; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp14:
; CHECK-NEXT: popq %rax
@@ -606,7 +606,7 @@ define void @addr_global() gc "statepoint-example" {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movq _G@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq _G at GOTPCREL(%rip), %rax
; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp15:
; CHECK-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/statepoint-no-realign-stack.ll b/llvm/test/CodeGen/X86/statepoint-no-realign-stack.ll
index e030be0555717..c3ab358f42abe 100644
--- a/llvm/test/CodeGen/X86/statepoint-no-realign-stack.ll
+++ b/llvm/test/CodeGen/X86/statepoint-no-realign-stack.ll
@@ -24,7 +24,7 @@ define void @can_realign(<8 x i32>* %p) {
; CHECK-NEXT: vmovaps (%rdi), %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: movq %rbp, %rsp
; CHECK-NEXT: popq %rbp
@@ -43,7 +43,7 @@ define void @no_realign(<8 x i32>* %p) "no-realign-stack" {
; CHECK-NEXT: vmovaps (%rdi), %ymm0
; CHECK-NEXT: vmovups %ymm0, (%rsp)
; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: callq foo
+; CHECK-NEXT: callq foo at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -68,7 +68,7 @@ define <4 x i8 addrspace(1)*> @spillfill_can_realign(<4 x i8 addrspace(1)*> %obj
; CHECK-NEXT: subq $64, %rsp
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: callq do_safepoint
+; CHECK-NEXT: callq do_safepoint at PLT
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: vmovaps (%rsp), %ymm0
; CHECK-NEXT: movq %rbp, %rsp
@@ -88,7 +88,7 @@ define <4 x i8 addrspace(1)*> @spillfill_no_realign(<4 x i8 addrspace(1)*> %obj)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: vmovups %ymm0, (%rsp)
; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: callq do_safepoint
+; CHECK-NEXT: callq do_safepoint at PLT
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: vmovups (%rsp), %ymm0
; CHECK-NEXT: addq $40, %rsp
diff --git a/llvm/test/CodeGen/X86/statepoint-regs.ll b/llvm/test/CodeGen/X86/statepoint-regs.ll
index 016d6fd037d09..9a590820b325b 100644
--- a/llvm/test/CodeGen/X86/statepoint-regs.ll
+++ b/llvm/test/CodeGen/X86/statepoint-regs.ll
@@ -702,7 +702,7 @@ define void @addr_func() gc "statepoint-example" {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: movq _bar@{{.*}}(%rip), %rbx
+; CHECK-NEXT: movq _bar at GOTPCREL(%rip), %rbx
; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp15:
; CHECK-NEXT: popq %rbx
@@ -720,7 +720,7 @@ define void @addr_global() gc "statepoint-example" {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: movq _G@{{.*}}(%rip), %rbx
+; CHECK-NEXT: movq _G at GOTPCREL(%rip), %rbx
; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp16:
; CHECK-NEXT: popq %rbx
diff --git a/llvm/test/CodeGen/X86/statepoint-spill-slot-size-promotion.ll b/llvm/test/CodeGen/X86/statepoint-spill-slot-size-promotion.ll
index 2388ea8ccd291..a3a772b543967 100644
--- a/llvm/test/CodeGen/X86/statepoint-spill-slot-size-promotion.ll
+++ b/llvm/test/CodeGen/X86/statepoint-spill-slot-size-promotion.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py then fixed by hand.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
;
; Test
diff erent type sizes of deop bundle operands.
diff --git a/llvm/test/CodeGen/X86/statepoint-uniqueing.ll b/llvm/test/CodeGen/X86/statepoint-uniqueing.ll
index 02f69f4f7cfff..a22439662c620 100644
--- a/llvm/test/CodeGen/X86/statepoint-uniqueing.ll
+++ b/llvm/test/CodeGen/X86/statepoint-uniqueing.ll
@@ -17,12 +17,12 @@ define void @test_gcrelocate_uniqueing(i32 addrspace(1)* %ptr) gc "statepoint-ex
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq f
+; CHECK-NEXT: callq f at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: movq (%rsp), %rdi
; CHECK-NEXT: movq %rdi, %rsi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq use
+; CHECK-NEXT: callq use at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -41,12 +41,12 @@ define void @test_gcptr_uniqueing(i32 addrspace(1)* %ptr) gc "statepoint-example
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq f
+; CHECK-NEXT: callq f at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: movq (%rsp), %rdi
; CHECK-NEXT: movq %rdi, %rsi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq use
+; CHECK-NEXT: callq use at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -67,7 +67,7 @@ define void @test_deopt_use(i32 addrspace(1)* %ptr) gc "statepoint-example" {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq f
+; CHECK-NEXT: callq f at PLT
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -83,7 +83,7 @@ define void @test_dse(i32 addrspace(1)* %ptr) gc "statepoint-example" {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq f
+; CHECK-NEXT: callq f at PLT
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/statepoint-vector.ll b/llvm/test/CodeGen/X86/statepoint-vector.ll
index 3131423696b29..7f7c7619b3a84 100644
--- a/llvm/test/CodeGen/X86/statepoint-vector.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vector.ll
@@ -11,7 +11,7 @@ define <2 x i8 addrspace(1)*> @test(<2 x i8 addrspace(1)*> %obj) gc "statepoint-
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: movaps %xmm0, (%rsp)
-; CHECK-NEXT: callq do_safepoint
+; CHECK-NEXT: callq do_safepoint at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: movaps (%rsp), %xmm0
; CHECK-NEXT: addq $24, %rsp
@@ -32,11 +32,11 @@ define <2 x i8 addrspace(1)*> @test2(<2 x i8 addrspace(1)*> %obj, i64 %offset) g
; CHECK-NEXT: movq %rdi, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; CHECK-NEXT: paddq %xmm0, %xmm1
-; CHECK-NEXT: movdqa %xmm0, {{[0-9]*}}(%rsp)
-; CHECK-NEXT: movdqa %xmm1, {{[0-9]*}}(%rsp)
-; CHECK-NEXT: callq do_safepoint
+; CHECK-NEXT: movdqa %xmm0, (%rsp)
+; CHECK-NEXT: movdqa %xmm1, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: callq do_safepoint at PLT
; CHECK-NEXT: .Ltmp1:
-; CHECK-NEXT: movaps {{[0-9]*}}(%rsp), %xmm0
+; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -63,7 +63,7 @@ define <2 x i64 addrspace(1)*> @test3(i1 %cnd, <2 x i64 addrspace(1)*>* %ptr) gc
; CHECK-NEXT: movaps (%rsi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp)
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: callq do_safepoint
+; CHECK-NEXT: callq do_safepoint at PLT
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: movaps (%rsp), %xmm0
; CHECK-NEXT: addq $40, %rsp
@@ -100,7 +100,7 @@ define <2 x i8 addrspace(1)*> @test4() gc "statepoint-example" {
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp)
-; CHECK-NEXT: callq do_safepoint
+; CHECK-NEXT: callq do_safepoint at PLT
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: movaps (%rsp), %xmm0
; CHECK-NEXT: addq $24, %rsp
@@ -115,7 +115,7 @@ entry:
; Check that we can lower a constant typed as i128 correctly. We don't have
; a representation of larger than 64 bit constant in the StackMap format. At
; the moment, this simply means spilling them, but there's a potential
-; optimization for values representable as sext(Con64).
+; optimization for values representable as sext(Con64).
define void @test5() gc "statepoint-example" {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
@@ -125,7 +125,7 @@ define void @test5() gc "statepoint-example" {
; CHECK-NEXT: movups %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $-1, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $-1, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: callq do_safepoint
+; CHECK-NEXT: callq do_safepoint at PLT
; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg.ll b/llvm/test/CodeGen/X86/statepoint-vreg.ll
index fd33cd9061b61..7581c5fb98c17 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vreg.ll
@@ -28,11 +28,11 @@ define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" {
; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: movl %eax, %ebp
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq consume
+; CHECK-NEXT: callq consume at PLT
; CHECK-NEXT: movl %ebp, %eax
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 24
@@ -65,14 +65,14 @@ define void @test_mixed(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspac
; CHECK-NEXT: movq %rdx, %r14
; CHECK-NEXT: movq %rsi, %r15
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: movq %r15, %rdx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movq %r14, %r8
-; CHECK-NEXT: callq consume5
+; CHECK-NEXT: callq consume5 at PLT
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: popq %r14
@@ -99,17 +99,17 @@ define i32 addrspace(1)* @test_alloca(i32 addrspace(1)* %ptr) gc "statepoint-exa
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 24
-; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %r14, -16
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: movq %rdi, {{[0-9]*}}(%rsp)
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: movq %rdi, (%rsp)
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp2:
-; CHECK-NEXT: movq {{[0-9]*}}(%rsp), %r14
+; CHECK-NEXT: movq (%rsp), %r14
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq consume
+; CHECK-NEXT: callq consume at PLT
; CHECK-NEXT: movq %r14, %rax
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 24
@@ -132,25 +132,25 @@ entry:
define void @test_base_derived(i32 addrspace(1)* %base, i32 addrspace(1)* %derived) gc "statepoint-example" {
; CHECK-LABEL: test_base_derived:
; CHECK: # %bb.0:
-; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 24
-; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %r14, -16
-; CHECK-NEXT: movq %rsi, %rbx
-; CHECK-NEXT: movq %rdi, %r14
-; CHECK-NEXT: callq func
+; CHECK-NEXT: movq %rsi, %rbx
+; CHECK-NEXT: movq %rdi, %r14
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq consume
-; CHECK-NEXT: addq $8, %rsp
+; CHECK-NEXT: callq consume at PLT
+; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 24
-; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
%safepoint_token = tail call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i32 addrspace(1)* %base, i32 addrspace(1)* %derived)]
@@ -173,10 +173,10 @@ define void @test_deopt_gcpointer(i32 addrspace(1)* %a, i32 addrspace(1)* %b) gc
; CHECK-NEXT: .cfi_offset %r14, -16
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq %rdi, %r14
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq consume
+; CHECK-NEXT: callq consume at PLT
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: popq %rbx
@@ -198,11 +198,11 @@ define void @test_gcrelocate_uniqueing(i32 addrspace(1)* %ptr) gc "statepoint-ex
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp5:
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movq %rbx, %rsi
-; CHECK-NEXT: callq consume2
+; CHECK-NEXT: callq consume2 at PLT
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -221,11 +221,11 @@ define void @test_gcptr_uniqueing(i32 addrspace(1)* %ptr) gc "statepoint-example
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp6:
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movq %rbx, %rsi
-; CHECK-NEXT: callq use1
+; CHECK-NEXT: callq use1 at PLT
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -254,14 +254,14 @@ define i1 @test_cross_bb(i32 addrspace(1)* %a, i1 %external_cond) gc "statepoint
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movl %esi, %ebp
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq return_i1
+; CHECK-NEXT: callq return_i1 at PLT
; CHECK-NEXT: .Ltmp7:
; CHECK-NEXT: testb $1, %bpl
; CHECK-NEXT: je .LBB7_2
; CHECK-NEXT: # %bb.1: # %left
; CHECK-NEXT: movl %eax, %r14d
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq consume
+; CHECK-NEXT: callq consume at PLT
; CHECK-NEXT: movl %r14d, %eax
; CHECK-NEXT: jmp .LBB7_3
; CHECK-NEXT: .LBB7_2: # %right
@@ -294,9 +294,9 @@ define i1 @duplicate_reloc() gc "statepoint-example" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp8:
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp9:
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: popq %rcx
@@ -323,7 +323,7 @@ define <2 x i8 addrspace(1)*> @test_vector(<2 x i8 addrspace(1)*> %obj) gc "stat
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: movaps %xmm0, (%rsp)
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp10:
; CHECK-NEXT: movaps (%rsp), %xmm0
; CHECK-NEXT: addq $24, %rsp
@@ -359,14 +359,14 @@ define void @test_limit(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspac
; CHECK-NEXT: movq %rdx, %r12
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq %rdi, (%rsp)
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp11:
; CHECK-NEXT: movq (%rsp), %rdi
; CHECK-NEXT: movq %rbx, %rsi
; CHECK-NEXT: movq %r12, %rdx
; CHECK-NEXT: movq %r15, %rcx
; CHECK-NEXT: movq %r14, %r8
-; CHECK-NEXT: callq consume5
+; CHECK-NEXT: callq consume5 at PLT
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 40
; CHECK-NEXT: popq %rbx
@@ -397,10 +397,10 @@ define void @test_const_base(i32 addrspace(1)* %a) gc "statepoint-example" {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
-; CHECK-NEXT: callq func
+; CHECK-NEXT: callq func at PLT
; CHECK-NEXT: .Ltmp12:
; CHECK-NEXT: movq %rbx, %rdi
-; CHECK-NEXT: callq consume
+; CHECK-NEXT: callq consume at PLT
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -427,7 +427,7 @@ define void @test_sched(float %0, i32 %1, i8 addrspace(1)* %2) gc "statepoint-ex
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT: callq consume3
+; CHECK-NEXT: callq consume3 at PLT
; CHECK-NEXT: .Ltmp13:
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: cvtsi2sd %ebp, %xmm0
diff --git a/llvm/test/CodeGen/X86/store-narrow.ll b/llvm/test/CodeGen/X86/store-narrow.ll
index 122e384ee3c89..007773af0afc1 100644
--- a/llvm/test/CodeGen/X86/store-narrow.ll
+++ b/llvm/test/CodeGen/X86/store-narrow.ll
@@ -191,7 +191,7 @@ entry:
define void @test8() nounwind {
; X64-LABEL: test8:
; X64: ## %bb.0:
-; X64-NEXT: orb $1, {{.*}}(%rip)
+; X64-NEXT: orb $1, _g_16(%rip)
; X64-NEXT: retq
;
; X86-LABEL: test8:
@@ -208,7 +208,7 @@ define void @test8() nounwind {
define void @test9() nounwind {
; X64-LABEL: test9:
; X64: ## %bb.0:
-; X64-NEXT: orb $1, {{.*}}(%rip)
+; X64-NEXT: orb $1, _g_16(%rip)
; X64-NEXT: retq
;
; X86-LABEL: test9:
diff --git a/llvm/test/CodeGen/X86/sub-with-overflow.ll b/llvm/test/CodeGen/X86/sub-with-overflow.ll
index 6de0beeabdfe0..8365f731995cb 100644
--- a/llvm/test/CodeGen/X86/sub-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/sub-with-overflow.ll
@@ -13,14 +13,14 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: jno .LBB0_1
; CHECK-NEXT: # %bb.2: # %overflow
; CHECK-NEXT: movl $no, (%esp)
-; CHECK-NEXT: calll printf
+; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %normal
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $ok, (%esp)
-; CHECK-NEXT: calll printf
+; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
@@ -49,14 +49,14 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: jae .LBB1_1
; CHECK-NEXT: # %bb.2: # %carry
; CHECK-NEXT: movl $no, (%esp)
-; CHECK-NEXT: calll printf
+; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_1: # %normal
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $ok, (%esp)
-; CHECK-NEXT: calll printf
+; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/subvector-broadcast.ll b/llvm/test/CodeGen/X86/subvector-broadcast.ll
index f031e7dcb08de..231d9618e6afc 100644
--- a/llvm/test/CodeGen/X86/subvector-broadcast.ll
+++ b/llvm/test/CodeGen/X86/subvector-broadcast.ll
@@ -870,10 +870,10 @@ define dso_local void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64>
; X64-AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
; X64-AVX1-NEXT: vandps %ymm6, %ymm1, %ymm1
; X64-AVX1-NEXT: vandps %ymm6, %ymm2, %ymm2
-; X64-AVX1-NEXT: vmovdqu %xmm0, ga4+{{.*}}(%rip)
-; X64-AVX1-NEXT: vmovdqu %xmm4, {{.*}}(%rip)
-; X64-AVX1-NEXT: vmovups %ymm2, gb4+{{.*}}(%rip)
-; X64-AVX1-NEXT: vmovups %ymm1, {{.*}}(%rip)
+; X64-AVX1-NEXT: vmovdqu %xmm0, ga4+16(%rip)
+; X64-AVX1-NEXT: vmovdqu %xmm4, ga4(%rip)
+; X64-AVX1-NEXT: vmovups %ymm2, gb4+32(%rip)
+; X64-AVX1-NEXT: vmovups %ymm1, gb4(%rip)
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -885,9 +885,9 @@ define dso_local void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64>
; X64-AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
; X64-AVX2-NEXT: vpand %ymm3, %ymm1, %ymm1
; X64-AVX2-NEXT: vpand %ymm3, %ymm2, %ymm2
-; X64-AVX2-NEXT: vmovdqu %ymm0, {{.*}}(%rip)
-; X64-AVX2-NEXT: vmovdqu %ymm2, gb4+{{.*}}(%rip)
-; X64-AVX2-NEXT: vmovdqu %ymm1, {{.*}}(%rip)
+; X64-AVX2-NEXT: vmovdqu %ymm0, ga4(%rip)
+; X64-AVX2-NEXT: vmovdqu %ymm2, gb4+32(%rip)
+; X64-AVX2-NEXT: vmovdqu %ymm1, gb4(%rip)
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -898,8 +898,8 @@ define dso_local void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64>
; X64-AVX512-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; X64-AVX512-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; X64-AVX512-NEXT: vpandq %zmm2, %zmm1, %zmm1
-; X64-AVX512-NEXT: vmovdqu %ymm0, {{.*}}(%rip)
-; X64-AVX512-NEXT: vmovdqu64 %zmm1, {{.*}}(%rip)
+; X64-AVX512-NEXT: vmovdqu %ymm0, ga4(%rip)
+; X64-AVX512-NEXT: vmovdqu64 %zmm1, gb4(%rip)
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
entry:
@@ -950,9 +950,9 @@ define dso_local void @fallback_broadcast_v4f64_to_v8f64(<4 x double> %a, <8 x d
; X64-AVX-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; X64-AVX-NEXT: vdivpd %ymm3, %ymm1, %ymm1
; X64-AVX-NEXT: vdivpd %ymm3, %ymm2, %ymm2
-; X64-AVX-NEXT: vmovupd %ymm0, {{.*}}(%rip)
-; X64-AVX-NEXT: vmovupd %ymm2, gb2+{{.*}}(%rip)
-; X64-AVX-NEXT: vmovupd %ymm1, {{.*}}(%rip)
+; X64-AVX-NEXT: vmovupd %ymm0, ga2(%rip)
+; X64-AVX-NEXT: vmovupd %ymm2, gb2+32(%rip)
+; X64-AVX-NEXT: vmovupd %ymm1, gb2(%rip)
; X64-AVX-NEXT: vzeroupper
; X64-AVX-NEXT: retq
;
@@ -963,8 +963,8 @@ define dso_local void @fallback_broadcast_v4f64_to_v8f64(<4 x double> %a, <8 x d
; X64-AVX512-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; X64-AVX512-NEXT: vaddpd %zmm2, %zmm1, %zmm1
; X64-AVX512-NEXT: vdivpd %zmm2, %zmm1, %zmm1
-; X64-AVX512-NEXT: vmovupd %ymm0, {{.*}}(%rip)
-; X64-AVX512-NEXT: vmovupd %zmm1, {{.*}}(%rip)
+; X64-AVX512-NEXT: vmovupd %ymm0, ga2(%rip)
+; X64-AVX512-NEXT: vmovupd %zmm1, gb2(%rip)
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
entry:
@@ -1072,10 +1072,10 @@ define dso_local void @fallback_broadcast_v4i32_v8i32_v16i32(<4 x i32> %a, <8 x
; X64-AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2
; X64-AVX1-NEXT: vandps %ymm4, %ymm2, %ymm2
; X64-AVX1-NEXT: vandps %ymm4, %ymm3, %ymm3
-; X64-AVX1-NEXT: vmovdqu %xmm0, {{.*}}(%rip)
-; X64-AVX1-NEXT: vmovups %ymm1, {{.*}}(%rip)
-; X64-AVX1-NEXT: vmovups %ymm3, hc4+{{.*}}(%rip)
-; X64-AVX1-NEXT: vmovups %ymm2, {{.*}}(%rip)
+; X64-AVX1-NEXT: vmovdqu %xmm0, ha4(%rip)
+; X64-AVX1-NEXT: vmovups %ymm1, hb4(%rip)
+; X64-AVX1-NEXT: vmovups %ymm3, hc4+32(%rip)
+; X64-AVX1-NEXT: vmovups %ymm2, hc4(%rip)
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1090,10 +1090,10 @@ define dso_local void @fallback_broadcast_v4i32_v8i32_v16i32(<4 x i32> %a, <8 x
; X64-AVX2-NEXT: vpaddd %ymm4, %ymm2, %ymm2
; X64-AVX2-NEXT: vpand %ymm4, %ymm2, %ymm2
; X64-AVX2-NEXT: vpand %ymm4, %ymm3, %ymm3
-; X64-AVX2-NEXT: vmovdqu %xmm0, {{.*}}(%rip)
-; X64-AVX2-NEXT: vmovdqu %ymm1, {{.*}}(%rip)
-; X64-AVX2-NEXT: vmovdqu %ymm3, hc4+{{.*}}(%rip)
-; X64-AVX2-NEXT: vmovdqu %ymm2, {{.*}}(%rip)
+; X64-AVX2-NEXT: vmovdqu %xmm0, ha4(%rip)
+; X64-AVX2-NEXT: vmovdqu %ymm1, hb4(%rip)
+; X64-AVX2-NEXT: vmovdqu %ymm3, hc4+32(%rip)
+; X64-AVX2-NEXT: vmovdqu %ymm2, hc4(%rip)
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1106,9 +1106,9 @@ define dso_local void @fallback_broadcast_v4i32_v8i32_v16i32(<4 x i32> %a, <8 x
; X64-AVX512-NEXT: vpand %ymm3, %ymm1, %ymm1
; X64-AVX512-NEXT: vpaddd %zmm3, %zmm2, %zmm2
; X64-AVX512-NEXT: vpandd %zmm3, %zmm2, %zmm2
-; X64-AVX512-NEXT: vmovdqu %xmm0, {{.*}}(%rip)
-; X64-AVX512-NEXT: vmovdqu %ymm1, {{.*}}(%rip)
-; X64-AVX512-NEXT: vmovdqu64 %zmm2, {{.*}}(%rip)
+; X64-AVX512-NEXT: vmovdqu %xmm0, ha4(%rip)
+; X64-AVX512-NEXT: vmovdqu %ymm1, hb4(%rip)
+; X64-AVX512-NEXT: vmovdqu64 %zmm2, hc4(%rip)
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/swift-return.ll b/llvm/test/CodeGen/X86/swift-return.ll
index b2d1130a9b640..202a05409c425 100644
--- a/llvm/test/CodeGen/X86/swift-return.ll
+++ b/llvm/test/CodeGen/X86/swift-return.ll
@@ -12,7 +12,7 @@ define i16 @test(i32 %key) {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movl %edi, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: callq gen
+; CHECK-NEXT: callq gen at PLT
; CHECK-NEXT: # kill: def $ax killed $ax def $eax
; CHECK-NEXT: movsbl %dl, %ecx
; CHECK-NEXT: addl %ecx, %eax
@@ -27,7 +27,7 @@ define i16 @test(i32 %key) {
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
; CHECK-O0-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edi
-; CHECK-O0-NEXT: callq gen
+; CHECK-O0-NEXT: callq gen at PLT
; CHECK-O0-NEXT: cwtl
; CHECK-O0-NEXT: movsbl %dl, %ecx
; CHECK-O0-NEXT: addl %ecx, %eax
@@ -61,7 +61,7 @@ define dso_local i32 @test2(i32 %key) #0 {
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rsp, %rax
-; CHECK-NEXT: callq gen2
+; CHECK-NEXT: callq gen2 at PLT
; CHECK-NEXT: movl (%rsp), %eax
; CHECK-NEXT: addl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: addl {{[0-9]+}}(%rsp), %eax
@@ -78,7 +78,7 @@ define dso_local i32 @test2(i32 %key) #0 {
; CHECK-O0-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-O0-NEXT: movq %rsp, %rax
-; CHECK-O0-NEXT: callq gen2
+; CHECK-O0-NEXT: callq gen2 at PLT
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %ecx
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edx
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %esi
@@ -146,7 +146,7 @@ define dso_local i32 @test3(i32 %key) #0 {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movl %edi, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: callq gen3
+; CHECK-NEXT: callq gen3 at PLT
; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: addl %r8d, %eax
@@ -160,7 +160,7 @@ define dso_local i32 @test3(i32 %key) #0 {
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
; CHECK-O0-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edi
-; CHECK-O0-NEXT: callq gen3
+; CHECK-O0-NEXT: callq gen3 at PLT
; CHECK-O0-NEXT: addl %edx, %eax
; CHECK-O0-NEXT: addl %ecx, %eax
; CHECK-O0-NEXT: addl %r8d, %eax
@@ -194,7 +194,7 @@ define dso_local float @test4(float %key) #0 {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: callq gen4
+; CHECK-NEXT: callq gen4 at PLT
; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: addss %xmm2, %xmm0
; CHECK-NEXT: addss %xmm3, %xmm0
@@ -208,7 +208,7 @@ define dso_local float @test4(float %key) #0 {
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
; CHECK-O0-NEXT: movss %xmm0, {{[0-9]+}}(%rsp)
; CHECK-O0-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-O0-NEXT: callq gen4
+; CHECK-O0-NEXT: callq gen4 at PLT
; CHECK-O0-NEXT: addss %xmm1, %xmm0
; CHECK-O0-NEXT: addss %xmm2, %xmm0
; CHECK-O0-NEXT: addss %xmm3, %xmm0
@@ -239,19 +239,19 @@ define dso_local void @consume_i1_ret() {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq produce_i1_ret
+; CHECK-NEXT: callq produce_i1_ret at PLT
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, var(%rip)
; CHECK-NEXT: movzbl %dl, %eax
; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, var(%rip)
; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, var(%rip)
; CHECK-NEXT: movzbl %r8b, %eax
; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: movl %eax, {{.*}}(%rip)
+; CHECK-NEXT: movl %eax, var(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -260,7 +260,7 @@ define dso_local void @consume_i1_ret() {
; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: pushq %rax
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-O0-NEXT: callq produce_i1_ret
+; CHECK-O0-NEXT: callq produce_i1_ret at PLT
; CHECK-O0-NEXT: andb $1, %al
; CHECK-O0-NEXT: movzbl %al, %eax
; CHECK-O0-NEXT: movl %eax, var
@@ -313,7 +313,7 @@ define swiftcc double @test5() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq gen5
+; CHECK-NEXT: callq gen5 at PLT
; CHECK-NEXT: addsd %xmm1, %xmm0
; CHECK-NEXT: addsd %xmm2, %xmm0
; CHECK-NEXT: addsd %xmm3, %xmm0
@@ -325,7 +325,7 @@ define swiftcc double @test5() #0 {
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: pushq %rax
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-O0-NEXT: callq gen5
+; CHECK-O0-NEXT: callq gen5 at PLT
; CHECK-O0-NEXT: addsd %xmm1, %xmm0
; CHECK-O0-NEXT: addsd %xmm2, %xmm0
; CHECK-O0-NEXT: addsd %xmm3, %xmm0
@@ -354,7 +354,7 @@ define swiftcc { double, i64 } @test6() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq gen6
+; CHECK-NEXT: callq gen6 at PLT
; CHECK-NEXT: addsd %xmm1, %xmm0
; CHECK-NEXT: addsd %xmm2, %xmm0
; CHECK-NEXT: addsd %xmm3, %xmm0
@@ -369,7 +369,7 @@ define swiftcc { double, i64 } @test6() #0 {
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: pushq %rax
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-O0-NEXT: callq gen6
+; CHECK-O0-NEXT: callq gen6 at PLT
; CHECK-O0-NEXT: addsd %xmm1, %xmm0
; CHECK-O0-NEXT: addsd %xmm2, %xmm0
; CHECK-O0-NEXT: addsd %xmm3, %xmm0
@@ -514,7 +514,7 @@ define swiftcc <4 x float> @test11() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq gen11
+; CHECK-NEXT: callq gen11 at PLT
; CHECK-NEXT: addps %xmm1, %xmm0
; CHECK-NEXT: addps %xmm2, %xmm0
; CHECK-NEXT: addps %xmm3, %xmm0
@@ -526,7 +526,7 @@ define swiftcc <4 x float> @test11() #0 {
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: pushq %rax
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-O0-NEXT: callq gen11
+; CHECK-O0-NEXT: callq gen11 at PLT
; CHECK-O0-NEXT: addps %xmm1, %xmm0
; CHECK-O0-NEXT: addps %xmm2, %xmm0
; CHECK-O0-NEXT: addps %xmm3, %xmm0
@@ -554,7 +554,7 @@ define swiftcc { <4 x float>, float } @test12() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq gen12
+; CHECK-NEXT: callq gen12 at PLT
; CHECK-NEXT: addps %xmm1, %xmm0
; CHECK-NEXT: addps %xmm2, %xmm0
; CHECK-NEXT: movaps %xmm3, %xmm1
@@ -566,7 +566,7 @@ define swiftcc { <4 x float>, float } @test12() #0 {
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: subq $24, %rsp
; CHECK-O0-NEXT: .cfi_def_cfa_offset 32
-; CHECK-O0-NEXT: callq gen12
+; CHECK-O0-NEXT: callq gen12 at PLT
; CHECK-O0-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-O0-NEXT: movaps %xmm3, %xmm1
; CHECK-O0-NEXT: movaps (%rsp), %xmm3 # 16-byte Reload
diff --git a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
index daee8057b7dbd..bdcc7ee61fecf 100644
--- a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
+++ b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
@@ -107,7 +107,7 @@ define i32 @loop_shared_header(i8* %exe, i32 %exesz, i32 %headsize, i32 %min, i3
; CHECK-NEXT: movl %r14d, %r15d
; CHECK-NEXT: movl $1, %esi
; CHECK-NEXT: movq %r15, %rdi
-; CHECK-NEXT: callq cli_calloc
+; CHECK-NEXT: callq cli_calloc at PLT
; CHECK-NEXT: testl %r13d, %r13d
; CHECK-NEXT: je .LBB1_26
; CHECK-NEXT: # %bb.2: # %if.end19
@@ -124,7 +124,7 @@ define i32 @loop_shared_header(i8* %exe, i32 %exesz, i32 %headsize, i32 %min, i3
; CHECK-NEXT: # %bb.5: # %if.end50
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movq %r15, %rdx
-; CHECK-NEXT: callq memcpy
+; CHECK-NEXT: callq memcpy at PLT
; CHECK-NEXT: cmpl $4, %r14d
; CHECK-NEXT: jb .LBB1_29
; CHECK-NEXT: # %bb.6: # %shared_preheader
@@ -204,10 +204,10 @@ define i32 @loop_shared_header(i8* %exe, i32 %exesz, i32 %headsize, i32 %min, i3
; CHECK-NEXT: jne .LBB1_27
; CHECK-NEXT: .LBB1_21: # %if.end41.us1436.i
; CHECK-NEXT: .LBB1_23: # %if.then99.i
-; CHECK-NEXT: movq .str.6@{{.*}}(%rip), %rdi
+; CHECK-NEXT: movq .str.6 at GOTPCREL(%rip), %rdi
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: callq cli_dbgmsg
+; CHECK-NEXT: callq cli_dbgmsg at PLT
; CHECK-NEXT: .LBB1_27: # %cleanup
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll
index dc98c362b0d9c..40207f814f3fb 100644
--- a/llvm/test/CodeGen/X86/tail-opts.ll
+++ b/llvm/test/CodeGen/X86/tail-opts.ll
@@ -18,7 +18,7 @@ define dso_local void @tail_merge_me() nounwind {
; CHECK-LABEL: tail_merge_me:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.6: # %A
@@ -26,7 +26,7 @@ define dso_local void @tail_merge_me() nounwind {
; CHECK-NEXT: callq bar
; CHECK-NEXT: jmp .LBB0_4
; CHECK-NEXT: .LBB0_1: # %next
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.2: # %B
@@ -37,9 +37,9 @@ define dso_local void @tail_merge_me() nounwind {
; CHECK-NEXT: movl $2, %edi
; CHECK-NEXT: callq dar
; CHECK-NEXT: .LBB0_4: # %M
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
-; CHECK-NEXT: movl $1, {{.*}}(%rip)
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: movl $0, GHJK(%rip)
+; CHECK-NEXT: movl $1, HABC(%rip)
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB0_5
; CHECK-NEXT: # %bb.7: # %return
@@ -98,18 +98,18 @@ define dso_local void @tail_duplicate_me() nounwind {
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: movl $.Ltmp0, %edi
; CHECK-NEXT: movl $.Ltmp1, %esi
; CHECK-NEXT: movl %eax, %ebx
-; CHECK-NEXT: callq choose
+; CHECK-NEXT: callq choose at PLT
; CHECK-NEXT: movq %rax, %r14
; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: je .LBB1_1
; CHECK-NEXT: # %bb.7: # %A
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: callq bar
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, GHJK(%rip)
; CHECK-NEXT: jmpq *%r14
; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: .LBB1_4: # %return
@@ -117,13 +117,13 @@ define dso_local void @tail_duplicate_me() nounwind {
; CHECK-NEXT: callq ear
; CHECK-NEXT: jmp .LBB1_5
; CHECK-NEXT: .LBB1_1: # %next
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB1_3
; CHECK-NEXT: # %bb.2: # %B
; CHECK-NEXT: movl $1, %edi
; CHECK-NEXT: callq car
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, GHJK(%rip)
; CHECK-NEXT: jmpq *%r14
; CHECK-NEXT: .Ltmp1: # Block address taken
; CHECK-NEXT: .LBB1_6: # %altret
@@ -137,7 +137,7 @@ define dso_local void @tail_duplicate_me() nounwind {
; CHECK-NEXT: .LBB1_3: # %C
; CHECK-NEXT: movl $2, %edi
; CHECK-NEXT: callq dar
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, GHJK(%rip)
; CHECK-NEXT: jmpq *%r14
entry:
%a = call i1 @qux()
@@ -270,7 +270,7 @@ define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind {
; CHECK-NEXT: jne .LBB3_15
; CHECK-NEXT: # %bb.7: # %bb.i.i
; CHECK-NEXT: xorl %edi, %edi
-; CHECK-NEXT: callq lvalue_p
+; CHECK-NEXT: callq lvalue_p at PLT
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: setne %al
; CHECK-NEXT: jmp .LBB3_16
@@ -529,8 +529,8 @@ define dso_local void @two() nounwind optsize {
; CHECK-NEXT: # %bb.2: # %return
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB7_1: # %bb7
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
-; CHECK-NEXT: movl $1, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, XYZ(%rip)
+; CHECK-NEXT: movl $1, XYZ(%rip)
entry:
%0 = icmp eq i32 undef, 0
br i1 %0, label %bbx, label %bby
@@ -570,8 +570,8 @@ define dso_local void @two_pgso() nounwind !prof !14 {
; CHECK-NEXT: # %bb.2: # %return
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB8_1: # %bb7
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
-; CHECK-NEXT: movl $1, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, XYZ(%rip)
+; CHECK-NEXT: movl $1, XYZ(%rip)
entry:
%0 = icmp eq i32 undef, 0
br i1 %0, label %bbx, label %bby
@@ -613,8 +613,8 @@ define dso_local void @two_minsize() nounwind minsize {
; CHECK-NEXT: # %bb.2: # %return
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB9_1: # %bb7
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
-; CHECK-NEXT: movl $1, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, XYZ(%rip)
+; CHECK-NEXT: movl $1, XYZ(%rip)
entry:
%0 = icmp eq i32 undef, 0
br i1 %0, label %bbx, label %bby
@@ -655,13 +655,13 @@ define dso_local void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: je .LBB10_4
; CHECK-NEXT: # %bb.2: # %bb7
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, XYZ(%rip)
; CHECK-NEXT: jmp tail_call_me # TAILCALL
; CHECK-NEXT: .LBB10_3: # %bbx
; CHECK-NEXT: cmpl $-1, %edx
; CHECK-NEXT: je .LBB10_4
; CHECK-NEXT: # %bb.5: # %bb12
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, XYZ(%rip)
; CHECK-NEXT: jmp tail_call_me # TAILCALL
; CHECK-NEXT: .LBB10_4: # %return
; CHECK-NEXT: retq
@@ -734,19 +734,19 @@ define dso_local void @merge_aborts() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB12_5
; CHECK-NEXT: # %bb.1: # %cont1
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB12_5
; CHECK-NEXT: # %bb.2: # %cont2
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB12_5
; CHECK-NEXT: # %bb.3: # %cont3
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB12_5
; CHECK-NEXT: # %bb.4: # %cont4
@@ -794,19 +794,19 @@ define dso_local void @merge_alternating_aborts() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB13_5
; CHECK-NEXT: # %bb.1: # %cont1
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB13_6
; CHECK-NEXT: # %bb.2: # %cont2
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB13_5
; CHECK-NEXT: # %bb.3: # %cont3
-; CHECK-NEXT: callq qux
+; CHECK-NEXT: callq qux at PLT
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: je .LBB13_6
; CHECK-NEXT: # %bb.4: # %cont4
@@ -870,7 +870,7 @@ define dso_local void @bfi_new_block_pgso(i32 %c) nounwind {
; CHECK-NEXT: # %bb.5: # %return
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB14_6: # %bb3
-; CHECK-NEXT: movl $0, {{.*}}(%rip)
+; CHECK-NEXT: movl $0, GV(%rip)
; CHECK-NEXT: .LBB14_7: # %bb4
; CHECK-NEXT: callq func
; CHECK-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/tail-threshold.ll b/llvm/test/CodeGen/X86/tail-threshold.ll
index 757824fd03647..41ea9127dfb42 100644
--- a/llvm/test/CodeGen/X86/tail-threshold.ll
+++ b/llvm/test/CodeGen/X86/tail-threshold.ll
@@ -16,11 +16,11 @@ define void @foo(i32 %xxx) nounwind {
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: jmpq *.LJTI0_0(,%rax,8)
; CHECK-NEXT: .LBB0_3: # %bb3
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_4: # %bb4
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
switch i32 %xxx, label %bb4 [
diff --git a/llvm/test/CodeGen/X86/tailcall-64.ll b/llvm/test/CodeGen/X86/tailcall-64.ll
index 784254560cb71..22dc565cb7032 100644
--- a/llvm/test/CodeGen/X86/tailcall-64.ll
+++ b/llvm/test/CodeGen/X86/tailcall-64.ll
@@ -218,7 +218,7 @@ define void @fold_indexed_load(i8* %mbstr, i64 %idxprom) nounwind uwtable ssp {
; CHECK-LABEL: fold_indexed_load:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: leaq (%rsi,%rsi,4), %rax
-; CHECK-NEXT: movq _func_table@{{.*}}(%rip), %rcx
+; CHECK-NEXT: movq _func_table at GOTPCREL(%rip), %rcx
; CHECK-NEXT: jmpq *16(%rcx,%rax,8) ## TAILCALL
entry:
%dsplen = getelementptr inbounds [0 x %struct.funcs], [0 x %struct.funcs]* @func_table, i64 0, i64 %idxprom, i32 2
@@ -245,7 +245,7 @@ define i32 @rdar12282281(i32 %n) nounwind uwtable ssp {
; CHECK-LABEL: rdar12282281:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movslq %edi, %rax
-; CHECK-NEXT: movq _funcs@{{.*}}(%rip), %rcx
+; CHECK-NEXT: movq _funcs at GOTPCREL(%rip), %rcx
; CHECK-NEXT: movq (%rcx,%rax,8), %r11
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: xorl %esi, %esi
diff --git a/llvm/test/CodeGen/X86/tailcc-fastcc.ll b/llvm/test/CodeGen/X86/tailcc-fastcc.ll
index 03369855de4ac..357dc0c0a7c67 100644
--- a/llvm/test/CodeGen/X86/tailcc-fastcc.ll
+++ b/llvm/test/CodeGen/X86/tailcc-fastcc.ll
@@ -12,14 +12,14 @@ define fastcc i32 @tailcaller1(i32 %in1, i32 %in2) nounwind {
; X64-NEXT: pushq %rax
; X64-NEXT: movl %edi, %edx
; X64-NEXT: movl %esi, %ecx
-; X64-NEXT: callq tailcallee1
+; X64-NEXT: callq tailcallee1 at PLT
; X64-NEXT: retq $8
;
; X32-LABEL: tailcaller1:
; X32: # %bb.0: # %entry
; X32-NEXT: pushl %edx
; X32-NEXT: pushl %ecx
-; X32-NEXT: calll tailcallee1
+; X32-NEXT: calll tailcallee1 at PLT
; X32-NEXT: retl
entry:
%tmp11 = tail call tailcc i32 @tailcallee1(i32 %in1, i32 %in2, i32 %in1, i32 %in2)
@@ -34,14 +34,14 @@ define tailcc i32 @tailcaller2(i32 %in1, i32 %in2) nounwind {
; X64-NEXT: pushq %rax
; X64-NEXT: movl %edi, %edx
; X64-NEXT: movl %esi, %ecx
-; X64-NEXT: callq tailcallee2
+; X64-NEXT: callq tailcallee2 at PLT
; X64-NEXT: retq $8
;
; X32-LABEL: tailcaller2:
; X32: # %bb.0: # %entry
; X32-NEXT: pushl %edx
; X32-NEXT: pushl %ecx
-; X32-NEXT: calll tailcallee2
+; X32-NEXT: calll tailcallee2 at PLT
; X32-NEXT: retl
entry:
%tmp11 = tail call fastcc i32 @tailcallee2(i32 %in1, i32 %in2, i32 %in1, i32 %in2)
diff --git a/llvm/test/CodeGen/X86/test-shrink-bug.ll b/llvm/test/CodeGen/X86/test-shrink-bug.ll
index 9a7d5f2b53ca7..c1734c1c3a86b 100644
--- a/llvm/test/CodeGen/X86/test-shrink-bug.ll
+++ b/llvm/test/CodeGen/X86/test-shrink-bug.ll
@@ -26,11 +26,11 @@ define dso_local i32 @func_35(i64 %p_38) nounwind ssp {
; CHECK-X64-LABEL: func_35:
; CHECK-X64: # %bb.0: # %entry
; CHECK-X64-NEXT: pushq %rax
-; CHECK-X64-NEXT: movsbl {{.*}}(%rip), %edi
+; CHECK-X64-NEXT: movsbl g_14(%rip), %edi
; CHECK-X64-NEXT: xorl %esi, %esi
; CHECK-X64-NEXT: testl $255, %edi
; CHECK-X64-NEXT: setg %sil
-; CHECK-X64-NEXT: callq func_16
+; CHECK-X64-NEXT: callq func_16 at PLT
; CHECK-X64-NEXT: movl $1, %eax
; CHECK-X64-NEXT: popq %rcx
; CHECK-X64-NEXT: retq
@@ -69,13 +69,13 @@ define dso_local void @fail(i16 %a, <2 x i8> %b) {
; CHECK-X64-NEXT: testl $263, %edi # imm = 0x107
; CHECK-X64-NEXT: je .LBB1_3
; CHECK-X64-NEXT: # %bb.1:
-; CHECK-X64-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; CHECK-X64-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-X64-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8]
; CHECK-X64-NEXT: pextrw $4, %xmm0, %eax
; CHECK-X64-NEXT: testb $1, %al
; CHECK-X64-NEXT: jne .LBB1_3
; CHECK-X64-NEXT: # %bb.2: # %no
-; CHECK-X64-NEXT: callq bar
+; CHECK-X64-NEXT: callq bar at PLT
; CHECK-X64-NEXT: .LBB1_3: # %yes
; CHECK-X64-NEXT: popq %rax
; CHECK-X64-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/test-shrink.ll b/llvm/test/CodeGen/X86/test-shrink.ll
index 5f7779fa19120..6a7a0ad24ed8e 100644
--- a/llvm/test/CodeGen/X86/test-shrink.ll
+++ b/llvm/test/CodeGen/X86/test-shrink.ll
@@ -10,7 +10,7 @@ define void @g64xh(i64 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: jne .LBB0_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB0_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -31,7 +31,7 @@ define void @g64xh(i64 inreg %x) nounwind {
; CHECK-X86-NEXT: testl $2048, %eax # imm = 0x800
; CHECK-X86-NEXT: jne .LBB0_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB0_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 2048
@@ -52,7 +52,7 @@ define void @g64xl(i64 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: jne .LBB1_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB1_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -73,7 +73,7 @@ define void @g64xl(i64 inreg %x) nounwind {
; CHECK-X86-NEXT: testb $8, %al
; CHECK-X86-NEXT: jne .LBB1_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB1_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 8
@@ -94,7 +94,7 @@ define void @g32xh(i32 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: jne .LBB2_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB2_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -115,7 +115,7 @@ define void @g32xh(i32 inreg %x) nounwind {
; CHECK-X86-NEXT: testl $2048, %eax # imm = 0x800
; CHECK-X86-NEXT: jne .LBB2_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB2_2: # %no
; CHECK-X86-NEXT: retl
%t = and i32 %x, 2048
@@ -136,7 +136,7 @@ define void @g32xl(i32 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: jne .LBB3_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB3_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -157,7 +157,7 @@ define void @g32xl(i32 inreg %x) nounwind {
; CHECK-X86-NEXT: testb $8, %al
; CHECK-X86-NEXT: jne .LBB3_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB3_2: # %no
; CHECK-X86-NEXT: retl
%t = and i32 %x, 8
@@ -178,7 +178,7 @@ define void @g16xh(i16 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: jne .LBB4_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB4_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -200,7 +200,7 @@ define void @g16xh(i16 inreg %x) nounwind {
; CHECK-X86-NEXT: testl $2048, %eax # imm = 0x800
; CHECK-X86-NEXT: jne .LBB4_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB4_2: # %no
; CHECK-X86-NEXT: retl
%t = and i16 %x, 2048
@@ -221,7 +221,7 @@ define void @g16xl(i16 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: jne .LBB5_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB5_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -243,7 +243,7 @@ define void @g16xl(i16 inreg %x) nounwind {
; CHECK-X86-NEXT: testb $8, %al
; CHECK-X86-NEXT: jne .LBB5_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB5_2: # %no
; CHECK-X86-NEXT: retl
%t = and i16 %x, 8
@@ -266,7 +266,7 @@ define void @g64x16(i64 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB6_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
@@ -290,7 +290,7 @@ define void @g64x16(i64 inreg %x) nounwind {
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB6_1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: retl
%t = and i64 %x, 32896
%s = icmp eq i64 %t, 0
@@ -312,7 +312,7 @@ define void @g64x16minsize(i64 inreg %x) nounwind minsize {
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB7_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
@@ -334,7 +334,7 @@ define void @g64x16minsize(i64 inreg %x) nounwind minsize {
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB7_1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: retl
%t = and i64 %x, 32896
%s = icmp eq i64 %t, 0
@@ -356,7 +356,7 @@ define void @g32x16(i32 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB8_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
@@ -380,7 +380,7 @@ define void @g32x16(i32 inreg %x) nounwind {
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB8_1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: retl
%t = and i32 %x, 32896
%s = icmp eq i32 %t, 0
@@ -402,7 +402,7 @@ define void @g32x16minsize(i32 inreg %x) nounwind minsize {
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB9_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
@@ -424,7 +424,7 @@ define void @g32x16minsize(i32 inreg %x) nounwind minsize {
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB9_1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: retl
%t = and i32 %x, 32896
%s = icmp eq i32 %t, 0
@@ -446,7 +446,7 @@ define void @g64x32(i64 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB10_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
@@ -470,7 +470,7 @@ define void @g64x32(i64 inreg %x) nounwind {
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB10_1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: retl
%t = and i64 %x, 268468352
%s = icmp eq i64 %t, 0
@@ -492,7 +492,7 @@ define void @truncand32(i16 inreg %x) nounwind {
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB11_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
@@ -517,7 +517,7 @@ define void @truncand32(i16 inreg %x) nounwind {
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB11_1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: retl
%t = and i16 %x, 2049
%s = icmp eq i16 %t, 0
@@ -539,7 +539,7 @@ define void @testw(i16 inreg %x) nounwind minsize {
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB12_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
@@ -562,7 +562,7 @@ define void @testw(i16 inreg %x) nounwind minsize {
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB12_1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: retl
%t = and i16 %x, 2049
%s = icmp eq i16 %t, 0
@@ -582,7 +582,7 @@ define void @and16_trunc_8_sign(i16 %x) nounwind {
; CHECK-LINUX64-NEXT: js .LBB13_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB13_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -603,7 +603,7 @@ define void @and16_trunc_8_sign(i16 %x) nounwind {
; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
; CHECK-X86-NEXT: js .LBB13_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB13_2: # %no
; CHECK-X86-NEXT: retl
%t = and i16 %x, 128
@@ -625,7 +625,7 @@ define void @and32_trunc_8_sign(i32 %x) nounwind {
; CHECK-LINUX64-NEXT: js .LBB14_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB14_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -646,7 +646,7 @@ define void @and32_trunc_8_sign(i32 %x) nounwind {
; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
; CHECK-X86-NEXT: js .LBB14_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB14_2: # %no
; CHECK-X86-NEXT: retl
%t = and i32 %x, 128
@@ -668,7 +668,7 @@ define void @and64_trunc_8_sign(i64 %x) nounwind {
; CHECK-LINUX64-NEXT: js .LBB15_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB15_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -689,7 +689,7 @@ define void @and64_trunc_8_sign(i64 %x) nounwind {
; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
; CHECK-X86-NEXT: js .LBB15_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB15_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 128
@@ -712,7 +712,7 @@ define void @and32_trunc_16_sign(i32 %x) nounwind {
; CHECK-LINUX64-NEXT: js .LBB16_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB16_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -736,7 +736,7 @@ define void @and32_trunc_16_sign(i32 %x) nounwind {
; CHECK-X86-NEXT: testw %ax, %ax
; CHECK-X86-NEXT: js .LBB16_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB16_2: # %no
; CHECK-X86-NEXT: retl
%t = and i32 %x, 32768
@@ -758,7 +758,7 @@ define void @and32_trunc_16_sign_minsize(i32 %x) minsize nounwind {
; CHECK-LINUX64-NEXT: js .LBB17_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB17_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -780,7 +780,7 @@ define void @and32_trunc_16_sign_minsize(i32 %x) minsize nounwind {
; CHECK-X86-NEXT: testw $-32768, %ax # imm = 0x8000
; CHECK-X86-NEXT: js .LBB17_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB17_2: # %no
; CHECK-X86-NEXT: retl
%t = and i32 %x, 32768
@@ -803,7 +803,7 @@ define void @and64_trunc_16_sign(i64 %x) nounwind {
; CHECK-LINUX64-NEXT: js .LBB18_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB18_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -827,7 +827,7 @@ define void @and64_trunc_16_sign(i64 %x) nounwind {
; CHECK-X86-NEXT: testw %ax, %ax
; CHECK-X86-NEXT: js .LBB18_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB18_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 32768
@@ -849,7 +849,7 @@ define void @and64_trunc_16_sign_minsize(i64 %x) minsize nounwind {
; CHECK-LINUX64-NEXT: js .LBB19_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB19_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -870,7 +870,7 @@ define void @and64_trunc_16_sign_minsize(i64 %x) minsize nounwind {
; CHECK-X86-NEXT: testw $-32768, {{[0-9]+}}(%esp) # imm = 0x8000
; CHECK-X86-NEXT: js .LBB19_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB19_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 32768
@@ -892,7 +892,7 @@ define void @and64_trunc_32_sign(i64 %x) nounwind {
; CHECK-LINUX64-NEXT: js .LBB20_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
-; CHECK-LINUX64-NEXT: callq bar
+; CHECK-LINUX64-NEXT: callq bar at PLT
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB20_2: # %no
; CHECK-LINUX64-NEXT: retq
@@ -913,7 +913,7 @@ define void @and64_trunc_32_sign(i64 %x) nounwind {
; CHECK-X86-NEXT: testl $-2147483648, {{[0-9]+}}(%esp) # imm = 0x80000000
; CHECK-X86-NEXT: js .LBB20_2
; CHECK-X86-NEXT: # %bb.1: # %yes
-; CHECK-X86-NEXT: calll bar
+; CHECK-X86-NEXT: calll bar at PLT
; CHECK-X86-NEXT: .LBB20_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 2147483648
diff --git a/llvm/test/CodeGen/X86/test-vs-bittest.ll b/llvm/test/CodeGen/X86/test-vs-bittest.ll
index 6c6282ce1ee0b..a37febbfbdbbb 100644
--- a/llvm/test/CodeGen/X86/test-vs-bittest.ll
+++ b/llvm/test/CodeGen/X86/test-vs-bittest.ll
@@ -9,7 +9,7 @@ define void @test64(i64 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB0_2: # %no
@@ -33,7 +33,7 @@ define void @test64_optsize(i64 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB1_2: # %no
@@ -57,7 +57,7 @@ define void @test64_pgso(i64 inreg %x) !prof !14 {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB2_2: # %no
@@ -86,7 +86,7 @@ define void @test64_2(i64 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB3_2: # %no
@@ -110,7 +110,7 @@ define void @test64_optsize_2(i64 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB4_2: # %no
@@ -134,7 +134,7 @@ define void @test64_pgso_2(i64 inreg %x) !prof !14 {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB5_2: # %no
@@ -158,7 +158,7 @@ define void @test64_3(i64 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB6_2: # %no
@@ -182,7 +182,7 @@ define void @test64_optsize_3(i64 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB7_2: # %no
@@ -206,7 +206,7 @@ define void @test64_pgso_3(i64 inreg %x) !prof !14 {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB8_2: # %no
@@ -230,7 +230,7 @@ define void @test64_4(i64 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB9_2: # %no
@@ -254,7 +254,7 @@ define void @test64_optsize_4(i64 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB10_2: # %no
@@ -278,7 +278,7 @@ define void @test64_pgso_4(i64 inreg %x) !prof !14 {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB11_2: # %no
@@ -302,7 +302,7 @@ define void @test32(i32 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB12_2: # %no
@@ -326,7 +326,7 @@ define void @test32_optsize(i32 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB13_2: # %no
@@ -350,7 +350,7 @@ define void @test32_2(i32 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB14_2: # %no
@@ -374,7 +374,7 @@ define void @test32_optsize_2(i32 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB15_2: # %no
@@ -398,7 +398,7 @@ define void @test32_pgso_2(i32 inreg %x) !prof !14 {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB16_2: # %no
@@ -422,7 +422,7 @@ define void @test16(i16 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB17_2: # %no
@@ -446,7 +446,7 @@ define void @test16_optsize(i16 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB18_2: # %no
@@ -470,7 +470,7 @@ define void @test16_pgso(i16 inreg %x) !prof !14 {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB19_2: # %no
@@ -494,7 +494,7 @@ define void @test16_2(i16 inreg %x) {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB20_2: # %no
@@ -518,7 +518,7 @@ define void @test16_optsize_2(i16 inreg %x) optsize {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB21_2: # %no
@@ -542,7 +542,7 @@ define void @test16_pgso_2(i16 inreg %x) !prof !14 {
; CHECK-NEXT: # %bb.1: # %yes
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq bar
+; CHECK-NEXT: callq bar at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .LBB22_2: # %no
diff --git a/llvm/test/CodeGen/X86/tls-pie.ll b/llvm/test/CodeGen/X86/tls-pie.ll
index 0659f287c1b21..73994e0dd3b33 100644
--- a/llvm/test/CodeGen/X86/tls-pie.ll
+++ b/llvm/test/CodeGen/X86/tls-pie.ll
@@ -64,14 +64,14 @@ define dso_local i32 @f3() {
;
; X32-LABEL: f3:
; X32: # %bb.0: # %entry
-; X32-NEXT: movl i2@{{.*}}(%rip), %eax
+; X32-NEXT: movl i2 at GOTTPOFF(%rip), %eax
; X32-NEXT: movl %fs:0, %ecx
; X32-NEXT: movl (%ecx,%eax), %eax
; X32-NEXT: retq
;
; X64-LABEL: f3:
; X64: # %bb.0: # %entry
-; X64-NEXT: movq i2@{{.*}}(%rip), %rax
+; X64-NEXT: movq i2 at GOTTPOFF(%rip), %rax
; X64-NEXT: movl %fs:(%rax), %eax
; X64-NEXT: retq
entry:
@@ -96,13 +96,13 @@ define dso_local i32* @f4() {
; X32-LABEL: f4:
; X32: # %bb.0: # %entry
; X32-NEXT: movl %fs:0, %eax
-; X32-NEXT: addl i2@{{.*}}(%rip), %eax
+; X32-NEXT: addl i2 at GOTTPOFF(%rip), %eax
; X32-NEXT: retq
;
; X64-LABEL: f4:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %fs:0, %rax
-; X64-NEXT: addq i2@{{.*}}(%rip), %rax
+; X64-NEXT: addq i2 at GOTTPOFF(%rip), %rax
; X64-NEXT: retq
entry:
ret i32* @i2
diff --git a/llvm/test/CodeGen/X86/trunc-and.ll b/llvm/test/CodeGen/X86/trunc-and.ll
index 812f838e36f03..8e9c8582e51b8 100644
--- a/llvm/test/CodeGen/X86/trunc-and.ll
+++ b/llvm/test/CodeGen/X86/trunc-and.ll
@@ -33,7 +33,7 @@ declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
define dso_local i32 @d() {
; CHECK-LABEL: d:
; CHECK: # %bb.0:
-; CHECK-NEXT: movzbl b+{{.*}}(%rip), %ecx
+; CHECK-NEXT: movzbl b+8(%rip), %ecx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: movl $d, %eax
; CHECK-NEXT: addl %ecx, %eax
diff --git a/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll b/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll
index f807444a36f5d..56ab23d494b54 100644
--- a/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll
+++ b/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll
@@ -8,7 +8,7 @@ define void @load_2_i8(<2 x i8>* %A) {
; SSE2: # %bb.0:
; SSE2-NEXT: movzwl (%rdi), %eax
; SSE2-NEXT: movd %eax, %xmm0
-; SSE2-NEXT: paddb {{.*}}(%rip), %xmm0
+; SSE2-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: movw %ax, (%rdi)
; SSE2-NEXT: retq
@@ -17,7 +17,7 @@ define void @load_2_i8(<2 x i8>* %A) {
; SSE41: # %bb.0:
; SSE41-NEXT: movzwl (%rdi), %eax
; SSE41-NEXT: movd %eax, %xmm0
-; SSE41-NEXT: paddb {{.*}}(%rip), %xmm0
+; SSE41-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pextrw $0, %xmm0, (%rdi)
; SSE41-NEXT: retq
%T = load <2 x i8>, <2 x i8>* %A
@@ -31,7 +31,7 @@ define void @load_2_i16(<2 x i16>* %A) {
; CHECK-LABEL: load_2_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: paddw {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movd %xmm0, (%rdi)
; CHECK-NEXT: retq
%T = load <2 x i16>, <2 x i16>* %A
@@ -44,7 +44,7 @@ define void @load_2_i32(<2 x i32>* %A) {
; CHECK-LABEL: load_2_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movq %xmm0, (%rdi)
; CHECK-NEXT: retq
%T = load <2 x i32>, <2 x i32>* %A
@@ -57,7 +57,7 @@ define void @load_4_i8(<4 x i8>* %A) {
; CHECK-LABEL: load_4_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: paddb {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movd %xmm0, (%rdi)
; CHECK-NEXT: retq
%T = load <4 x i8>, <4 x i8>* %A
@@ -70,7 +70,7 @@ define void @load_4_i16(<4 x i16>* %A) {
; CHECK-LABEL: load_4_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: paddw {{.*}}(%rip), %xmm0
+; CHECK-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movq %xmm0, (%rdi)
; CHECK-NEXT: retq
%T = load <4 x i16>, <4 x i16>* %A
diff --git a/llvm/test/CodeGen/X86/twoaddr-coalesce.ll b/llvm/test/CodeGen/X86/twoaddr-coalesce.ll
index 0ab3d6ba2b616..000ffeef9c8f4 100644
--- a/llvm/test/CodeGen/X86/twoaddr-coalesce.ll
+++ b/llvm/test/CodeGen/X86/twoaddr-coalesce.ll
@@ -19,7 +19,7 @@ define i32 @foo() nounwind {
; CHECK-NEXT: movsbl %al, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $LC
-; CHECK-NEXT: calll printf
+; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: incl %ebx
; CHECK-NEXT: cmpl $258, %ebx # imm = 0x102
diff --git a/llvm/test/CodeGen/X86/udiv_fix.ll b/llvm/test/CodeGen/X86/udiv_fix.ll
index a6b7e5b70d8a7..eba1fd1565e1b 100644
--- a/llvm/test/CodeGen/X86/udiv_fix.ll
+++ b/llvm/test/CodeGen/X86/udiv_fix.ll
@@ -143,7 +143,7 @@ define i64 @func5(i64 %x, i64 %y) nounwind {
; X64-NEXT: shlq $31, %rdi
; X64-NEXT: shrq $33, %rsi
; X64-NEXT: xorl %ecx, %ecx
-; X64-NEXT: callq __udivti3
+; X64-NEXT: callq __udivti3 at PLT
; X64-NEXT: popq %rcx
; X64-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/uint64-to-float.ll b/llvm/test/CodeGen/X86/uint64-to-float.ll
index ab230c65e7dcf..8b6623476ebaa 100644
--- a/llvm/test/CodeGen/X86/uint64-to-float.ll
+++ b/llvm/test/CodeGen/X86/uint64-to-float.ll
@@ -18,7 +18,7 @@ define float @test(i64 %a) nounwind {
; X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll {{[0-9]+}}(%esp)
-; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: fstps {{[0-9]+}}(%esp)
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: movss %xmm0, (%esp)
diff --git a/llvm/test/CodeGen/X86/uint_to_fp-2.ll b/llvm/test/CodeGen/X86/uint_to_fp-2.ll
index da27f04e2df18..8c356d5432ce9 100644
--- a/llvm/test/CodeGen/X86/uint_to_fp-2.ll
+++ b/llvm/test/CodeGen/X86/uint_to_fp-2.ll
@@ -7,8 +7,8 @@ define float @test1(i32 %x) nounwind readnone {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; CHECK-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; CHECK-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; CHECK-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: cvtsd2ss %xmm0, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp)
@@ -26,8 +26,8 @@ define float @test2(<4 x i32> %x) nounwind readnone ssp {
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
-; CHECK-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; CHECK-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; CHECK-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: cvtsd2ss %xmm1, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp)
diff --git a/llvm/test/CodeGen/X86/uint_to_fp-3.ll b/llvm/test/CodeGen/X86/uint_to_fp-3.ll
index b6846a68f23b8..cbbbceb7733d4 100644
--- a/llvm/test/CodeGen/X86/uint_to_fp-3.ll
+++ b/llvm/test/CodeGen/X86/uint_to_fp-3.ll
@@ -9,25 +9,25 @@
define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) {
; X32-SSE-LABEL: mask_ucvt_4i32_4f32:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X32-SSE-NEXT: retl
;
; X32-AVX-LABEL: mask_ucvt_4i32_4f32:
; X32-AVX: # %bb.0:
-; X32-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-AVX-NEXT: retl
;
; X64-SSE-LABEL: mask_ucvt_4i32_4f32:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mask_ucvt_4i32_4f32:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-AVX-NEXT: retq
%and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
@@ -38,7 +38,7 @@ define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) {
define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {
; X32-SSE-LABEL: mask_ucvt_4i32_4f64:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm1
@@ -47,13 +47,13 @@ define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {
;
; X32-AVX-LABEL: mask_ucvt_4i32_4f64:
; X32-AVX: # %bb.0:
-; X32-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; X32-AVX-NEXT: retl
;
; X64-SSE-LABEL: mask_ucvt_4i32_4f64:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm1
@@ -62,7 +62,7 @@ define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {
;
; X64-AVX-LABEL: mask_ucvt_4i32_4f64:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; X64-AVX-NEXT: retq
%and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
@@ -80,7 +80,7 @@ define <4 x float> @lshr_truncate_mask_ucvt_4i64_4f32(<4 x i64> *%p0) {
; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X32-SSE-NEXT: psrld $16, %xmm0
; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
-; X32-SSE-NEXT: mulps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl
;
; X32-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
@@ -90,7 +90,7 @@ define <4 x float> @lshr_truncate_mask_ucvt_4i64_4f32(<4 x i64> *%p0) {
; X32-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2]
; X32-AVX-NEXT: vpsrld $16, %xmm0, %xmm0
; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-AVX-NEXT: vmulps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32-AVX-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-AVX-NEXT: retl
;
; X64-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
@@ -100,7 +100,7 @@ define <4 x float> @lshr_truncate_mask_ucvt_4i64_4f32(<4 x i64> *%p0) {
; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X64-SSE-NEXT: psrld $16, %xmm0
; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
-; X64-SSE-NEXT: mulps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
@@ -109,7 +109,7 @@ define <4 x float> @lshr_truncate_mask_ucvt_4i64_4f32(<4 x i64> *%p0) {
; X64-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2]
; X64-AVX-NEXT: vpsrld $16, %xmm0, %xmm0
; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X64-AVX-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%load = load <4 x i64>, <4 x i64>* %p0, align 2
%lshr = lshr <4 x i64> %load, <i64 16, i64 16, i64 16, i64 16>
diff --git a/llvm/test/CodeGen/X86/uintr-intrinsics.ll b/llvm/test/CodeGen/X86/uintr-intrinsics.ll
index cab0a2831e5e7..47ec3046912f9 100644
--- a/llvm/test/CodeGen/X86/uintr-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/uintr-intrinsics.ll
@@ -11,7 +11,7 @@ define i8 @test_uintr(i64 %arg) {
; X64-NEXT: testui
; X64-NEXT: setb %al
; X64-NEXT: retq
-
+;
; X32-LABEL: test_uintr:
; X32: # %bb.0: # %entry
; X32-NEXT: clui
@@ -20,6 +20,7 @@ define i8 @test_uintr(i64 %arg) {
; X32-NEXT: testui
; X32-NEXT: setb %al
; X32-NEXT: retq
+
entry:
call void @llvm.x86.clui()
call void @llvm.x86.stui()
diff --git a/llvm/test/CodeGen/X86/umul-with-carry.ll b/llvm/test/CodeGen/X86/umul-with-carry.ll
index 621a484fe7427..075439f09fa03 100644
--- a/llvm/test/CodeGen/X86/umul-with-carry.ll
+++ b/llvm/test/CodeGen/X86/umul-with-carry.ll
@@ -14,14 +14,14 @@ define i1 @func(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: jno .LBB0_1
; CHECK-NEXT: # %bb.2: # %carry
; CHECK-NEXT: pushl $no
-; CHECK-NEXT: calll printf
+; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %normal
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $ok
-; CHECK-NEXT: calll printf
+; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/umul-with-overflow.ll b/llvm/test/CodeGen/X86/umul-with-overflow.ll
index c2a0dc047bc73..e5c61c418a705 100644
--- a/llvm/test/CodeGen/X86/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/umul-with-overflow.ll
@@ -73,6 +73,555 @@ entry:
; Intentionally not testing codegen here, only that this doesn't assert.
declare {i300, i1} @llvm.umul.with.overflow.i300(i300 %a, i300 %b)
define i300 @test4(i300 %a, i300 %b) nounwind {
+; X86-LABEL: test4:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $76, %esp
+; X86-NEXT: movl $4095, %ecx # imm = 0xFFF
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, %ebp
+; X86-NEXT: addl %esi, %ebp
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: addl %ebp, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl %edi, %esi
+; X86-NEXT: setb %cl
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %ebx
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: addl %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: adcl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %ebp
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: addl %esi, %ecx
+; X86-NEXT: adcl $0, %ebp
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl %ebp, %ebx
+; X86-NEXT: setb %cl
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: addl %ebx, %esi
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: adcl %eax, %edx
+; X86-NEXT: addl (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: addl %ecx, %edi
+; X86-NEXT: adcl $0, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %ebp
+; X86-NEXT: addl %edi, %eax
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: adcl %ebx, %ebp
+; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl %eax, %ebx
+; X86-NEXT: addl %ebp, %ebx
+; X86-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 1-byte Folded Reload
+; X86-NEXT: adcl %eax, %ecx
+; X86-NEXT: addl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %ebx
+; X86-NEXT: adcl $0, %ecx
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-NEXT: adcl (%esp), %ecx # 4-byte Folded Reload
+; X86-NEXT: setb (%esp) # 1-byte Folded Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, %ebp
+; X86-NEXT: addl %esi, %ebp
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: mull %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: addl %ebp, %eax
+; X86-NEXT: movl %eax, %ebp
+; X86-NEXT: adcl %edi, %esi
+; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull {{[0-9]+}}(%esp)
+; X86-NEXT: addl %esi, %eax
+; X86-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 1-byte Folded Reload
+; X86-NEXT: adcl %esi, %edx
+; X86-NEXT: addl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl %ecx, %ebp
+; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movzbl (%esp), %ecx # 1-byte Folded Reload
+; X86-NEXT: adcl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl %eax, %ebx
+; X86-NEXT: addl %ecx, %ebx
+; X86-NEXT: adcl $0, %esi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %ebp
+; X86-NEXT: addl %ebx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl %esi, %ebp
+; X86-NEXT: setb %cl
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: addl %ebp, %eax
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: adcl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: movl %eax, %ebp
+; X86-NEXT: addl %esi, %ebp
+; X86-NEXT: adcl $0, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull {{[0-9]+}}(%esp)
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: addl %ebp, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl %ebx, %esi
+; X86-NEXT: setb %cl
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %eax, %ebx
+; X86-NEXT: mull {{[0-9]+}}(%esp)
+; X86-NEXT: addl %esi, %eax
+; X86-NEXT: movzbl %cl, %ecx
+; X86-NEXT: adcl %ecx, %edx
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, (%esp) # 4-byte Folded Spill
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: addl %esi, %edi
+; X86-NEXT: adcl $0, %ecx
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %edx, %ebp
+; X86-NEXT: addl %edi, %eax
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: adcl %ecx, %ebp
+; X86-NEXT: setb %cl
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: addl %ebp, %esi
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: adcl %eax, %ebx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %esi
+; X86-NEXT: adcl $0, %ebx
+; X86-NEXT: addl (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: imull %edx, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: mull %edx
+; X86-NEXT: addl %edx, %ecx
+; X86-NEXT: imull {{[0-9]+}}(%esp), %edi
+; X86-NEXT: addl %ecx, %edi
+; X86-NEXT: movl %eax, %edx
+; X86-NEXT: addl %esi, %edx
+; X86-NEXT: adcl %ebx, %edi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: addl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload
+; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, %ebx
+; X86-NEXT: addl %ecx, %ebx
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %edx, %ebp
+; X86-NEXT: addl %ebx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl %edi, %ebp
+; X86-NEXT: setb %cl
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %esi
+; X86-NEXT: addl %ebp, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: adcl %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: movl %eax, %ebp
+; X86-NEXT: addl %edi, %ebp
+; X86-NEXT: adcl $0, %ebx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: addl %ebp, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl %ebx, %edi
+; X86-NEXT: setb %cl
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %eax, %ebx
+; X86-NEXT: addl %edi, %ebx
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: adcl %eax, %edx
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: addl %esi, %ecx
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: mull %esi
+; X86-NEXT: movl %esi, %ebp
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: adcl %edi, %esi
+; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: mull %ebp
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, %ebp
+; X86-NEXT: addl %esi, %ebp
+; X86-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 1-byte Folded Reload
+; X86-NEXT: adcl %eax, %edi
+; X86-NEXT: addl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %ebp
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: imull %ecx, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: mull %ecx
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: addl %edx, %ebx
+; X86-NEXT: imull {{[0-9]+}}(%esp), %esi
+; X86-NEXT: addl %ebx, %esi
+; X86-NEXT: addl %ebp, %ecx
+; X86-NEXT: adcl %edi, %esi
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %ecx
+; X86-NEXT: adcl $0, %esi
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: imull %edx, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: mull %edx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: addl %edx, %ebp
+; X86-NEXT: imull {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: addl %ebp, %ebx
+; X86-NEXT: addl %ecx, %edi
+; X86-NEXT: adcl %esi, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: imull %edx, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: mull %edx
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: addl %edx, %ebx
+; X86-NEXT: imull {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: addl %ebx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: imull %edx, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: mull %edx
+; X86-NEXT: addl %edx, %ebp
+; X86-NEXT: imull {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: addl %ebp, %ebx
+; X86-NEXT: addl %esi, %eax
+; X86-NEXT: adcl %ecx, %ebx
+; X86-NEXT: addl %edi, %eax
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, (%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 4(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 8(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 12(%ecx)
+; X86-NEXT: movl (%esp), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 16(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 20(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 24(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 28(%ecx)
+; X86-NEXT: movl %eax, 32(%ecx)
+; X86-NEXT: andl $4095, %ebx # imm = 0xFFF
+; X86-NEXT: movw %bx, 36(%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: addl $76, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+;
+; X64-LABEL: test4:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rbp
+; X64-NEXT: pushq %r15
+; X64-NEXT: pushq %r14
+; X64-NEXT: pushq %r13
+; X64-NEXT: pushq %r12
+; X64-NEXT: pushq %rbx
+; X64-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; X64-NEXT: movq %r8, %r11
+; X64-NEXT: movq %rcx, %r8
+; X64-NEXT: movq %rdx, %r13
+; X64-NEXT: movq %rdi, %r12
+; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: mulq %r10
+; X64-NEXT: movq %rdx, %r14
+; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; X64-NEXT: movq %r13, %rax
+; X64-NEXT: mulq %r10
+; X64-NEXT: movq %rdx, %rbx
+; X64-NEXT: movq %rax, %rdi
+; X64-NEXT: addq %r14, %rdi
+; X64-NEXT: adcq $0, %rbx
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: mulq %rbp
+; X64-NEXT: movq %rdx, %rcx
+; X64-NEXT: movq %rax, %r9
+; X64-NEXT: addq %rdi, %r9
+; X64-NEXT: adcq %rbx, %rcx
+; X64-NEXT: setb %al
+; X64-NEXT: movzbl %al, %edi
+; X64-NEXT: movq %r13, %rax
+; X64-NEXT: mulq %rbp
+; X64-NEXT: movq %rdx, %rbx
+; X64-NEXT: movq %rax, %rbp
+; X64-NEXT: addq %rcx, %rbp
+; X64-NEXT: adcq %rdi, %rbx
+; X64-NEXT: movq %r8, %rax
+; X64-NEXT: mulq %r10
+; X64-NEXT: movq %rdx, %rcx
+; X64-NEXT: movq %rax, %r15
+; X64-NEXT: movq %r11, %rax
+; X64-NEXT: mulq %r10
+; X64-NEXT: movq %rdx, %r10
+; X64-NEXT: movq %rax, %r14
+; X64-NEXT: addq %rcx, %r14
+; X64-NEXT: adcq $0, %r10
+; X64-NEXT: movq %r8, %rax
+; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; X64-NEXT: mulq %rcx
+; X64-NEXT: movq %rax, %rdi
+; X64-NEXT: addq %r14, %rdi
+; X64-NEXT: adcq %r10, %rdx
+; X64-NEXT: imulq %rcx, %r11
+; X64-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; X64-NEXT: addq %rbp, %r15
+; X64-NEXT: adcq %rbx, %rdi
+; X64-NEXT: adcq %rdx, %r11
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: mulq %r14
+; X64-NEXT: movq %rdx, %rcx
+; X64-NEXT: movq %rax, %r10
+; X64-NEXT: movq %r13, %rax
+; X64-NEXT: mulq %r14
+; X64-NEXT: movq %rdx, %rbp
+; X64-NEXT: movq %rax, %rbx
+; X64-NEXT: addq %rcx, %rbx
+; X64-NEXT: adcq $0, %rbp
+; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: mulq %rcx
+; X64-NEXT: addq %rbx, %rax
+; X64-NEXT: adcq %rbp, %rdx
+; X64-NEXT: imulq %rcx, %r13
+; X64-NEXT: addq %rdx, %r13
+; X64-NEXT: addq %r15, %r10
+; X64-NEXT: adcq %rdi, %rax
+; X64-NEXT: adcq %r11, %r13
+; X64-NEXT: imulq %r14, %r8
+; X64-NEXT: addq %r13, %r8
+; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; X64-NEXT: imulq {{[0-9]+}}(%rsp), %rcx
+; X64-NEXT: imulq {{[0-9]+}}(%rsp), %rsi
+; X64-NEXT: addq %rcx, %rsi
+; X64-NEXT: addq %r8, %rsi
+; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; X64-NEXT: movq %rcx, (%r12)
+; X64-NEXT: movq %r9, 8(%r12)
+; X64-NEXT: movq %r10, 16(%r12)
+; X64-NEXT: movq %rax, 24(%r12)
+; X64-NEXT: movl %esi, 32(%r12)
+; X64-NEXT: shrq $32, %rsi
+; X64-NEXT: andl $4095, %esi # imm = 0xFFF
+; X64-NEXT: movw %si, 36(%r12)
+; X64-NEXT: movq %r12, %rax
+; X64-NEXT: popq %rbx
+; X64-NEXT: popq %r12
+; X64-NEXT: popq %r13
+; X64-NEXT: popq %r14
+; X64-NEXT: popq %r15
+; X64-NEXT: popq %rbp
+; X64-NEXT: retq
%x = call {i300, i1} @llvm.umul.with.overflow.i300(i300 %a, i300 %b)
%y = extractvalue {i300, i1} %x, 0
ret i300 %y
diff --git a/llvm/test/CodeGen/X86/unaligned-load.ll b/llvm/test/CodeGen/X86/unaligned-load.ll
index be8ca0132d9a0..0ab5889b14d1a 100644
--- a/llvm/test/CodeGen/X86/unaligned-load.ll
+++ b/llvm/test/CodeGen/X86/unaligned-load.ll
@@ -42,8 +42,8 @@ define void @func() nounwind ssp {
;
; COREI7-LABEL: func:
; COREI7: ## %bb.0: ## %entry
-; COREI7-NEXT: movups _.str3+{{.*}}(%rip), %xmm0
-; COREI7-NEXT: movups {{.*}}(%rip), %xmm1
+; COREI7-NEXT: movups _.str3+15(%rip), %xmm0
+; COREI7-NEXT: movups _.str3(%rip), %xmm1
; COREI7-NEXT: .p2align 4, 0x90
; COREI7-NEXT: LBB0_1: ## %bb
; COREI7-NEXT: ## =>This Inner Loop Header: Depth=1
@@ -95,8 +95,8 @@ define void @func_aligned() nounwind ssp {
;
; COREI7-LABEL: func_aligned:
; COREI7: ## %bb.0: ## %entry
-; COREI7-NEXT: movups _.str3+{{.*}}(%rip), %xmm0
-; COREI7-NEXT: movups {{.*}}(%rip), %xmm1
+; COREI7-NEXT: movups _.str3+15(%rip), %xmm0
+; COREI7-NEXT: movups _.str3(%rip), %xmm1
; COREI7-NEXT: .p2align 4, 0x90
; COREI7-NEXT: LBB1_1: ## %bb
; COREI7-NEXT: ## =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
index 8daa0a6e969af..9a8719f9a64fa 100644
--- a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
+++ b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
@@ -346,7 +346,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %ebp
; CHECK-NOBMI-NEXT: andl $16776960, %ebp # imm = 0xFFFF00
; CHECK-NOBMI-NEXT: movl %ebp, %edi
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -364,7 +364,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %ebp
; CHECK-BMI-NEXT: andl $16776960, %ebp # imm = 0xFFFF00
; CHECK-BMI-NEXT: movl %ebp, %edi
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
@@ -388,7 +388,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %edi
; CHECK-NOBMI-NEXT: movl %edi, %ebp
; CHECK-NOBMI-NEXT: andl $16776960, %ebp # imm = 0xFFFF00
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -405,7 +405,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %edi
; CHECK-BMI-NEXT: movl %edi, %ebp
; CHECK-BMI-NEXT: andl $16776960, %ebp # imm = 0xFFFF00
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
index 33b6b66b66d7c..c4c4e5ed1fdde 100644
--- a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
+++ b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
@@ -346,7 +346,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %ebp
; CHECK-NOBMI-NEXT: andl $1431655765, %ebp # imm = 0x55555555
; CHECK-NOBMI-NEXT: movl %ebp, %edi
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -364,7 +364,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %ebp
; CHECK-BMI-NEXT: andl $1431655765, %ebp # imm = 0x55555555
; CHECK-BMI-NEXT: movl %ebp, %edi
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
@@ -388,7 +388,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %edi
; CHECK-NOBMI-NEXT: movl %edi, %ebp
; CHECK-NOBMI-NEXT: andl $1431655765, %ebp # imm = 0x55555555
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -405,7 +405,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %edi
; CHECK-BMI-NEXT: movl %edi, %ebp
; CHECK-BMI-NEXT: andl $1431655765, %ebp # imm = 0x55555555
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
index bbc987d4474ac..2ea74f3942387 100644
--- a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
+++ b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
@@ -346,7 +346,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %ebp
; CHECK-NOBMI-NEXT: andl $252645135, %ebp # imm = 0xF0F0F0F
; CHECK-NOBMI-NEXT: movl %ebp, %edi
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -364,7 +364,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %ebp
; CHECK-BMI-NEXT: andl $252645135, %ebp # imm = 0xF0F0F0F
; CHECK-BMI-NEXT: movl %ebp, %edi
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
@@ -388,7 +388,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %edi
; CHECK-NOBMI-NEXT: movl %edi, %ebp
; CHECK-NOBMI-NEXT: andl $252645135, %ebp # imm = 0xF0F0F0F
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -405,7 +405,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %edi
; CHECK-BMI-NEXT: movl %edi, %ebp
; CHECK-BMI-NEXT: andl $252645135, %ebp # imm = 0xF0F0F0F
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
index 78faa3ca717ea..eb6accd3e623b 100644
--- a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
+++ b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
@@ -319,7 +319,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %edi
; CHECK-NOBMI-NEXT: movzwl %di, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %edi
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -336,7 +336,7 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %edi
; CHECK-BMI-NEXT: movzwl %di, %ebp
; CHECK-BMI-NEXT: movl %ebp, %edi
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
@@ -359,7 +359,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-NOBMI-NEXT: movl %esi, %ebx
; CHECK-NOBMI-NEXT: xorl %esi, %edi
; CHECK-NOBMI-NEXT: movzwl %di, %ebp
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -375,7 +375,7 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-BMI-NEXT: movl %esi, %ebx
; CHECK-BMI-NEXT: xorl %esi, %edi
; CHECK-BMI-NEXT: movzwl %di, %ebp
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
index 1f125d9ec7a3c..140c5a2a4b289 100644
--- a/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
+++ b/llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
@@ -908,7 +908,7 @@ define i32 @in_multiuse_A(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind {
; CHECK-NOBMI-NEXT: xorl %esi, %ebp
; CHECK-NOBMI-NEXT: andl %ecx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %edi
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebx, %ebp
; CHECK-NOBMI-NEXT: movl %ebp, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -926,7 +926,7 @@ define i32 @in_multiuse_A(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind {
; CHECK-BMI-NEXT: xorl %esi, %ebp
; CHECK-BMI-NEXT: andl %ecx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %edi
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebx, %ebp
; CHECK-BMI-NEXT: movl %ebp, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
@@ -949,7 +949,7 @@ define i32 @in_multiuse_B(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind {
; CHECK-NOBMI-NEXT: movl %esi, %ebp
; CHECK-NOBMI-NEXT: xorl %esi, %edi
; CHECK-NOBMI-NEXT: andl %edi, %ebx
-; CHECK-NOBMI-NEXT: callq use32
+; CHECK-NOBMI-NEXT: callq use32 at PLT
; CHECK-NOBMI-NEXT: xorl %ebp, %ebx
; CHECK-NOBMI-NEXT: movl %ebx, %eax
; CHECK-NOBMI-NEXT: addq $8, %rsp
@@ -966,7 +966,7 @@ define i32 @in_multiuse_B(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind {
; CHECK-BMI-NEXT: movl %esi, %ebp
; CHECK-BMI-NEXT: xorl %esi, %edi
; CHECK-BMI-NEXT: andl %edi, %ebx
-; CHECK-BMI-NEXT: callq use32
+; CHECK-BMI-NEXT: callq use32 at PLT
; CHECK-BMI-NEXT: xorl %ebp, %ebx
; CHECK-BMI-NEXT: movl %ebx, %eax
; CHECK-BMI-NEXT: addq $8, %rsp
diff --git a/llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll b/llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll
index 90b9a4779d200..2d6c4dc829ed9 100644
--- a/llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll
+++ b/llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll
@@ -52,7 +52,7 @@ define <4 x i32> @in_constant_varx_mone(<4 x i32> *%px, <4 x i32> *%py, <4 x i32
; CHECK-SSE1-NEXT: movq %rdi, %rax
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm0
; CHECK-SSE1-NEXT: andnps (%rcx), %xmm0
-; CHECK-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0
+; CHECK-SSE1-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
; CHECK-SSE1-NEXT: retq
;
@@ -160,7 +160,7 @@ define <4 x i32> @out_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm1
; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
-; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm0
+; CHECK-SSE1-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
; CHECK-SSE1-NEXT: retq
@@ -170,7 +170,7 @@ define <4 x i32> @out_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
; CHECK-SSE2-NEXT: movaps (%rdi), %xmm1
; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
-; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -178,7 +178,7 @@ define <4 x i32> @out_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-XOP: # %bb.0:
; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
-; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-XOP-NEXT: vpcmov %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-XOP-NEXT: retq
%x = load <4 x i32>, <4 x i32> *%px, align 16
%y = load <4 x i32>, <4 x i32> *%py, align 16
@@ -197,7 +197,7 @@ define <4 x i32> @in_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm1
; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
-; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm0
+; CHECK-SSE1-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
; CHECK-SSE1-NEXT: retq
@@ -207,7 +207,7 @@ define <4 x i32> @in_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
; CHECK-SSE2-NEXT: movaps (%rdi), %xmm1
; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
-; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -215,7 +215,7 @@ define <4 x i32> @in_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-XOP: # %bb.0:
; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
-; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-XOP-NEXT: vpcmov %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-XOP-NEXT: retq
%x = load <4 x i32>, <4 x i32> *%px, align 16
%y = load <4 x i32>, <4 x i32> *%py, align 16
@@ -234,7 +234,7 @@ define <4 x i32> @out_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
; CHECK-SSE1-NEXT: andnps (%rsi), %xmm1
-; CHECK-SSE1-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-SSE1-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
; CHECK-SSE1-NEXT: retq
@@ -244,7 +244,7 @@ define <4 x i32> @out_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
; CHECK-SSE2-NEXT: andnps (%rdi), %xmm1
-; CHECK-SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -272,7 +272,7 @@ define <4 x i32> @in_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <4
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
; CHECK-SSE1-NEXT: andnps (%rsi), %xmm1
-; CHECK-SSE1-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-SSE1-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
; CHECK-SSE1-NEXT: retq
@@ -282,7 +282,7 @@ define <4 x i32> @in_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <4
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
; CHECK-SSE2-NEXT: andnps (%rdi), %xmm1
-; CHECK-SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -487,7 +487,7 @@ define <4 x i32> @in_constant_42_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
; CHECK-SSE1-NEXT: andnps (%rdx), %xmm1
-; CHECK-SSE1-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-SSE1-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
; CHECK-SSE1-NEXT: retq
@@ -497,7 +497,7 @@ define <4 x i32> @in_constant_42_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32>
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
; CHECK-SSE2-NEXT: andnps (%rsi), %xmm1
-; CHECK-SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -523,7 +523,7 @@ define <4 x i32> @out_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <
; CHECK-SSE1-NEXT: movq %rdi, %rax
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
-; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm1
+; CHECK-SSE1-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE1-NEXT: andps (%rdx), %xmm0
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
@@ -533,7 +533,7 @@ define <4 x i32> @out_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
-; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: andps (%rsi), %xmm0
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
@@ -542,7 +542,7 @@ define <4 x i32> @out_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <
; CHECK-XOP: # %bb.0:
; CHECK-XOP-NEXT: vmovdqa (%rsi), %xmm0
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
-; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-XOP-NEXT: vpcmov %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-XOP-NEXT: retq
%x = load <4 x i32>, <4 x i32> *%px, align 16
%y = load <4 x i32>, <4 x i32> *%py, align 16
@@ -562,7 +562,7 @@ define <4 x i32> @in_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
; CHECK-SSE1-NEXT: movaps (%rdx), %xmm1
; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
-; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm0
+; CHECK-SSE1-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
; CHECK-SSE1-NEXT: retq
@@ -572,7 +572,7 @@ define <4 x i32> @in_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
; CHECK-SSE2-NEXT: movaps (%rsi), %xmm1
; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
-; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -580,7 +580,7 @@ define <4 x i32> @in_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4
; CHECK-XOP: # %bb.0:
; CHECK-XOP-NEXT: vmovdqa (%rsi), %xmm0
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
-; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-XOP-NEXT: vpcmov %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-XOP-NEXT: retq
%x = load <4 x i32>, <4 x i32> *%px, align 16
%y = load <4 x i32>, <4 x i32> *%py, align 16
diff --git a/llvm/test/CodeGen/X86/urem-power-of-two.ll b/llvm/test/CodeGen/X86/urem-power-of-two.ll
index 89555a61ea6b0..60ae891a4820a 100644
--- a/llvm/test/CodeGen/X86/urem-power-of-two.ll
+++ b/llvm/test/CodeGen/X86/urem-power-of-two.ll
@@ -106,12 +106,12 @@ define i8 @and_pow_2(i8 %x, i8 %y) {
define <4 x i32> @vec_const_uniform_pow_2(<4 x i32> %x) {
; X86-LABEL: vec_const_uniform_pow_2:
; X86: # %bb.0:
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vec_const_uniform_pow_2:
; X64: # %bb.0:
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %urem
@@ -120,12 +120,12 @@ define <4 x i32> @vec_const_uniform_pow_2(<4 x i32> %x) {
define <4 x i32> @vec_const_nonuniform_pow_2(<4 x i32> %x) {
; X86-LABEL: vec_const_nonuniform_pow_2:
; X86: # %bb.0:
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vec_const_nonuniform_pow_2:
; X64: # %bb.0:
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%urem = urem <4 x i32> %x, <i32 2, i32 4, i32 8, i32 16>
ret <4 x i32> %urem
diff --git a/llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
index 073161189f976..ab5371554576b 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
@@ -136,7 +136,7 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movd %edx, %xmm0
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSE2-NEXT: psubd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = <683,1463,819,u>
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm0, %xmm1
@@ -155,7 +155,7 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: orps %xmm3, %xmm2
; SSE2-NEXT: andps %xmm0, %xmm2
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %dl
@@ -167,8 +167,8 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; SSE41-NEXT: movd %edi, %xmm0
; SSE41-NEXT: pinsrd $1, %esi, %xmm0
; SSE41-NEXT: pinsrd $2, %edx, %xmm0
-; SSE41-NEXT: psubd {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; SSE41-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2047,2047,2047,2047]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pand %xmm1, %xmm2
@@ -179,7 +179,7 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0,1],xmm3[2,3,4,5,6,7]
; SSE41-NEXT: por %xmm2, %xmm3
; SSE41-NEXT: pand %xmm1, %xmm3
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: movd %xmm3, %eax
; SSE41-NEXT: pextrb $4, %xmm3, %edx
; SSE41-NEXT: pextrb $8, %xmm3, %ecx
@@ -193,8 +193,8 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
; AVX1-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
-; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2047,2047,2047,2047]
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vpsrld $1, %xmm2, %xmm2
@@ -204,7 +204,7 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3,4,5,6,7]
; AVX1-NEXT: vpor %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: vpextrb $4, %xmm0, %edx
; AVX1-NEXT: vpextrb $8, %xmm0, %ecx
@@ -218,15 +218,15 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
; AVX2-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
-; AVX2-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2047,2047,2047,2047]
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: vpextrb $4, %xmm0, %edx
; AVX2-NEXT: vpextrb $8, %xmm0, %ecx
@@ -240,14 +240,14 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; AVX512VL-NEXT: vmovd %edi, %xmm0
; AVX512VL-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
; AVX512VL-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
-; AVX512VL-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm1
+; AVX512VL-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2047,2047,2047,2047]
; AVX512VL-NEXT: vpand %xmm2, %xmm0, %xmm0
-; AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vpternlogd $200, %xmm1, %xmm2, %xmm0
-; AVX512VL-NEXT: vpcmpnleud {{.*}}(%rip), %xmm0, %k0
+; AVX512VL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; AVX512VL-NEXT: kshiftrw $1, %k0, %k1
; AVX512VL-NEXT: kmovw %k1, %edx
; AVX512VL-NEXT: kshiftrw $2, %k0, %k1
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
index 8f9c45ae3b270..b76567b8ded15 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
@@ -25,16 +25,16 @@ define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -53,7 +53,7 @@ define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -62,27 +62,27 @@ define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -99,19 +99,19 @@ define <4 x i32> @test_urem_odd_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_odd_allones_eq:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_allones_eq:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,858993459,1,858993459]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -120,8 +120,8 @@ define <4 x i32> @test_urem_odd_allones_eq(<4 x i32> %X) nounwind {
;
; CHECK-AVX-LABEL: test_urem_odd_allones_eq:
; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX-NEXT: retq
@@ -134,19 +134,19 @@ define <4 x i32> @test_urem_odd_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_odd_allones_ne:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_allones_ne:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993460,858993460,2,858993460]
; CHECK-SSE41-NEXT: pmaxud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -155,8 +155,8 @@ define <4 x i32> @test_urem_odd_allones_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX-LABEL: test_urem_odd_allones_ne:
; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX-NEXT: retq
@@ -171,12 +171,12 @@ define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_allones_eq:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
@@ -184,16 +184,16 @@ define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm2, %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_allones_eq:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -207,36 +207,36 @@ define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_even_allones_eq:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_allones_eq:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_allones_eq:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -249,12 +249,12 @@ define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_allones_ne:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
@@ -262,16 +262,16 @@ define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm2, %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_allones_ne:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -285,36 +285,36 @@ define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_even_allones_ne:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_allones_ne:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_allones_ne:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -344,16 +344,16 @@ define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even_allones_eq:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -372,7 +372,7 @@ define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -381,27 +381,27 @@ define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_allones_eq:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_allones_eq:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -429,8 +429,8 @@ define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -438,7 +438,7 @@ define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -457,7 +457,7 @@ define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -466,27 +466,27 @@ define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_allones_ne:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_allones_ne:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -503,29 +503,29 @@ define <4 x i32> @test_urem_odd_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_odd_poweroftwo:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_poweroftwo:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -539,36 +539,36 @@ define <4 x i32> @test_urem_odd_poweroftwo(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_odd_poweroftwo:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -583,12 +583,12 @@ define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_poweroftwo:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
@@ -596,16 +596,16 @@ define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm2, %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_poweroftwo:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -619,36 +619,36 @@ define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_even_poweroftwo:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -678,16 +678,16 @@ define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even_poweroftwo:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,268435456,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -706,7 +706,7 @@ define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,268435456,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -715,27 +715,27 @@ define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -758,14 +758,14 @@ define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,858993459,4294967295,858993459]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -774,8 +774,8 @@ define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_odd_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -784,15 +784,15 @@ define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
; CHECK-AVX2: # %bb.0:
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -817,14 +817,14 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: pslld $31, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pslld $31, %xmm0
@@ -837,11 +837,11 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_even_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -853,16 +853,16 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -892,16 +892,16 @@ define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -920,7 +920,7 @@ define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -929,27 +929,27 @@ define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -966,29 +966,29 @@ define <4 x i32> @test_urem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_odd_INT_MIN:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_INT_MIN:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -1002,36 +1002,36 @@ define <4 x i32> @test_urem_odd_INT_MIN(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_odd_INT_MIN:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_INT_MIN:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_INT_MIN:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1046,12 +1046,12 @@ define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_INT_MIN:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
@@ -1059,16 +1059,16 @@ define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm2, %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_INT_MIN:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -1082,36 +1082,36 @@ define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_even_INT_MIN:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_INT_MIN:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_INT_MIN:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1141,16 +1141,16 @@ define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even_INT_MIN:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2147483648,2,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1169,7 +1169,7 @@ define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2147483648,2,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1178,27 +1178,27 @@ define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_INT_MIN:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_INT_MIN:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1217,7 +1217,7 @@ define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,4294967295,1,3435973837]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
@@ -1229,17 +1229,17 @@ define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -1253,36 +1253,36 @@ define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1312,16 +1312,16 @@ define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,1,268435456,2147483648]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1340,7 +1340,7 @@ define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2147483648,1,268435456,2147483648]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1349,27 +1349,27 @@ define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_allones_and_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_allones_and_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1399,16 +1399,16 @@ define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,268435456,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1427,7 +1427,7 @@ define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,268435456,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1436,27 +1436,27 @@ define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_allones_and_poweroftwo:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_allones_and_poweroftwo:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1480,14 +1480,14 @@ define <4 x i32> @test_urem_odd_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_allones_and_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,1,4294967295,858993459]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -1496,8 +1496,8 @@ define <4 x i32> @test_urem_odd_allones_and_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX-LABEL: test_urem_odd_allones_and_one:
; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX-NEXT: retq
@@ -1527,16 +1527,16 @@ define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_allones_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,1,1,2147483648]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1555,7 +1555,7 @@ define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2147483648,1,1,2147483648]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1564,27 +1564,27 @@ define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_allones_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_allones_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1614,16 +1614,16 @@ define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even_allones_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1642,7 +1642,7 @@ define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1651,27 +1651,27 @@ define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_allones_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_allones_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1703,16 +1703,16 @@ define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,268435456,1,1]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1731,7 +1731,7 @@ define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,268435456,1,1]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1740,27 +1740,27 @@ define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1790,16 +1790,16 @@ define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,268435456,1,2147483648]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1818,7 +1818,7 @@ define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2147483648,268435456,1,2147483648]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1827,27 +1827,27 @@ define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1877,16 +1877,16 @@ define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm4, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_even_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,268435456,1,1073741824]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm0
@@ -1905,7 +1905,7 @@ define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,268435456,1,1073741824]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1914,27 +1914,27 @@ define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_even_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_even_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -1952,7 +1952,7 @@ define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nou
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,4294967295,1,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
@@ -1964,17 +1964,17 @@ define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nou
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -1988,36 +1988,36 @@ define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nou
;
; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -2033,7 +2033,7 @@ define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) no
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3067833783,4294967295,1,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
@@ -2045,17 +2045,17 @@ define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) no
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: por %xmm3, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
@@ -2069,36 +2069,36 @@ define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) no
;
; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
-; CHECK-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vprorvd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vprorvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
index f98f7428164f1..97e42b5908364 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
@@ -8,7 +8,7 @@
define <4 x i1> @t32_3(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: t32_3:
; CHECK-SSE2: # %bb.0:
-; CHECK-SSE2-NEXT: psubd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -16,16 +16,16 @@ define <4 x i1> @t32_3(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm3, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: t32_3:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: psubd {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,1431655764,1431655764,1431655764]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -33,26 +33,26 @@ define <4 x i1> @t32_3(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: t32_3:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: t32_3:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: t32_3:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
%urem = urem <4 x i32> %X, <i32 3, i32 3, i32 3, i32 3>
@@ -63,7 +63,7 @@ define <4 x i1> @t32_3(<4 x i32> %X) nounwind {
define <4 x i1> @t32_5(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: t32_5:
; CHECK-SSE2: # %bb.0:
-; CHECK-SSE2-NEXT: psubd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -71,16 +71,16 @@ define <4 x i1> @t32_5(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm3, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: t32_5:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: psubd {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,858993458,858993458,858993458]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -88,15 +88,15 @@ define <4 x i1> @t32_5(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: t32_5:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: t32_5:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [858993458,858993458,858993458,858993458]
@@ -106,9 +106,9 @@ define <4 x i1> @t32_5(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t32_5:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5>
@@ -119,7 +119,7 @@ define <4 x i1> @t32_5(<4 x i32> %X) nounwind {
define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: t32_6_part0:
; CHECK-SSE2: # %bb.0:
-; CHECK-SSE2-NEXT: psubd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -131,16 +131,16 @@ define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: psrld $1, %xmm0
; CHECK-SSE2-NEXT: pslld $31, %xmm3
; CHECK-SSE2-NEXT: por %xmm0, %xmm3
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm3, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: t32_6_part0:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: psubd {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pslld $31, %xmm0
@@ -152,18 +152,18 @@ define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: t32_6_part0:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: t32_6_part0:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm1
@@ -176,10 +176,10 @@ define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t32_6_part0:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
%urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>
@@ -190,7 +190,7 @@ define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: t32_6_part1:
; CHECK-SSE2: # %bb.0:
-; CHECK-SSE2-NEXT: psubd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -202,16 +202,16 @@ define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: psrld $1, %xmm0
; CHECK-SSE2-NEXT: pslld $31, %xmm3
; CHECK-SSE2-NEXT: por %xmm0, %xmm3
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm3
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm3, %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: t32_6_part1:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: psubd {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pslld $31, %xmm0
@@ -223,33 +223,33 @@ define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: t32_6_part1:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: t32_6_part1:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: t32_6_part1:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
%urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>
@@ -260,7 +260,7 @@ define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {
define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: t32_tautological:
; CHECK-SSE2: # %bb.0:
-; CHECK-SSE2-NEXT: psubd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -268,15 +268,15 @@ define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: t32_tautological:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: psubd {{.*}}(%rip), %xmm0
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295,4294967295,1431655764]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm0, %xmm1
@@ -286,9 +286,9 @@ define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: t32_tautological:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
@@ -296,10 +296,10 @@ define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
;
; CHECK-AVX2-LABEL: t32_tautological:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
@@ -307,9 +307,9 @@ define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t32_tautological:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
index ef7a07092b773..28ffa025d8a2e 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
@@ -16,14 +16,14 @@ define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_25:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [171798691,171798691,171798691,171798691]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -32,8 +32,8 @@ define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_odd_25:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -50,8 +50,8 @@ define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_urem_odd_25:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -76,14 +76,14 @@ define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: pslld $30, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_100:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $2, %xmm1
; CHECK-SSE41-NEXT: pslld $30, %xmm0
@@ -96,11 +96,11 @@ define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_even_100:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $30, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -120,9 +120,9 @@ define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_urem_even_100:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $2, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -146,14 +146,14 @@ define <4 x i32> @test_urem_odd_neg25(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_odd_neg25:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [171798691,1,1,171798691]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -162,8 +162,8 @@ define <4 x i32> @test_urem_odd_neg25(<4 x i32> %X) nounwind {
;
; CHECK-AVX-LABEL: test_urem_odd_neg25:
; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX-NEXT: retq
@@ -178,23 +178,23 @@ define <4 x i32> @test_urem_even_neg100(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_neg100:
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: pslld $30, %xmm0
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: test_urem_even_neg100:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $2, %xmm1
; CHECK-SSE41-NEXT: pslld $30, %xmm0
@@ -207,31 +207,31 @@ define <4 x i32> @test_urem_even_neg100(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_even_neg100:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpslld $30, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
;
; CHECK-AVX2-LABEL: test_urem_even_neg100:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $2, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpslld $30, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
; CHECK-AVX512VL-LABEL: test_urem_even_neg100:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vprord $2, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
@@ -279,7 +279,7 @@ define <4 x i32> @test_urem_odd_undef1(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: psrld $3, %xmm2
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -295,7 +295,7 @@ define <4 x i32> @test_urem_odd_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpsrld $3, %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -328,7 +328,7 @@ define <4 x i32> @test_urem_odd_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
; CHECK-AVX512VL-NEXT: vpsrld $3, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -374,7 +374,7 @@ define <4 x i32> @test_urem_even_undef1(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: psrld $5, %xmm2
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -390,7 +390,7 @@ define <4 x i32> @test_urem_even_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -423,7 +423,7 @@ define <4 x i32> @test_urem_even_undef1(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
; CHECK-AVX512VL-NEXT: vpsrld $5, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
@@ -484,7 +484,7 @@ define <4 x i32> @test_urem_one_ne(<4 x i32> %X) nounwind {
define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind {
; CHECK-SSE-LABEL: test_urem_pow2:
; CHECK-SSE: # %bb.0:
-; CHECK-SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE-NEXT: psrld $31, %xmm0
@@ -492,7 +492,7 @@ define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_pow2:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -509,7 +509,7 @@ define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_urem_pow2:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -524,7 +524,7 @@ define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind {
define <4 x i32> @test_urem_int_min(<4 x i32> %X) nounwind {
; CHECK-SSE-LABEL: test_urem_int_min:
; CHECK-SSE: # %bb.0:
-; CHECK-SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE-NEXT: psrld $31, %xmm0
@@ -532,7 +532,7 @@ define <4 x i32> @test_urem_int_min(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_urem_int_min:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -549,7 +549,7 @@ define <4 x i32> @test_urem_int_min(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: test_urem_int_min:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -566,9 +566,9 @@ define <4 x i32> @test_urem_allones(<4 x i32> %X) nounwind {
; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: psubd %xmm0, %xmm1
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm1
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm0
; CHECK-SSE2-NEXT: retq
;
@@ -586,7 +586,7 @@ define <4 x i32> @test_urem_allones(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq
@@ -605,7 +605,7 @@ define <4 x i32> @test_urem_allones(<4 x i32> %X) nounwind {
; CHECK-AVX512VL: # %bb.0:
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpsubd %xmm0, %xmm1, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
index 4291000382ab3..280c97bcefedc 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
@@ -8,14 +8,14 @@
define <4 x i1> @t0_all_tautological(<4 x i32> %X) nounwind {
; CHECK-SSE-LABEL: t0_all_tautological:
; CHECK-SSE: # %bb.0:
-; CHECK-SSE-NEXT: pand {{.*}}(%rip), %xmm0
-; CHECK-SSE-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
+; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE-NEXT: retq
;
; CHECK-AVX-LABEL: t0_all_tautological:
; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX-NEXT: retq
%urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 2>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>
@@ -32,14 +32,14 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: t1_all_odd_eq:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,4294967295,4294967295,4294967295]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -49,8 +49,8 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: t1_all_odd_eq:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
@@ -60,7 +60,7 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
; CHECK-AVX2: # %bb.0:
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
@@ -68,8 +68,8 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t1_all_odd_eq:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
@@ -89,8 +89,8 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
@@ -98,7 +98,7 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
;
; CHECK-SSE41-LABEL: t1_all_odd_ne:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,4294967295,4294967295,4294967295]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
@@ -109,8 +109,8 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: t1_all_odd_ne:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
@@ -121,7 +121,7 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
; CHECK-AVX2: # %bb.0:
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
@@ -130,8 +130,8 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t1_all_odd_ne:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
@@ -145,16 +145,16 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
; CHECK-SSE2-LABEL: t2_narrow:
; CHECK-SSE2: # %bb.0:
-; CHECK-SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
-; CHECK-SSE2-NEXT: psubusw {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: psubusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqw %xmm1, %xmm0
-; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq
;
; CHECK-SSE41-LABEL: t2_narrow:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0
+; CHECK-SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [21845,65535,65535,65535,21845,65535,65535,65535]
; CHECK-SSE41-NEXT: pminuw %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqw %xmm1, %xmm0
@@ -164,8 +164,8 @@ define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
;
; CHECK-AVX1-LABEL: t2_narrow:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
@@ -173,8 +173,8 @@ define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
;
; CHECK-AVX2-LABEL: t2_narrow:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
@@ -182,8 +182,8 @@ define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t2_narrow:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX512VL-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
@@ -202,11 +202,11 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
; CHECK-SSE-NEXT: movdqa %xmm0, %xmm3
; CHECK-SSE-NEXT: psrlq $32, %xmm3
; CHECK-SSE-NEXT: pmuludq %xmm1, %xmm3
-; CHECK-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; CHECK-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE-NEXT: paddq %xmm3, %xmm0
; CHECK-SSE-NEXT: psllq $32, %xmm0
; CHECK-SSE-NEXT: paddq %xmm2, %xmm0
-; CHECK-SSE-NEXT: pxor {{.*}}(%rip), %xmm0
+; CHECK-SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE-NEXT: movdqa {{.*#+}} xmm1 = [15372286730238776661,9223372034707292159]
; CHECK-SSE-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE-NEXT: pcmpgtd %xmm1, %xmm2
@@ -227,12 +227,12 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpsrlq $32, %xmm0, %xmm3
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddq %xmm0, %xmm2, %xmm0
-; CHECK-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
@@ -244,12 +244,12 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; CHECK-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; CHECK-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
-; CHECK-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
@@ -261,11 +261,11 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm3
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; CHECK-AVX512VL-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpaddq %xmm0, %xmm2, %xmm0
-; CHECK-AVX512VL-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; CHECK-AVX512VL-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/urem-vector-lkk.ll b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
index 65eb3557f4ce0..db8841b946ee9 100644
--- a/llvm/test/CodeGen/X86/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
@@ -92,15 +92,15 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,44151,44151,44151,44151]
; SSE-NEXT: pmulhuw %xmm0, %xmm1
; SSE-NEXT: psrlw $6, %xmm1
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: fold_urem_vec_2:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsrlw $6, %xmm1, %xmm1
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
@@ -123,9 +123,9 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
;
; AVX-LABEL: combine_urem_udiv:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsrlw $6, %xmm1, %xmm1
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm2
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; AVX-NEXT: vpsubw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
@@ -375,4 +375,4 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; AVX2-NEXT: retq
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/X86/use-add-flags.ll b/llvm/test/CodeGen/X86/use-add-flags.ll
index 3e7d84c05d2e6..dac170dbc4570 100644
--- a/llvm/test/CodeGen/X86/use-add-flags.ll
+++ b/llvm/test/CodeGen/X86/use-add-flags.ll
@@ -40,7 +40,7 @@ define void @test2(i32 %x) nounwind {
; LNX-NEXT: jne .LBB1_2
; LNX-NEXT: # %bb.1: # %true
; LNX-NEXT: pushq %rax
-; LNX-NEXT: callq foo
+; LNX-NEXT: callq foo at PLT
; LNX-NEXT: popq %rax
; LNX-NEXT: .LBB1_2: # %false
; LNX-NEXT: retq
@@ -74,7 +74,7 @@ define void @test3(i32 %x) nounwind {
; LNX-NEXT: jne .LBB2_2
; LNX-NEXT: # %bb.1: # %true
; LNX-NEXT: pushq %rax
-; LNX-NEXT: callq foo
+; LNX-NEXT: callq foo at PLT
; LNX-NEXT: popq %rax
; LNX-NEXT: .LBB2_2: # %false
; LNX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/usub_sat_vec.ll b/llvm/test/CodeGen/X86/usub_sat_vec.ll
index c9220c358a904..54d5584e636a1 100644
--- a/llvm/test/CodeGen/X86/usub_sat_vec.ll
+++ b/llvm/test/CodeGen/X86/usub_sat_vec.ll
@@ -503,31 +503,31 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; SSE-LABEL: v16i1:
; SSE: # %bb.0:
-; SSE-NEXT: xorps {{.*}}(%rip), %xmm1
+; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: andps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: v16i1:
; AVX1: # %bb.0:
-; AVX1-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: v16i1:
; AVX2: # %bb.0:
-; AVX2-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v16i1:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: v16i1:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpternlogq $96, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512BW-NEXT: vpternlogq $96, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512BW-NEXT: retq
%z = call <16 x i1> @llvm.usub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z
@@ -1135,7 +1135,7 @@ define void @PR48223(<32 x i16>* %p0) {
; AVX512BW-LABEL: PR48223:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
-; AVX512BW-NEXT: vpsubusw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpsubusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rdi)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/v8i1-masks.ll b/llvm/test/CodeGen/X86/v8i1-masks.ll
index 0cd3ef75ca7cd..c3f3877a7e0ca 100644
--- a/llvm/test/CodeGen/X86/v8i1-masks.ll
+++ b/llvm/test/CodeGen/X86/v8i1-masks.ll
@@ -16,7 +16,7 @@ define void @and_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi
; X32-NEXT: vmovups (%eax), %ymm2
; X32-NEXT: vcmpltps %ymm0, %ymm2, %ymm0
; X32-NEXT: vandps %ymm1, %ymm0, %ymm0
-; X32-NEXT: vandps LCPI0_0, %ymm0, %ymm0
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vmovaps %ymm0, (%eax)
; X32-NEXT: vzeroupper
; X32-NEXT: retl
@@ -29,7 +29,7 @@ define void @and_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi
; X64-NEXT: vmovups (%rdx), %ymm2
; X64-NEXT: vcmpltps %ymm0, %ymm2, %ymm0
; X64-NEXT: vandps %ymm1, %ymm0, %ymm0
-; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vmovaps %ymm0, (%rax)
; X64-NEXT: vzeroupper
; X64-NEXT: retq
@@ -80,7 +80,7 @@ define void @neg_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vmovups (%ecx), %ymm0
; X32-NEXT: vcmpnltps (%eax), %ymm0, %ymm0
-; X32-NEXT: vandps LCPI1_0, %ymm0, %ymm0
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vmovaps %ymm0, (%eax)
; X32-NEXT: vzeroupper
; X32-NEXT: retl
@@ -89,7 +89,7 @@ define void @neg_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi
; X64: ## %bb.0:
; X64-NEXT: vmovups (%rsi), %ymm0
; X64-NEXT: vcmpnltps (%rdi), %ymm0, %ymm0
-; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vmovaps %ymm0, (%rax)
; X64-NEXT: vzeroupper
; X64-NEXT: retq
@@ -132,7 +132,7 @@ define <8 x i32> @and_mask_constant(<8 x i32> %v0, <8 x i32> %v1) {
; X32-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
; X32-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X32-NEXT: vandps LCPI2_0, %ymm0, %ymm0
+; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: and_mask_constant:
@@ -142,21 +142,21 @@ define <8 x i32> @and_mask_constant(<8 x i32> %v0, <8 x i32> %v1) {
; X64-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
; X64-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
;
; X32-AVX2-LABEL: and_mask_constant:
; X32-AVX2: ## %bb.0:
; X32-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
-; X32-AVX2-NEXT: vpand LCPI2_0, %ymm0, %ymm0
+; X32-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-AVX2-NEXT: retl
;
; X64-AVX2-LABEL: and_mask_constant:
; X64-AVX2: ## %bb.0:
; X64-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: retq
%m = icmp eq <8 x i32> %v0, zeroinitializer
%mand = and <8 x i1> %m, <i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 false>
@@ -169,7 +169,7 @@ define <8 x i32> @two_ands(<8 x float> %x) local_unnamed_addr #0 {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI3_1, %ymm0, %ymm0
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
;
@@ -177,7 +177,7 @@ define <8 x i32> @two_ands(<8 x float> %x) local_unnamed_addr #0 {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
;
@@ -211,7 +211,7 @@ define <8 x i32> @three_ands(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI4_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm2, %ymm0
@@ -222,7 +222,7 @@ define <8 x i32> @three_ands(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm2, %ymm0
@@ -267,11 +267,11 @@ define <8 x i32> @four_ands(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI5_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X32-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X32-NEXT: vcmpneqps LCPI5_2, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm2, %ymm0
; X32-NEXT: vandps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
@@ -280,11 +280,11 @@ define <8 x i32> @four_ands(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X64-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm2, %ymm0
; X64-NEXT: vandps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
@@ -335,13 +335,13 @@ define <8 x i32> @five_ands(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI6_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X32-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X32-NEXT: vcmpneqps LCPI6_2, %ymm0, %ymm3
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm3
; X32-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X32-NEXT: vcmpneqps LCPI6_3, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm2, %ymm0
; X32-NEXT: vandps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
@@ -350,13 +350,13 @@ define <8 x i32> @five_ands(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X64-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm3
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; X64-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm2, %ymm0
; X64-NEXT: vandps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
@@ -415,7 +415,7 @@ define <8 x i32> @two_or(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI7_1, %ymm0, %ymm0
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vorps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
;
@@ -423,7 +423,7 @@ define <8 x i32> @two_or(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vorps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
;
@@ -457,7 +457,7 @@ define <8 x i32> @three_or(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI8_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm0
; X32-NEXT: vorps %ymm0, %ymm2, %ymm0
@@ -468,7 +468,7 @@ define <8 x i32> @three_or(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm0
; X64-NEXT: vorps %ymm0, %ymm2, %ymm0
@@ -513,11 +513,11 @@ define <8 x i32> @four_or(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI9_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X32-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X32-NEXT: vcmpneqps LCPI9_2, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vorps %ymm0, %ymm2, %ymm0
; X32-NEXT: vorps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
@@ -526,11 +526,11 @@ define <8 x i32> @four_or(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X64-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vorps %ymm0, %ymm2, %ymm0
; X64-NEXT: vorps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
@@ -581,13 +581,13 @@ define <8 x i32> @five_or(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI10_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X32-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X32-NEXT: vcmpneqps LCPI10_2, %ymm0, %ymm3
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm3
; X32-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X32-NEXT: vcmpneqps LCPI10_3, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vorps %ymm0, %ymm2, %ymm0
; X32-NEXT: vorps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
@@ -596,13 +596,13 @@ define <8 x i32> @five_or(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X64-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm3
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; X64-NEXT: vorps %ymm3, %ymm2, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vorps %ymm0, %ymm2, %ymm0
; X64-NEXT: vorps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
@@ -661,7 +661,7 @@ define <8 x i32> @three_or_and(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI11_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm2, %ymm0
@@ -672,7 +672,7 @@ define <8 x i32> @three_or_and(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm2, %ymm0
@@ -717,11 +717,11 @@ define <8 x i32> @four_or_and(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI12_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vandps %ymm2, %ymm1, %ymm1
; X32-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X32-NEXT: vcmpneqps %ymm2, %ymm0, %ymm2
-; X32-NEXT: vcmpneqps LCPI12_2, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm2, %ymm0
; X32-NEXT: vorps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
@@ -730,11 +730,11 @@ define <8 x i32> @four_or_and(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vandps %ymm2, %ymm1, %ymm1
; X64-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X64-NEXT: vcmpneqps %ymm2, %ymm0, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm2, %ymm0
; X64-NEXT: vorps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
@@ -785,12 +785,12 @@ define <8 x i32> @five_or_and(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI13_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X32-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X32-NEXT: vcmpneqps LCPI13_2, %ymm0, %ymm3
-; X32-NEXT: vcmpneqps LCPI13_3, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm3
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm3, %ymm0
; X32-NEXT: vorps %ymm0, %ymm1, %ymm0
; X32-NEXT: vorps %ymm0, %ymm2, %ymm0
@@ -800,12 +800,12 @@ define <8 x i32> @five_or_and(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
; X64-NEXT: vandps %ymm3, %ymm2, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm3
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm3, %ymm0
; X64-NEXT: vorps %ymm0, %ymm1, %ymm0
; X64-NEXT: vorps %ymm0, %ymm2, %ymm0
@@ -865,11 +865,11 @@ define <8 x i32> @four_or_and_xor(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI14_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %ymm2, %ymm1, %ymm1
; X32-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X32-NEXT: vcmpneqps %ymm2, %ymm0, %ymm2
-; X32-NEXT: vcmpneqps LCPI14_2, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm2, %ymm0
; X32-NEXT: vorps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
@@ -878,11 +878,11 @@ define <8 x i32> @four_or_and_xor(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %ymm2, %ymm1, %ymm1
; X64-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X64-NEXT: vcmpneqps %ymm2, %ymm0, %ymm2
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm2, %ymm0
; X64-NEXT: vorps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
@@ -933,11 +933,11 @@ define <8 x i32> @five_or_and_xor(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI15_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
-; X32-NEXT: vcmpneqps LCPI15_2, %ymm0, %ymm4
-; X32-NEXT: vcmpneqps LCPI15_3, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm4
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vandps %ymm0, %ymm4, %ymm0
; X32-NEXT: vxorps %ymm0, %ymm3, %ymm0
; X32-NEXT: vxorps %ymm0, %ymm2, %ymm0
@@ -948,11 +948,11 @@ define <8 x i32> @five_or_and_xor(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm4
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm4
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps %ymm0, %ymm4, %ymm0
; X64-NEXT: vxorps %ymm0, %ymm3, %ymm0
; X64-NEXT: vxorps %ymm0, %ymm2, %ymm0
@@ -1012,16 +1012,16 @@ define <8 x i32> @six_or_and_xor(<8 x float> %x) {
; X32: ## %bb.0: ## %entry
; X32-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X32-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X32-NEXT: vcmpltps LCPI16_1, %ymm0, %ymm2
+; X32-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
-; X32-NEXT: vcmpneqps LCPI16_2, %ymm0, %ymm4
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm4
; X32-NEXT: vandps %ymm4, %ymm3, %ymm3
; X32-NEXT: vandps %ymm3, %ymm2, %ymm2
; X32-NEXT: vxorps %ymm2, %ymm1, %ymm1
-; X32-NEXT: vcmpneqps LCPI16_3, %ymm0, %ymm2
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm2
; X32-NEXT: vxorps %ymm1, %ymm2, %ymm1
-; X32-NEXT: vcmpneqps LCPI16_4, %ymm0, %ymm0
+; X32-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vorps %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
;
@@ -1029,16 +1029,16 @@ define <8 x i32> @six_or_and_xor(<8 x float> %x) {
; X64: ## %bb.0: ## %entry
; X64-NEXT: vmovaps {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; X64-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
-; X64-NEXT: vcmpltps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpltps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmpneqps %ymm3, %ymm0, %ymm3
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm4
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm4
; X64-NEXT: vandps %ymm4, %ymm3, %ymm3
; X64-NEXT: vandps %ymm3, %ymm2, %ymm2
; X64-NEXT: vxorps %ymm2, %ymm1, %ymm1
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm2
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; X64-NEXT: vxorps %ymm1, %ymm2, %ymm1
-; X64-NEXT: vcmpneqps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vcmpneqps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vorps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/var-permute-128.ll b/llvm/test/CodeGen/X86/var-permute-128.ll
index a28e16417a382..a2d5055396926 100644
--- a/llvm/test/CodeGen/X86/var-permute-128.ll
+++ b/llvm/test/CodeGen/X86/var-permute-128.ll
@@ -96,14 +96,14 @@ define <4 x i32> @var_shuffle_v4i32(<4 x i32> %v, <4 x i32> %indices) nounwind {
; SSSE3-NEXT: pmuludq %xmm2, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
-; SSSE3-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pshufb %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: var_shuffle_v4i32:
; SSE41: # %bb.0:
-; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
-; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pshufb %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -173,22 +173,22 @@ define <8 x i16> @var_shuffle_v8i16(<8 x i16> %v, <8 x i16> %indices) nounwind {
;
; SSSE3-LABEL: var_shuffle_v8i16:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: pmullw {{.*}}(%rip), %xmm1
-; SSSE3-NEXT: paddw {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSSE3-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pshufb %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: var_shuffle_v8i16:
; SSE41: # %bb.0:
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm1
-; SSE41-NEXT: paddw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pshufb %xmm1, %xmm0
; SSE41-NEXT: retq
;
; AVXNOVLBW-LABEL: var_shuffle_v8i16:
; AVXNOVLBW: # %bb.0:
-; AVXNOVLBW-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
-; AVXNOVLBW-NEXT: vpaddw {{.*}}(%rip), %xmm1, %xmm1
+; AVXNOVLBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVXNOVLBW-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVXNOVLBW-NEXT: vpshufb %xmm1, %xmm0, %xmm0
; AVXNOVLBW-NEXT: retq
;
@@ -457,14 +457,14 @@ define <4 x float> @var_shuffle_v4f32(<4 x float> %v, <4 x i32> %indices) nounwi
; SSSE3-NEXT: pmuludq %xmm2, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
-; SSSE3-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pshufb %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: var_shuffle_v4f32:
; SSE41: # %bb.0:
-; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
-; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pshufb %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -1007,7 +1007,7 @@ define <16 x i8> @var_shuffle_v16i8_from_v32i8_v16i8(<32 x i8> %v, <16 x i8> %in
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -1017,7 +1017,7 @@ define <16 x i8> @var_shuffle_v16i8_from_v32i8_v16i8(<32 x i8> %v, <16 x i8> %in
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpshufb %xmm1, %xmm2, %xmm2
; AVX2-NEXT: vpshufb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtb {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -1027,7 +1027,7 @@ define <16 x i8> @var_shuffle_v16i8_from_v32i8_v16i8(<32 x i8> %v, <16 x i8> %in
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX512-NEXT: vpshufb %xmm1, %xmm2, %xmm2
; AVX512-NEXT: vpshufb %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpcmpgtb {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
@@ -1038,7 +1038,7 @@ define <16 x i8> @var_shuffle_v16i8_from_v32i8_v16i8(<32 x i8> %v, <16 x i8> %in
; AVX512VLBW-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX512VLBW-NEXT: vpshufb %xmm1, %xmm2, %xmm2
; AVX512VLBW-NEXT: vpshufb %xmm1, %xmm0, %xmm0
-; AVX512VLBW-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %k1
+; AVX512VLBW-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512VLBW-NEXT: vmovdqu8 %ymm2, %ymm0 {%k1}
; AVX512VLBW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512VLBW-NEXT: vzeroupper
@@ -1161,7 +1161,7 @@ define void @indices_convert() {
; XOP-LABEL: indices_convert:
; XOP: # %bb.0: # %bb
; XOP-NEXT: vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; XOP-NEXT: vmovapd (%rax), %xmm1
; XOP-NEXT: vpaddq %xmm0, %xmm0, %xmm0
@@ -1172,7 +1172,7 @@ define void @indices_convert() {
; AVX1-LABEL: indices_convert:
; AVX1: # %bb.0: # %bb
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vmovapd (%rax), %xmm1
; AVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0
@@ -1207,7 +1207,7 @@ define void @indices_convert() {
; AVX512VL-LABEL: indices_convert:
; AVX512VL: # %bb.0: # %bb
; AVX512VL-NEXT: vpbroadcastq (%rax), %xmm0
-; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX512VL-NEXT: vpermq (%rax), %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqu %xmm0, (%rax)
diff --git a/llvm/test/CodeGen/X86/var-permute-256.ll b/llvm/test/CodeGen/X86/var-permute-256.ll
index 3327704c04a08..5ffeb90aa6340 100644
--- a/llvm/test/CodeGen/X86/var-permute-256.ll
+++ b/llvm/test/CodeGen/X86/var-permute-256.ll
@@ -33,8 +33,8 @@ define <4 x i64> @var_shuffle_v4i64(<4 x i64> %v, <4 x i64> %indices) nounwind {
; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -92,9 +92,9 @@ define <8 x i32> @var_shuffle_v8i32(<8 x i32> %v, <8 x i32> %indices) nounwind {
; AVX1-NEXT: vpermilps %ymm1, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -168,37 +168,37 @@ define <16 x i16> @var_shuffle_v16i16(<16 x i16> %v, <16 x i16> %indices) nounwi
;
; AVX2-LABEL: var_shuffle_v16i16:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX2-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm0[2,3,2,3]
; AVX2-NEXT: vpshufb %ymm1, %ymm2, %ymm2
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: var_shuffle_v16i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX512-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512-NEXT: vpermq {{.*#+}} ymm2 = ymm0[2,3,2,3]
; AVX512-NEXT: vpshufb %ymm1, %ymm2, %ymm2
; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq
;
; AVX512VLDQ-LABEL: var_shuffle_v16i16:
; AVX512VLDQ: # %bb.0:
-; AVX512VLDQ-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX512VLDQ-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLDQ-NEXT: vpermq {{.*#+}} ymm2 = ymm0[2,3,2,3]
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm2, %ymm2
; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512VLDQ-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLDQ-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512VLDQ-NEXT: retq
;
@@ -294,7 +294,7 @@ define <32 x i8> @var_shuffle_v32i8(<32 x i8> %v, <32 x i8> %indices) nounwind {
; AVX2-NEXT: vpshufb %ymm1, %ymm2, %ymm2
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -304,7 +304,7 @@ define <32 x i8> @var_shuffle_v32i8(<32 x i8> %v, <32 x i8> %indices) nounwind {
; AVX512-NEXT: vpshufb %ymm1, %ymm2, %ymm2
; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq
;
@@ -314,7 +314,7 @@ define <32 x i8> @var_shuffle_v32i8(<32 x i8> %v, <32 x i8> %indices) nounwind {
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm2, %ymm2
; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512VLDQ-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLDQ-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512VLDQ-NEXT: retq
;
@@ -323,7 +323,7 @@ define <32 x i8> @var_shuffle_v32i8(<32 x i8> %v, <32 x i8> %indices) nounwind {
; AVX512VLBW-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm2
; AVX512VLBW-NEXT: vpshufb %ymm1, %ymm2, %ymm2
; AVX512VLBW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3]
-; AVX512VLBW-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %k1
+; AVX512VLBW-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512VLBW-NEXT: vpshufb %ymm1, %ymm0, %ymm2 {%k1}
; AVX512VLBW-NEXT: vmovdqa %ymm2, %ymm0
; AVX512VLBW-NEXT: retq
@@ -453,8 +453,8 @@ define <4 x double> @var_shuffle_v4f64(<4 x double> %v, <4 x i64> %indices) noun
; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -512,9 +512,9 @@ define <8 x float> @var_shuffle_v8f32(<8 x float> %v, <8 x i32> %indices) nounwi
; AVX1-NEXT: vpermilps %ymm1, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -575,8 +575,8 @@ define <4 x i64> @var_shuffle_v4i64_from_v2i64(<2 x i64> %v, <4 x i64> %indices)
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
@@ -636,9 +636,9 @@ define <8 x i32> @var_shuffle_v8i32_from_v4i32(<4 x i32> %v, <8 x i32> %indices)
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -713,36 +713,36 @@ define <16 x i16> @var_shuffle_v16i16_from_v8i16(<8 x i16> %v, <16 x i16> %indic
; AVX2-LABEL: var_shuffle_v16i16_from_v8i16:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX2-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: var_shuffle_v16i16_from_v8i16:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX512-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX512-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512-NEXT: vpshufb %ymm1, %ymm0, %ymm2
; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq
;
; AVX512VLDQ-LABEL: var_shuffle_v16i16_from_v8i16:
; AVX512VLDQ: # %bb.0:
; AVX512VLDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX512VLDQ-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX512VLDQ-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm0, %ymm2
; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512VLDQ-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLDQ-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512VLDQ-NEXT: retq
;
@@ -838,7 +838,7 @@ define <32 x i8> @var_shuffle_v32i8_from_v16i8(<16 x i8> %v, <32 x i8> %indices)
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -848,7 +848,7 @@ define <32 x i8> @var_shuffle_v32i8_from_v16i8(<16 x i8> %v, <32 x i8> %indices)
; AVX512-NEXT: vpshufb %ymm1, %ymm0, %ymm2
; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq
;
@@ -858,7 +858,7 @@ define <32 x i8> @var_shuffle_v32i8_from_v16i8(<16 x i8> %v, <32 x i8> %indices)
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm0, %ymm2
; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512VLDQ-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512VLDQ-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLDQ-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512VLDQ-NEXT: retq
;
@@ -867,7 +867,7 @@ define <32 x i8> @var_shuffle_v32i8_from_v16i8(<16 x i8> %v, <32 x i8> %indices)
; AVX512VLBW-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512VLBW-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; AVX512VLBW-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX512VLBW-NEXT: vpcmpgtb {{.*}}(%rip), %ymm1, %k1
+; AVX512VLBW-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %k1
; AVX512VLBW-NEXT: vpshufb %ymm1, %ymm0, %ymm0 {%k1}
; AVX512VLBW-NEXT: retq
;
@@ -996,8 +996,8 @@ define <4 x double> @var_shuffle_v4f64_from_v2f64(<2 x double> %v, <4 x i64> %in
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
@@ -1057,9 +1057,9 @@ define <8 x float> @var_shuffle_v8f32_from_v4f32(<4 x float> %v, <8 x i32> %indi
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -1110,7 +1110,7 @@ define <4 x i32> @var_shuffle_v4i32_from_v8i32(<8 x i32> %v, <4 x i32> %indices)
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpermilps %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpermilps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -1145,7 +1145,7 @@ entry:
define <4 x i64> @PR50356(<4 x i64> %0, <4 x i32> %1, <4 x i64> %2) unnamed_addr nounwind {
; XOP-LABEL: PR50356:
; XOP: # %bb.0:
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
; XOP-NEXT: vpaddq %xmm1, %xmm1, %xmm1
@@ -1156,18 +1156,18 @@ define <4 x i64> @PR50356(<4 x i64> %0, <4 x i32> %1, <4 x i64> %2) unnamed_addr
; XOP-NEXT: vpcomltq %xmm1, %xmm2, %xmm1
; XOP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; XOP-NEXT: vmovapd {{.*#+}} ymm1 = [34,68,102,136]
-; XOP-NEXT: vblendvpd %ymm0, {{.*}}(%rip), %ymm1, %ymm0
+; XOP-NEXT: vblendvpd %ymm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; XOP-NEXT: retq
;
; AVX1-LABEL: PR50356:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpermilpd %xmm1, %xmm3, %xmm3
; AVX1-NEXT: vpermilpd %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1
@@ -1175,7 +1175,7 @@ define <4 x i64> @PR50356(<4 x i64> %0, <4 x i32> %1, <4 x i64> %2) unnamed_addr
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [34,68,102,136]
-; AVX1-NEXT: vblendvpd %ymm0, {{.*}}(%rip), %ymm1, %ymm0
+; AVX1-NEXT: vblendvpd %ymm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: PR50356:
@@ -1196,7 +1196,7 @@ define <4 x i64> @PR50356(<4 x i64> %0, <4 x i32> %1, <4 x i64> %2) unnamed_addr
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vmovapd {{.*#+}} ymm1 = [34,68,102,136]
-; AVX2-NEXT: vblendvpd %ymm0, {{.*}}(%rip), %ymm1, %ymm0
+; AVX2-NEXT: vblendvpd %ymm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX2-NEXT: movq %rbp, %rsp
; AVX2-NEXT: popq %rbp
; AVX2-NEXT: retq
@@ -1233,7 +1233,7 @@ define <4 x i64> @PR50356(<4 x i64> %0, <4 x i32> %1, <4 x i64> %2) unnamed_addr
; AVX512VL-NEXT: movq %rsp, %rbp
; AVX512VL-NEXT: andq $-32, %rsp
; AVX512VL-NEXT: subq $64, %rsp
-; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; AVX512VL-NEXT: vmovd %xmm1, %eax
; AVX512VL-NEXT: vmovaps %ymm0, (%rsp)
; AVX512VL-NEXT: andl $3, %eax
@@ -1244,7 +1244,7 @@ define <4 x i64> @PR50356(<4 x i64> %0, <4 x i32> %1, <4 x i64> %2) unnamed_addr
; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX512VL-NEXT: vpcmpgtq %ymm0, %ymm2, %k1
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm0 = [34,68,102,136]
-; AVX512VL-NEXT: vmovdqa64 {{.*}}(%rip), %ymm0 {%k1}
+; AVX512VL-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 {%k1}
; AVX512VL-NEXT: movq %rbp, %rsp
; AVX512VL-NEXT: popq %rbp
; AVX512VL-NEXT: retq
@@ -1286,8 +1286,8 @@ define <4 x i64> @var_shuffle_v4i64_with_v16i8_indices(<4 x i64> %v, <16 x i8> %
; AVX1-NEXT: vpermilpd %ymm4, %ymm3, %ymm3
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}+16(%rip), %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
; AVX1-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/var-permute-512.ll b/llvm/test/CodeGen/X86/var-permute-512.ll
index 674e69c84f11b..347bfc5210fa3 100644
--- a/llvm/test/CodeGen/X86/var-permute-512.ll
+++ b/llvm/test/CodeGen/X86/var-permute-512.ll
@@ -1067,7 +1067,7 @@ define void @var_cvt_shuffle_v64f32_v64i8_idx(<64 x float>* %dst, <64 x i8> %src
; AVX512F-NEXT: subq $128, %rsp
; AVX512F-NEXT: # kill: def $esi killed $esi def $rsi
; AVX512F-NEXT: vpbroadcastd %esi, %zmm2
-; AVX512F-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm1
+; AVX512F-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm1
; AVX512F-NEXT: vmovd %xmm1, %eax
; AVX512F-NEXT: vmovaps %zmm0, (%rsp)
; AVX512F-NEXT: andl $63, %eax
@@ -1102,9 +1102,9 @@ define void @var_cvt_shuffle_v64f32_v64i8_idx(<64 x float>* %dst, <64 x i8> %src
; AVX512F-NEXT: vpextrd $1, %xmm4, %eax
; AVX512F-NEXT: andl $63, %eax
; AVX512F-NEXT: vpinsrb $9, (%rsp,%rax), %xmm0, %xmm0
-; AVX512F-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm5
-; AVX512F-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm3
-; AVX512F-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm2
+; AVX512F-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm5
+; AVX512F-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm3
+; AVX512F-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512F-NEXT: andl $63, %esi
; AVX512F-NEXT: vpinsrb $10, (%rsp,%rsi), %xmm0, %xmm0
; AVX512F-NEXT: vpextrd $3, %xmm4, %eax
@@ -1318,7 +1318,7 @@ define void @var_cvt_shuffle_v64f32_v64i8_idx(<64 x float>* %dst, <64 x i8> %src
; AVX512BW-NEXT: subq $128, %rsp
; AVX512BW-NEXT: # kill: def $esi killed $esi def $rsi
; AVX512BW-NEXT: vpbroadcastd %esi, %zmm2
-; AVX512BW-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm1
+; AVX512BW-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm1
; AVX512BW-NEXT: vmovd %xmm1, %eax
; AVX512BW-NEXT: vmovaps %zmm0, (%rsp)
; AVX512BW-NEXT: andl $63, %eax
@@ -1353,9 +1353,9 @@ define void @var_cvt_shuffle_v64f32_v64i8_idx(<64 x float>* %dst, <64 x i8> %src
; AVX512BW-NEXT: vpextrd $1, %xmm4, %eax
; AVX512BW-NEXT: andl $63, %eax
; AVX512BW-NEXT: vpinsrb $9, (%rsp,%rax), %xmm0, %xmm0
-; AVX512BW-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm5
-; AVX512BW-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm3
-; AVX512BW-NEXT: vpaddd {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm5
+; AVX512BW-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm3
+; AVX512BW-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: andl $63, %esi
; AVX512BW-NEXT: vpinsrb $10, (%rsp,%rsi), %xmm0, %xmm0
; AVX512BW-NEXT: vpextrd $3, %xmm4, %eax
@@ -1569,7 +1569,7 @@ define void @var_cvt_shuffle_v64f32_v64i8_idx(<64 x float>* %dst, <64 x i8> %src
; AVX512VBMI-NEXT: subq $128, %rsp
; AVX512VBMI-NEXT: # kill: def $esi killed $esi def $rsi
; AVX512VBMI-NEXT: vpbroadcastd %esi, %zmm1
-; AVX512VBMI-NEXT: vpaddd {{.*}}(%rip), %zmm1, %zmm2
+; AVX512VBMI-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm2
; AVX512VBMI-NEXT: vmovd %xmm2, %eax
; AVX512VBMI-NEXT: vmovdqa64 %zmm0, (%rsp)
; AVX512VBMI-NEXT: andl $63, %eax
@@ -1622,11 +1622,11 @@ define void @var_cvt_shuffle_v64f32_v64i8_idx(<64 x float>* %dst, <64 x i8> %src
; AVX512VBMI-NEXT: vpextrd $3, %xmm2, %eax
; AVX512VBMI-NEXT: andl $63, %eax
; AVX512VBMI-NEXT: vpinsrb $15, (%rsp,%rax), %xmm3, %xmm2
-; AVX512VBMI-NEXT: vpaddd {{.*}}(%rip), %zmm1, %zmm3
+; AVX512VBMI-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm3
; AVX512VBMI-NEXT: vpmovdb %zmm3, %xmm3
-; AVX512VBMI-NEXT: vpaddd {{.*}}(%rip), %zmm1, %zmm4
+; AVX512VBMI-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm4
; AVX512VBMI-NEXT: vpmovdb %zmm4, %xmm4
-; AVX512VBMI-NEXT: vpaddd {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VBMI-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VBMI-NEXT: vpmovdb %zmm1, %xmm1
; AVX512VBMI-NEXT: vpmovsxbd %xmm2, %zmm2
; AVX512VBMI-NEXT: vcvtdq2ps %zmm2, %zmm2
diff --git a/llvm/test/CodeGen/X86/vec-copysign-avx512.ll b/llvm/test/CodeGen/X86/vec-copysign-avx512.ll
index 2103fc24a5cda..f47187fd05267 100644
--- a/llvm/test/CodeGen/X86/vec-copysign-avx512.ll
+++ b/llvm/test/CodeGen/X86/vec-copysign-avx512.ll
@@ -5,7 +5,7 @@
define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: v4f32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogd $228, {{.*}}(%rip){1to4}, %xmm1, %xmm0
+; CHECK-NEXT: vpternlogd $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
; CHECK-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )
ret <4 x float> %tmp
@@ -14,7 +14,7 @@ define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
; CHECK-LABEL: v8f32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogd $228, {{.*}}(%rip){1to8}, %ymm1, %ymm0
+; CHECK-NEXT: vpternlogd $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
; CHECK-NEXT: retq
%tmp = tail call <8 x float> @llvm.copysign.v8f32( <8 x float> %a, <8 x float> %b )
ret <8 x float> %tmp
@@ -23,7 +23,7 @@ define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
define <16 x float> @v16f32(<16 x float> %a, <16 x float> %b) nounwind {
; CHECK-LABEL: v16f32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogd $228, {{.*}}(%rip){1to16}, %zmm1, %zmm0
+; CHECK-NEXT: vpternlogd $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
; CHECK-NEXT: retq
%tmp = tail call <16 x float> @llvm.copysign.v16f32( <16 x float> %a, <16 x float> %b )
ret <16 x float> %tmp
@@ -32,7 +32,7 @@ define <16 x float> @v16f32(<16 x float> %a, <16 x float> %b) nounwind {
define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
; CHECK-LABEL: v2f64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogq $228, {{.*}}(%rip), %xmm1, %xmm0
+; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; CHECK-NEXT: retq
%tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
ret <2 x double> %tmp
@@ -41,7 +41,7 @@ define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
; CHECK-LABEL: v4f64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogq $228, {{.*}}(%rip){1to4}, %ymm1, %ymm0
+; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm0
; CHECK-NEXT: retq
%tmp = tail call <4 x double> @llvm.copysign.v4f64( <4 x double> %a, <4 x double> %b )
ret <4 x double> %tmp
@@ -50,7 +50,7 @@ define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
define <8 x double> @v8f64(<8 x double> %a, <8 x double> %b) nounwind {
; CHECK-LABEL: v8f64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogq $228, {{.*}}(%rip){1to8}, %zmm1, %zmm0
+; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm0
; CHECK-NEXT: retq
%tmp = tail call <8 x double> @llvm.copysign.v8f64( <8 x double> %a, <8 x double> %b )
ret <8 x double> %tmp
diff --git a/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll b/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
index 72fcb41248197..8e790e9728846 100644
--- a/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
@@ -2031,7 +2031,7 @@ define <2 x i8> @strict_vector_fptosi_v2f64_to_v2i8(<2 x double> %a) #0 {
; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i8:
; SSE-32: # %bb.0:
; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm0
-; SSE-32-NEXT: andpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl
@@ -2039,7 +2039,7 @@ define <2 x i8> @strict_vector_fptosi_v2f64_to_v2i8(<2 x double> %a) #0 {
; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i8:
; SSE-64: # %bb.0:
; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm0
-; SSE-64-NEXT: andpd {{.*}}(%rip), %xmm0
+; SSE-64-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: retq
@@ -2082,7 +2082,7 @@ define <2 x i8> @strict_vector_fptoui_v2f64_to_v2i8(<2 x double> %a) #0 {
; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i8:
; SSE-32: # %bb.0:
; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm0
-; SSE-32-NEXT: andpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl
@@ -2090,7 +2090,7 @@ define <2 x i8> @strict_vector_fptoui_v2f64_to_v2i8(<2 x double> %a) #0 {
; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i8:
; SSE-64: # %bb.0:
; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm0
-; SSE-64-NEXT: andpd {{.*}}(%rip), %xmm0
+; SSE-64-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: retq
@@ -2134,7 +2134,7 @@ define <2 x i8> @strict_vector_fptosi_v2f32_to_v2i8(<2 x float> %a) #0 {
; SSE-32: # %bb.0:
; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl
@@ -2143,7 +2143,7 @@ define <2 x i8> @strict_vector_fptosi_v2f32_to_v2i8(<2 x float> %a) #0 {
; SSE-64: # %bb.0:
; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-64-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-64-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: retq
@@ -2192,7 +2192,7 @@ define <2 x i8> @strict_vector_fptoui_v2f32_to_v2i8(<2 x float> %a) #0 {
; SSE-32: # %bb.0:
; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl
@@ -2201,7 +2201,7 @@ define <2 x i8> @strict_vector_fptoui_v2f32_to_v2i8(<2 x float> %a) #0 {
; SSE-64: # %bb.0:
; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-64-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-64-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: packuswb %xmm0, %xmm0
; SSE-64-NEXT: retq
@@ -3037,7 +3037,7 @@ define <4 x i32> @strict_vector_fptoui_v4f32_to_v4i32(<4 x float> %a) #0 {
; SSE-32-NEXT: movaps %xmm0, %xmm3
; SSE-32-NEXT: cmpltps %xmm2, %xmm3
; SSE-32-NEXT: movaps %xmm3, %xmm1
-; SSE-32-NEXT: andnps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE-32-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; SSE-32-NEXT: andnps %xmm2, %xmm3
; SSE-32-NEXT: subps %xmm3, %xmm0
; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0
@@ -3051,7 +3051,7 @@ define <4 x i32> @strict_vector_fptoui_v4f32_to_v4i32(<4 x float> %a) #0 {
; SSE-64-NEXT: movaps %xmm0, %xmm3
; SSE-64-NEXT: cmpltps %xmm2, %xmm3
; SSE-64-NEXT: movaps %xmm3, %xmm1
-; SSE-64-NEXT: andnps {{.*}}(%rip), %xmm1
+; SSE-64-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-64-NEXT: andnps %xmm2, %xmm3
; SSE-64-NEXT: subps %xmm3, %xmm0
; SSE-64-NEXT: cvttps2dq %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll b/llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll
index 5c92db796933f..bc2038e326e4b 100644
--- a/llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll
@@ -278,14 +278,14 @@ define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {
; SSE-32-NEXT: movd %xmm1, %eax
; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstps (%esp)
; SSE-32-NEXT: wait
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-32-NEXT: movd %xmm0, %eax
; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE-32-NEXT: wait
; SSE-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -347,14 +347,14 @@ define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {
; SSE41-32-NEXT: movd %xmm1, %eax
; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstps (%esp)
; SSE41-32-NEXT: wait
; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE41-32-NEXT: movd %xmm0, %eax
; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE41-32-NEXT: wait
; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -415,13 +415,13 @@ define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {
; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps (%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -433,7 +433,7 @@ define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {
;
; AVX1-64-LABEL: uitofp_v2i64_v2f32:
; AVX1-64: # %bb.0:
-; AVX1-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-64-NEXT: vpsrlq $1, %xmm0, %xmm2
; AVX1-64-NEXT: vpor %xmm1, %xmm2, %xmm1
; AVX1-64-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm1
@@ -526,37 +526,37 @@ define <4 x float> @sitofp_v4i1_v4f32(<4 x i1> %x) #0 {
define <4 x float> @uitofp_v4i1_v4f32(<4 x i1> %x) #0 {
; SSE-32-LABEL: uitofp_v4i1_v4f32:
; SSE-32: # %bb.0:
-; SSE-32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-32-NEXT: retl
;
; SSE-64-LABEL: uitofp_v4i1_v4f32:
; SSE-64: # %bb.0:
-; SSE-64-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-64-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-64-NEXT: retq
;
; SSE41-32-LABEL: uitofp_v4i1_v4f32:
; SSE41-32: # %bb.0:
-; SSE41-32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE41-32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE41-32-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE41-32-NEXT: retl
;
; SSE41-64-LABEL: uitofp_v4i1_v4f32:
; SSE41-64: # %bb.0:
-; SSE41-64-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE41-64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-64-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE41-64-NEXT: retq
;
; AVX1-32-LABEL: uitofp_v4i1_v4f32:
; AVX1-32: # %bb.0:
-; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX1-32-NEXT: retl
;
; AVX1-64-LABEL: uitofp_v4i1_v4f32:
; AVX1-64: # %bb.0:
-; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX1-64-NEXT: retq
;
@@ -569,13 +569,13 @@ define <4 x float> @uitofp_v4i1_v4f32(<4 x i1> %x) #0 {
;
; AVX512VL-32-LABEL: uitofp_v4i1_v4f32:
; AVX512VL-32: # %bb.0:
-; AVX512VL-32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; AVX512VL-32-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512VL-32-NEXT: retl
;
; AVX512VL-64-LABEL: uitofp_v4i1_v4f32:
; AVX512VL-64: # %bb.0:
-; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512VL-64-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512VL-64-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512VL-64-NEXT: retq
;
@@ -588,13 +588,13 @@ define <4 x float> @uitofp_v4i1_v4f32(<4 x i1> %x) #0 {
;
; AVX512DQVL-32-LABEL: uitofp_v4i1_v4f32:
; AVX512DQVL-32: # %bb.0:
-; AVX512DQVL-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; AVX512DQVL-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512DQVL-32-NEXT: retl
;
; AVX512DQVL-64-LABEL: uitofp_v4i1_v4f32:
; AVX512DQVL-64: # %bb.0:
-; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512DQVL-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512DQVL-64-NEXT: retq
%result = call <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i1(<4 x i1> %x,
@@ -737,10 +737,10 @@ define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {
; SSE-32: # %bb.0:
; SSE-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE-32-NEXT: pand %xmm0, %xmm1
-; SSE-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; SSE-32-NEXT: psrld $16, %xmm0
-; SSE-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE-32-NEXT: subps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: addps %xmm1, %xmm0
; SSE-32-NEXT: retl
;
@@ -748,10 +748,10 @@ define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {
; SSE-64: # %bb.0:
; SSE-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE-64-NEXT: pand %xmm0, %xmm1
-; SSE-64-NEXT: por {{.*}}(%rip), %xmm1
+; SSE-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-64-NEXT: psrld $16, %xmm0
-; SSE-64-NEXT: por {{.*}}(%rip), %xmm0
-; SSE-64-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-64-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-64-NEXT: addps %xmm1, %xmm0
; SSE-64-NEXT: retq
;
@@ -759,10 +759,10 @@ define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {
; SSE41-32: # %bb.0:
; SSE41-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE41-32-NEXT: pand %xmm0, %xmm1
-; SSE41-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE41-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; SSE41-32-NEXT: psrld $16, %xmm0
-; SSE41-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE41-32-NEXT: subps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE41-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE41-32-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE41-32-NEXT: addps %xmm1, %xmm0
; SSE41-32-NEXT: retl
;
@@ -770,10 +770,10 @@ define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {
; SSE41-64: # %bb.0:
; SSE41-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE41-64-NEXT: pand %xmm0, %xmm1
-; SSE41-64-NEXT: por {{.*}}(%rip), %xmm1
+; SSE41-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-64-NEXT: psrld $16, %xmm0
-; SSE41-64-NEXT: por {{.*}}(%rip), %xmm0
-; SSE41-64-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE41-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-64-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-64-NEXT: addps %xmm1, %xmm0
; SSE41-64-NEXT: retq
;
@@ -782,7 +782,7 @@ define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {
; AVX1-32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-32-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; AVX1-32-NEXT: vsubps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-32-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-32-NEXT: retl
;
@@ -791,7 +791,7 @@ define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {
; AVX1-64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-64-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; AVX1-64-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-64-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-64-NEXT: retq
;
@@ -860,42 +860,42 @@ define <2 x double> @uitofp_v2i1_v2f64(<2 x i1> %x) #0 {
; SSE-32-LABEL: uitofp_v2i1_v2f64:
; SSE-32: # %bb.0:
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-32-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-32-NEXT: retl
;
; SSE-64-LABEL: uitofp_v2i1_v2f64:
; SSE-64: # %bb.0:
; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE-64-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-64-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-64-NEXT: retq
;
; SSE41-32-LABEL: uitofp_v2i1_v2f64:
; SSE41-32: # %bb.0:
; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE41-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE41-32-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE41-32-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-32-NEXT: retl
;
; SSE41-64-LABEL: uitofp_v2i1_v2f64:
; SSE41-64: # %bb.0:
; SSE41-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE41-64-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-64-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-64-NEXT: retq
;
; AVX1-32-LABEL: uitofp_v2i1_v2f64:
; AVX1-32: # %bb.0:
; AVX1-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX1-32-NEXT: retl
;
; AVX1-64-LABEL: uitofp_v2i1_v2f64:
; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX1-64-NEXT: retq
;
@@ -910,14 +910,14 @@ define <2 x double> @uitofp_v2i1_v2f64(<2 x i1> %x) #0 {
; AVX512VL-32-LABEL: uitofp_v2i1_v2f64:
; AVX512VL-32: # %bb.0:
; AVX512VL-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AVX512VL-32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; AVX512VL-32-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VL-32-NEXT: retl
;
; AVX512VL-64-LABEL: uitofp_v2i1_v2f64:
; AVX512VL-64: # %bb.0:
; AVX512VL-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512VL-64-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512VL-64-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VL-64-NEXT: retq
;
@@ -932,14 +932,14 @@ define <2 x double> @uitofp_v2i1_v2f64(<2 x i1> %x) #0 {
; AVX512DQVL-32-LABEL: uitofp_v2i1_v2f64:
; AVX512DQVL-32: # %bb.0:
; AVX512DQVL-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AVX512DQVL-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; AVX512DQVL-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512DQVL-32-NEXT: retl
;
; AVX512DQVL-64-LABEL: uitofp_v2i1_v2f64:
; AVX512DQVL-64: # %bb.0:
; AVX512DQVL-64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512DQVL-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512DQVL-64-NEXT: retq
%result = call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i1(<2 x i1> %x,
@@ -1276,14 +1276,14 @@ define <2 x double> @uitofp_v2i64_v2f64(<2 x i64> %x) #0 {
; SSE-32-NEXT: movd %xmm1, %eax
; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE-32-NEXT: wait
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-32-NEXT: movd %xmm0, %eax
; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstpl (%esp)
; SSE-32-NEXT: wait
; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
@@ -1344,14 +1344,14 @@ define <2 x double> @uitofp_v2i64_v2f64(<2 x i64> %x) #0 {
; SSE41-32-NEXT: movd %xmm1, %eax
; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE41-32-NEXT: wait
; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-32-NEXT: movd %xmm0, %eax
; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
-; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstpl (%esp)
; SSE41-32-NEXT: wait
; SSE41-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
@@ -1411,13 +1411,13 @@ define <2 x double> @uitofp_v2i64_v2f64(<2 x i64> %x) #0 {
; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl (%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
diff --git a/llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll b/llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
index 3d1f87f3fc069..80ce4a96ac903 100644
--- a/llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
@@ -94,7 +94,7 @@ define <8 x float> @sitofp_v8i1_v8f32(<8 x i1> %x) #0 {
define <8 x float> @uitofp_v8i1_v8f32(<8 x i1> %x) #0 {
; AVX1-32-LABEL: uitofp_v8i1_v8f32:
; AVX1-32: # %bb.0:
-; AVX1-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-32-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-32-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
@@ -104,7 +104,7 @@ define <8 x float> @uitofp_v8i1_v8f32(<8 x i1> %x) #0 {
;
; AVX1-64-LABEL: uitofp_v8i1_v8f32:
; AVX1-64: # %bb.0:
-; AVX1-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-64-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-64-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
@@ -114,70 +114,70 @@ define <8 x float> @uitofp_v8i1_v8f32(<8 x i1> %x) #0 {
;
; AVX2-32-LABEL: uitofp_v8i1_v8f32:
; AVX2-32: # %bb.0:
-; AVX2-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX2-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX2-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-32-NEXT: retl
;
; AVX2-64-LABEL: uitofp_v8i1_v8f32:
; AVX2-64: # %bb.0:
-; AVX2-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-64-NEXT: retq
;
; AVX512F-32-LABEL: uitofp_v8i1_v8f32:
; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX512F-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512F-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512F-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512F-32-NEXT: retl
;
; AVX512F-64-LABEL: uitofp_v8i1_v8f32:
; AVX512F-64: # %bb.0:
-; AVX512F-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512F-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512F-64-NEXT: retq
;
; AVX512VL-32-LABEL: uitofp_v8i1_v8f32:
; AVX512VL-32: # %bb.0:
-; AVX512VL-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX512VL-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VL-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512VL-32-NEXT: retl
;
; AVX512VL-64-LABEL: uitofp_v8i1_v8f32:
; AVX512VL-64: # %bb.0:
-; AVX512VL-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VL-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512VL-64-NEXT: retq
;
; AVX512DQ-32-LABEL: uitofp_v8i1_v8f32:
; AVX512DQ-32: # %bb.0:
-; AVX512DQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX512DQ-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512DQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQ-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQ-32-NEXT: retl
;
; AVX512DQ-64-LABEL: uitofp_v8i1_v8f32:
; AVX512DQ-64: # %bb.0:
-; AVX512DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512DQ-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512DQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQ-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQ-64-NEXT: retq
;
; AVX512DQVL-32-LABEL: uitofp_v8i1_v8f32:
; AVX512DQVL-32: # %bb.0:
-; AVX512DQVL-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX512DQVL-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQVL-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQVL-32-NEXT: retl
;
; AVX512DQVL-64-LABEL: uitofp_v8i1_v8f32:
; AVX512DQVL-64: # %bb.0:
-; AVX512DQVL-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512DQVL-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQVL-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQVL-64-NEXT: retq
@@ -386,8 +386,8 @@ define <8 x float> @uitofp_v8i32_v8f32(<8 x i32> %x) #0 {
; AVX1-32-NEXT: vpsrld $16, %xmm2, %xmm2
; AVX1-32-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-32-NEXT: vcvtdq2ps %ymm1, %ymm1
-; AVX1-32-NEXT: vmulps {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
-; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; AVX1-32-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
+; AVX1-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX1-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-32-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX1-32-NEXT: retl
@@ -399,8 +399,8 @@ define <8 x float> @uitofp_v8i32_v8f32(<8 x i32> %x) #0 {
; AVX1-64-NEXT: vpsrld $16, %xmm2, %xmm2
; AVX1-64-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-64-NEXT: vcvtdq2ps %ymm1, %ymm1
-; AVX1-64-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-64-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-64-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX1-64-NEXT: retq
@@ -462,13 +462,13 @@ define <4 x double> @sitofp_v4i1_v4f64(<4 x i1> %x) #0 {
define <4 x double> @uitofp_v4i1_v4f64(<4 x i1> %x) #0 {
; AVX1-32-LABEL: uitofp_v4i1_v4f64:
; AVX1-32: # %bb.0:
-; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX1-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-32-NEXT: retl
;
; AVX1-64-LABEL: uitofp_v4i1_v4f64:
; AVX1-64: # %bb.0:
-; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-64-NEXT: retq
;
@@ -488,13 +488,13 @@ define <4 x double> @uitofp_v4i1_v4f64(<4 x i1> %x) #0 {
;
; AVX512VL-32-LABEL: uitofp_v4i1_v4f64:
; AVX512VL-32: # %bb.0:
-; AVX512VL-32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; AVX512VL-32-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512VL-32-NEXT: retl
;
; AVX512VL-64-LABEL: uitofp_v4i1_v4f64:
; AVX512VL-64: # %bb.0:
-; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512VL-64-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512VL-64-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512VL-64-NEXT: retq
;
@@ -507,13 +507,13 @@ define <4 x double> @uitofp_v4i1_v4f64(<4 x i1> %x) #0 {
;
; AVX512DQVL-32-LABEL: uitofp_v4i1_v4f64:
; AVX512DQVL-32: # %bb.0:
-; AVX512DQVL-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; AVX512DQVL-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512DQVL-32-NEXT: retl
;
; AVX512DQVL-64-LABEL: uitofp_v4i1_v4f64:
; AVX512DQVL-64: # %bb.0:
-; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512DQVL-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512DQVL-64-NEXT: retq
%result = call <4 x double> @llvm.experimental.constrained.uitofp.v4f64.v4i1(<4 x i1> %x,
@@ -767,25 +767,25 @@ define <4 x double> @uitofp_v4i64_v4f64(<4 x i64> %x) #0 {
; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl (%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $1, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -824,7 +824,7 @@ define <4 x double> @uitofp_v4i64_v4f64(<4 x i64> %x) #0 {
; AVX1-64-NEXT: vcvtsi2sd %rax, %xmm5, %xmm0
; AVX1-64-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX1-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-64-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-64-NEXT: vmulpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-64-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-64-NEXT: retq
;
@@ -1051,25 +1051,25 @@ define <4 x float> @uitofp_v4i64_v4f32(<4 x i64> %x) #0 {
; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps (%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $1, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
-; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -1088,7 +1088,7 @@ define <4 x float> @uitofp_v4i64_v4f32(<4 x i64> %x) #0 {
; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-64-NEXT: vpsrlq $1, %xmm2, %xmm3
; AVX1-64-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
-; AVX1-64-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3
+; AVX1-64-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; AVX1-64-NEXT: vorpd %ymm3, %ymm1, %ymm1
; AVX1-64-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax
diff --git a/llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll b/llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
index 4d54e96a22522..f0d861f2973b6 100644
--- a/llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
@@ -42,28 +42,28 @@ define <16 x float> @sitofp_v16i1_v16f32(<16 x i1> %x) #0 {
define <16 x float> @uitofp_v16i1_v16f32(<16 x i1> %x) #0 {
; NODQ-32-LABEL: uitofp_v16i1_v16f32:
; NODQ-32: # %bb.0:
-; NODQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; NODQ-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; NODQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; NODQ-32-NEXT: vcvtdq2ps %zmm0, %zmm0
; NODQ-32-NEXT: retl
;
; NODQ-64-LABEL: uitofp_v16i1_v16f32:
; NODQ-64: # %bb.0:
-; NODQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; NODQ-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; NODQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; NODQ-64-NEXT: vcvtdq2ps %zmm0, %zmm0
; NODQ-64-NEXT: retq
;
; DQ-32-LABEL: uitofp_v16i1_v16f32:
; DQ-32: # %bb.0:
-; DQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; DQ-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; DQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; DQ-32-NEXT: vcvtdq2ps %zmm0, %zmm0
; DQ-32-NEXT: retl
;
; DQ-64-LABEL: uitofp_v16i1_v16f32:
; DQ-64: # %bb.0:
-; DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; DQ-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; DQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; DQ-64-NEXT: vcvtdq2ps %zmm0, %zmm0
; DQ-64-NEXT: retq
@@ -160,28 +160,28 @@ define <8 x double> @sitofp_v8i1_v8f64(<8 x i1> %x) #0 {
define <8 x double> @uitofp_v8i1_v8f64(<8 x i1> %x) #0 {
; NODQ-32-LABEL: uitofp_v8i1_v8f64:
; NODQ-32: # %bb.0:
-; NODQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; NODQ-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; NODQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; NODQ-32-NEXT: vcvtdq2pd %ymm0, %zmm0
; NODQ-32-NEXT: retl
;
; NODQ-64-LABEL: uitofp_v8i1_v8f64:
; NODQ-64: # %bb.0:
-; NODQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; NODQ-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; NODQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; NODQ-64-NEXT: vcvtdq2pd %ymm0, %zmm0
; NODQ-64-NEXT: retq
;
; DQ-32-LABEL: uitofp_v8i1_v8f64:
; DQ-32: # %bb.0:
-; DQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; DQ-32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; DQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; DQ-32-NEXT: vcvtdq2pd %ymm0, %zmm0
; DQ-32-NEXT: retl
;
; DQ-64-LABEL: uitofp_v8i1_v8f64:
; DQ-64: # %bb.0:
-; DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; DQ-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; DQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; DQ-64-NEXT: vcvtdq2pd %ymm0, %zmm0
; DQ-64-NEXT: retq
@@ -387,49 +387,49 @@ define <8 x double> @uitofp_v8i64_v8f64(<8 x i64> %x) #0 {
; NODQ-32-NEXT: vextractps $1, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl (%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -612,49 +612,49 @@ define <8 x float> @uitofp_v8i64_v8f32(<8 x i64> %x) #0 {
; NODQ-32-NEXT: vextractps $1, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps (%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
-; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
+; NODQ-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
diff --git a/llvm/test/CodeGen/X86/vec_cast3.ll b/llvm/test/CodeGen/X86/vec_cast3.ll
index 00c222e7cbbf0..749188c5542a8 100644
--- a/llvm/test/CodeGen/X86/vec_cast3.ll
+++ b/llvm/test/CodeGen/X86/vec_cast3.ll
@@ -119,7 +119,7 @@ define <2 x i32> @cvt_v2f32_v2u32(<2 x float> %src) {
; CHECK-NEXT: vcmpltps %xmm1, %xmm0, %xmm2
; CHECK-NEXT: vsubps %xmm1, %xmm0, %xmm1
; CHECK-NEXT: vcvttps2dq %xmm1, %xmm1
-; CHECK-NEXT: vxorps LCPI11_1, %xmm1, %xmm1
+; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/vec_ctbits.ll b/llvm/test/CodeGen/X86/vec_ctbits.ll
index e0ea1a29821ba..1a924043b254b 100644
--- a/llvm/test/CodeGen/X86/vec_ctbits.ll
+++ b/llvm/test/CodeGen/X86/vec_ctbits.ll
@@ -13,7 +13,7 @@ define <2 x i64> @footz(<2 x i64> %a) nounwind {
; CHECK-NEXT: pandn %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2
@@ -24,7 +24,7 @@ define <2 x i64> @footz(<2 x i64> %a) nounwind {
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: psadbw %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
@@ -58,7 +58,7 @@ define <2 x i64> @foolz(<2 x i64> %a) nounwind {
; CHECK-NEXT: pxor %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: psrlw $1, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: psubb %xmm0, %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm1, %xmm2
@@ -69,7 +69,7 @@ define <2 x i64> @foolz(<2 x i64> %a) nounwind {
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: psrlw $4, %xmm2
; CHECK-NEXT: paddb %xmm1, %xmm2
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm2
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: psadbw %xmm2, %xmm0
; CHECK-NEXT: retq
@@ -83,7 +83,7 @@ define <2 x i64> @foopop(<2 x i64> %a) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2
@@ -94,7 +94,7 @@ define <2 x i64> @foopop(<2 x i64> %a) nounwind {
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: psadbw %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
@@ -115,7 +115,7 @@ define <2 x i32> @promtz(<2 x i32> %a) nounwind {
; CHECK-NEXT: pandn %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2
@@ -126,7 +126,7 @@ define <2 x i32> @promtz(<2 x i32> %a) nounwind {
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -162,7 +162,7 @@ define <2 x i32> @promlz(<2 x i32> %a) nounwind {
; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: psrlw $1, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: psubb %xmm0, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm2, %xmm1
@@ -173,7 +173,7 @@ define <2 x i32> @promlz(<2 x i32> %a) nounwind {
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: psrlw $4, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
@@ -192,7 +192,7 @@ define <2 x i32> @prompop(<2 x i32> %a) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2
@@ -203,7 +203,7 @@ define <2 x i32> @prompop(<2 x i32> %a) nounwind {
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
diff --git a/llvm/test/CodeGen/X86/vec_ext_inreg.ll b/llvm/test/CodeGen/X86/vec_ext_inreg.ll
index 76d5ed856dece..367f1acc16d42 100644
--- a/llvm/test/CodeGen/X86/vec_ext_inreg.ll
+++ b/llvm/test/CodeGen/X86/vec_ext_inreg.ll
@@ -69,7 +69,7 @@ define <8 x i32> @d(<8 x i32> %a) nounwind {
;
; AVX1-LABEL: d:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: d:
@@ -85,7 +85,7 @@ define <8 x i32> @d(<8 x i32> %a) nounwind {
define <3 x i32> @e(<3 x i32> %a) nounwind {
; SSE-LABEL: e:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: e:
diff --git a/llvm/test/CodeGen/X86/vec_extract.ll b/llvm/test/CodeGen/X86/vec_extract.ll
index 46cd15357c72c..947712e7b78dd 100644
--- a/llvm/test/CodeGen/X86/vec_extract.ll
+++ b/llvm/test/CodeGen/X86/vec_extract.ll
@@ -79,7 +79,7 @@ define double @test4(double %A) nounwind {
; X32-LABEL: test4:
; X32: # %bb.0: # %entry
; X32-NEXT: subl $12, %esp
-; X32-NEXT: calll foo
+; X32-NEXT: calll foo at PLT
; X32-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; X32-NEXT: addsd {{[0-9]+}}(%esp), %xmm0
; X32-NEXT: movsd %xmm0, (%esp)
@@ -91,7 +91,7 @@ define double @test4(double %A) nounwind {
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
; X64-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
-; X64-NEXT: callq foo
+; X64-NEXT: callq foo at PLT
; X64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; X64-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload
; X64-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index 8ce675054f413..64bd0f7939685 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -9,12 +9,12 @@
define <2 x double> @fabs_v2f64(<2 x double> %p) {
; X86-LABEL: fabs_v2f64:
; X86: # %bb.0:
-; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: fabs_v2f64:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
ret <2 x double> %t
@@ -24,32 +24,32 @@ declare <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
define <4 x float> @fabs_v4f32(<4 x float> %p) {
; X86-AVX-LABEL: fabs_v4f32:
; X86-AVX: # %bb.0:
-; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl
;
; X86-AVX512VL-LABEL: fabs_v4f32:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; X86-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; X86-AVX512VL-NEXT: retl
;
; X86-AVX512VLDQ-LABEL: fabs_v4f32:
; X86-AVX512VLDQ: # %bb.0:
-; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
+; X86-AVX512VLDQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; X86-AVX512VLDQ-NEXT: retl
;
; X64-AVX-LABEL: fabs_v4f32:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
;
; X64-AVX512VL-LABEL: fabs_v4f32:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; X64-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512VLDQ-LABEL: fabs_v4f32:
; X64-AVX512VLDQ: # %bb.0:
-; X64-AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; X64-AVX512VLDQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512VLDQ-NEXT: retq
%t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
ret <4 x float> %t
@@ -59,32 +59,32 @@ declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
define <4 x double> @fabs_v4f64(<4 x double> %p) {
; X86-AVX-LABEL: fabs_v4f64:
; X86-AVX: # %bb.0:
-; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX-NEXT: retl
;
; X86-AVX512VL-LABEL: fabs_v4f64:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vpandq {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
+; X86-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
; X86-AVX512VL-NEXT: retl
;
; X86-AVX512VLDQ-LABEL: fabs_v4f64:
; X86-AVX512VLDQ: # %bb.0:
-; X86-AVX512VLDQ-NEXT: vandpd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
+; X86-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
; X86-AVX512VLDQ-NEXT: retl
;
; X64-AVX-LABEL: fabs_v4f64:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX-NEXT: retq
;
; X64-AVX512VL-LABEL: fabs_v4f64:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512VLDQ-LABEL: fabs_v4f64:
; X64-AVX512VLDQ: # %bb.0:
-; X64-AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; X64-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; X64-AVX512VLDQ-NEXT: retq
%t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
ret <4 x double> %t
@@ -94,32 +94,32 @@ declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
define <8 x float> @fabs_v8f32(<8 x float> %p) {
; X86-AVX-LABEL: fabs_v8f32:
; X86-AVX: # %bb.0:
-; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX-NEXT: retl
;
; X86-AVX512VL-LABEL: fabs_v8f32:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
+; X86-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X86-AVX512VL-NEXT: retl
;
; X86-AVX512VLDQ-LABEL: fabs_v8f32:
; X86-AVX512VLDQ: # %bb.0:
-; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
+; X86-AVX512VLDQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X86-AVX512VLDQ-NEXT: retl
;
; X64-AVX-LABEL: fabs_v8f32:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX-NEXT: retq
;
; X64-AVX512VL-LABEL: fabs_v8f32:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; X64-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512VLDQ-LABEL: fabs_v8f32:
; X64-AVX512VLDQ: # %bb.0:
-; X64-AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; X64-AVX512VLDQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-AVX512VLDQ-NEXT: retq
%t = call <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
ret <8 x float> %t
@@ -136,12 +136,12 @@ define <8 x double> @fabs_v8f64(<8 x double> %p) {
;
; X86-AVX512VL-LABEL: fabs_v8f64:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vpandq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
+; X86-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-AVX512VL-NEXT: retl
;
; X86-AVX512VLDQ-LABEL: fabs_v8f64:
; X86-AVX512VLDQ: # %bb.0:
-; X86-AVX512VLDQ-NEXT: vandpd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
+; X86-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-AVX512VLDQ-NEXT: retl
;
; X64-AVX-LABEL: fabs_v8f64:
@@ -153,12 +153,12 @@ define <8 x double> @fabs_v8f64(<8 x double> %p) {
;
; X64-AVX512VL-LABEL: fabs_v8f64:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; X64-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512VLDQ-LABEL: fabs_v8f64:
; X64-AVX512VLDQ: # %bb.0:
-; X64-AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; X64-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-AVX512VLDQ-NEXT: retq
%t = call <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
ret <8 x double> %t
@@ -175,12 +175,12 @@ define <16 x float> @fabs_v16f32(<16 x float> %p) {
;
; X86-AVX512VL-LABEL: fabs_v16f32:
; X86-AVX512VL: # %bb.0:
-; X86-AVX512VL-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
+; X86-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-AVX512VL-NEXT: retl
;
; X86-AVX512VLDQ-LABEL: fabs_v16f32:
; X86-AVX512VLDQ: # %bb.0:
-; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
+; X86-AVX512VLDQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-AVX512VLDQ-NEXT: retl
;
; X64-AVX-LABEL: fabs_v16f32:
@@ -192,12 +192,12 @@ define <16 x float> @fabs_v16f32(<16 x float> %p) {
;
; X64-AVX512VL-LABEL: fabs_v16f32:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; X64-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512VLDQ-LABEL: fabs_v16f32:
; X64-AVX512VLDQ: # %bb.0:
-; X64-AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to16}, %zmm0, %zmm0
+; X64-AVX512VLDQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; X64-AVX512VLDQ-NEXT: retq
%t = call <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
ret <16 x float> %t
diff --git a/llvm/test/CodeGen/X86/vec_fneg.ll b/llvm/test/CodeGen/X86/vec_fneg.ll
index 9c162d2123c6f..df7dcc0f15280 100644
--- a/llvm/test/CodeGen/X86/vec_fneg.ll
+++ b/llvm/test/CodeGen/X86/vec_fneg.ll
@@ -10,12 +10,12 @@
define <4 x float> @t1(<4 x float> %Q) nounwind {
; X32-SSE-LABEL: t1:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl
;
; X64-SSE-LABEL: t1:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
%tmp = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %Q
ret <4 x float> %tmp
@@ -166,12 +166,12 @@ define <2 x float> @fneg_bitcast(i64 %i) nounwind {
define <4 x float> @fneg_undef_elts_v4f32(<4 x float> %x) {
; X32-SSE-LABEL: fneg_undef_elts_v4f32:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl
;
; X64-SSE-LABEL: fneg_undef_elts_v4f32:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
%r = fsub <4 x float> <float -0.0, float undef, float undef, float -0.0>, %x
ret <4 x float> %r
@@ -194,12 +194,12 @@ define <4 x float> @fsub0_undef_elts_v4f32(<4 x float> %x) {
define <4 x float> @fneg(<4 x float> %Q) nounwind {
; X32-SSE-LABEL: fneg:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl
;
; X64-SSE-LABEL: fneg:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
%tmp = fneg <4 x float> %Q
ret <4 x float> %tmp
diff --git a/llvm/test/CodeGen/X86/vec_fp_to_int.ll b/llvm/test/CodeGen/X86/vec_fp_to_int.ll
index 49708fda44c92..dfbebfd6a8caa 100644
--- a/llvm/test/CodeGen/X86/vec_fp_to_int.ll
+++ b/llvm/test/CodeGen/X86/vec_fp_to_int.ll
@@ -352,7 +352,7 @@ define <4 x i32> @fptoui_2f64_to_4i32(<2 x double> %a) {
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm3
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX1-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm2, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX1-NEXT: vzeroupper
@@ -426,7 +426,7 @@ define <4 x i32> @fptoui_2f64_to_2i32(<2 x double> %a) {
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm3
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX1-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm2, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -498,7 +498,7 @@ define <4 x i32> @fptoui_4f64_to_2i32(<2 x double> %a) {
; AVX1-NEXT: vpackssdw %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm1
; AVX1-NEXT: vcvttpd2dq %ymm1, %xmm1
-; AVX1-NEXT: vxorpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vzeroupper
@@ -756,7 +756,7 @@ define <4 x i32> @fptoui_4f64_to_4i32(<4 x double> %a) {
; AVX1-NEXT: vpackssdw %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm1
; AVX1-NEXT: vcvttpd2dq %ymm1, %xmm1
-; AVX1-NEXT: vxorpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vzeroupper
@@ -1205,7 +1205,7 @@ define <2 x i32> @fptoui_2f32_to_2i32(<2 x float> %a) {
; SSE-NEXT: cvttps2dq %xmm0, %xmm3
; SSE-NEXT: subps %xmm2, %xmm0
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-NEXT: xorps {{.*}}(%rip), %xmm0
+; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: andnps %xmm0, %xmm1
; SSE-NEXT: orps %xmm3, %xmm1
@@ -1218,7 +1218,7 @@ define <2 x i32> @fptoui_2f32_to_2i32(<2 x float> %a) {
; AVX1-NEXT: vcmpltps %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vsubps %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
-; AVX1-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
@@ -1273,7 +1273,7 @@ define <4 x i32> @fptoui_4f32_to_4i32(<4 x float> %a) {
; SSE-NEXT: cvttps2dq %xmm0, %xmm3
; SSE-NEXT: subps %xmm2, %xmm0
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-NEXT: xorps {{.*}}(%rip), %xmm0
+; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: andnps %xmm0, %xmm1
; SSE-NEXT: orps %xmm3, %xmm1
@@ -1286,7 +1286,7 @@ define <4 x i32> @fptoui_4f32_to_4i32(<4 x float> %a) {
; AVX1-NEXT: vcmpltps %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vsubps %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
-; AVX1-NEXT: vxorps {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
@@ -1537,7 +1537,7 @@ define <8 x i32> @fptoui_8f32_to_8i32(<8 x float> %a) {
; AVX1-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vsubps %ymm1, %ymm0, %ymm1
; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1
-; AVX1-NEXT: vxorps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX1-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
@@ -2158,10 +2158,10 @@ define <4 x i32> @fptosi_2f16_to_4i32(<2 x half> %a) nounwind {
; SSE-NEXT: pushq %rax
; SSE-NEXT: movl %esi, %ebx
; SSE-NEXT: movzwl %di, %edi
-; SSE-NEXT: callq __gnu_h2f_ieee
+; SSE-NEXT: callq __gnu_h2f_ieee at PLT
; SSE-NEXT: cvttss2si %xmm0, %ebp
; SSE-NEXT: movzwl %bx, %edi
-; SSE-NEXT: callq __gnu_h2f_ieee
+; SSE-NEXT: callq __gnu_h2f_ieee at PLT
; SSE-NEXT: cvttss2si %xmm0, %eax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: movd %ebp, %xmm1
@@ -2179,10 +2179,10 @@ define <4 x i32> @fptosi_2f16_to_4i32(<2 x half> %a) nounwind {
; VEX-NEXT: pushq %rax
; VEX-NEXT: movl %esi, %ebx
; VEX-NEXT: movzwl %di, %edi
-; VEX-NEXT: callq __gnu_h2f_ieee
+; VEX-NEXT: callq __gnu_h2f_ieee at PLT
; VEX-NEXT: vcvttss2si %xmm0, %ebp
; VEX-NEXT: movzwl %bx, %edi
-; VEX-NEXT: callq __gnu_h2f_ieee
+; VEX-NEXT: callq __gnu_h2f_ieee at PLT
; VEX-NEXT: vcvttss2si %xmm0, %eax
; VEX-NEXT: vmovd %eax, %xmm0
; VEX-NEXT: vmovd %ebp, %xmm1
@@ -2260,10 +2260,10 @@ define <4 x i32> @fptosi_2f128_to_4i32(<2 x fp128> %a) nounwind {
; SSE-NEXT: pushq %rbx
; SSE-NEXT: subq $16, %rsp
; SSE-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
-; SSE-NEXT: callq __fixtfsi
+; SSE-NEXT: callq __fixtfsi at PLT
; SSE-NEXT: movl %eax, %ebx
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: callq __fixtfsi
+; SSE-NEXT: callq __fixtfsi at PLT
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: movd %ebx, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
@@ -2277,10 +2277,10 @@ define <4 x i32> @fptosi_2f128_to_4i32(<2 x fp128> %a) nounwind {
; AVX-NEXT: pushq %rbx
; AVX-NEXT: subq $16, %rsp
; AVX-NEXT: vmovaps %xmm1, (%rsp) # 16-byte Spill
-; AVX-NEXT: callq __fixtfsi
+; AVX-NEXT: callq __fixtfsi at PLT
; AVX-NEXT: movl %eax, %ebx
; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; AVX-NEXT: callq __fixtfsi
+; AVX-NEXT: callq __fixtfsi at PLT
; AVX-NEXT: vmovd %eax, %xmm0
; AVX-NEXT: vmovd %ebx, %xmm1
; AVX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
@@ -2297,7 +2297,7 @@ define <2 x i8> @fptosi_2f32_to_2i8(<2 x float> %a) {
; SSE-LABEL: fptosi_2f32_to_2i8:
; SSE: # %bb.0:
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: retq
@@ -2355,7 +2355,7 @@ define <2 x i8> @fptoui_2f32_to_2i8(<2 x float> %a) {
; SSE-LABEL: fptoui_2f32_to_2i8:
; SSE: # %bb.0:
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: retq
@@ -2413,7 +2413,7 @@ define <2 x i8> @fptosi_2f64_to_2i8(<2 x double> %a) {
; SSE-LABEL: fptosi_2f64_to_2i8:
; SSE: # %bb.0:
; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
-; SSE-NEXT: andpd {{.*}}(%rip), %xmm0
+; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: retq
@@ -2471,7 +2471,7 @@ define <2 x i8> @fptoui_2f64_to_2i8(<2 x double> %a) {
; SSE-LABEL: fptoui_2f64_to_2i8:
; SSE: # %bb.0:
; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
-; SSE-NEXT: andpd {{.*}}(%rip), %xmm0
+; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: packuswb %xmm0, %xmm0
; SSE-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vec_fpext.ll b/llvm/test/CodeGen/X86/vec_fpext.ll
index 84b6039dc1ad8..7ecb177ae4708 100644
--- a/llvm/test/CodeGen/X86/vec_fpext.ll
+++ b/llvm/test/CodeGen/X86/vec_fpext.ll
@@ -255,42 +255,42 @@ define <2 x double> @fpext_fromconst() {
; X32-SSE: # %bb.0: # %entry
; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X32-SSE-NEXT: # encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X32-SSE-NEXT: # fixup A - offset: 3, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X32-SSE-NEXT: # fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X32-SSE-NEXT: retl # encoding: [0xc3]
;
; X32-AVX-LABEL: fpext_fromconst:
; X32-AVX: # %bb.0: # %entry
; X32-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X32-AVX-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X32-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X32-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X32-AVX-NEXT: retl # encoding: [0xc3]
;
; X32-AVX512VL-LABEL: fpext_fromconst:
; X32-AVX512VL: # %bb.0: # %entry
-; X32-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0]
+; X32-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0]
; X32-AVX512VL-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X32-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X32-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X32-AVX512VL-NEXT: retl # encoding: [0xc3]
;
; X64-SSE-LABEL: fpext_fromconst:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X64-SSE-NEXT: # encoding: [0x0f,0x28,0x05,A,A,A,A]
-; X64-SSE-NEXT: # fixup A - offset: 3, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-SSE-NEXT: # fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: retq # encoding: [0xc3]
;
; X64-AVX-LABEL: fpext_fromconst:
; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X64-AVX-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3]
;
; X64-AVX512VL-LABEL: fpext_fromconst:
; X64-AVX512VL: # %bb.0: # %entry
-; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0]
+; X64-AVX512VL-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
entry:
%0 = insertelement <2 x float> undef, float 1.0, i32 0
diff --git a/llvm/test/CodeGen/X86/vec_fptrunc.ll b/llvm/test/CodeGen/X86/vec_fptrunc.ll
index 56da56204799a..18f8781faccad 100644
--- a/llvm/test/CodeGen/X86/vec_fptrunc.ll
+++ b/llvm/test/CodeGen/X86/vec_fptrunc.ll
@@ -186,26 +186,26 @@ define <4 x float> @fptrunc_fromreg2_zext(<2 x double> %arg) {
define <4 x float> @fptrunc_fromconst() {
; X32-SSE-LABEL: fptrunc_fromconst:
; X32-SSE: # %bb.0: # %entry
-; X32-SSE-NEXT: cvtpd2ps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
-; X32-SSE-NEXT: cvtpd2ps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: cvtpd2ps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE-NEXT: cvtpd2ps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32-SSE-NEXT: retl
;
; X32-AVX-LABEL: fptrunc_fromconst:
; X32-AVX: # %bb.0: # %entry
-; X32-AVX-NEXT: vcvtpd2psy {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-AVX-NEXT: vcvtpd2psy {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-AVX-NEXT: retl
;
; X64-SSE-LABEL: fptrunc_fromconst:
; X64-SSE: # %bb.0: # %entry
-; X64-SSE-NEXT: cvtpd2ps {{.*}}(%rip), %xmm1
-; X64-SSE-NEXT: cvtpd2ps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: cvtpd2ps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; X64-SSE-NEXT: cvtpd2ps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: fptrunc_fromconst:
; X64-AVX: # %bb.0: # %entry
-; X64-AVX-NEXT: vcvtpd2psy {{.*}}(%rip), %xmm0
+; X64-AVX-NEXT: vcvtpd2psy {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-AVX-NEXT: retq
entry:
%0 = insertelement <4 x double> undef, double 1.0, i32 0
diff --git a/llvm/test/CodeGen/X86/vec_insert-7.ll b/llvm/test/CodeGen/X86/vec_insert-7.ll
index e4b9806ab7e67..b7a63b6cac824 100644
--- a/llvm/test/CodeGen/X86/vec_insert-7.ll
+++ b/llvm/test/CodeGen/X86/vec_insert-7.ll
@@ -8,7 +8,7 @@
define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
; X32-LABEL: mmx_movzl:
; X32: ## %bb.0:
-; X32-NEXT: movq LCPI0_0, %mm0
+; X32-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}, %mm0
; X32-NEXT: retl
;
; X64-LABEL: mmx_movzl:
diff --git a/llvm/test/CodeGen/X86/vec_insert-mmx.ll b/llvm/test/CodeGen/X86/vec_insert-mmx.ll
index 1c190f333f417..6e7805d98e328 100644
--- a/llvm/test/CodeGen/X86/vec_insert-mmx.ll
+++ b/llvm/test/CodeGen/X86/vec_insert-mmx.ll
@@ -67,8 +67,8 @@ define void @t3() {
;
; X64-LABEL: t3:
; X64: ## %bb.0:
-; X64-NEXT: movq _g0@{{.*}}(%rip), %rax
-; X64-NEXT: movq _g1@{{.*}}(%rip), %rcx
+; X64-NEXT: movq _g0 at GOTPCREL(%rip), %rax
+; X64-NEXT: movq _g1 at GOTPCREL(%rip), %rcx
; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: pinsrw $0, (%rax), %xmm0
; X64-NEXT: movq %xmm0, (%rcx)
diff --git a/llvm/test/CodeGen/X86/vec_int_to_fp.ll b/llvm/test/CodeGen/X86/vec_int_to_fp.ll
index 08f65b94af6ec..12d7b05bf3dac 100644
--- a/llvm/test/CodeGen/X86/vec_int_to_fp.ll
+++ b/llvm/test/CodeGen/X86/vec_int_to_fp.ll
@@ -571,10 +571,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295]
; SSE2-NEXT: pand %xmm0, %xmm1
-; SSE2-NEXT: por {{.*}}(%rip), %xmm1
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlq $32, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
-; SSE2-NEXT: subpd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: addpd %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -582,10 +582,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; SSE41-NEXT: por {{.*}}(%rip), %xmm1
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: psrlq $32, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
-; SSE41-NEXT: subpd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: addpd %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -593,10 +593,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; AVX1-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -604,10 +604,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX2-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX2-NEXT: retq
;
@@ -615,10 +615,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX512F-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: retq
;
@@ -626,10 +626,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
@@ -931,11 +931,11 @@ define <4 x double> @uitofp_4i64_to_4f64(<4 x i64> %a) {
; AVX1: # %bb.0:
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm2, %ymm2
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm0, %ymm2, %ymm0
; AVX1-NEXT: retq
;
@@ -971,10 +971,10 @@ define <4 x double> @uitofp_4i64_to_4f64(<4 x i64> %a) {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
-; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm1, %ymm1
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlq $32, %ymm0, %ymm0
-; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm0, %ymm0
-; AVX512VL-NEXT: vsubpd {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512VL-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: retq
;
@@ -1910,7 +1910,7 @@ define <4 x float> @uitofp_2i64_to_4f32(<2 x i64> %a) {
;
; VEX-LABEL: uitofp_2i64_to_4f32:
; VEX: # %bb.0:
-; VEX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
+; VEX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; VEX-NEXT: vpsrlq $1, %xmm0, %xmm2
; VEX-NEXT: vpor %xmm1, %xmm2, %xmm1
; VEX-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm1
@@ -2025,7 +2025,7 @@ define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) {
;
; VEX-LABEL: uitofp_2i64_to_2f32:
; VEX: # %bb.0:
-; VEX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
+; VEX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; VEX-NEXT: vpsrlq $1, %xmm0, %xmm2
; VEX-NEXT: vpor %xmm1, %xmm2, %xmm1
; VEX-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm1
@@ -2140,7 +2140,7 @@ define <4 x float> @uitofp_4i64_to_4f32_undef(<2 x i64> %a) {
; AVX1-LABEL: uitofp_4i64_to_4f32_undef:
; AVX1: # %bb.0:
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm2
; AVX1-NEXT: vorps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
@@ -2230,10 +2230,10 @@ define <4 x float> @uitofp_4i32_to_4f32(<4 x i32> %a) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE2-NEXT: pand %xmm0, %xmm1
-; SSE2-NEXT: por {{.*}}(%rip), %xmm1
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrld $16, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
-; SSE2-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -2243,7 +2243,7 @@ define <4 x float> @uitofp_4i32_to_4f32(<4 x i32> %a) {
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; SSE41-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE41-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -2252,7 +2252,7 @@ define <4 x float> @uitofp_4i32_to_4f32(<4 x i32> %a) {
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; AVX1-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -2555,7 +2555,7 @@ define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
-; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3
+; AVX1-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; AVX1-NEXT: vorpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax
@@ -2700,8 +2700,8 @@ define <8 x float> @uitofp_8i32_to_8f32(<8 x i32> %a) {
; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1
-; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
@@ -3282,10 +3282,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; SSE2-NEXT: movdqa (%rdi), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295]
; SSE2-NEXT: pand %xmm0, %xmm1
-; SSE2-NEXT: por {{.*}}(%rip), %xmm1
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlq $32, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
-; SSE2-NEXT: subpd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: addpd %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -3294,10 +3294,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; SSE41-NEXT: movdqa (%rdi), %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; SSE41-NEXT: por {{.*}}(%rip), %xmm1
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: psrlq $32, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
-; SSE41-NEXT: subpd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: addpd %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -3306,10 +3306,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; AVX1-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; AVX1-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -3318,10 +3318,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; AVX2-NEXT: vmovdqa (%rdi), %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX2-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX2-NEXT: retq
;
@@ -3330,10 +3330,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; AVX512F-NEXT: vmovdqa (%rdi), %xmm0
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX512F-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: retq
;
@@ -3342,10 +3342,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
@@ -3671,11 +3671,11 @@ define <4 x double> @uitofp_load_4i64_to_4f64(<4 x i64> *%a) {
; AVX1-NEXT: vmovaps (%rdi), %ymm0
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm2, %ymm2
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[1,3],ymm0[1,3],ymm1[5,7],ymm0[5,7]
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
-; AVX1-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm0, %ymm2, %ymm0
; AVX1-NEXT: retq
;
@@ -3714,10 +3714,10 @@ define <4 x double> @uitofp_load_4i64_to_4f64(<4 x i64> *%a) {
; AVX512VL-NEXT: vmovdqa (%rdi), %ymm0
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
-; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm1, %ymm1
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlq $32, %ymm0, %ymm0
-; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm0, %ymm0
-; AVX512VL-NEXT: vsubpd {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512VL-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: retq
;
@@ -4470,7 +4470,7 @@ define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) {
; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm3
; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
-; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm4
+; AVX1-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm4
; AVX1-NEXT: vorpd %ymm4, %ymm3, %ymm3
; AVX1-NEXT: vblendvpd %ymm0, %ymm3, %ymm0, %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
@@ -4575,10 +4575,10 @@ define <4 x float> @uitofp_load_4i32_to_4f32(<4 x i32> *%a) {
; SSE2-NEXT: movdqa (%rdi), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE2-NEXT: pand %xmm0, %xmm1
-; SSE2-NEXT: por {{.*}}(%rip), %xmm1
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrld $16, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
-; SSE2-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -4589,7 +4589,7 @@ define <4 x float> @uitofp_load_4i32_to_4f32(<4 x i32> *%a) {
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; SSE41-NEXT: subps {{.*}}(%rip), %xmm0
+; SSE41-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -4599,7 +4599,7 @@ define <4 x float> @uitofp_load_4i32_to_4f32(<4 x i32> *%a) {
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; AVX1-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
@@ -5148,8 +5148,8 @@ define <8 x float> @uitofp_load_8i32_to_8f32(<8 x i32> *%a) {
; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1
-; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
@@ -5791,7 +5791,7 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX1-LABEL: PR43609:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
@@ -5817,7 +5817,7 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX2-LABEL: PR43609:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
@@ -5843,7 +5843,7 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX512F-LABEL: PR43609:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpblendd {{.*#+}} xmm3 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
@@ -5869,7 +5869,7 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX512VL-LABEL: PR43609:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm3 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
@@ -5896,7 +5896,7 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
; AVX512DQ-LABEL: PR43609:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512DQ-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
+; AVX512DQ-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0
; AVX512DQ-NEXT: vcvtuqq2pd %zmm1, %zmm1
; AVX512DQ-NEXT: vmovapd {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
@@ -5909,7 +5909,7 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX512VLDQ-LABEL: PR43609:
; AVX512VLDQ: # %bb.0:
-; AVX512VLDQ-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
+; AVX512VLDQ-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm1, %xmm1
; AVX512VLDQ-NEXT: vmovapd {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
diff --git a/llvm/test/CodeGen/X86/vec_logical.ll b/llvm/test/CodeGen/X86/vec_logical.ll
index 12ee3a7336faa..87a8ab6d1615c 100644
--- a/llvm/test/CodeGen/X86/vec_logical.ll
+++ b/llvm/test/CodeGen/X86/vec_logical.ll
@@ -5,13 +5,13 @@
define void @t(<4 x float> %A) {
; SSE-LABEL: t:
; SSE: # %bb.0:
-; SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-NEXT: movaps %xmm0, 0
; SSE-NEXT: retl
;
; AVX-LABEL: t:
; AVX: # %bb.0:
-; AVX-NEXT: vxorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; AVX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX-NEXT: vmovaps %xmm0, 0
; AVX-NEXT: retl
%tmp1277 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %A
diff --git a/llvm/test/CodeGen/X86/vec_minmax_match.ll b/llvm/test/CodeGen/X86/vec_minmax_match.ll
index 526503ce4bfee..6334e6706d2ec 100644
--- a/llvm/test/CodeGen/X86/vec_minmax_match.ll
+++ b/llvm/test/CodeGen/X86/vec_minmax_match.ll
@@ -119,7 +119,7 @@ define <4 x i32> @smax_vec4(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @umax_vec1(<4 x i32> %x) {
; CHECK-LABEL: umax_vec1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
@@ -129,7 +129,7 @@ define <4 x i32> @umax_vec1(<4 x i32> %x) {
define <4 x i32> @umax_vec2(<4 x i32> %x) {
; CHECK-LABEL: umax_vec2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>, <4 x i32> %x
@@ -139,7 +139,7 @@ define <4 x i32> @umax_vec2(<4 x i32> %x) {
define <4 x i32> @umin_vec1(<4 x i32> %x) {
; CHECK-LABEL: umin_vec1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %x
@@ -149,7 +149,7 @@ define <4 x i32> @umin_vec1(<4 x i32> %x) {
define <4 x i32> @umin_vec2(<4 x i32> %x) {
; CHECK-LABEL: umin_vec2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
@@ -164,8 +164,8 @@ define <4 x i32> @umin_vec2(<4 x i32> %x) {
define <4 x i32> @clamp_signed1(<4 x i32> %x) {
; CHECK-LABEL: clamp_signed1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp2 = icmp slt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
%min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>
@@ -179,8 +179,8 @@ define <4 x i32> @clamp_signed1(<4 x i32> %x) {
define <4 x i32> @clamp_signed2(<4 x i32> %x) {
; CHECK-LABEL: clamp_signed2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp2 = icmp sgt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
%max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>
@@ -194,8 +194,8 @@ define <4 x i32> @clamp_signed2(<4 x i32> %x) {
define <4 x i32> @clamp_unsigned1(<4 x i32> %x) {
; CHECK-LABEL: clamp_unsigned1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp2 = icmp ult <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
%min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>
@@ -209,8 +209,8 @@ define <4 x i32> @clamp_unsigned1(<4 x i32> %x) {
define <4 x i32> @clamp_unsigned2(<4 x i32> %x) {
; CHECK-LABEL: clamp_unsigned2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%cmp2 = icmp ugt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
%max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>
@@ -224,7 +224,7 @@ define <4 x i32> @umin_not_ops(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%cmp = icmp ugt <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
diff --git a/llvm/test/CodeGen/X86/vec_partial.ll b/llvm/test/CodeGen/X86/vec_partial.ll
index f3c8369e78348..e0d74151ef48e 100644
--- a/llvm/test/CodeGen/X86/vec_partial.ll
+++ b/llvm/test/CodeGen/X86/vec_partial.ll
@@ -6,12 +6,12 @@
define <3 x float> @addf3(<3 x float> %x) {
; X86-LABEL: addf3:
; X86: # %bb.0: # %entry
-; X86-NEXT: addps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: addf3:
; X64: # %bb.0: # %entry
-; X64-NEXT: addps {{.*}}(%rip), %xmm0
+; X64-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
entry:
%add = fadd <3 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
diff --git a/llvm/test/CodeGen/X86/vec_reassociate.ll b/llvm/test/CodeGen/X86/vec_reassociate.ll
index 277f877cacf0c..a9473fff942c0 100644
--- a/llvm/test/CodeGen/X86/vec_reassociate.ll
+++ b/llvm/test/CodeGen/X86/vec_reassociate.ll
@@ -38,13 +38,13 @@ define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: mul_4i32:
; X86: # %bb.0:
; X86-NEXT: pmulld %xmm1, %xmm0
-; X86-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: mul_4i32:
; X64: # %bb.0:
; X64-NEXT: pmulld %xmm1, %xmm0
-; X64-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
%2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>
@@ -56,13 +56,13 @@ define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: mul_4i32_commute:
; X86: # %bb.0:
; X86-NEXT: pmulld %xmm1, %xmm0
-; X86-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: mul_4i32_commute:
; X64: # %bb.0:
; X64-NEXT: pmulld %xmm1, %xmm0
-; X64-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0
%2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1
@@ -74,13 +74,13 @@ define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: and_4i32:
; X86: # %bb.0:
; X86-NEXT: andps %xmm1, %xmm0
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: and_4i32:
; X64: # %bb.0:
; X64-NEXT: andps %xmm1, %xmm0
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
@@ -92,13 +92,13 @@ define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: and_4i32_commute:
; X86: # %bb.0:
; X86-NEXT: andps %xmm1, %xmm0
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: and_4i32_commute:
; X64: # %bb.0:
; X64-NEXT: andps %xmm1, %xmm0
-; X64-NEXT: andps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
@@ -110,13 +110,13 @@ define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: or_4i32:
; X86: # %bb.0:
; X86-NEXT: orps %xmm1, %xmm0
-; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: or_4i32:
; X64: # %bb.0:
; X64-NEXT: orps %xmm1, %xmm0
-; X64-NEXT: orps {{.*}}(%rip), %xmm0
+; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
@@ -128,13 +128,13 @@ define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: or_4i32_commute:
; X86: # %bb.0:
; X86-NEXT: orps %xmm1, %xmm0
-; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: or_4i32_commute:
; X64: # %bb.0:
; X64-NEXT: orps %xmm1, %xmm0
-; X64-NEXT: orps {{.*}}(%rip), %xmm0
+; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
@@ -146,13 +146,13 @@ define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: xor_4i32:
; X86: # %bb.0:
; X86-NEXT: xorps %xmm1, %xmm0
-; X86-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: xor_4i32:
; X64: # %bb.0:
; X64-NEXT: xorps %xmm1, %xmm0
-; X64-NEXT: xorps {{.*}}(%rip), %xmm0
+; X64-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
@@ -164,13 +164,13 @@ define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: xor_4i32_commute:
; X86: # %bb.0:
; X86-NEXT: xorps %xmm1, %xmm0
-; X86-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: xor_4i32_commute:
; X64: # %bb.0:
; X64-NEXT: xorps %xmm1, %xmm0
-; X64-NEXT: xorps {{.*}}(%rip), %xmm0
+; X64-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
%1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
diff --git a/llvm/test/CodeGen/X86/vec_setcc-2.ll b/llvm/test/CodeGen/X86/vec_setcc-2.ll
index fb377a251bc91..673bc9f150faa 100644
--- a/llvm/test/CodeGen/X86/vec_setcc-2.ll
+++ b/llvm/test/CodeGen/X86/vec_setcc-2.ll
@@ -213,8 +213,8 @@ define <8 x i1> @ugt_v8i16_splat(<8 x i16> %x) {
define <4 x i1> @ugt_v4i32_splat(<4 x i32> %x) {
; SSE2-LABEL: ugt_v4i32_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: ugt_v4i32_splat:
@@ -230,7 +230,7 @@ define <4 x i1> @ugt_v4i32_splat(<4 x i32> %x) {
define <2 x i1> @ugt_v2i64_splat(<2 x i64> %x) {
; SSE2-LABEL: ugt_v2i64_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259898,9223372039002259898]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -244,8 +244,8 @@ define <2 x i1> @ugt_v2i64_splat(<2 x i64> %x) {
;
; SSE41-LABEL: ugt_v2i64_splat:
; SSE41: ## %bb.0:
-; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pcmpgtq {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
%cmp = icmp ugt <2 x i64> %x, <i64 442, i64 442>
ret <2 x i1> %cmp
@@ -284,7 +284,7 @@ define <8 x i1> @uge_v8i16_splat(<8 x i16> %x) {
define <4 x i1> @uge_v4i32_splat(<4 x i32> %x) {
; SSE2-LABEL: uge_v4i32_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483606,2147483606,2147483606,2147483606]
; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
@@ -304,7 +304,7 @@ define <4 x i1> @uge_v4i32_splat(<4 x i32> %x) {
define <2 x i1> @uge_v2i64_splat(<2 x i64> %x) {
; SSE2-LABEL: uge_v2i64_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259898,9223372039002259898]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -320,7 +320,7 @@ define <2 x i1> @uge_v2i64_splat(<2 x i64> %x) {
;
; SSE41-LABEL: uge_v2i64_splat:
; SSE41: ## %bb.0:
-; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [9223372036854776250,9223372036854776250]
; SSE41-NEXT: pcmpgtq %xmm0, %xmm1
; SSE41-NEXT: pcmpeqd %xmm0, %xmm0
@@ -344,7 +344,7 @@ define <16 x i1> @ult_v16i8_splat(<16 x i8> %x) {
define <8 x i1> @ult_v8i16_splat(<8 x i16> %x) {
; SSE2-LABEL: ult_v8i16_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: psubusw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: psubusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -362,7 +362,7 @@ define <8 x i1> @ult_v8i16_splat(<8 x i16> %x) {
define <4 x i1> @ult_v4i32_splat(<4 x i32> %x) {
; SSE2-LABEL: ult_v4i32_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483606,2147483606,2147483606,2147483606]
; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
@@ -381,7 +381,7 @@ define <4 x i1> @ult_v4i32_splat(<4 x i32> %x) {
define <2 x i1> @ult_v2i64_splat(<2 x i64> %x) {
; SSE2-LABEL: ult_v2i64_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259898,9223372039002259898]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -395,7 +395,7 @@ define <2 x i1> @ult_v2i64_splat(<2 x i64> %x) {
;
; SSE41-LABEL: ult_v2i64_splat:
; SSE41: ## %bb.0:
-; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [9223372036854776250,9223372036854776250]
; SSE41-NEXT: pcmpgtq %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
@@ -418,7 +418,7 @@ define <16 x i1> @ule_v16i8_splat(<16 x i8> %x) {
define <8 x i1> @ule_v8i16_splat(<8 x i16> %x) {
; SSE2-LABEL: ule_v8i16_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: psubusw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: psubusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -436,8 +436,8 @@ define <8 x i1> @ule_v8i16_splat(<8 x i16> %x) {
define <4 x i1> @ule_v4i32_splat(<4 x i32> %x) {
; SSE2-LABEL: ule_v4i32_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -455,7 +455,7 @@ define <4 x i1> @ule_v4i32_splat(<4 x i32> %x) {
define <2 x i1> @ule_v2i64_splat(<2 x i64> %x) {
; SSE2-LABEL: ule_v2i64_splat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259898,9223372039002259898]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -471,8 +471,8 @@ define <2 x i1> @ule_v2i64_splat(<2 x i64> %x) {
;
; SSE41-LABEL: ule_v2i64_splat:
; SSE41: ## %bb.0:
-; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pcmpgtq {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
; SSE41-NEXT: pxor %xmm1, %xmm0
; SSE41-NEXT: retq
@@ -507,8 +507,8 @@ define <4 x i1> @ugt_v4i32_splat_maxval_simplify(<4 x i32> %x) {
define <4 x i1> @ugt_v4i32_nonsplat(<4 x i32> %x) {
; SSE2-LABEL: ugt_v4i32_nonsplat:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: ugt_v4i32_nonsplat:
@@ -524,7 +524,7 @@ define <4 x i1> @ugt_v4i32_nonsplat(<4 x i32> %x) {
define <4 x i1> @ugt_v4i32_splat_commute(<4 x i32> %x) {
; SSE2-LABEL: ugt_v4i32_splat_commute:
; SSE2: ## %bb.0:
-; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652,2147483652,2147483652]
; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/vec_shift4.ll b/llvm/test/CodeGen/X86/vec_shift4.ll
index e0428b185e5fd..bcef1d4d51b2b 100644
--- a/llvm/test/CodeGen/X86/vec_shift4.ll
+++ b/llvm/test/CodeGen/X86/vec_shift4.ll
@@ -6,7 +6,7 @@ define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
; X86-LABEL: shl1:
; X86: # %bb.0: # %entry
; X86-NEXT: pslld $23, %xmm1
-; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: cvttps2dq %xmm1, %xmm1
; X86-NEXT: pmulld %xmm1, %xmm0
; X86-NEXT: retl
@@ -14,7 +14,7 @@ define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
; X64-LABEL: shl1:
; X64: # %bb.0: # %entry
; X64-NEXT: pslld $23, %xmm1
-; X64-NEXT: paddd {{.*}}(%rip), %xmm1
+; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-NEXT: cvttps2dq %xmm1, %xmm1
; X64-NEXT: pmulld %xmm1, %xmm0
; X64-NEXT: retq
@@ -31,12 +31,12 @@ define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
; X86-NEXT: psllw $5, %xmm1
; X86-NEXT: movdqa %xmm0, %xmm3
; X86-NEXT: psllw $4, %xmm3
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X86-NEXT: movdqa %xmm2, %xmm3
; X86-NEXT: psllw $2, %xmm3
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
@@ -54,12 +54,12 @@ define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
; X64-NEXT: psllw $5, %xmm1
; X64-NEXT: movdqa %xmm0, %xmm3
; X64-NEXT: psllw $4, %xmm3
-; X64-NEXT: pand {{.*}}(%rip), %xmm3
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X64-NEXT: movdqa %xmm2, %xmm3
; X64-NEXT: psllw $2, %xmm3
-; X64-NEXT: pand {{.*}}(%rip), %xmm3
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; X64-NEXT: paddb %xmm1, %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: pblendvb %xmm0, %xmm3, %xmm2
diff --git a/llvm/test/CodeGen/X86/vec_smulo.ll b/llvm/test/CodeGen/X86/vec_smulo.ll
index 115183fbdeeba..49ee5cd98ef94 100644
--- a/llvm/test/CodeGen/X86/vec_smulo.ll
+++ b/llvm/test/CodeGen/X86/vec_smulo.ll
@@ -1434,7 +1434,7 @@ define <16 x i32> @smulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nou
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpackuswb %xmm2, %xmm0, %xmm2
; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
index 259c19c681512..b79c30a61b999 100644
--- a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
+++ b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
@@ -10,11 +10,11 @@ define i16 @test1(float %f) nounwind {
; X32-LABEL: test1:
; X32: ## %bb.0:
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: addss LCPI0_0, %xmm0
-; X32-NEXT: mulss LCPI0_1, %xmm0
+; X32-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: xorps %xmm1, %xmm1
; X32-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
-; X32-NEXT: minss LCPI0_2, %xmm0
+; X32-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: maxss %xmm1, %xmm0
; X32-NEXT: cvttss2si %xmm0, %eax
; X32-NEXT: ## kill: def $ax killed $ax killed $eax
@@ -22,11 +22,11 @@ define i16 @test1(float %f) nounwind {
;
; X64-LABEL: test1:
; X64: ## %bb.0:
-; X64-NEXT: addss {{.*}}(%rip), %xmm0
-; X64-NEXT: mulss {{.*}}(%rip), %xmm0
+; X64-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
-; X64-NEXT: minss {{.*}}(%rip), %xmm0
+; X64-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: maxss %xmm1, %xmm0
; X64-NEXT: cvttss2si %xmm0, %eax
; X64-NEXT: ## kill: def $ax killed $ax killed $eax
@@ -35,11 +35,11 @@ define i16 @test1(float %f) nounwind {
; X32_AVX1-LABEL: test1:
; X32_AVX1: ## %bb.0:
; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32_AVX1-NEXT: vaddss LCPI0_0, %xmm0, %xmm0
-; X32_AVX1-NEXT: vmulss LCPI0_1, %xmm0, %xmm0
+; X32_AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32_AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32_AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32_AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
-; X32_AVX1-NEXT: vminss LCPI0_2, %xmm0, %xmm0
+; X32_AVX1-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32_AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X32_AVX1-NEXT: vcvttss2si %xmm0, %eax
; X32_AVX1-NEXT: ## kill: def $ax killed $ax killed $eax
@@ -47,11 +47,11 @@ define i16 @test1(float %f) nounwind {
;
; X64_AVX1-LABEL: test1:
; X64_AVX1: ## %bb.0:
-; X64_AVX1-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
-; X64_AVX1-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; X64_AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64_AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64_AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64_AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
-; X64_AVX1-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
+; X64_AVX1-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64_AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X64_AVX1-NEXT: vcvttss2si %xmm0, %eax
; X64_AVX1-NEXT: ## kill: def $ax killed $ax killed $eax
@@ -60,11 +60,11 @@ define i16 @test1(float %f) nounwind {
; X32_AVX512-LABEL: test1:
; X32_AVX512: ## %bb.0:
; X32_AVX512-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32_AVX512-NEXT: vaddss LCPI0_0, %xmm0, %xmm0
-; X32_AVX512-NEXT: vmulss LCPI0_1, %xmm0, %xmm0
+; X32_AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32_AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32_AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32_AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
-; X32_AVX512-NEXT: vminss LCPI0_2, %xmm0, %xmm0
+; X32_AVX512-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32_AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32_AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X32_AVX512-NEXT: vcvttss2si %xmm0, %eax
@@ -73,11 +73,11 @@ define i16 @test1(float %f) nounwind {
;
; X64_AVX512-LABEL: test1:
; X64_AVX512: ## %bb.0:
-; X64_AVX512-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
-; X64_AVX512-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; X64_AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64_AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64_AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64_AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
-; X64_AVX512-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
+; X64_AVX512-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64_AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64_AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X64_AVX512-NEXT: vcvttss2si %xmm0, %eax
@@ -100,9 +100,9 @@ define i16 @test2(float %f) nounwind {
; X32-LABEL: test2:
; X32: ## %bb.0:
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: addss LCPI1_0, %xmm0
-; X32-NEXT: mulss LCPI1_1, %xmm0
-; X32-NEXT: minss LCPI1_2, %xmm0
+; X32-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: xorps %xmm1, %xmm1
; X32-NEXT: maxss %xmm1, %xmm0
; X32-NEXT: cvttss2si %xmm0, %eax
@@ -111,9 +111,9 @@ define i16 @test2(float %f) nounwind {
;
; X64-LABEL: test2:
; X64: ## %bb.0:
-; X64-NEXT: addss {{.*}}(%rip), %xmm0
-; X64-NEXT: mulss {{.*}}(%rip), %xmm0
-; X64-NEXT: minss {{.*}}(%rip), %xmm0
+; X64-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: minss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: maxss %xmm1, %xmm0
; X64-NEXT: cvttss2si %xmm0, %eax
@@ -123,9 +123,9 @@ define i16 @test2(float %f) nounwind {
; X32_AVX-LABEL: test2:
; X32_AVX: ## %bb.0:
; X32_AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32_AVX-NEXT: vaddss LCPI1_0, %xmm0, %xmm0
-; X32_AVX-NEXT: vmulss LCPI1_1, %xmm0, %xmm0
-; X32_AVX-NEXT: vminss LCPI1_2, %xmm0, %xmm0
+; X32_AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32_AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32_AVX-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X32_AVX-NEXT: vcvttss2si %xmm0, %eax
@@ -134,9 +134,9 @@ define i16 @test2(float %f) nounwind {
;
; X64_AVX-LABEL: test2:
; X64_AVX: ## %bb.0:
-; X64_AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
-; X64_AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
-; X64_AVX-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
+; X64_AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64_AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64_AVX-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X64_AVX-NEXT: vcvttss2si %xmm0, %eax
diff --git a/llvm/test/CodeGen/X86/vec_umulo.ll b/llvm/test/CodeGen/X86/vec_umulo.ll
index b46702410d05b..5e9497f78fc2d 100644
--- a/llvm/test/CodeGen/X86/vec_umulo.ll
+++ b/llvm/test/CodeGen/X86/vec_umulo.ll
@@ -1229,7 +1229,7 @@ define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nou
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX2-NEXT: vpmullw %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm2
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll b/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll
index 340177ec49ae0..23d22e75d1e9d 100644
--- a/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll
+++ b/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll
@@ -16,7 +16,7 @@ define <4 x float> @vec_fsub_zero(<4 x float> %x) {
define <4 x float> @vec_fneg(<4 x float> %x) {
; CHECK-LABEL: vec_fneg:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%sub = fsub <4 x float> zeroinitializer, %x
ret <4 x float> %sub
diff --git a/llvm/test/CodeGen/X86/vec_zero_cse.ll b/llvm/test/CodeGen/X86/vec_zero_cse.ll
index 7f20ddec3bfc0..8a78b0196ed53 100644
--- a/llvm/test/CodeGen/X86/vec_zero_cse.ll
+++ b/llvm/test/CodeGen/X86/vec_zero_cse.ll
@@ -21,8 +21,8 @@ define void @test1() {
;
; X64-LABEL: test1:
; X64: # %bb.0:
-; X64-NEXT: movq $0, {{.*}}(%rip)
-; X64-NEXT: movq $0, {{.*}}(%rip)
+; X64-NEXT: movq $0, M1(%rip)
+; X64-NEXT: movq $0, M2(%rip)
; X64-NEXT: retq
store <1 x i64> zeroinitializer, <1 x i64>* @M1
store <2 x i32> zeroinitializer, <2 x i32>* @M2
@@ -40,8 +40,8 @@ define void @test2() {
;
; X64-LABEL: test2:
; X64: # %bb.0:
-; X64-NEXT: movq $-1, {{.*}}(%rip)
-; X64-NEXT: movq $-1, {{.*}}(%rip)
+; X64-NEXT: movq $-1, M1(%rip)
+; X64-NEXT: movq $-1, M2(%rip)
; X64-NEXT: retq
store <1 x i64> < i64 -1 >, <1 x i64>* @M1
store <2 x i32> < i32 -1, i32 -1 >, <2 x i32>* @M2
@@ -59,8 +59,8 @@ define void @test3() {
; X64-LABEL: test3:
; X64: # %bb.0:
; X64-NEXT: xorps %xmm0, %xmm0
-; X64-NEXT: movaps %xmm0, {{.*}}(%rip)
-; X64-NEXT: movaps %xmm0, {{.*}}(%rip)
+; X64-NEXT: movaps %xmm0, S1(%rip)
+; X64-NEXT: movaps %xmm0, S2(%rip)
; X64-NEXT: retq
store <2 x i64> zeroinitializer, <2 x i64>* @S1
store <4 x i32> zeroinitializer, <4 x i32>* @S2
@@ -78,8 +78,8 @@ define void @test4() {
; X64-LABEL: test4:
; X64: # %bb.0:
; X64-NEXT: pcmpeqd %xmm0, %xmm0
-; X64-NEXT: movdqa %xmm0, {{.*}}(%rip)
-; X64-NEXT: movdqa %xmm0, {{.*}}(%rip)
+; X64-NEXT: movdqa %xmm0, S1(%rip)
+; X64-NEXT: movdqa %xmm0, S2(%rip)
; X64-NEXT: retq
store <2 x i64> < i64 -1, i64 -1>, <2 x i64>* @S1
store <4 x i32> < i32 -1, i32 -1, i32 -1, i32 -1 >, <4 x i32>* @S2
diff --git a/llvm/test/CodeGen/X86/vector-bitreverse.ll b/llvm/test/CodeGen/X86/vector-bitreverse.ll
index a5af0fa53bca1..4f73bdac52de1 100644
--- a/llvm/test/CodeGen/X86/vector-bitreverse.ll
+++ b/llvm/test/CodeGen/X86/vector-bitreverse.ll
@@ -58,7 +58,7 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind {
; XOP-LABEL: test_bitreverse_i8:
; XOP: # %bb.0:
; XOP-NEXT: vmovd %edi, %xmm0
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: vmovd %xmm0, %eax
; XOP-NEXT: # kill: def $al killed $al killed $eax
; XOP-NEXT: retq
@@ -211,7 +211,7 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind {
; XOP-LABEL: test_bitreverse_i16:
; XOP: # %bb.0:
; XOP-NEXT: vmovd %edi, %xmm0
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: vmovd %xmm0, %eax
; XOP-NEXT: # kill: def $ax killed $ax killed $eax
; XOP-NEXT: retq
@@ -382,7 +382,7 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
; XOP-LABEL: test_bitreverse_i32:
; XOP: # %bb.0:
; XOP-NEXT: vmovd %edi, %xmm0
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: vmovd %xmm0, %eax
; XOP-NEXT: retq
;
@@ -551,7 +551,7 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
; XOP-LABEL: test_bitreverse_i64:
; XOP: # %bb.0:
; XOP-NEXT: vmovq %rdi, %xmm0
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: vmovq %xmm0, %rax
; XOP-NEXT: retq
;
@@ -683,20 +683,20 @@ define <16 x i8> @test_bitreverse_v16i8(<16 x i8> %a) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $4, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlw $4, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -731,32 +731,32 @@ define <16 x i8> @test_bitreverse_v16i8(<16 x i8> %a) nounwind {
;
; XOP-LABEL: test_bitreverse_v16i8:
; XOP: # %bb.0:
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: retq
;
; GFNISSE-LABEL: test_bitreverse_v16i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: gf2p8affineqb $0, {{.*}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX-LABEL: test_bitreverse_v16i8:
; GFNIAVX: # %bb.0:
-; GFNIAVX-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX-NEXT: retq
;
; GFNIAVX2-LABEL: test_bitreverse_v16i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512F-LABEL: test_bitreverse_v16i8:
; GFNIAVX512F: # %bb.0:
-; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512F-NEXT: retq
;
; GFNIAVX512BW-LABEL: test_bitreverse_v16i8:
; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512BW-NEXT: retq
%b = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %a)
ret <16 x i8> %b
@@ -771,20 +771,20 @@ define <8 x i16> @test_bitreverse_v8i16(<8 x i16> %a) nounwind {
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $4, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlw $4, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -821,37 +821,37 @@ define <8 x i16> @test_bitreverse_v8i16(<8 x i16> %a) nounwind {
;
; XOP-LABEL: test_bitreverse_v8i16:
; XOP: # %bb.0:
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: retq
;
; GFNISSE-LABEL: test_bitreverse_v8i16:
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; GFNISSE-NEXT: gf2p8affineqb $0, {{.*}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX-LABEL: test_bitreverse_v8i16:
; GFNIAVX: # %bb.0:
; GFNIAVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; GFNIAVX-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX-NEXT: retq
;
; GFNIAVX2-LABEL: test_bitreverse_v8i16:
; GFNIAVX2: # %bb.0:
; GFNIAVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512F-LABEL: test_bitreverse_v8i16:
; GFNIAVX512F: # %bb.0:
; GFNIAVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512F-NEXT: retq
;
; GFNIAVX512BW-LABEL: test_bitreverse_v8i16:
; GFNIAVX512BW: # %bb.0:
; GFNIAVX512BW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512BW-NEXT: retq
%b = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %a)
ret <8 x i16> %b
@@ -871,20 +871,20 @@ define <4 x i32> @test_bitreverse_v4i32(<4 x i32> %a) nounwind {
; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $4, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlw $4, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -921,37 +921,37 @@ define <4 x i32> @test_bitreverse_v4i32(<4 x i32> %a) nounwind {
;
; XOP-LABEL: test_bitreverse_v4i32:
; XOP: # %bb.0:
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: retq
;
; GFNISSE-LABEL: test_bitreverse_v4i32:
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
-; GFNISSE-NEXT: gf2p8affineqb $0, {{.*}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX-LABEL: test_bitreverse_v4i32:
; GFNIAVX: # %bb.0:
; GFNIAVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
-; GFNIAVX-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX-NEXT: retq
;
; GFNIAVX2-LABEL: test_bitreverse_v4i32:
; GFNIAVX2: # %bb.0:
; GFNIAVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
-; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512F-LABEL: test_bitreverse_v4i32:
; GFNIAVX512F: # %bb.0:
; GFNIAVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
-; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512F-NEXT: retq
;
; GFNIAVX512BW-LABEL: test_bitreverse_v4i32:
; GFNIAVX512BW: # %bb.0:
; GFNIAVX512BW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512BW-NEXT: retq
%b = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %a)
ret <4 x i32> %b
@@ -973,20 +973,20 @@ define <2 x i64> @test_bitreverse_v2i64(<2 x i64> %a) nounwind {
; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $4, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlw $4, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -1023,37 +1023,37 @@ define <2 x i64> @test_bitreverse_v2i64(<2 x i64> %a) nounwind {
;
; XOP-LABEL: test_bitreverse_v2i64:
; XOP: # %bb.0:
-; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: retq
;
; GFNISSE-LABEL: test_bitreverse_v2i64:
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
-; GFNISSE-NEXT: gf2p8affineqb $0, {{.*}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX-LABEL: test_bitreverse_v2i64:
; GFNIAVX: # %bb.0:
; GFNIAVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
-; GFNIAVX-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX-NEXT: retq
;
; GFNIAVX2-LABEL: test_bitreverse_v2i64:
; GFNIAVX2: # %bb.0:
; GFNIAVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
-; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512F-LABEL: test_bitreverse_v2i64:
; GFNIAVX512F: # %bb.0:
; GFNIAVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
-; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512F-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512F-NEXT: retq
;
; GFNIAVX512BW-LABEL: test_bitreverse_v2i64:
; GFNIAVX512BW: # %bb.0:
; GFNIAVX512BW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip), %xmm0, %xmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX512BW-NEXT: retq
%b = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a)
ret <2 x i64> %b
@@ -2130,7 +2130,7 @@ define <64 x i8> @test_bitreverse_v64i8(<64 x i8> %a) nounwind {
;
; GFNIAVX512BW-LABEL: test_bitreverse_v64i8:
; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; GFNIAVX512BW-NEXT: retq
%b = call <64 x i8> @llvm.bitreverse.v64i8(<64 x i8> %a)
ret <64 x i8> %b
@@ -2469,7 +2469,7 @@ define <32 x i16> @test_bitreverse_v32i16(<32 x i16> %a) nounwind {
; GFNIAVX512BW-LABEL: test_bitreverse_v32i16:
; GFNIAVX512BW: # %bb.0:
; GFNIAVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14,17,16,19,18,21,20,23,22,25,24,27,26,29,28,31,30,33,32,35,34,37,36,39,38,41,40,43,42,45,44,47,46,49,48,51,50,53,52,55,54,57,56,59,58,61,60,63,62]
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; GFNIAVX512BW-NEXT: retq
%b = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
ret <32 x i16> %b
@@ -2825,7 +2825,7 @@ define <16 x i32> @test_bitreverse_v16i32(<16 x i32> %a) nounwind {
; GFNIAVX512BW-LABEL: test_bitreverse_v16i32:
; GFNIAVX512BW: # %bb.0:
; GFNIAVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12,19,18,17,16,23,22,21,20,27,26,25,24,31,30,29,28,35,34,33,32,39,38,37,36,43,42,41,40,47,46,45,44,51,50,49,48,55,54,53,52,59,58,57,56,63,62,61,60]
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; GFNIAVX512BW-NEXT: retq
%b = call <16 x i32> @llvm.bitreverse.v16i32(<16 x i32> %a)
ret <16 x i32> %b
@@ -3189,7 +3189,7 @@ define <8 x i64> @test_bitreverse_v8i64(<8 x i64> %a) nounwind {
; GFNIAVX512BW-LABEL: test_bitreverse_v8i64:
; GFNIAVX512BW: # %bb.0:
; GFNIAVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24,39,38,37,36,35,34,33,32,47,46,45,44,43,42,41,40,55,54,53,52,51,50,49,48,63,62,61,60,59,58,57,56]
-; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; GFNIAVX512BW-NEXT: retq
%b = call <8 x i64> @llvm.bitreverse.v8i64(<8 x i64> %a)
ret <8 x i64> %b
diff --git a/llvm/test/CodeGen/X86/vector-compare-simplify.ll b/llvm/test/CodeGen/X86/vector-compare-simplify.ll
index 289d7bde09359..f1a6a44228b94 100644
--- a/llvm/test/CodeGen/X86/vector-compare-simplify.ll
+++ b/llvm/test/CodeGen/X86/vector-compare-simplify.ll
@@ -26,7 +26,7 @@ define <4 x i32> @sge_min(<4 x i32> %x) {
define <4 x i32> @sgt_min(<4 x i32> %x) {
; CHECK-LABEL: sgt_min:
; CHECK: # %bb.0:
-; CHECK-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cmp = icmp sgt <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%r = sext <4 x i1> %cmp to <4 x i32>
@@ -36,7 +36,7 @@ define <4 x i32> @sgt_min(<4 x i32> %x) {
define <4 x i32> @sle_min(<4 x i32> %x) {
; CHECK-LABEL: sle_min:
; CHECK: # %bb.0:
-; CHECK-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retq
@@ -173,7 +173,7 @@ define <4 x i32> @uge_max(<4 x i32> %x) {
; CHECK-LABEL: uge_max:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
-; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647]
; CHECK-NEXT: pcmpgtd %xmm0, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm1
@@ -187,7 +187,7 @@ define <4 x i32> @uge_max(<4 x i32> %x) {
define <4 x i32> @slt_min_plus1(<4 x i32> %x) {
; CHECK-LABEL: slt_min_plus1:
; CHECK: # %bb.0:
-; CHECK-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cmp = icmp slt <4 x i32> %x, <i32 -2147483647, i32 -2147483647, i32 -2147483647, i32 -2147483647>
%r = sext <4 x i1> %cmp to <4 x i32>
@@ -210,7 +210,7 @@ define <4 x i32> @sge_min_plus1(<4 x i32> %x) {
define <4 x i32> @sgt_max_minus1(<4 x i32> %x) {
; CHECK-LABEL: sgt_max_minus1:
; CHECK: # %bb.0:
-; CHECK-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cmp = icmp sgt <4 x i32> %x, <i32 2147483646, i32 2147483646, i32 2147483646, i32 2147483646>
%r = sext <4 x i1> %cmp to <4 x i32>
@@ -220,7 +220,7 @@ define <4 x i32> @sgt_max_minus1(<4 x i32> %x) {
define <4 x i32> @sle_max_minus1(<4 x i32> %x) {
; CHECK-LABEL: sle_max_minus1:
; CHECK: # %bb.0:
-; CHECK-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retq
@@ -243,7 +243,7 @@ define <4 x i32> @ult_one(<4 x i32> %x) {
define <4 x i32> @uge_one(<4 x i32> %x) {
; CHECK-LABEL: uge_one:
; CHECK: # %bb.0:
-; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483649,2147483649,2147483649,2147483649]
; CHECK-NEXT: pcmpgtd %xmm0, %xmm1
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
@@ -268,8 +268,8 @@ define <4 x i32> @ugt_max_minus1(<4 x i32> %x) {
define <4 x i32> @ule_max_minus1(<4 x i32> %x) {
; CHECK-LABEL: ule_max_minus1:
; CHECK: # %bb.0:
-; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
-; CHECK-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retq
@@ -328,7 +328,7 @@ define <4 x i32> @uge_smin(<4 x i32> %x) {
define <4 x i32> @ne_smin(<4 x i32> %x) {
; CHECK-LABEL: ne_smin:
; CHECK: # %bb.0:
-; CHECK-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: retq
%cmp = icmp ne <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%r = sext <4 x i1> %cmp to <4 x i32>
diff --git a/llvm/test/CodeGen/X86/vector-ext-logic.ll b/llvm/test/CodeGen/X86/vector-ext-logic.ll
index bfaec98d07248..e1a9ef5fdbe7e 100644
--- a/llvm/test/CodeGen/X86/vector-ext-logic.ll
+++ b/llvm/test/CodeGen/X86/vector-ext-logic.ll
@@ -272,7 +272,7 @@ define <8 x i32> @bool_zext_and(<8 x i1> %x, <8 x i1> %y) {
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
@@ -285,7 +285,7 @@ define <8 x i32> @bool_zext_and(<8 x i1> %x, <8 x i1> %y) {
; AVX2-LABEL: bool_zext_and:
; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
@@ -300,7 +300,7 @@ define <8 x i32> @bool_zext_or(<8 x i1> %x, <8 x i1> %y) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: por %xmm1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
@@ -311,7 +311,7 @@ define <8 x i32> @bool_zext_or(<8 x i1> %x, <8 x i1> %y) {
; AVX2-LABEL: bool_zext_or:
; AVX2: # %bb.0:
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq
%xz = zext <8 x i1> %x to <8 x i32>
@@ -325,7 +325,7 @@ define <8 x i32> @bool_zext_xor(<8 x i1> %x, <8 x i1> %y) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
@@ -336,7 +336,7 @@ define <8 x i32> @bool_zext_xor(<8 x i1> %x, <8 x i1> %y) {
; AVX2-LABEL: bool_zext_xor:
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq
%xz = zext <8 x i1> %x to <8 x i32>
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
index d82003dfcd2ec..9841a42163897 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
@@ -149,7 +149,7 @@ define <4 x i32> @test_div7_4i32(<4 x i32> %a) nounwind {
define <8 x i16> @test_div7_8i16(<8 x i16> %a) nounwind {
; SSE-LABEL: test_div7_8i16:
; SSE: # %bb.0:
-; SSE-NEXT: pmulhw {{.*}}(%rip), %xmm0
+; SSE-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrlw $15, %xmm1
; SSE-NEXT: psraw $1, %xmm0
@@ -158,7 +158,7 @@ define <8 x i16> @test_div7_8i16(<8 x i16> %a) nounwind {
;
; AVX-LABEL: test_div7_8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsrlw $15, %xmm0, %xmm1
; AVX-NEXT: vpsraw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -184,11 +184,11 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrlw $2, %xmm1
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; SSE-NEXT: pxor %xmm2, %xmm1
; SSE-NEXT: psrlw $7, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: psubb %xmm2, %xmm0
; SSE-NEXT: retq
@@ -206,11 +206,11 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -218,17 +218,17 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-LABEL: test_div7_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vpsrlw $2, %xmm0, %xmm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
@@ -237,16 +237,16 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX512BW-LABEL: test_div7_16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vpsrlw $2, %xmm0, %xmm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX512BW-NEXT: vpxor %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
@@ -265,27 +265,27 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; SSE-NEXT: pmulhw {{.*}}(%rip), %xmm2
+; SSE-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: psrlw $8, %xmm2
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE-NEXT: pmulhw {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psrlw $8, %xmm1
; SSE-NEXT: packuswb %xmm2, %xmm1
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; SSE-NEXT: psraw $8, %xmm1
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psrlw $8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
; SSE-NEXT: psraw $8, %xmm2
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: psrlw $8, %xmm2
; SSE-NEXT: packuswb %xmm1, %xmm2
; SSE-NEXT: psrlw $7, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: paddb %xmm2, %xmm0
; SSE-NEXT: retq
;
@@ -293,44 +293,44 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-NEXT: vpsraw $8, %xmm1, %xmm1
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_divconstant_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
@@ -339,16 +339,16 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [2,2,1,2,3,1,2,3,3,2,1,3,2,1,1,2]
; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm2
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm2
; AVX512BW-NEXT: vpsravw %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsrlw $7, %xmm0, %xmm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -490,7 +490,7 @@ define <4 x i32> @test_rem7_4i32(<4 x i32> %a) nounwind {
; SSE41-NEXT: psrld $31, %xmm1
; SSE41-NEXT: psrad $2, %xmm2
; SSE41-NEXT: paddd %xmm1, %xmm2
-; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psubd %xmm2, %xmm0
; SSE41-NEXT: retq
;
@@ -506,7 +506,7 @@ define <4 x i32> @test_rem7_4i32(<4 x i32> %a) nounwind {
; AVX1-NEXT: vpsrld $31, %xmm1, %xmm2
; AVX1-NEXT: vpsrad $2, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -539,17 +539,17 @@ define <8 x i16> @test_rem7_8i16(<8 x i16> %a) nounwind {
; SSE-NEXT: psrlw $15, %xmm2
; SSE-NEXT: psraw $1, %xmm1
; SSE-NEXT: paddw %xmm2, %xmm1
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_rem7_8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsrlw $15, %xmm1, %xmm2
; AVX-NEXT: vpsraw $1, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%res = srem <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -572,16 +572,16 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: paddb %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: psrlw $2, %xmm2
-; SSE-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; SSE-NEXT: pxor %xmm3, %xmm2
; SSE-NEXT: psrlw $7, %xmm1
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: paddb %xmm2, %xmm1
; SSE-NEXT: psubb %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: psllw $3, %xmm2
-; SSE-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: psubb %xmm2, %xmm1
; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: retq
@@ -599,15 +599,15 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpsllw $3, %xmm1, %xmm2
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -615,21 +615,21 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-LABEL: test_rem7_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsrlw $2, %xmm1, %xmm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %xmm3, %xmm2, %xmm2
; AVX2NOBW-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsllw $3, %xmm1, %xmm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
@@ -638,20 +638,20 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX512BW-LABEL: test_rem7_16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm1
; AVX512BW-NEXT: vpsrlw $2, %xmm1, %xmm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX512BW-NEXT: vpxor %xmm3, %xmm2, %xmm2
; AVX512BW-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX512BW-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512BW-NEXT: vpsllw $3, %xmm1, %xmm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
@@ -670,10 +670,10 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
-; SSE2-NEXT: pmulhw {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; SSE2-NEXT: pmulhw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: packuswb %xmm1, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,0,0,255,0,0,255,255,0,0,255,0,0,0,255]
@@ -682,24 +682,24 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: psraw $8, %xmm2
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
; SSE2-NEXT: psraw $8, %xmm3
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psrlw $8, %xmm3
; SSE2-NEXT: packuswb %xmm2, %xmm3
; SSE2-NEXT: psrlw $7, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: paddb %xmm3, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; SSE2-NEXT: pand %xmm3, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pand %xmm3, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
@@ -710,10 +710,10 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
-; SSE41-NEXT: pmulhw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: psrlw $8, %xmm1
; SSE41-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; SSE41-NEXT: pmulhw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm1, %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [255,255,0,0,255,0,0,255,255,0,0,255,0,0,0,255]
@@ -722,23 +722,23 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE41-NEXT: psraw $8, %xmm2
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
; SSE41-NEXT: psraw $8, %xmm3
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: psrlw $8, %xmm3
; SSE41-NEXT: packuswb %xmm2, %xmm3
; SSE41-NEXT: psrlw $7, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: paddb %xmm3, %xmm1
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; SSE41-NEXT: pand %xmm3, %xmm1
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: pand %xmm3, %xmm2
; SSE41-NEXT: packuswb %xmm1, %xmm2
; SSE41-NEXT: psubb %xmm2, %xmm0
@@ -748,32 +748,32 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm2
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX1-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -782,23 +782,23 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-LABEL: test_remconstant_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX2NOBW-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpmovsxbw %xmm1, %ymm2
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2NOBW-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
; AVX2NOBW-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -809,19 +809,19 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [2,2,1,2,3,1,2,3,3,2,1,3,2,1,1,2]
; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm2
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm3
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX512BW-NEXT: vpaddb %xmm3, %xmm2, %xmm2
; AVX512BW-NEXT: vpmovsxbw %xmm2, %ymm3
; AVX512BW-NEXT: vpsravw %zmm1, %zmm3, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsrlw $7, %xmm2, %xmm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512BW-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index 30e7949535700..17dc0778d6830 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -146,7 +146,7 @@ define <16 x i16> @test_div7_16i16(<16 x i16> %a) nounwind {
;
; AVX2-LABEL: test_div7_16i16:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpmulhw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $15, %ymm0, %ymm1
; AVX2-NEXT: vpsraw $1, %ymm0, %ymm0
; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
@@ -210,11 +210,11 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2NOBW-NEXT: vpsrlw $2, %ymm0, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $7, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX2NOBW-NEXT: retq
@@ -222,16 +222,16 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX512BW-LABEL: test_div7_32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX512BW-NEXT: vpxor %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $7, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX512BW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX512BW-NEXT: retq
@@ -249,22 +249,22 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm3
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
; AVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpsrlw $7, %xmm1, %xmm1
@@ -272,20 +272,20 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm1, %xmm4, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0
@@ -298,40 +298,40 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
-; AVX2NOBW-NEXT: vpmulhw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
-; AVX2NOBW-NEXT: vpmulhw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm1 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2NOBW-NEXT: vpsraw $8, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
; AVX2NOBW-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpackuswb %ymm1, %ymm2, %ymm1
; AVX2NOBW-NEXT: vpsrlw $7, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2NOBW-NEXT: retq
;
; AVX512BW-LABEL: test_divconstant_32i8:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm0
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpsrlw $7, %ymm0, %ymm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm0
-; AVX512BW-NEXT: vpsravw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: retq
@@ -529,11 +529,11 @@ define <16 x i16> @test_rem7_16i16(<16 x i16> %a) nounwind {
;
; AVX2-LABEL: test_rem7_16i16:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpmulhw {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpsrlw $15, %ymm1, %ymm2
; AVX2-NEXT: vpsraw $1, %ymm1, %ymm1
; AVX2-NEXT: vpaddw %ymm2, %ymm1, %ymm1
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpsubw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
%res = srem <16 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -604,15 +604,15 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $2, %ymm1, %ymm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} ymm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %ymm3, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $7, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsllw $3, %ymm1, %ymm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX2NOBW-NEXT: retq
@@ -620,20 +620,20 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX512BW-LABEL: test_rem7_32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm0, %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $2, %ymm1, %ymm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX512BW-NEXT: vpxor %ymm3, %ymm2, %ymm2
; AVX512BW-NEXT: vpsrlw $7, %ymm1, %ymm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX512BW-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512BW-NEXT: vpsllw $3, %ymm1, %ymm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: retq
@@ -651,22 +651,22 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm3
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm2
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm5
; AVX1-NEXT: vpaddb %xmm5, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm6 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpsraw $8, %xmm6, %xmm6
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm6, %xmm6
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6, %xmm6
; AVX1-NEXT: vpsrlw $8, %xmm6, %xmm6
; AVX1-NEXT: vpackuswb %xmm5, %xmm6, %xmm5
; AVX1-NEXT: vpsrlw $7, %xmm3, %xmm3
@@ -674,39 +674,39 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm3, %xmm5, %xmm5
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm7
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm7
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm3, %xmm7, %xmm7
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = xmm5[0],zero,xmm5[1],zero,xmm5[2],zero,xmm5[3],zero,xmm5[4],zero,xmm5[5],zero,xmm5[6],zero,xmm5[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpand %xmm3, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm7, %xmm5, %xmm5
; AVX1-NEXT: vpsubb %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpackuswb %xmm5, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm2, %xmm5, %xmm2
; AVX1-NEXT: vpsrlw $7, %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm6, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -717,32 +717,32 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
-; AVX2NOBW-NEXT: vpmulhw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
-; AVX2NOBW-NEXT: vpmulhw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
; AVX2NOBW-NEXT: vpaddb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX2NOBW-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
; AVX2NOBW-NEXT: vpsraw $8, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpsrlw $7, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} ymm3 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX2NOBW-NEXT: vpand %ymm3, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
@@ -750,20 +750,20 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
;
; AVX512BW-LABEL: test_remconstant_32i8:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm2
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX512BW-NEXT: vpsrlw $7, %ymm1, %ymm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpmovsxbw %ymm1, %zmm1
-; AVX512BW-NEXT: vpsravw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index c5d45e1258e6d..7a9a468122f6b 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -117,7 +117,7 @@ define <32 x i16> @test_div7_32i16(<32 x i16> %a) nounwind {
;
; AVX512BW-LABEL: test_div7_32i16:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpmulhw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $15, %zmm0, %zmm1
; AVX512BW-NEXT: vpsraw $1, %zmm0, %zmm0
; AVX512BW-NEXT: vpaddw %zmm1, %zmm0, %zmm0
@@ -182,9 +182,9 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm1
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpternlogq $108, {{.*}}(%rip), %zmm2, %zmm1
+; AVX512BW-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm1
; AVX512BW-NEXT: vpsrlw $7, %zmm0, %zmm0
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsubb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: retq
@@ -202,22 +202,22 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15],ymm2[24],ymm1[24],ymm2[25],ymm1[25],ymm2[26],ymm1[26],ymm2[27],ymm1[27],ymm2[28],ymm1[28],ymm2[29],ymm1[29],ymm2[30],ymm1[30],ymm2[31],ymm1[31]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[16],ymm1[16],ymm2[17],ymm1[17],ymm2[18],ymm1[18],ymm2[19],ymm1[19],ymm2[20],ymm1[20],ymm2[21],ymm1[21],ymm2[22],ymm1[22],ymm2[23],ymm1[23]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512F-NEXT: vpackuswb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm3
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3
; AVX512F-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-NEXT: vpaddb %ymm4, %ymm1, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpsraw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm1
@@ -225,20 +225,20 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vpaddb %ymm1, %ymm4, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[16],ymm0[16],ymm2[17],ymm0[17],ymm2[18],ymm0[18],ymm2[19],ymm0[19],ymm2[20],ymm0[20],ymm2[21],ymm0[21],ymm2[22],ymm0[22],ymm2[23],ymm0[23]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
; AVX512F-NEXT: vpsraw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm0
@@ -251,25 +251,25 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[12],zmm0[12],zmm1[13],zmm0[13],zmm1[14],zmm0[14],zmm1[15],zmm0[15],zmm1[24],zmm0[24],zmm1[25],zmm0[25],zmm1[26],zmm0[26],zmm1[27],zmm0[27],zmm1[28],zmm0[28],zmm1[29],zmm0[29],zmm1[30],zmm0[30],zmm1[31],zmm0[31],zmm1[40],zmm0[40],zmm1[41],zmm0[41],zmm1[42],zmm0[42],zmm1[43],zmm0[43],zmm1[44],zmm0[44],zmm1[45],zmm0[45],zmm1[46],zmm0[46],zmm1[47],zmm0[47],zmm1[56],zmm0[56],zmm1[57],zmm0[57],zmm1[58],zmm0[58],zmm1[59],zmm0[59],zmm1[60],zmm0[60],zmm1[61],zmm0[61],zmm1[62],zmm0[62],zmm1[63],zmm0[63]
-; AVX512BW-NEXT: vpmulhw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[16],zmm0[16],zmm1[17],zmm0[17],zmm1[18],zmm0[18],zmm1[19],zmm0[19],zmm1[20],zmm0[20],zmm1[21],zmm0[21],zmm1[22],zmm0[22],zmm1[23],zmm0[23],zmm1[32],zmm0[32],zmm1[33],zmm0[33],zmm1[34],zmm0[34],zmm1[35],zmm0[35],zmm1[36],zmm0[36],zmm1[37],zmm0[37],zmm1[38],zmm0[38],zmm1[39],zmm0[39],zmm1[48],zmm0[48],zmm1[49],zmm0[49],zmm1[50],zmm0[50],zmm1[51],zmm0[51],zmm1[52],zmm0[52],zmm1[53],zmm0[53],zmm1[54],zmm0[54],zmm1[55],zmm0[55]
-; AVX512BW-NEXT: vpmulhw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm1 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpsraw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm2 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
; AVX512BW-NEXT: vpsraw $8, %zmm2, %zmm2
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpackuswb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpsrlw $7, %zmm0, %zmm0
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: retq
%res = sdiv <64 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
@@ -400,7 +400,7 @@ define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind {
; AVX-NEXT: vpsrld $31, %zmm1, %zmm2
; AVX-NEXT: vpsrad $2, %zmm1, %zmm1
; AVX-NEXT: vpaddd %zmm2, %zmm1, %zmm1
-; AVX-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm1, %zmm1
+; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1
; AVX-NEXT: vpsubd %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = srem <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
@@ -431,11 +431,11 @@ define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind {
;
; AVX512BW-LABEL: test_rem7_32i16:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpmulhw {{.*}}(%rip), %zmm0, %zmm1
+; AVX512BW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
; AVX512BW-NEXT: vpsrlw $15, %zmm1, %zmm2
; AVX512BW-NEXT: vpsraw $1, %zmm1, %zmm1
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = srem <32 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -507,13 +507,13 @@ define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm2
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpternlogq $108, {{.*}}(%rip), %zmm3, %zmm2
+; AVX512BW-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm2
; AVX512BW-NEXT: vpsrlw $7, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpsubb %zmm3, %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $3, %zmm1, %zmm2
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
@@ -531,22 +531,22 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm4
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8],ymm4[8],ymm1[9],ymm4[9],ymm1[10],ymm4[10],ymm1[11],ymm4[11],ymm1[12],ymm4[12],ymm1[13],ymm4[13],ymm1[14],ymm4[14],ymm1[15],ymm4[15],ymm1[24],ymm4[24],ymm1[25],ymm4[25],ymm1[26],ymm4[26],ymm1[27],ymm4[27],ymm1[28],ymm4[28],ymm1[29],ymm4[29],ymm1[30],ymm4[30],ymm1[31],ymm4[31]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm1[0],ymm4[0],ymm1[1],ymm4[1],ymm1[2],ymm4[2],ymm1[3],ymm4[3],ymm1[4],ymm4[4],ymm1[5],ymm4[5],ymm1[6],ymm4[6],ymm1[7],ymm4[7],ymm1[16],ymm4[16],ymm1[17],ymm4[17],ymm1[18],ymm4[18],ymm1[19],ymm4[19],ymm1[20],ymm4[20],ymm1[21],ymm4[21],ymm1[22],ymm4[22],ymm1[23],ymm4[23]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpackuswb %ymm2, %ymm3, %ymm3
-; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm2
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
; AVX512F-NEXT: vextracti64x4 $1, %zmm2, %ymm5
; AVX512F-NEXT: vpaddb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm6 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
; AVX512F-NEXT: vpsraw $8, %ymm6, %ymm6
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm6, %ymm6
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6
; AVX512F-NEXT: vpsrlw $8, %ymm6, %ymm6
; AVX512F-NEXT: vpackuswb %ymm5, %ymm6, %ymm5
; AVX512F-NEXT: vpsrlw $7, %ymm3, %ymm3
@@ -554,39 +554,39 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
; AVX512F-NEXT: vpaddb %ymm3, %ymm5, %ymm5
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm7
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm7
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-NEXT: vpand %ymm3, %ymm7, %ymm7
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm5[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpand %ymm3, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm7, %ymm5, %ymm5
; AVX512F-NEXT: vpsubb %ymm5, %ymm4, %ymm4
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
-; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512F-NEXT: vpackuswb %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vpaddb %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; AVX512F-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm2, %ymm5, %ymm2
; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1
; AVX512F-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsubb %ymm1, %ymm0, %ymm0
@@ -597,32 +597,32 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[12],zmm0[12],zmm1[13],zmm0[13],zmm1[14],zmm0[14],zmm1[15],zmm0[15],zmm1[24],zmm0[24],zmm1[25],zmm0[25],zmm1[26],zmm0[26],zmm1[27],zmm0[27],zmm1[28],zmm0[28],zmm1[29],zmm0[29],zmm1[30],zmm0[30],zmm1[31],zmm0[31],zmm1[40],zmm0[40],zmm1[41],zmm0[41],zmm1[42],zmm0[42],zmm1[43],zmm0[43],zmm1[44],zmm0[44],zmm1[45],zmm0[45],zmm1[46],zmm0[46],zmm1[47],zmm0[47],zmm1[56],zmm0[56],zmm1[57],zmm0[57],zmm1[58],zmm0[58],zmm1[59],zmm0[59],zmm1[60],zmm0[60],zmm1[61],zmm0[61],zmm1[62],zmm0[62],zmm1[63],zmm0[63]
-; AVX512BW-NEXT: vpmulhw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[16],zmm0[16],zmm1[17],zmm0[17],zmm1[18],zmm0[18],zmm1[19],zmm0[19],zmm1[20],zmm0[20],zmm1[21],zmm0[21],zmm1[22],zmm0[22],zmm1[23],zmm0[23],zmm1[32],zmm0[32],zmm1[33],zmm0[33],zmm1[34],zmm0[34],zmm1[35],zmm0[35],zmm1[36],zmm0[36],zmm1[37],zmm0[37],zmm1[38],zmm0[38],zmm1[39],zmm0[39],zmm1[48],zmm0[48],zmm1[49],zmm0[49],zmm1[50],zmm0[50],zmm1[51],zmm0[51],zmm1[52],zmm0[52],zmm1[53],zmm0[53],zmm1[54],zmm0[54],zmm1[55],zmm0[55]
-; AVX512BW-NEXT: vpmulhw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm2
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
; AVX512BW-NEXT: vpaddb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
; AVX512BW-NEXT: vpsraw $8, %zmm2, %zmm2
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm3 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
; AVX512BW-NEXT: vpsraw $8, %zmm3, %zmm3
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm3, %zmm2
; AVX512BW-NEXT: vpsrlw $7, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512BW-NEXT: vpandq %zmm3, %zmm2, %zmm2
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpandq %zmm3, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
index f5fd239223424..365e8fe1ff5a5 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
@@ -153,7 +153,7 @@ define <8 x i16> @test_div7_8i16(<8 x i16> %a) nounwind {
;
; AVX-LABEL: test_div7_8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -179,10 +179,10 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: packuswb %xmm2, %xmm4
; SSE2-NEXT: psubb %xmm4, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: paddb %xmm4, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: test_div7_16i8:
@@ -199,10 +199,10 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: packuswb %xmm2, %xmm3
; SSE41-NEXT: psubb %xmm3, %xmm0
; SSE41-NEXT: psrlw $1, %xmm0
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $2, %xmm0
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: test_div7_16i8:
@@ -218,40 +218,40 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_div7_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
;
; AVX512BW-LABEL: test_div7_16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpsrlw $1, %xmm0, %xmm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%res = udiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
@@ -268,33 +268,33 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psrlw $8, %xmm3
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psrlw $8, %xmm3
; SSE2-NEXT: packuswb %xmm2, %xmm3
; SSE2-NEXT: psubb %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: paddb %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: retq
@@ -309,7 +309,7 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: psllw $7, %xmm3
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm2[1,2,3,4,5,6,7]
; SSE41-NEXT: psrlw $8, %xmm3
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: psrlw $8, %xmm3
; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
@@ -317,23 +317,23 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: psllw $7, %xmm4
; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm2[0,1,2,3,4,5,6],xmm4[7]
; SSE41-NEXT: psrlw $8, %xmm4
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm4
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: psrlw $8, %xmm4
; SSE41-NEXT: packuswb %xmm3, %xmm4
; SSE41-NEXT: psubb %xmm4, %xmm0
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm0, %xmm2
; SSE41-NEXT: paddb %xmm4, %xmm2
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
; SSE41-NEXT: packuswb %xmm2, %xmm0
; SSE41-NEXT: retq
@@ -346,30 +346,30 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsllw $7, %xmm3, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3,4,5,6,7]
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX1-NEXT: vpsllw $7, %xmm4, %xmm4
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6],xmm4[7]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -377,21 +377,21 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-LABEL: test_divconstant_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2NOBW-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
@@ -403,12 +403,12 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0]
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm2, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
@@ -559,7 +559,7 @@ define <4 x i32> @test_rem7_4i32(<4 x i32> %a) nounwind {
; SSE41-NEXT: psrld $1, %xmm1
; SSE41-NEXT: paddd %xmm2, %xmm1
; SSE41-NEXT: psrld $2, %xmm1
-; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: psubd %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -575,7 +575,7 @@ define <4 x i32> @test_rem7_4i32(<4 x i32> %a) nounwind {
; AVX1-NEXT: vpsrld $1, %xmm2, %xmm2
; AVX1-NEXT: vpaddd %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsrld $2, %xmm1, %xmm1
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -609,18 +609,18 @@ define <8 x i16> @test_rem7_8i16(<8 x i16> %a) nounwind {
; SSE-NEXT: psrlw $1, %xmm2
; SSE-NEXT: paddw %xmm1, %xmm2
; SSE-NEXT: psrlw $2, %xmm2
-; SSE-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: psubw %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_rem7_8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm2
; AVX-NEXT: vpsrlw $1, %xmm2, %xmm2
; AVX-NEXT: vpaddw %xmm1, %xmm2, %xmm1
; AVX-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%res = urem <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -644,13 +644,13 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psubb %xmm4, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: paddb %xmm4, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $3, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psubb %xmm2, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
@@ -671,13 +671,13 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psubb %xmm3, %xmm1
; SSE41-NEXT: psrlw $1, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: paddb %xmm3, %xmm1
; SSE41-NEXT: psrlw $2, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psllw $3, %xmm2
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psubb %xmm2, %xmm1
; SSE41-NEXT: paddb %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
@@ -696,12 +696,12 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm2
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsllw $3, %xmm1, %xmm2
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
@@ -709,18 +709,18 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-LABEL: test_rem7_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm2
; AVX2NOBW-NEXT: vpsrlw $1, %xmm2, %xmm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX2NOBW-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsllw $3, %xmm1, %xmm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
@@ -729,17 +729,17 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX512BW-LABEL: test_rem7_16i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm2
; AVX512BW-NEXT: vpsrlw $1, %xmm2, %xmm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512BW-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX512BW-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-NEXT: vpsllw $3, %xmm1, %xmm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
@@ -758,39 +758,39 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psrlw $8, %xmm3
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psrlw $8, %xmm3
; SSE2-NEXT: packuswb %xmm2, %xmm3
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psubb %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm4
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: psrlw $8, %xmm4
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: packuswb %xmm4, %xmm2
; SSE2-NEXT: paddb %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psrlw $8, %xmm3
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255]
; SSE2-NEXT: pand %xmm4, %xmm3
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
-; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pand %xmm4, %xmm2
; SSE2-NEXT: packuswb %xmm3, %xmm2
; SSE2-NEXT: psubb %xmm2, %xmm0
@@ -806,7 +806,7 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: psllw $7, %xmm3
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm2[1,2,3,4,5,6,7]
; SSE41-NEXT: psrlw $8, %xmm3
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: psrlw $8, %xmm3
; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
@@ -814,29 +814,29 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: psllw $7, %xmm4
; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm2[0,1,2,3,4,5,6],xmm4[7]
; SSE41-NEXT: psrlw $8, %xmm4
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm4
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: psrlw $8, %xmm4
; SSE41-NEXT: packuswb %xmm3, %xmm4
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psubb %xmm4, %xmm3
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15]
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: psrlw $8, %xmm3
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm3, %xmm2
; SSE41-NEXT: paddb %xmm4, %xmm2
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
; SSE41-NEXT: pand %xmm1, %xmm2
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: psrlw $8, %xmm3
-; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: pand %xmm1, %xmm3
; SSE41-NEXT: packuswb %xmm2, %xmm3
; SSE41-NEXT: psubb %xmm3, %xmm0
@@ -850,35 +850,35 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsllw $7, %xmm3, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3,4,5,6,7]
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX1-NEXT: vpsllw $7, %xmm4, %xmm4
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6],xmm4[7]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm3
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -887,24 +887,24 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-LABEL: test_remconstant_16i8:
; AVX2NOBW: # %bb.0:
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm2
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2NOBW-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
; AVX2NOBW-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -916,19 +916,19 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0]
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm2, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm2
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpaddb %xmm1, %xmm2, %xmm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [2,0,1,3,3,3,2,2,2,2,3,3,3,1,1,2]
; AVX512BW-NEXT: vpsrlvw %zmm2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
index dbe8ed2f6ea54..56a2f7f69bb3f 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
@@ -151,7 +151,7 @@ define <16 x i16> @test_div7_16i16(<16 x i16> %a) nounwind {
;
; AVX2-LABEL: test_div7_16i16:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpmulhuw {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpsubw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0
; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
@@ -211,24 +211,24 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: retq
;
; AVX512BW-LABEL: test_div7_32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpsrlw $1, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: retq
%res = udiv <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %res
@@ -248,30 +248,30 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsllw $7, %xmm4, %xmm4
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm4[0],xmm3[1,2,3,4,5,6,7]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0],xmm4[1,2,3,4,5,6,7]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsubb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
; AVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
@@ -279,30 +279,30 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsllw $7, %xmm4, %xmm4
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6],xmm4[7]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5,6],xmm5[7]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
@@ -315,28 +315,28 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} ymm3 = [256,256,256,256,256,256,256,128,128,256,256,256,256,256,256,256]
; AVX2NOBW-NEXT: vpmullw %ymm3, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
; AVX2NOBW-NEXT: vpmullw %ymm3, %ymm4, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX2NOBW-NEXT: retq
@@ -344,18 +344,18 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX512BW-LABEL: test_divconstant_32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm1, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: retq
%res = udiv <32 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
@@ -562,12 +562,12 @@ define <16 x i16> @test_rem7_16i16(<16 x i16> %a) nounwind {
;
; AVX2-LABEL: test_rem7_16i16:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpmulhuw {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpsubw %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vpsrlw $1, %ymm2, %ymm2
; AVX2-NEXT: vpaddw %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpsrlw $2, %ymm1, %ymm1
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpsubw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
%res = urem <16 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -633,12 +633,12 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm2
; AVX2NOBW-NEXT: vpsrlw $1, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2NOBW-NEXT: vpsrlw $2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsllw $3, %ymm1, %ymm2
-; AVX2NOBW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX2NOBW-NEXT: retq
@@ -646,17 +646,17 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX512BW-LABEL: test_rem7_32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm2
; AVX512BW-NEXT: vpsrlw $1, %ymm2, %ymm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX512BW-NEXT: vpsrlw $2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsllw $3, %ymm1, %ymm2
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: retq
@@ -678,35 +678,35 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsllw $7, %xmm4, %xmm4
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0],xmm2[1,2,3,4,5,6,7]
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0],xmm4[1,2,3,4,5,6,7]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm2, %xmm4, %xmm2
; AVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm4
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vpaddb %xmm2, %xmm4, %xmm4
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm5
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm2, %xmm5, %xmm5
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vpsubb %xmm4, %xmm3, %xmm3
@@ -715,34 +715,34 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5,6],xmm5[7]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm6 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX1-NEXT: vpsllw $7, %xmm6, %xmm6
; AVX1-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0,1,2,3,4,5,6],xmm6[7]
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpsubb %xmm4, %xmm0, %xmm5
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm5[8],xmm1[8],xmm5[9],xmm1[9],xmm5[10],xmm1[10],xmm5[11],xmm1[11],xmm5[12],xmm1[12],xmm5[13],xmm1[13],xmm5[14],xmm1[14],xmm5[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm6, %xmm6
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6, %xmm6
; AVX1-NEXT: vpsrlw $8, %xmm6, %xmm6
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = xmm5[0],zero,xmm5[1],zero,xmm5[2],zero,xmm5[3],zero,xmm5[4],zero,xmm5[5],zero,xmm5[6],zero,xmm5[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm6, %xmm5, %xmm5
; AVX1-NEXT: vpaddb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm2
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
@@ -756,33 +756,33 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} ymm3 = [256,256,256,256,256,256,256,128,128,256,256,256,256,256,256,256]
; AVX2NOBW-NEXT: vpmullw %ymm3, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
; AVX2NOBW-NEXT: vpmullw %ymm3, %ymm4, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm0, %ymm3
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm3[8],ymm1[8],ymm3[9],ymm1[9],ymm3[10],ymm1[10],ymm3[11],ymm1[11],ymm3[12],ymm1[12],ymm3[13],ymm1[13],ymm3[14],ymm1[14],ymm3[15],ymm1[15],ymm3[24],ymm1[24],ymm3[25],ymm1[25],ymm3[26],ymm1[26],ymm3[27],ymm1[27],ymm3[28],ymm1[28],ymm3[29],ymm1[29],ymm3[30],ymm1[30],ymm3[31],ymm1[31]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX2NOBW-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm3[0],ymm1[0],ymm3[1],ymm1[1],ymm3[2],ymm1[2],ymm3[3],ymm1[3],ymm3[4],ymm1[4],ymm3[5],ymm1[5],ymm3[6],ymm1[6],ymm3[7],ymm1[7],ymm3[16],ymm1[16],ymm3[17],ymm1[17],ymm3[18],ymm1[18],ymm3[19],ymm1[19],ymm3[20],ymm1[20],ymm3[21],ymm1[21],ymm3[22],ymm1[22],ymm3[23],ymm1[23]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm4, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpaddb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15],ymm2[24],ymm1[24],ymm2[25],ymm1[25],ymm2[26],ymm1[26],ymm2[27],ymm1[27],ymm2[28],ymm1[28],ymm2[29],ymm1[29],ymm2[30],ymm1[30],ymm2[31],ymm1[31]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2NOBW-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX2NOBW-NEXT: vpand %ymm4, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[16],ymm1[16],ymm2[17],ymm1[17],ymm2[18],ymm1[18],ymm2[19],ymm1[19],ymm2[20],ymm1[20],ymm2[21],ymm1[21],ymm2[22],ymm1[22],ymm2[23],ymm1[23]
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2NOBW-NEXT: vpand %ymm4, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpackuswb %ymm3, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
@@ -791,19 +791,19 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX512BW-LABEL: test_remconstant_32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm1, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm2
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm2 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero,ymm2[16],zero,ymm2[17],zero,ymm2[18],zero,ymm2[19],zero,ymm2[20],zero,ymm2[21],zero,ymm2[22],zero,ymm2[23],zero,ymm2[24],zero,ymm2[25],zero,ymm2[26],zero,ymm2[27],zero,ymm2[28],zero,ymm2[29],zero,ymm2[30],zero,ymm2[31],zero
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
-; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm1, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
index 0c85d5c7b79ff..1baac968cdc52 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
@@ -120,7 +120,7 @@ define <32 x i16> @test_div7_32i16(<32 x i16> %a) nounwind {
;
; AVX512BW-LABEL: test_div7_32i16:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpmulhuw {{.*}}(%rip), %zmm0, %zmm1
+; AVX512BW-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm0
; AVX512BW-NEXT: vpaddw %zmm1, %zmm0, %zmm0
@@ -162,7 +162,7 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
-; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: test_div7_64i8:
@@ -178,10 +178,10 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = udiv <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <64 x i8> %res
@@ -197,57 +197,57 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm2
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15],ymm2[24],ymm1[24],ymm2[25],ymm1[25],ymm2[26],ymm1[26],ymm2[27],ymm1[27],ymm2[28],ymm1[28],ymm2[29],ymm1[29],ymm2[30],ymm1[30],ymm2[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[16],ymm1[16],ymm2[17],ymm1[17],ymm2[18],ymm1[18],ymm2[19],ymm1[19],ymm2[20],ymm1[20],ymm2[21],ymm1[21],ymm2[22],ymm1[22],ymm2[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
; AVX512F-NEXT: vpsubb %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15],ymm2[24],ymm1[24],ymm2[25],ymm1[25],ymm2[26],ymm1[26],ymm2[27],ymm1[27],ymm2[28],ymm1[28],ymm2[29],ymm1[29],ymm2[30],ymm1[30],ymm2[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[16],ymm1[16],ymm2[17],ymm1[17],ymm2[18],ymm1[18],ymm2[19],ymm1[19],ymm2[20],ymm1[20],ymm2[21],ymm1[21],ymm2[22],ymm1[22],ymm2[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512F-NEXT: vpackuswb %ymm4, %ymm2, %ymm2
; AVX512F-NEXT: vpaddb %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15],ymm2[24],ymm1[24],ymm2[25],ymm1[25],ymm2[26],ymm1[26],ymm2[27],ymm1[27],ymm2[28],ymm1[28],ymm2[29],ymm1[29],ymm2[30],ymm1[30],ymm2[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[16],ymm1[16],ymm2[17],ymm1[17],ymm2[18],ymm1[18],ymm2[19],ymm1[19],ymm2[20],ymm1[20],ymm2[21],ymm1[21],ymm2[22],ymm1[22],ymm2[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512F-NEXT: vpackuswb %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
; AVX512F-NEXT: vpsubb %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
@@ -257,30 +257,30 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm3 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm3, %zmm2
; AVX512BW-NEXT: vpsubb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm3 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm3, %zmm0, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: retq
@@ -420,7 +420,7 @@ define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind {
; AVX-NEXT: vpsrld $1, %zmm1, %zmm1
; AVX-NEXT: vpaddd %zmm3, %zmm1, %zmm1
; AVX-NEXT: vpsrld $2, %zmm1, %zmm1
-; AVX-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm1, %zmm1
+; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1
; AVX-NEXT: vpsubd %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = urem <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
@@ -453,12 +453,12 @@ define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind {
;
; AVX512BW-LABEL: test_rem7_32i16:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpmulhuw {{.*}}(%rip), %zmm0, %zmm1
+; AVX512BW-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm2
; AVX512BW-NEXT: vpsrlw $1, %zmm2, %zmm2
; AVX512BW-NEXT: vpaddw %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = urem <32 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -524,12 +524,12 @@ define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm2
; AVX512BW-NEXT: vpsrlw $1, %zmm2, %zmm2
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpaddb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $3, %zmm1, %zmm2
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
@@ -547,67 +547,67 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm3[8],ymm1[8],ymm3[9],ymm1[9],ymm3[10],ymm1[10],ymm3[11],ymm1[11],ymm3[12],ymm1[12],ymm3[13],ymm1[13],ymm3[14],ymm1[14],ymm3[15],ymm1[15],ymm3[24],ymm1[24],ymm3[25],ymm1[25],ymm3[26],ymm1[26],ymm3[27],ymm1[27],ymm3[28],ymm1[28],ymm3[29],ymm1[29],ymm3[30],ymm1[30],ymm3[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm3[0],ymm1[0],ymm3[1],ymm1[1],ymm3[2],ymm1[2],ymm3[3],ymm1[3],ymm3[4],ymm1[4],ymm3[5],ymm1[5],ymm3[6],ymm1[6],ymm3[7],ymm1[7],ymm3[16],ymm1[16],ymm3[17],ymm1[17],ymm3[18],ymm1[18],ymm3[19],ymm1[19],ymm3[20],ymm1[20],ymm3[21],ymm1[21],ymm3[22],ymm1[22],ymm3[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpackuswb %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsubb %ymm2, %ymm3, %ymm4
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm4[8],ymm1[8],ymm4[9],ymm1[9],ymm4[10],ymm1[10],ymm4[11],ymm1[11],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15],ymm4[24],ymm1[24],ymm4[25],ymm1[25],ymm4[26],ymm1[26],ymm4[27],ymm1[27],ymm4[28],ymm1[28],ymm4[29],ymm1[29],ymm4[30],ymm1[30],ymm4[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[2],ymm1[2],ymm4[3],ymm1[3],ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[16],ymm1[16],ymm4[17],ymm1[17],ymm4[18],ymm1[18],ymm4[19],ymm1[19],ymm4[20],ymm1[20],ymm4[21],ymm1[21],ymm4[22],ymm1[22],ymm4[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpackuswb %ymm5, %ymm4, %ymm4
; AVX512F-NEXT: vpaddb %ymm2, %ymm4, %ymm4
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm4[8],ymm1[8],ymm4[9],ymm1[9],ymm4[10],ymm1[10],ymm4[11],ymm1[11],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15],ymm4[24],ymm1[24],ymm4[25],ymm1[25],ymm4[26],ymm1[26],ymm4[27],ymm1[27],ymm4[28],ymm1[28],ymm4[29],ymm1[29],ymm4[30],ymm1[30],ymm4[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm5
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-NEXT: vpand %ymm2, %ymm5, %ymm5
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[2],ymm1[2],ymm4[3],ymm1[3],ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[16],ymm1[16],ymm4[17],ymm1[17],ymm4[18],ymm1[18],ymm4[19],ymm1[19],ymm4[20],ymm1[20],ymm4[21],ymm1[21],ymm4[22],ymm1[22],ymm4[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpand %ymm2, %ymm4, %ymm4
; AVX512F-NEXT: vpackuswb %ymm5, %ymm4, %ymm4
; AVX512F-NEXT: vpsubb %ymm4, %ymm3, %ymm3
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpsubb %ymm4, %ymm0, %ymm5
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm6 = ymm5[8],ymm1[8],ymm5[9],ymm1[9],ymm5[10],ymm1[10],ymm5[11],ymm1[11],ymm5[12],ymm1[12],ymm5[13],ymm1[13],ymm5[14],ymm1[14],ymm5[15],ymm1[15],ymm5[24],ymm1[24],ymm5[25],ymm1[25],ymm5[26],ymm1[26],ymm5[27],ymm1[27],ymm5[28],ymm1[28],ymm5[29],ymm1[29],ymm5[30],ymm1[30],ymm5[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm6, %ymm6
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6
; AVX512F-NEXT: vpsrlw $8, %ymm6, %ymm6
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm5[0],ymm1[0],ymm5[1],ymm1[1],ymm5[2],ymm1[2],ymm5[3],ymm1[3],ymm5[4],ymm1[4],ymm5[5],ymm1[5],ymm5[6],ymm1[6],ymm5[7],ymm1[7],ymm5[16],ymm1[16],ymm5[17],ymm1[17],ymm5[18],ymm1[18],ymm5[19],ymm1[19],ymm5[20],ymm1[20],ymm5[21],ymm1[21],ymm5[22],ymm1[22],ymm5[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm6, %ymm5, %ymm5
; AVX512F-NEXT: vpaddb %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm4[8],ymm1[8],ymm4[9],ymm1[9],ymm4[10],ymm1[10],ymm4[11],ymm1[11],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15],ymm4[24],ymm1[24],ymm4[25],ymm1[25],ymm4[26],ymm1[26],ymm4[27],ymm1[27],ymm4[28],ymm1[28],ymm4[29],ymm1[29],ymm4[30],ymm1[30],ymm4[31],ymm1[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
; AVX512F-NEXT: vpand %ymm2, %ymm5, %ymm5
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[2],ymm1[2],ymm4[3],ymm1[3],ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[16],ymm1[16],ymm4[17],ymm1[17],ymm4[18],ymm1[18],ymm4[19],ymm1[19],ymm4[20],ymm1[20],ymm4[21],ymm1[21],ymm4[22],ymm1[22],ymm4[23],ymm1[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $8, %ymm1, %ymm1
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpackuswb %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vpsubb %ymm1, %ymm0, %ymm0
@@ -618,35 +618,35 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm3 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm3, %zmm2
; AVX512BW-NEXT: vpsubb %zmm2, %zmm0, %zmm3
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm4 = zmm3[8],zmm1[8],zmm3[9],zmm1[9],zmm3[10],zmm1[10],zmm3[11],zmm1[11],zmm3[12],zmm1[12],zmm3[13],zmm1[13],zmm3[14],zmm1[14],zmm3[15],zmm1[15],zmm3[24],zmm1[24],zmm3[25],zmm1[25],zmm3[26],zmm1[26],zmm3[27],zmm1[27],zmm3[28],zmm1[28],zmm3[29],zmm1[29],zmm3[30],zmm1[30],zmm3[31],zmm1[31],zmm3[40],zmm1[40],zmm3[41],zmm1[41],zmm3[42],zmm1[42],zmm3[43],zmm1[43],zmm3[44],zmm1[44],zmm3[45],zmm1[45],zmm3[46],zmm1[46],zmm3[47],zmm1[47],zmm3[56],zmm1[56],zmm3[57],zmm1[57],zmm3[58],zmm1[58],zmm3[59],zmm1[59],zmm3[60],zmm1[60],zmm3[61],zmm1[61],zmm3[62],zmm1[62],zmm3[63],zmm1[63]
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm4, %zmm4
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm4
; AVX512BW-NEXT: vpsrlw $8, %zmm4, %zmm4
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm3 = zmm3[0],zmm1[0],zmm3[1],zmm1[1],zmm3[2],zmm1[2],zmm3[3],zmm1[3],zmm3[4],zmm1[4],zmm3[5],zmm1[5],zmm3[6],zmm1[6],zmm3[7],zmm1[7],zmm3[16],zmm1[16],zmm3[17],zmm1[17],zmm3[18],zmm1[18],zmm3[19],zmm1[19],zmm3[20],zmm1[20],zmm3[21],zmm1[21],zmm3[22],zmm1[22],zmm3[23],zmm1[23],zmm3[32],zmm1[32],zmm3[33],zmm1[33],zmm3[34],zmm1[34],zmm3[35],zmm1[35],zmm3[36],zmm1[36],zmm3[37],zmm1[37],zmm3[38],zmm1[38],zmm3[39],zmm1[39],zmm3[48],zmm1[48],zmm3[49],zmm1[49],zmm3[50],zmm1[50],zmm3[51],zmm1[51],zmm3[52],zmm1[52],zmm3[53],zmm1[53],zmm3[54],zmm1[54],zmm3[55],zmm1[55]
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512BW-NEXT: vpackuswb %zmm4, %zmm3, %zmm3
; AVX512BW-NEXT: vpaddb %zmm2, %zmm3, %zmm2
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm3 = zmm2[8],zmm1[8],zmm2[9],zmm1[9],zmm2[10],zmm1[10],zmm2[11],zmm1[11],zmm2[12],zmm1[12],zmm2[13],zmm1[13],zmm2[14],zmm1[14],zmm2[15],zmm1[15],zmm2[24],zmm1[24],zmm2[25],zmm1[25],zmm2[26],zmm1[26],zmm2[27],zmm1[27],zmm2[28],zmm1[28],zmm2[29],zmm1[29],zmm2[30],zmm1[30],zmm2[31],zmm1[31],zmm2[40],zmm1[40],zmm2[41],zmm1[41],zmm2[42],zmm1[42],zmm2[43],zmm1[43],zmm2[44],zmm1[44],zmm2[45],zmm1[45],zmm2[46],zmm1[46],zmm2[47],zmm1[47],zmm2[56],zmm1[56],zmm2[57],zmm1[57],zmm2[58],zmm1[58],zmm2[59],zmm1[59],zmm2[60],zmm1[60],zmm2[61],zmm1[61],zmm2[62],zmm1[62],zmm2[63],zmm1[63]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512BW-NEXT: vpandq %zmm4, %zmm3, %zmm3
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm2[0],zmm1[0],zmm2[1],zmm1[1],zmm2[2],zmm1[2],zmm2[3],zmm1[3],zmm2[4],zmm1[4],zmm2[5],zmm1[5],zmm2[6],zmm1[6],zmm2[7],zmm1[7],zmm2[16],zmm1[16],zmm2[17],zmm1[17],zmm2[18],zmm1[18],zmm2[19],zmm1[19],zmm2[20],zmm1[20],zmm2[21],zmm1[21],zmm2[22],zmm1[22],zmm2[23],zmm1[23],zmm2[32],zmm1[32],zmm2[33],zmm1[33],zmm2[34],zmm1[34],zmm2[35],zmm1[35],zmm2[36],zmm1[36],zmm2[37],zmm1[37],zmm2[38],zmm1[38],zmm2[39],zmm1[39],zmm2[48],zmm1[48],zmm2[49],zmm1[49],zmm2[50],zmm1[50],zmm2[51],zmm1[51],zmm2[52],zmm1[52],zmm2[53],zmm1[53],zmm2[54],zmm1[54],zmm2[55],zmm1[55]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpandq %zmm4, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm3, %zmm1, %zmm1
; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
diff --git a/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll b/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
index 85157d11e4b4a..07dc0fe0b44f8 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
@@ -259,7 +259,7 @@ define void @test_urem_pow2_v2i32(<2 x i32>* %x, <2 x i32>* %y) nounwind {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movlps %xmm0, (%eax)
; X86-NEXT: retl
%a = load <2 x i32>, <2 x i32>* %x
diff --git a/llvm/test/CodeGen/X86/vector-intrinsics.ll b/llvm/test/CodeGen/X86/vector-intrinsics.ll
index becb28323deb5..8bbcbdec9677e 100644
--- a/llvm/test/CodeGen/X86/vector-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/vector-intrinsics.ll
@@ -13,20 +13,20 @@ define <4 x double> @foo(<4 x double> %p)
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq sin
+; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq sin
+; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: callq sin
+; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq sin
+; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
@@ -44,20 +44,20 @@ define <4 x double> @goo(<4 x double> %p)
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq cos
+; CHECK-NEXT: callq cos at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq cos
+; CHECK-NEXT: callq cos at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: callq cos
+; CHECK-NEXT: callq cos at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq cos
+; CHECK-NEXT: callq cos at PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
@@ -78,25 +78,25 @@ define <4 x double> @moo(<4 x double> %p, <4 x double> %q)
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, %xmm1
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
@@ -118,23 +118,23 @@ define <4 x double> @zoo(<4 x double> %p, i32 %q)
; CHECK-NEXT: movl %edi, %ebx
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebx, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebx, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebx, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
@@ -169,44 +169,44 @@ define void @a(<9 x double>* %p) nounwind {
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: callq exp
+; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx)
@@ -251,49 +251,49 @@ define void @b(<9 x double>* %p, <9 x double>* %q) nounwind {
; CHECK-NEXT: movaps 48(%rsi), %xmm1
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, %xmm0
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
@@ -301,7 +301,7 @@ define void @b(<9 x double>* %p, <9 x double>* %q) nounwind {
; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
-; CHECK-NEXT: callq pow
+; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx)
@@ -339,52 +339,52 @@ define void @c(<9 x double>* %p, i32 %n) nounwind {
; CHECK-NEXT: movaps 48(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movl %esi, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movl %ebp, %edi
-; CHECK-NEXT: callq __powidf2
+; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx)
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
index 9576a0d7a8dc1..6a9a4f6ded5f3 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
@@ -38,7 +38,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm1, %xmm2
@@ -49,7 +49,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm2, %xmm0
; SSE2-NEXT: retq
@@ -78,7 +78,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE3-NEXT: pxor %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm1, %xmm2
@@ -89,7 +89,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm2, %xmm0
; SSE3-NEXT: retq
@@ -101,7 +101,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: psrlw $4, %xmm1
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pxor %xmm4, %xmm4
; SSSE3-NEXT: pshufb %xmm1, %xmm2
; SSSE3-NEXT: pcmpeqb %xmm4, %xmm1
@@ -134,7 +134,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE41-NEXT: pshufb %xmm0, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $4, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pshufb %xmm1, %xmm2
; SSE41-NEXT: pcmpeqb %xmm4, %xmm1
@@ -165,7 +165,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -193,7 +193,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX512VLBWDQ-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -236,7 +236,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
@@ -291,7 +291,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm1, %xmm2
@@ -302,7 +302,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm2, %xmm0
; SSE2-NEXT: retq
@@ -331,7 +331,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE3-NEXT: pxor %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm1, %xmm2
@@ -342,7 +342,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm2, %xmm0
; SSE3-NEXT: retq
@@ -354,7 +354,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: psrlw $4, %xmm1
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pxor %xmm4, %xmm4
; SSSE3-NEXT: pshufb %xmm1, %xmm2
; SSSE3-NEXT: pcmpeqb %xmm4, %xmm1
@@ -387,7 +387,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE41-NEXT: pshufb %xmm0, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $4, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pshufb %xmm1, %xmm2
; SSE41-NEXT: pcmpeqb %xmm4, %xmm1
@@ -418,7 +418,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -446,7 +446,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX512VLBWDQ-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -489,7 +489,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
@@ -541,7 +541,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE2-NEXT: pxor %xmm1, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm2, %xmm1
@@ -552,7 +552,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
@@ -583,7 +583,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE3-NEXT: pxor %xmm1, %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm2
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm2, %xmm1
@@ -594,7 +594,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psrlw $4, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
@@ -611,7 +611,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: psrlw $4, %xmm1
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pxor %xmm4, %xmm4
; SSSE3-NEXT: pshufb %xmm1, %xmm2
; SSSE3-NEXT: pcmpeqb %xmm4, %xmm1
@@ -638,7 +638,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE41-NEXT: pshufb %xmm0, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $4, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pshufb %xmm1, %xmm2
; SSE41-NEXT: pcmpeqb %xmm4, %xmm1
@@ -663,7 +663,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -686,7 +686,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX512VLBWDQ-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -724,7 +724,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
@@ -770,7 +770,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE2-NEXT: pxor %xmm1, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm2, %xmm1
@@ -781,7 +781,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
@@ -812,7 +812,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE3-NEXT: pxor %xmm1, %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm2
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm2, %xmm1
@@ -823,7 +823,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psrlw $4, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
@@ -840,7 +840,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: psrlw $4, %xmm1
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pxor %xmm4, %xmm4
; SSSE3-NEXT: pshufb %xmm1, %xmm2
; SSSE3-NEXT: pcmpeqb %xmm4, %xmm1
@@ -867,7 +867,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE41-NEXT: pshufb %xmm0, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $4, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pshufb %xmm1, %xmm2
; SSE41-NEXT: pcmpeqb %xmm4, %xmm1
@@ -892,7 +892,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -915,7 +915,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX512VLBWDQ-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -953,7 +953,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
@@ -996,7 +996,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm1, %xmm2
@@ -1007,7 +1007,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0
@@ -1032,7 +1032,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE3-NEXT: pxor %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm1, %xmm2
@@ -1043,7 +1043,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0
@@ -1057,7 +1057,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: psrlw $4, %xmm1
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pxor %xmm4, %xmm4
; SSSE3-NEXT: pshufb %xmm1, %xmm2
; SSSE3-NEXT: pcmpeqb %xmm4, %xmm1
@@ -1078,7 +1078,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE41-NEXT: pshufb %xmm0, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $4, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pshufb %xmm1, %xmm2
; SSE41-NEXT: pcmpeqb %xmm4, %xmm1
@@ -1097,7 +1097,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -1115,7 +1115,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX512VLBWDQ-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -1133,7 +1133,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; AVX512VLCD-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VLCD-NEXT: vplzcntd %ymm0, %ymm0
; AVX512VLCD-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VLCD-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VLCD-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLCD-NEXT: vzeroupper
; AVX512VLCD-NEXT: retq
;
@@ -1142,7 +1142,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; AVX512CD-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0
; AVX512CD-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512CD-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512CD-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512CD-NEXT: vzeroupper
; AVX512CD-NEXT: retq
;
@@ -1153,7 +1153,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
@@ -1189,7 +1189,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm1, %xmm2
@@ -1200,7 +1200,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0
@@ -1225,7 +1225,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE3-NEXT: pxor %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm1, %xmm2
@@ -1236,7 +1236,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0
@@ -1250,7 +1250,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: psrlw $4, %xmm1
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: pxor %xmm4, %xmm4
; SSSE3-NEXT: pshufb %xmm1, %xmm2
; SSSE3-NEXT: pcmpeqb %xmm4, %xmm1
@@ -1271,7 +1271,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE41-NEXT: pshufb %xmm0, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $4, %xmm1
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pshufb %xmm1, %xmm2
; SSE41-NEXT: pcmpeqb %xmm4, %xmm1
@@ -1290,7 +1290,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -1308,7 +1308,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm5
; AVX512VLBWDQ-NEXT: vpand %xmm5, %xmm2, %xmm2
@@ -1326,7 +1326,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; AVX512VLCD-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VLCD-NEXT: vplzcntd %ymm0, %ymm0
; AVX512VLCD-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VLCD-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VLCD-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLCD-NEXT: vzeroupper
; AVX512VLCD-NEXT: retq
;
@@ -1335,7 +1335,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; AVX512CD-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0
; AVX512CD-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512CD-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512CD-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512CD-NEXT: vzeroupper
; AVX512CD-NEXT: retq
;
@@ -1346,7 +1346,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
@@ -1368,11 +1368,11 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: por %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
@@ -1383,7 +1383,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE2-NEXT: pxor %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm3, %xmm1
@@ -1401,11 +1401,11 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: por %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psrlw $2, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
@@ -1416,7 +1416,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE3-NEXT: pxor %xmm1, %xmm3
; SSE3-NEXT: movdqa %xmm3, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm3
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm3, %xmm1
@@ -1436,7 +1436,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pshufb %xmm0, %xmm2
; SSSE3-NEXT: psrlw $4, %xmm0
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm3
; SSSE3-NEXT: pcmpeqb %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3
@@ -1451,7 +1451,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pshufb %xmm0, %xmm2
; SSE41-NEXT: psrlw $4, %xmm0
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pxor %xmm3, %xmm3
; SSE41-NEXT: pcmpeqb %xmm0, %xmm3
; SSE41-NEXT: pand %xmm2, %xmm3
@@ -1465,7 +1465,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm3
; AVX-NEXT: vpand %xmm3, %xmm2, %xmm2
@@ -1478,7 +1478,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLBWDQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm3
; AVX512VLBWDQ-NEXT: vpand %xmm3, %xmm2, %xmm2
@@ -1491,7 +1491,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512-NEXT: vplzcntd %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512-NEXT: vpsubb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpsubb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
;
@@ -1501,7 +1501,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: pshufb %xmm0, %xmm2
; X32-SSE-NEXT: psrlw $4, %xmm0
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: pxor %xmm3, %xmm3
; X32-SSE-NEXT: pcmpeqb %xmm0, %xmm3
; X32-SSE-NEXT: pand %xmm2, %xmm3
@@ -1518,11 +1518,11 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: por %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
@@ -1533,7 +1533,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE2-NEXT: pxor %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm0
; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm3, %xmm1
@@ -1551,11 +1551,11 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: por %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psrlw $2, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
@@ -1566,7 +1566,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE3-NEXT: pxor %xmm1, %xmm3
; SSE3-NEXT: movdqa %xmm3, %xmm0
; SSE3-NEXT: psrlw $1, %xmm0
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm3
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm3, %xmm1
@@ -1586,7 +1586,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pshufb %xmm0, %xmm2
; SSSE3-NEXT: psrlw $4, %xmm0
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm3
; SSSE3-NEXT: pcmpeqb %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3
@@ -1601,7 +1601,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pshufb %xmm0, %xmm2
; SSE41-NEXT: psrlw $4, %xmm0
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pxor %xmm3, %xmm3
; SSE41-NEXT: pcmpeqb %xmm0, %xmm3
; SSE41-NEXT: pand %xmm2, %xmm3
@@ -1615,7 +1615,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm3
; AVX-NEXT: vpand %xmm3, %xmm2, %xmm2
@@ -1628,7 +1628,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %xmm0, %xmm1, %xmm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLBWDQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm3
; AVX512VLBWDQ-NEXT: vpand %xmm3, %xmm2, %xmm2
@@ -1641,7 +1641,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512-NEXT: vplzcntd %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512-NEXT: vpsubb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpsubb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
;
@@ -1651,7 +1651,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: pshufb %xmm0, %xmm2
; X32-SSE-NEXT: psrlw $4, %xmm0
-; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X32-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: pxor %xmm3, %xmm3
; X32-SSE-NEXT: pcmpeqb %xmm0, %xmm3
; X32-SSE-NEXT: pand %xmm2, %xmm3
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-256.ll b/llvm/test/CodeGen/X86/vector-lzcnt-256.ll
index 9624b3601a95f..7c481b3d2b378 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-256.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-256.ll
@@ -68,7 +68,7 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -96,7 +96,7 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VL-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -124,7 +124,7 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VLBWDQ-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -164,7 +164,7 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -250,7 +250,7 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -278,7 +278,7 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VL-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -306,7 +306,7 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VLBWDQ-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -346,7 +346,7 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -422,7 +422,7 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -445,7 +445,7 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VL-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -468,7 +468,7 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VLBWDQ-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -503,7 +503,7 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -574,7 +574,7 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -597,7 +597,7 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VL-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -620,7 +620,7 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VLBWDQ-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -655,7 +655,7 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -716,7 +716,7 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -734,7 +734,7 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VL-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -752,7 +752,7 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VLBWDQ-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -770,7 +770,7 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind {
; AVX512-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512-NEXT: vplzcntd %zmm0, %zmm0
; AVX512-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
;
; X32-AVX-LABEL: testv16i16:
@@ -778,7 +778,7 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -833,7 +833,7 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -851,7 +851,7 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VL-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -869,7 +869,7 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VLBWDQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; AVX512VLBWDQ-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -887,7 +887,7 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind {
; AVX512-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512-NEXT: vplzcntd %zmm0, %zmm0
; AVX512-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
;
; X32-AVX-LABEL: testv16i16u:
@@ -895,7 +895,7 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
@@ -940,7 +940,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; AVX2-NEXT: vpand %ymm3, %ymm2, %ymm2
@@ -953,7 +953,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512VL-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2
@@ -966,7 +966,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBWDQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; AVX512VLBWDQ-NEXT: vpand %ymm3, %ymm2, %ymm2
@@ -994,7 +994,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2
@@ -1034,7 +1034,7 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind {
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; AVX2-NEXT: vpand %ymm3, %ymm2, %ymm2
@@ -1047,7 +1047,7 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind {
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512VL-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2
@@ -1060,7 +1060,7 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind {
; AVX512VLBWDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512VLBWDQ-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; AVX512VLBWDQ-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VLBWDQ-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBWDQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBWDQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512VLBWDQ-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; AVX512VLBWDQ-NEXT: vpand %ymm3, %ymm2, %ymm2
@@ -1088,7 +1088,7 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind {
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
-; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-512.ll b/llvm/test/CodeGen/X86/vector-lzcnt-512.ll
index ae5f0c8ee5289..5b7cc54c8eb69 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-512.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-512.ll
@@ -362,7 +362,7 @@ define <32 x i16> @testv32i16(<32 x i16> %in) nounwind {
; AVX512BW-LABEL: testv32i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3
; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm2
@@ -448,7 +448,7 @@ define <32 x i16> @testv32i16u(<32 x i16> %in) nounwind {
; AVX512BW-LABEL: testv32i16u:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3
; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm2
@@ -558,7 +558,7 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind {
; AVX512BW-LABEL: testv64i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3
; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm0
@@ -652,7 +652,7 @@ define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind {
; AVX512BW-LABEL: testv64i8u:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3
; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm0
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll b/llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
index c1e7e42ac7ea0..e903c09b9b8f1 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
@@ -25,7 +25,7 @@ define <2 x i32> @illegal_ctlz(<2 x i32> %v1) {
; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: psrlw $1, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: psubb %xmm0, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm2, %xmm1
@@ -36,7 +36,7 @@ define <2 x i32> @illegal_ctlz(<2 x i32> %v1) {
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: psrlw $4, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
@@ -59,7 +59,7 @@ define <2 x i32> @illegal_cttz(<2 x i32> %v1) {
; CHECK-NEXT: pandn %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2
@@ -70,7 +70,7 @@ define <2 x i32> @illegal_cttz(<2 x i32> %v1) {
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
diff --git a/llvm/test/CodeGen/X86/vector-mul.ll b/llvm/test/CodeGen/X86/vector-mul.ll
index 837bf8a27f3aa..15cb162f029f8 100644
--- a/llvm/test/CodeGen/X86/vector-mul.ll
+++ b/llvm/test/CodeGen/X86/vector-mul.ll
@@ -55,30 +55,30 @@ define <16 x i8> @mul_v16i8_32(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: mul_v16i8_32:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllw $5, %xmm0
-; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v16i8_32:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: psllw $5, %xmm0
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v16i8_32:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v16i8_32:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpsllw $5, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v16i8_32:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpsllw $5, %xmm0, %xmm0
-; X64-AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <16 x i8> %a0, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
ret <16 x i8> %1
@@ -99,17 +99,17 @@ define <2 x i64> @mul_v2i64_32_8(<2 x i64> %a0) nounwind {
;
; X64-XOP-LABEL: mul_v2i64_32_8:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v2i64_32_8:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v2i64_32_8:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 32, i64 8>
ret <2 x i64> %1
@@ -118,27 +118,27 @@ define <2 x i64> @mul_v2i64_32_8(<2 x i64> %a0) nounwind {
define <4 x i32> @mul_v4i32_1_2_4_8(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_1_2_4_8:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v4i32_1_2_4_8:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v4i32_1_2_4_8:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v4i32_1_2_4_8:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v4i32_1_2_4_8:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
ret <4 x i32> %1
@@ -147,27 +147,27 @@ define <4 x i32> @mul_v4i32_1_2_4_8(<4 x i32> %a0) nounwind {
define <8 x i16> @mul_v8i16_1_2_4_8_16_32_64_128(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 1, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128>
ret <8 x i16> %1
@@ -190,14 +190,14 @@ define <16 x i8> @mul_v16i8_1_2_4_8_1_2_4_8_1_2_4_8_1_2_4_8(<16 x i8> %a0) nounw
;
; X64-XOP-LABEL: mul_v16i8_1_2_4_8_1_2_4_8_1_2_4_8_1_2_4_8:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v16i8_1_2_4_8_1_2_4_8_1_2_4_8_1_2_4_8:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X64-AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vzeroupper
@@ -206,7 +206,7 @@ define <16 x i8> @mul_v16i8_1_2_4_8_1_2_4_8_1_2_4_8_1_2_4_8(<16 x i8> %a0) nounw
; X64-AVX512DQ-LABEL: mul_v16i8_1_2_4_8_1_2_4_8_1_2_4_8_1_2_4_8:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; X64-AVX512DQ-NEXT: vpsllvd {{.*}}(%rip), %zmm0, %zmm0
+; X64-AVX512DQ-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; X64-AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
; X64-AVX512DQ-NEXT: vzeroupper
; X64-AVX512DQ-NEXT: retq
@@ -241,7 +241,7 @@ define <2 x i64> @mul_v2i64_17(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_17:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 17, i64 17>
ret <2 x i64> %1
@@ -250,17 +250,17 @@ define <2 x i64> @mul_v2i64_17(<2 x i64> %a0) nounwind {
define <4 x i32> @mul_v4i32_17(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_17:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v4i32_17:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v4i32_17:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v4i32_17:
@@ -271,7 +271,7 @@ define <4 x i32> @mul_v4i32_17(<4 x i32> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v4i32_17:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
ret <4 x i32> %1
@@ -280,17 +280,17 @@ define <4 x i32> @mul_v4i32_17(<4 x i32> %a0) nounwind {
define <8 x i16> @mul_v8i16_17(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_17:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v8i16_17:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v8i16_17:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17>
ret <8 x i16> %1
@@ -301,7 +301,7 @@ define <16 x i8> @mul_v16i8_17(<16 x i8> %a0) nounwind {
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $4, %xmm1
-; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm1
; X86-SSE-NEXT: movdqa %xmm1, %xmm0
; X86-SSE-NEXT: retl
@@ -310,28 +310,28 @@ define <16 x i8> @mul_v16i8_17(<16 x i8> %a0) nounwind {
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1
; X64-SSE-NEXT: psllw $4, %xmm1
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: paddb %xmm0, %xmm1
; X64-SSE-NEXT: movdqa %xmm1, %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v16i8_17:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm1
+; X64-XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-XOP-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v16i8_17:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpsllw $4, %xmm0, %xmm1
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v16i8_17:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpsllw $4, %xmm0, %xmm1
-; X64-AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX512DQ-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <16 x i8> %a0, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17>
@@ -369,7 +369,7 @@ define <4 x i64> @mul_v4i64_17(<4 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v4i64_17:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i64> %a0, <i64 17, i64 17, i64 17, i64 17>
ret <4 x i64> %1
@@ -401,7 +401,7 @@ define <8 x i32> @mul_v8i32_17(<8 x i32> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v8i32_17:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmulld {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <8 x i32> %a0, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
ret <8 x i32> %1
@@ -427,12 +427,12 @@ define <16 x i16> @mul_v16i16_17(<16 x i16> %a0) nounwind {
;
; X64-AVX2-LABEL: mul_v16i16_17:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v16i16_17:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <16 x i16> %a0, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17>
ret <16 x i16> %1
@@ -468,14 +468,14 @@ define <32 x i8> @mul_v32i8_17(<32 x i8> %a0) nounwind {
; X64-AVX2-LABEL: mul_v32i8_17:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpsllw $4, %ymm0, %ymm1
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v32i8_17:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpsllw $4, %ymm0, %ymm1
-; X64-AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX512DQ-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <32 x i8> %a0, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17>
@@ -514,7 +514,7 @@ define <2 x i64> @mul_v2i64_neg1025(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_neg1025:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 -1025, i64 -1025>
ret <2 x i64> %1
@@ -523,17 +523,17 @@ define <2 x i64> @mul_v2i64_neg1025(<2 x i64> %a0) nounwind {
define <4 x i32> @mul_v4i32_neg33(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_neg33:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v4i32_neg33:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v4i32_neg33:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v4i32_neg33:
@@ -544,7 +544,7 @@ define <4 x i32> @mul_v4i32_neg33(<4 x i32> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v4i32_neg33:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 -33, i32 -33, i32 -33, i32 -33>
ret <4 x i32> %1
@@ -553,17 +553,17 @@ define <4 x i32> @mul_v4i32_neg33(<4 x i32> %a0) nounwind {
define <8 x i16> @mul_v8i16_neg9(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_neg9:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v8i16_neg9:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v8i16_neg9:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9>
ret <8 x i16> %1
@@ -574,7 +574,7 @@ define <16 x i8> @mul_v16i8_neg5(<16 x i8> %a0) nounwind {
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $2, %xmm1
-; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm1
; X86-SSE-NEXT: pxor %xmm0, %xmm0
; X86-SSE-NEXT: psubb %xmm1, %xmm0
@@ -584,7 +584,7 @@ define <16 x i8> @mul_v16i8_neg5(<16 x i8> %a0) nounwind {
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1
; X64-SSE-NEXT: psllw $2, %xmm1
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: paddb %xmm0, %xmm1
; X64-SSE-NEXT: pxor %xmm0, %xmm0
; X64-SSE-NEXT: psubb %xmm1, %xmm0
@@ -592,7 +592,7 @@ define <16 x i8> @mul_v16i8_neg5(<16 x i8> %a0) nounwind {
;
; X64-XOP-LABEL: mul_v16i8_neg5:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm1
+; X64-XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-XOP-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; X64-XOP-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-XOP-NEXT: vpsubb %xmm0, %xmm1, %xmm0
@@ -601,7 +601,7 @@ define <16 x i8> @mul_v16i8_neg5(<16 x i8> %a0) nounwind {
; X64-AVX2-LABEL: mul_v16i8_neg5:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpsllw $2, %xmm0, %xmm1
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vpsubb %xmm0, %xmm1, %xmm0
@@ -610,7 +610,7 @@ define <16 x i8> @mul_v16i8_neg5(<16 x i8> %a0) nounwind {
; X64-AVX512DQ-LABEL: mul_v16i8_neg5:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpsllw $2, %xmm0, %xmm1
-; X64-AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX512DQ-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; X64-AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX512DQ-NEXT: vpsubb %xmm0, %xmm1, %xmm0
@@ -658,7 +658,7 @@ define <4 x i64> @mul_v4i64_neg1025(<4 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v4i64_neg1025:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i64> %a0, <i64 -1025, i64 -1025, i64 -1025, i64 -1025>
ret <4 x i64> %1
@@ -693,7 +693,7 @@ define <8 x i32> @mul_v8i32_neg33(<8 x i32> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v8i32_neg33:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmulld {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <8 x i32> %a0, <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33>
ret <8 x i32> %1
@@ -722,12 +722,12 @@ define <16 x i16> @mul_v16i16_neg9(<16 x i16> %a0) nounwind {
;
; X64-AVX2-LABEL: mul_v16i16_neg9:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v16i16_neg9:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <16 x i16> %a0, <i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9>
ret <16 x i16> %1
@@ -769,7 +769,7 @@ define <32 x i8> @mul_v32i8_neg5(<32 x i8> %a0) nounwind {
; X64-AVX2-LABEL: mul_v32i8_neg5:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpsllw $2, %ymm0, %ymm1
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm0
@@ -778,7 +778,7 @@ define <32 x i8> @mul_v32i8_neg5(<32 x i8> %a0) nounwind {
; X64-AVX512DQ-LABEL: mul_v32i8_neg5:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpsllw $2, %ymm0, %ymm1
-; X64-AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; X64-AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; X64-AVX512DQ-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; X64-AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX512DQ-NEXT: vpsubb %ymm0, %ymm1, %ymm0
@@ -836,7 +836,7 @@ define <2 x i64> @mul_v2i64_17_65(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_17_65:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 17, i64 65>
ret <2 x i64> %1
@@ -845,17 +845,17 @@ define <2 x i64> @mul_v2i64_17_65(<2 x i64> %a0) nounwind {
define <4 x i32> @mul_v4i32_5_17_33_65(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_5_17_33_65:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v4i32_5_17_33_65:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v4i32_5_17_33_65:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 5, i32 17, i32 33, i32 65>
ret <4 x i32> %1
@@ -864,17 +864,17 @@ define <4 x i32> @mul_v4i32_5_17_33_65(<4 x i32> %a0) nounwind {
define <8 x i16> @mul_v8i16_2_3_9_17_33_65_129_257(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_2_3_9_17_33_65_129_257:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v8i16_2_3_9_17_33_65_129_257:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v8i16_2_3_9_17_33_65_129_257:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 2, i16 3, i16 9, i16 17, i16 33, i16 65, i16 129, i16 257>
ret <8 x i16> %1
@@ -885,10 +885,10 @@ define <16 x i8> @mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3(<16 x i8>
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; X86-SSE-NEXT: pand %xmm2, %xmm0
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: pand %xmm2, %xmm1
; X86-SSE-NEXT: packuswb %xmm0, %xmm1
; X86-SSE-NEXT: movdqa %xmm1, %xmm0
@@ -898,10 +898,10 @@ define <16 x i8> @mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3(<16 x i8>
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; X64-SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; X64-SSE-NEXT: pand %xmm2, %xmm0
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: pand %xmm2, %xmm1
; X64-SSE-NEXT: packuswb %xmm0, %xmm1
; X64-SSE-NEXT: movdqa %xmm1, %xmm0
@@ -910,17 +910,17 @@ define <16 x i8> @mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3(<16 x i8>
; X64-XOP-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3:
; X64-XOP: # %bb.0:
; X64-XOP-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; X64-XOP-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; X64-XOP-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-XOP-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; X64-XOP-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: vpperm {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],xmm1[0,2,4,6,8,10,12,14]
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X64-AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vzeroupper
@@ -929,7 +929,7 @@ define <16 x i8> @mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3(<16 x i8>
; X64-AVX512DQ-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X64-AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; X64-AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
; X64-AVX512DQ-NEXT: vzeroupper
@@ -965,7 +965,7 @@ define <2 x i64> @mul_v2i64_7(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_7:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 7, i64 7>
ret <2 x i64> %1
@@ -974,17 +974,17 @@ define <2 x i64> @mul_v2i64_7(<2 x i64> %a0) nounwind {
define <4 x i32> @mul_v4i32_7(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_7:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v4i32_7:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v4i32_7:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v4i32_7:
@@ -995,7 +995,7 @@ define <4 x i32> @mul_v4i32_7(<4 x i32> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v4i32_7:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %1
@@ -1004,17 +1004,17 @@ define <4 x i32> @mul_v4i32_7(<4 x i32> %a0) nounwind {
define <8 x i16> @mul_v8i16_7(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_7:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v8i16_7:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v8i16_7:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %1
@@ -1025,7 +1025,7 @@ define <16 x i8> @mul_v16i8_31(<16 x i8> %a0) nounwind {
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $5, %xmm1
-; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: psubb %xmm0, %xmm1
; X86-SSE-NEXT: movdqa %xmm1, %xmm0
; X86-SSE-NEXT: retl
@@ -1034,28 +1034,28 @@ define <16 x i8> @mul_v16i8_31(<16 x i8> %a0) nounwind {
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1
; X64-SSE-NEXT: psllw $5, %xmm1
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: psubb %xmm0, %xmm1
; X64-SSE-NEXT: movdqa %xmm1, %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v16i8_31:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm1
+; X64-XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-XOP-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v16i8_31:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpsllw $5, %xmm0, %xmm1
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX2-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v16i8_31:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpsllw $5, %xmm0, %xmm1
-; X64-AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX512DQ-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <16 x i8> %a0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
@@ -1088,7 +1088,7 @@ define <2 x i64> @mul_v2i64_neg7(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_neg7:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 -7, i64 -7>
ret <2 x i64> %1
@@ -1097,17 +1097,17 @@ define <2 x i64> @mul_v2i64_neg7(<2 x i64> %a0) nounwind {
define <4 x i32> @mul_v4i32_neg63(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_neg63:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v4i32_neg63:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v4i32_neg63:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v4i32_neg63:
@@ -1118,7 +1118,7 @@ define <4 x i32> @mul_v4i32_neg63(<4 x i32> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v4i32_neg63:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 -63, i32 -63, i32 -63, i32 -63>
ret <4 x i32> %1
@@ -1127,17 +1127,17 @@ define <4 x i32> @mul_v4i32_neg63(<4 x i32> %a0) nounwind {
define <8 x i16> @mul_v8i16_neg31(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_neg31:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v8i16_neg31:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v8i16_neg31:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31>
ret <8 x i16> %1
@@ -1148,7 +1148,7 @@ define <16 x i8> @mul_v16i8_neg15(<16 x i8> %a0) nounwind {
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $4, %xmm1
-; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
+; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: psubb %xmm1, %xmm0
; X86-SSE-NEXT: retl
;
@@ -1156,27 +1156,27 @@ define <16 x i8> @mul_v16i8_neg15(<16 x i8> %a0) nounwind {
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1
; X64-SSE-NEXT: psllw $4, %xmm1
-; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; X64-SSE-NEXT: psubb %xmm1, %xmm0
; X64-SSE-NEXT: retq
;
; X64-XOP-LABEL: mul_v16i8_neg15:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm1
+; X64-XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-XOP-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v16i8_neg15:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpsllw $4, %xmm0, %xmm1
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX2-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v16i8_neg15:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpsllw $4, %xmm0, %xmm1
-; X64-AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; X64-AVX512DQ-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <16 x i8> %a0, <i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15>
@@ -1232,7 +1232,7 @@ define <2 x i64> @mul_v2i64_15_63(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_15_63:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 15, i64 63>
ret <2 x i64> %1
@@ -1261,7 +1261,7 @@ define <2 x i64> @mul_v2i64_neg_15_63(<2 x i64> %a0) nounwind {
; X64-SSE-NEXT: movdqa %xmm0, %xmm3
; X64-SSE-NEXT: psrlq $32, %xmm3
; X64-SSE-NEXT: pmuludq %xmm1, %xmm3
-; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: paddq %xmm3, %xmm0
; X64-SSE-NEXT: psllq $32, %xmm0
; X64-SSE-NEXT: paddq %xmm2, %xmm0
@@ -1273,7 +1273,7 @@ define <2 x i64> @mul_v2i64_neg_15_63(<2 x i64> %a0) nounwind {
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-XOP-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-XOP-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1285,7 +1285,7 @@ define <2 x i64> @mul_v2i64_neg_15_63(<2 x i64> %a0) nounwind {
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1293,7 +1293,7 @@ define <2 x i64> @mul_v2i64_neg_15_63(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_neg_15_63:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 -15, i64 -63>
ret <2 x i64> %1
@@ -1322,7 +1322,7 @@ define <2 x i64> @mul_v2i64_neg_17_65(<2 x i64> %a0) nounwind {
; X64-SSE-NEXT: movdqa %xmm0, %xmm3
; X64-SSE-NEXT: psrlq $32, %xmm3
; X64-SSE-NEXT: pmuludq %xmm1, %xmm3
-; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: paddq %xmm3, %xmm0
; X64-SSE-NEXT: psllq $32, %xmm0
; X64-SSE-NEXT: paddq %xmm2, %xmm0
@@ -1334,7 +1334,7 @@ define <2 x i64> @mul_v2i64_neg_17_65(<2 x i64> %a0) nounwind {
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-XOP-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-XOP-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1346,7 +1346,7 @@ define <2 x i64> @mul_v2i64_neg_17_65(<2 x i64> %a0) nounwind {
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1354,7 +1354,7 @@ define <2 x i64> @mul_v2i64_neg_17_65(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_neg_17_65:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 -17, i64 -65>
ret <2 x i64> %1
@@ -1400,7 +1400,7 @@ define <2 x i64> @mul_v2i64_neg_0_1(<2 x i64> %a0) nounwind {
; X64-SSE-NEXT: movdqa %xmm0, %xmm3
; X64-SSE-NEXT: psrlq $32, %xmm3
; X64-SSE-NEXT: pmuludq %xmm1, %xmm3
-; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: paddq %xmm3, %xmm0
; X64-SSE-NEXT: psllq $32, %xmm0
; X64-SSE-NEXT: paddq %xmm2, %xmm0
@@ -1412,7 +1412,7 @@ define <2 x i64> @mul_v2i64_neg_0_1(<2 x i64> %a0) nounwind {
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-XOP-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-XOP-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1424,7 +1424,7 @@ define <2 x i64> @mul_v2i64_neg_0_1(<2 x i64> %a0) nounwind {
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1432,7 +1432,7 @@ define <2 x i64> @mul_v2i64_neg_0_1(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_neg_0_1:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 0, i64 -1>
ret <2 x i64> %1
@@ -1462,7 +1462,7 @@ define <2 x i64> @mul_v2i64_15_neg_63(<2 x i64> %a0) nounwind {
; X64-SSE-NEXT: movdqa %xmm0, %xmm3
; X64-SSE-NEXT: psrlq $32, %xmm3
; X64-SSE-NEXT: pmuludq %xmm1, %xmm3
-; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: paddq %xmm3, %xmm0
; X64-SSE-NEXT: psllq $32, %xmm0
; X64-SSE-NEXT: paddq %xmm2, %xmm0
@@ -1474,7 +1474,7 @@ define <2 x i64> @mul_v2i64_15_neg_63(<2 x i64> %a0) nounwind {
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-XOP-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-XOP-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-XOP-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1486,7 +1486,7 @@ define <2 x i64> @mul_v2i64_15_neg_63(<2 x i64> %a0) nounwind {
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; X64-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
@@ -1494,7 +1494,7 @@ define <2 x i64> @mul_v2i64_15_neg_63(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_15_neg_63:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 15, i64 -63>
ret <2 x i64> %1
@@ -1503,17 +1503,17 @@ define <2 x i64> @mul_v2i64_15_neg_63(<2 x i64> %a0) nounwind {
define <4 x i32> @mul_v4i32_0_15_31_7(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_0_15_31_7:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v4i32_0_15_31_7:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v4i32_0_15_31_7:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 0, i32 15, i32 31, i32 7>
ret <4 x i32> %1
@@ -1522,17 +1522,17 @@ define <4 x i32> @mul_v4i32_0_15_31_7(<4 x i32> %a0) nounwind {
define <8 x i16> @mul_v8i16_0_1_7_15_31_63_127_255(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_0_1_7_15_31_63_127_255:
; X86-SSE: # %bb.0:
-; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: mul_v8i16_0_1_7_15_31_63_127_255:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: mul_v8i16_0_1_7_15_31_63_127_255:
; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 0, i16 1, i16 7, i16 15, i16 31, i16 63, i16 127, i16 255>
ret <8 x i16> %1
@@ -1566,8 +1566,8 @@ define <16 x i8> @mul_v16i8_0_1_3_7_15_31_63_127_0_1_3_7_15_31_63_127(<16 x i8>
; X64-AVX2-LABEL: mul_v16i8_0_1_3_7_15_31_63_127_0_1_3_7_15_31_63_127:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X64-AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vzeroupper
@@ -1576,7 +1576,7 @@ define <16 x i8> @mul_v16i8_0_1_3_7_15_31_63_127_0_1_3_7_15_31_63_127(<16 x i8>
; X64-AVX512DQ-LABEL: mul_v16i8_0_1_3_7_15_31_63_127_0_1_3_7_15_31_63_127:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X64-AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; X64-AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; X64-AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
; X64-AVX512DQ-NEXT: vzeroupper
@@ -1630,7 +1630,7 @@ define <2 x i64> @mul_v2i64_68_132(<2 x i64> %x) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_68_132:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%mul = mul <2 x i64> %x, <i64 68, i64 132>
ret <2 x i64> %mul
@@ -1681,7 +1681,7 @@ define <2 x i64> @mul_v2i64_60_120(<2 x i64> %x) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_60_120:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%mul = mul <2 x i64> %x, <i64 60, i64 124>
ret <2 x i64> %mul
diff --git a/llvm/test/CodeGen/X86/vector-narrow-binop.ll b/llvm/test/CodeGen/X86/vector-narrow-binop.ll
index a25c7adc2f34b..1d4b4574bf105 100644
--- a/llvm/test/CodeGen/X86/vector-narrow-binop.ll
+++ b/llvm/test/CodeGen/X86/vector-narrow-binop.ll
@@ -86,12 +86,12 @@ define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
define <3 x float> @PR39511(<4 x float> %t0, <3 x float>* %b) {
; SSE-LABEL: PR39511:
; SSE: # %bb.0:
-; SSE-NEXT: addps {{.*}}(%rip), %xmm0
+; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: PR39511:
; AVX: # %bb.0:
-; AVX-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%add = fadd <4 x float> %t0, <float 1.0, float 2.0, float 3.0, float 4.0>
%ext = shufflevector <4 x float> %add, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
diff --git a/llvm/test/CodeGen/X86/vector-pack-128.ll b/llvm/test/CodeGen/X86/vector-pack-128.ll
index ab647c6b258bf..4f6c795404a18 100644
--- a/llvm/test/CodeGen/X86/vector-pack-128.ll
+++ b/llvm/test/CodeGen/X86/vector-pack-128.ll
@@ -12,14 +12,14 @@ define <8 x i16> @trunc_concat_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; SSE-LABEL: trunc_concat_packssdw_128:
; SSE: # %bb.0:
; SSE-NEXT: psrad $17, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: trunc_concat_packssdw_128:
; AVX1: # %bb.0:
; AVX1-NEXT: vpsrad $17, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -34,7 +34,7 @@ define <8 x i16> @trunc_concat_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; AVX512-LABEL: trunc_concat_packssdw_128:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsrad $17, %xmm0, %xmm0
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; AVX512-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
@@ -48,21 +48,21 @@ define <8 x i16> @trunc_concat_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; SSE2-LABEL: trunc_concat_packusdw_128:
; SSE2: # %bb.0:
; SSE2-NEXT: psrld $17, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: packssdw %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: trunc_concat_packusdw_128:
; SSE4: # %bb.0:
; SSE4-NEXT: psrld $17, %xmm0
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: packusdw %xmm1, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: trunc_concat_packusdw_128:
; AVX1: # %bb.0:
; AVX1-NEXT: vpsrld $17, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -77,7 +77,7 @@ define <8 x i16> @trunc_concat_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; AVX512-LABEL: trunc_concat_packusdw_128:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsrld $17, %xmm0, %xmm0
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; AVX512-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = lshr <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
@@ -91,14 +91,14 @@ define <16 x i8> @trunc_concat_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) nounwi
; SSE-LABEL: trunc_concat_packsswb_128:
; SSE: # %bb.0:
; SSE-NEXT: psraw $15, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: packsswb %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: trunc_concat_packsswb_128:
; AVX: # %bb.0:
; AVX-NEXT: vpsraw $15, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
@@ -112,14 +112,14 @@ define <16 x i8> @trunc_concat_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) nounwi
; SSE-LABEL: trunc_concat_packuswb_128:
; SSE: # %bb.0:
; SSE-NEXT: psrlw $15, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: packuswb %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: trunc_concat_packuswb_128:
; AVX: # %bb.0:
; AVX-NEXT: vpsrlw $15, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = lshr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
@@ -135,7 +135,7 @@ define <8 x i16> @concat_trunc_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; SSE2-LABEL: concat_trunc_packssdw_128:
; SSE2: # %bb.0:
; SSE2-NEXT: psrad $17, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: packssdw %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm1
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
@@ -144,14 +144,14 @@ define <8 x i16> @concat_trunc_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; SSE4-LABEL: concat_trunc_packssdw_128:
; SSE4: # %bb.0:
; SSE4-NEXT: psrad $17, %xmm0
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: packssdw %xmm1, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: concat_trunc_packssdw_128:
; AVX1: # %bb.0:
; AVX1-NEXT: vpsrad $17, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -168,7 +168,7 @@ define <8 x i16> @concat_trunc_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; AVX512-LABEL: concat_trunc_packssdw_128:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsrad $17, %xmm0, %xmm0
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; AVX512-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
@@ -183,7 +183,7 @@ define <8 x i16> @concat_trunc_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; SSE2-LABEL: concat_trunc_packusdw_128:
; SSE2: # %bb.0:
; SSE2-NEXT: psrld $17, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: packssdw %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm1
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
@@ -192,14 +192,14 @@ define <8 x i16> @concat_trunc_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; SSE4-LABEL: concat_trunc_packusdw_128:
; SSE4: # %bb.0:
; SSE4-NEXT: psrld $17, %xmm0
-; SSE4-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: packusdw %xmm1, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: concat_trunc_packusdw_128:
; AVX1: # %bb.0:
; AVX1-NEXT: vpsrld $17, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -214,7 +214,7 @@ define <8 x i16> @concat_trunc_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) nounwi
; AVX512-LABEL: concat_trunc_packusdw_128:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsrld $17, %xmm0, %xmm0
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
; AVX512-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = lshr <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
@@ -229,14 +229,14 @@ define <16 x i8> @concat_trunc_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) nounwi
; SSE-LABEL: concat_trunc_packsswb_128:
; SSE: # %bb.0:
; SSE-NEXT: psraw $15, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: packsswb %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: concat_trunc_packsswb_128:
; AVX: # %bb.0:
; AVX-NEXT: vpsraw $15, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
@@ -251,14 +251,14 @@ define <16 x i8> @concat_trunc_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) nounwi
; SSE-LABEL: concat_trunc_packuswb_128:
; SSE: # %bb.0:
; SSE-NEXT: psrlw $15, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: packuswb %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: concat_trunc_packuswb_128:
; AVX: # %bb.0:
; AVX-NEXT: vpsrlw $15, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = lshr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
diff --git a/llvm/test/CodeGen/X86/vector-pack-256.ll b/llvm/test/CodeGen/X86/vector-pack-256.ll
index b789b46906cb2..684a1ac4e75cc 100644
--- a/llvm/test/CodeGen/X86/vector-pack-256.ll
+++ b/llvm/test/CodeGen/X86/vector-pack-256.ll
@@ -49,7 +49,7 @@ define <16 x i16> @trunc_concat_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) nounw
; AVX1-NEXT: vpsrld $17, %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsrld $17, %xmm0, %xmm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpackusdw %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
@@ -67,7 +67,7 @@ define <16 x i16> @trunc_concat_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) nounw
; AVX512-LABEL: trunc_concat_packusdw_256:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsrld $17, %ymm0, %ymm0
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to8}, %ymm1, %ymm1
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm1
; AVX512-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
@@ -86,7 +86,7 @@ define <32 x i8> @trunc_concat_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpacksswb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm1, %xmm2, %xmm1
@@ -96,14 +96,14 @@ define <32 x i8> @trunc_concat_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX2-LABEL: trunc_concat_packsswb_256:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsraw $15, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpacksswb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: trunc_concat_packsswb_256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsraw $15, %ymm0, %ymm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
@@ -116,7 +116,7 @@ define <32 x i8> @trunc_concat_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX512BW-LABEL: trunc_concat_packsswb_256:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsraw $15, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512BW-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
@@ -135,7 +135,7 @@ define <32 x i8> @trunc_concat_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX1-NEXT: vpsrlw $15, %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsrlw $15, %xmm0, %xmm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
@@ -145,14 +145,14 @@ define <32 x i8> @trunc_concat_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX2-LABEL: trunc_concat_packuswb_256:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $15, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: trunc_concat_packuswb_256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $15, %ymm0, %ymm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
@@ -165,7 +165,7 @@ define <32 x i8> @trunc_concat_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX512BW-LABEL: trunc_concat_packuswb_256:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $15, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512BW-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
@@ -232,7 +232,7 @@ define <16 x i16> @concat_trunc_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) nounw
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
@@ -245,7 +245,7 @@ define <16 x i16> @concat_trunc_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) nounw
; AVX2-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -256,7 +256,7 @@ define <16 x i16> @concat_trunc_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) nounw
; AVX512-NEXT: vpsrld $17, %ymm0, %ymm0
; AVX512-NEXT: vpmovdw %ymm0, %xmm0
; AVX512-NEXT: vpmovdw %ymm1, %xmm1
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -276,10 +276,10 @@ define <32 x i8> @concat_trunc_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX1-NEXT: vpsraw $15, %xmm2, %xmm2
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
@@ -290,10 +290,10 @@ define <32 x i8> @concat_trunc_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX2-NEXT: vpsraw $15, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -306,7 +306,7 @@ define <32 x i8> @concat_trunc_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512F-NEXT: vpmovdb %zmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -317,7 +317,7 @@ define <32 x i8> @concat_trunc_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX512BW-NEXT: vpsraw $15, %ymm0, %ymm0
; AVX512BW-NEXT: vpmovwb %ymm0, %xmm0
; AVX512BW-NEXT: vpmovwb %ymm1, %xmm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512BW-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -337,10 +337,10 @@ define <32 x i8> @concat_trunc_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX1-NEXT: vpsrlw $15, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $15, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
@@ -351,10 +351,10 @@ define <32 x i8> @concat_trunc_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX2-NEXT: vpsrlw $15, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -367,7 +367,7 @@ define <32 x i8> @concat_trunc_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512F-NEXT: vpmovdb %zmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -378,7 +378,7 @@ define <32 x i8> @concat_trunc_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) noun
; AVX512BW-NEXT: vpsrlw $15, %ymm0, %ymm0
; AVX512BW-NEXT: vpmovwb %ymm0, %xmm0
; AVX512BW-NEXT: vpmovwb %ymm1, %xmm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} xmm2 = xmm0[1],xmm1[1]
; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512BW-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-pack-512.ll b/llvm/test/CodeGen/X86/vector-pack-512.ll
index 432927d510617..31ef3c6d8fb8b 100644
--- a/llvm/test/CodeGen/X86/vector-pack-512.ll
+++ b/llvm/test/CodeGen/X86/vector-pack-512.ll
@@ -28,7 +28,7 @@ define <32 x i16> @trunc_concat_packusdw_512(<16 x i32> %a0, <16 x i32> %a1) nou
; AVX512-LABEL: trunc_concat_packusdw_512:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsrld $17, %zmm0, %zmm0
-; AVX512-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm1, %zmm1
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm2 = [4,5,12,13,6,7,14,15]
; AVX512-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,1,8,9,2,3,10,11]
@@ -51,7 +51,7 @@ define <64 x i8> @trunc_concat_packsswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm0
; AVX512F-NEXT: vpsraw $15, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
-; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,8,9,2,3,10,11]
; AVX512F-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm3 = [4,5,12,13,6,7,14,15]
@@ -74,7 +74,7 @@ define <64 x i8> @trunc_concat_packsswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512BW-LABEL: trunc_concat_packsswb_512:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsraw $15, %zmm0, %zmm0
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [4,5,12,13,6,7,14,15]
; AVX512BW-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,1,8,9,2,3,10,11]
@@ -97,7 +97,7 @@ define <64 x i8> @trunc_concat_packuswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm0
; AVX512F-NEXT: vpsrlw $15, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
-; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,8,9,2,3,10,11]
; AVX512F-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm3 = [4,5,12,13,6,7,14,15]
@@ -120,7 +120,7 @@ define <64 x i8> @trunc_concat_packuswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512BW-LABEL: trunc_concat_packuswb_512:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $15, %zmm0, %zmm0
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [4,5,12,13,6,7,14,15]
; AVX512BW-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,1,8,9,2,3,10,11]
@@ -195,7 +195,7 @@ define <64 x i8> @concat_trunc_packsswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512F-NEXT: vpmovdb %zmm1, %xmm1
; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm2
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,8,1,9,6,14,7,15]
@@ -207,7 +207,7 @@ define <64 x i8> @concat_trunc_packsswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512BW-NEXT: vpsraw $15, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1
; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,8,1,9,6,14,7,15]
@@ -238,7 +238,7 @@ define <64 x i8> @concat_trunc_packuswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512F-NEXT: vpmovdb %zmm1, %xmm1
; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm2
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,8,1,9,6,14,7,15]
@@ -250,7 +250,7 @@ define <64 x i8> @concat_trunc_packuswb_512(<32 x i16> %a0, <32 x i16> %a1) noun
; AVX512BW-NEXT: vpsrlw $15, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1
; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,8,1,9,6,14,7,15]
diff --git a/llvm/test/CodeGen/X86/vector-partial-undef.ll b/llvm/test/CodeGen/X86/vector-partial-undef.ll
index 69f7ebbfe48aa..21d82efbe6108 100644
--- a/llvm/test/CodeGen/X86/vector-partial-undef.ll
+++ b/llvm/test/CodeGen/X86/vector-partial-undef.ll
@@ -86,7 +86,7 @@ define <4 x i64> @and_undef_elts(<2 x i64> %x) {
; AVX-LABEL: and_undef_elts:
; AVX: # %bb.0:
; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,1,2]
; AVX-NEXT: retq
%extend = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
@@ -107,7 +107,7 @@ define <4 x i64> @or_undef_elts(<2 x i64> %x) {
; AVX-LABEL: or_undef_elts:
; AVX: # %bb.0:
; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,1,2]
; AVX-NEXT: retq
%extend = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
@@ -141,7 +141,7 @@ define <8 x i32> @xor_undef_elts_alt(<4 x i32> %x) {
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movaps {{.*#+}} xmm2 = <u,u,44,12>
; SSE-NEXT: xorps %xmm0, %xmm2
-; SSE-NEXT: xorps {{.*}}(%rip), %xmm1
+; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[2,0]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[1,0]
@@ -153,7 +153,7 @@ define <8 x i32> @xor_undef_elts_alt(<4 x i32> %x) {
; AVX: # %bb.0:
; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vmovaps {{.*#+}} ymm1 = [6,1,5,4,3,2,0,7]
; AVX-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-pcmp.ll b/llvm/test/CodeGen/X86/vector-pcmp.ll
index 656f678ca2bf1..082822b9620fa 100644
--- a/llvm/test/CodeGen/X86/vector-pcmp.ll
+++ b/llvm/test/CodeGen/X86/vector-pcmp.ll
@@ -226,13 +226,13 @@ define <16 x i8> @cmpeq_zext_v16i8(<16 x i8> %a, <16 x i8> %b) {
; SSE-LABEL: cmpeq_zext_v16i8:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqb %xmm1, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: cmpeq_zext_v16i8:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%cmp = icmp eq <16 x i8> %a, %b
%zext = zext <16 x i1> %cmp to <16 x i8>
@@ -255,7 +255,7 @@ define <16 x i16> @cmpeq_zext_v16i16(<16 x i16> %a, <16 x i16> %b) {
; AVX1-NEXT: vpcmpeqw %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: cmpeq_zext_v16i16:
@@ -314,7 +314,7 @@ define <4 x i64> @cmpeq_zext_v4i64(<4 x i64> %a, <4 x i64> %b) {
; AVX1-NEXT: vpcmpeqq %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: cmpeq_zext_v4i64:
@@ -344,13 +344,13 @@ define <32 x i8> @cmpgt_zext_v32i8(<32 x i8> %a, <32 x i8> %b) {
; AVX1-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: cmpgt_zext_v32i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
%cmp = icmp sgt <32 x i8> %a, %b
%zext = zext <32 x i1> %cmp to <32 x i8>
@@ -390,7 +390,7 @@ define <8 x i32> @cmpgt_zext_v8i32(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: cmpgt_zext_v8i32:
@@ -416,7 +416,7 @@ define <2 x i64> @cmpgt_zext_v2i64(<2 x i64> %a, <2 x i64> %b) {
; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSE2-NEXT: por %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE42-LABEL: cmpgt_zext_v2i64:
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
index 28578078ee1e7..5e58482c9ddf8 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
@@ -70,14 +70,14 @@ define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_1_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -117,7 +117,7 @@ define <16 x i8> @ult_2_v16i8(<16 x i8> %0) {
; BITALG-LABEL: ult_2_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -131,7 +131,7 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -142,8 +142,8 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -151,7 +151,7 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -162,8 +162,8 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE3-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -211,7 +211,7 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -225,7 +225,7 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -234,7 +234,7 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -243,7 +243,7 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -251,14 +251,14 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_2_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -272,7 +272,7 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -283,7 +283,7 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -292,7 +292,7 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -303,7 +303,7 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]
; SSE3-NEXT: pcmpgtb %xmm1, %xmm0
; SSE3-NEXT: retq
@@ -352,7 +352,7 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -366,7 +366,7 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -402,7 +402,7 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; BITALG-LABEL: ult_3_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -416,7 +416,7 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -427,8 +427,8 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -436,7 +436,7 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -447,8 +447,8 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE3-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -496,7 +496,7 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -510,7 +510,7 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -519,7 +519,7 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -528,7 +528,7 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -536,14 +536,14 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_3_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -557,7 +557,7 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -568,7 +568,7 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -577,7 +577,7 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -588,7 +588,7 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
; SSE3-NEXT: pcmpgtb %xmm1, %xmm0
; SSE3-NEXT: retq
@@ -637,7 +637,7 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -651,7 +651,7 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -687,7 +687,7 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; BITALG-LABEL: ult_4_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -701,7 +701,7 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -712,8 +712,8 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -721,7 +721,7 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -732,8 +732,8 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE3-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -781,7 +781,7 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -795,7 +795,7 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -804,7 +804,7 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -813,7 +813,7 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -821,14 +821,14 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_4_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -842,7 +842,7 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -853,7 +853,7 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5]
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -862,7 +862,7 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -873,7 +873,7 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5]
; SSE3-NEXT: pcmpgtb %xmm1, %xmm0
; SSE3-NEXT: retq
@@ -922,7 +922,7 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -936,7 +936,7 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -972,7 +972,7 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; BITALG-LABEL: ult_5_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -986,7 +986,7 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -997,8 +997,8 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -1006,7 +1006,7 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1017,8 +1017,8 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE3-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -1066,7 +1066,7 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1080,7 +1080,7 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -1089,7 +1089,7 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -1098,7 +1098,7 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -1106,14 +1106,14 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_5_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -1127,7 +1127,7 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1138,7 +1138,7 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6]
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -1147,7 +1147,7 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1158,7 +1158,7 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6]
; SSE3-NEXT: pcmpgtb %xmm1, %xmm0
; SSE3-NEXT: retq
@@ -1207,7 +1207,7 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1221,7 +1221,7 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -1257,7 +1257,7 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; BITALG-LABEL: ult_6_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -1271,7 +1271,7 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1282,8 +1282,8 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -1291,7 +1291,7 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1302,8 +1302,8 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
-; SSE3-NEXT: pcmpgtb {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -1351,7 +1351,7 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1365,7 +1365,7 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -1374,7 +1374,7 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -1383,7 +1383,7 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdb %zmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -1391,14 +1391,14 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_6_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -1412,7 +1412,7 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1423,7 +1423,7 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -1432,7 +1432,7 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1443,7 +1443,7 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; SSE3-NEXT: pcmpgtb %xmm1, %xmm0
; SSE3-NEXT: retq
@@ -1492,7 +1492,7 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1506,7 +1506,7 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
@@ -1542,7 +1542,7 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; BITALG-LABEL: ult_7_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
@@ -1610,14 +1610,14 @@ define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_1_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -1657,7 +1657,7 @@ define <8 x i16> @ult_2_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_2_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -1671,7 +1671,7 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1682,19 +1682,19 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_2_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1705,12 +1705,12 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_2_v8i16:
@@ -1729,7 +1729,7 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_2_v8i16:
@@ -1748,7 +1748,7 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_2_v8i16:
@@ -1764,7 +1764,7 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_2_v8i16:
@@ -1780,7 +1780,7 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_2_v8i16:
@@ -1788,7 +1788,7 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -1797,7 +1797,7 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -1805,14 +1805,14 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_2_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -1826,7 +1826,7 @@ define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1837,7 +1837,7 @@ define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -1850,7 +1850,7 @@ define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1861,7 +1861,7 @@ define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -1976,7 +1976,7 @@ define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_3_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -1990,7 +1990,7 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -2001,19 +2001,19 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_3_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -2024,12 +2024,12 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_3_v8i16:
@@ -2048,7 +2048,7 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_3_v8i16:
@@ -2067,7 +2067,7 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_3_v8i16:
@@ -2083,7 +2083,7 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_3_v8i16:
@@ -2099,7 +2099,7 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_3_v8i16:
@@ -2107,7 +2107,7 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -2116,7 +2116,7 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -2124,14 +2124,14 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_3_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -2145,7 +2145,7 @@ define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -2156,7 +2156,7 @@ define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -2169,7 +2169,7 @@ define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -2180,7 +2180,7 @@ define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -2295,7 +2295,7 @@ define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_4_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -2309,7 +2309,7 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -2320,19 +2320,19 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_4_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -2343,12 +2343,12 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_4_v8i16:
@@ -2367,7 +2367,7 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_4_v8i16:
@@ -2386,7 +2386,7 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_4_v8i16:
@@ -2402,7 +2402,7 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_4_v8i16:
@@ -2418,7 +2418,7 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_4_v8i16:
@@ -2426,7 +2426,7 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -2435,7 +2435,7 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -2443,14 +2443,14 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_4_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -2464,7 +2464,7 @@ define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -2475,7 +2475,7 @@ define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -2488,7 +2488,7 @@ define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -2499,7 +2499,7 @@ define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -2614,7 +2614,7 @@ define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_5_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -2628,7 +2628,7 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -2639,19 +2639,19 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_5_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -2662,12 +2662,12 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_5_v8i16:
@@ -2686,7 +2686,7 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_5_v8i16:
@@ -2705,7 +2705,7 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_5_v8i16:
@@ -2721,7 +2721,7 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_5_v8i16:
@@ -2737,7 +2737,7 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_5_v8i16:
@@ -2745,7 +2745,7 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -2754,7 +2754,7 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -2762,14 +2762,14 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_5_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -2783,7 +2783,7 @@ define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -2794,7 +2794,7 @@ define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -2807,7 +2807,7 @@ define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -2818,7 +2818,7 @@ define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -2933,7 +2933,7 @@ define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_6_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -2947,7 +2947,7 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -2958,19 +2958,19 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_6_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -2981,12 +2981,12 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_6_v8i16:
@@ -3005,7 +3005,7 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_6_v8i16:
@@ -3024,7 +3024,7 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_6_v8i16:
@@ -3040,7 +3040,7 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_6_v8i16:
@@ -3056,7 +3056,7 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_6_v8i16:
@@ -3064,7 +3064,7 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3073,7 +3073,7 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -3081,14 +3081,14 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_6_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -3102,7 +3102,7 @@ define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -3113,7 +3113,7 @@ define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -3126,7 +3126,7 @@ define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -3137,7 +3137,7 @@ define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -3252,7 +3252,7 @@ define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_7_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -3266,7 +3266,7 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -3277,19 +3277,19 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_7_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -3300,12 +3300,12 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_7_v8i16:
@@ -3324,7 +3324,7 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_7_v8i16:
@@ -3343,7 +3343,7 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_7_v8i16:
@@ -3359,7 +3359,7 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_7_v8i16:
@@ -3375,7 +3375,7 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_7_v8i16:
@@ -3383,7 +3383,7 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3392,7 +3392,7 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -3400,14 +3400,14 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_7_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -3421,7 +3421,7 @@ define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -3432,7 +3432,7 @@ define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -3445,7 +3445,7 @@ define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -3456,7 +3456,7 @@ define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -3571,7 +3571,7 @@ define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_8_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -3585,7 +3585,7 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -3596,19 +3596,19 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_8_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -3619,12 +3619,12 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_8_v8i16:
@@ -3643,7 +3643,7 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_8_v8i16:
@@ -3662,7 +3662,7 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_8_v8i16:
@@ -3678,7 +3678,7 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_8_v8i16:
@@ -3694,7 +3694,7 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_8_v8i16:
@@ -3702,7 +3702,7 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3711,7 +3711,7 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -3719,14 +3719,14 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_8_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -3740,7 +3740,7 @@ define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -3751,7 +3751,7 @@ define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -3764,7 +3764,7 @@ define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -3775,7 +3775,7 @@ define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -3890,7 +3890,7 @@ define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_9_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -3904,7 +3904,7 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -3915,19 +3915,19 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_9_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -3938,12 +3938,12 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_9_v8i16:
@@ -3962,7 +3962,7 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_9_v8i16:
@@ -3981,7 +3981,7 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_9_v8i16:
@@ -3997,7 +3997,7 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_9_v8i16:
@@ -4013,7 +4013,7 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_9_v8i16:
@@ -4021,7 +4021,7 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4030,7 +4030,7 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -4038,14 +4038,14 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_9_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -4059,7 +4059,7 @@ define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -4070,7 +4070,7 @@ define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -4083,7 +4083,7 @@ define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -4094,7 +4094,7 @@ define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -4209,7 +4209,7 @@ define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_10_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -4223,7 +4223,7 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -4234,19 +4234,19 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_10_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -4257,12 +4257,12 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_10_v8i16:
@@ -4281,7 +4281,7 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_10_v8i16:
@@ -4300,7 +4300,7 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_10_v8i16:
@@ -4316,7 +4316,7 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_10_v8i16:
@@ -4332,7 +4332,7 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_10_v8i16:
@@ -4340,7 +4340,7 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4349,7 +4349,7 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -4357,14 +4357,14 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_10_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -4378,7 +4378,7 @@ define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -4389,7 +4389,7 @@ define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -4402,7 +4402,7 @@ define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -4413,7 +4413,7 @@ define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -4528,7 +4528,7 @@ define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_11_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -4542,7 +4542,7 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -4553,19 +4553,19 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_11_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -4576,12 +4576,12 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_11_v8i16:
@@ -4600,7 +4600,7 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_11_v8i16:
@@ -4619,7 +4619,7 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_11_v8i16:
@@ -4635,7 +4635,7 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_11_v8i16:
@@ -4651,7 +4651,7 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_11_v8i16:
@@ -4659,7 +4659,7 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4668,7 +4668,7 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -4676,14 +4676,14 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_11_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -4697,7 +4697,7 @@ define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -4708,7 +4708,7 @@ define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -4721,7 +4721,7 @@ define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -4732,7 +4732,7 @@ define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -4847,7 +4847,7 @@ define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_12_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -4861,7 +4861,7 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -4872,19 +4872,19 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_12_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -4895,12 +4895,12 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_12_v8i16:
@@ -4919,7 +4919,7 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_12_v8i16:
@@ -4938,7 +4938,7 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_12_v8i16:
@@ -4954,7 +4954,7 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_12_v8i16:
@@ -4970,7 +4970,7 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_12_v8i16:
@@ -4978,7 +4978,7 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4987,7 +4987,7 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -4995,14 +4995,14 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_12_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -5016,7 +5016,7 @@ define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -5027,7 +5027,7 @@ define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -5040,7 +5040,7 @@ define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -5051,7 +5051,7 @@ define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -5166,7 +5166,7 @@ define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_13_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -5180,7 +5180,7 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -5191,19 +5191,19 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_13_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -5214,12 +5214,12 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_13_v8i16:
@@ -5238,7 +5238,7 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_13_v8i16:
@@ -5257,7 +5257,7 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_13_v8i16:
@@ -5273,7 +5273,7 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_13_v8i16:
@@ -5289,7 +5289,7 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_13_v8i16:
@@ -5297,7 +5297,7 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5306,7 +5306,7 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -5314,14 +5314,14 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_13_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -5335,7 +5335,7 @@ define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -5346,7 +5346,7 @@ define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -5359,7 +5359,7 @@ define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -5370,7 +5370,7 @@ define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -5485,7 +5485,7 @@ define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_14_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -5499,7 +5499,7 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -5510,19 +5510,19 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: ugt_14_v8i16:
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -5533,12 +5533,12 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0
-; SSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: ugt_14_v8i16:
@@ -5557,7 +5557,7 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; SSSE3-NEXT: psllw $8, %xmm0
; SSSE3-NEXT: paddb %xmm3, %xmm0
; SSSE3-NEXT: psrlw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: ugt_14_v8i16:
@@ -5576,7 +5576,7 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: paddb %xmm3, %xmm0
; SSE41-NEXT: psrlw $8, %xmm0
-; SSE41-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_14_v8i16:
@@ -5592,7 +5592,7 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_14_v8i16:
@@ -5608,7 +5608,7 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX2-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_14_v8i16:
@@ -5616,7 +5616,7 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5625,7 +5625,7 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %ymm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vzeroupper
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -5633,14 +5633,14 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_14_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -5654,7 +5654,7 @@ define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -5665,7 +5665,7 @@ define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psllw $8, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
@@ -5678,7 +5678,7 @@ define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -5689,7 +5689,7 @@ define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psllw $8, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
@@ -5804,7 +5804,7 @@ define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ult_15_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %xmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -5858,7 +5858,7 @@ define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_1_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5930,7 +5930,7 @@ define <4 x i32> @ult_2_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_2_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5963,7 +5963,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -5974,7 +5974,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -5982,7 +5982,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -5990,7 +5990,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -6001,7 +6001,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6009,7 +6009,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -6032,7 +6032,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -6054,7 +6054,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_2_v4i32:
@@ -6073,7 +6073,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_2_v4i32:
@@ -6108,7 +6108,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_2_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6137,7 +6137,7 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6152,7 +6152,7 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -6163,7 +6163,7 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6179,7 +6179,7 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -6190,7 +6190,7 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6299,7 +6299,7 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_3_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6328,7 +6328,7 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6343,7 +6343,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -6354,7 +6354,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6362,7 +6362,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -6370,7 +6370,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -6381,7 +6381,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6389,7 +6389,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -6412,7 +6412,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -6434,7 +6434,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_3_v4i32:
@@ -6453,7 +6453,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_3_v4i32:
@@ -6488,7 +6488,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_3_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6517,7 +6517,7 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6532,7 +6532,7 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -6543,7 +6543,7 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6559,7 +6559,7 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -6570,7 +6570,7 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6679,7 +6679,7 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_4_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6708,7 +6708,7 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6723,7 +6723,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -6734,7 +6734,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6742,7 +6742,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -6750,7 +6750,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -6761,7 +6761,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6769,7 +6769,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -6792,7 +6792,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -6814,7 +6814,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_4_v4i32:
@@ -6833,7 +6833,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_4_v4i32:
@@ -6868,7 +6868,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_4_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6897,7 +6897,7 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6912,7 +6912,7 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -6923,7 +6923,7 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -6939,7 +6939,7 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -6950,7 +6950,7 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7059,7 +7059,7 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_5_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7088,7 +7088,7 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7103,7 +7103,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -7114,7 +7114,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7122,7 +7122,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -7130,7 +7130,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -7141,7 +7141,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7149,7 +7149,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -7172,7 +7172,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -7194,7 +7194,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_5_v4i32:
@@ -7213,7 +7213,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_5_v4i32:
@@ -7248,7 +7248,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_5_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7277,7 +7277,7 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7292,7 +7292,7 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -7303,7 +7303,7 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7319,7 +7319,7 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -7330,7 +7330,7 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7439,7 +7439,7 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_6_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7468,7 +7468,7 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7483,7 +7483,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -7494,7 +7494,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7502,7 +7502,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -7510,7 +7510,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -7521,7 +7521,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7529,7 +7529,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -7552,7 +7552,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -7574,7 +7574,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_6_v4i32:
@@ -7593,7 +7593,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_6_v4i32:
@@ -7628,7 +7628,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_6_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7657,7 +7657,7 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7672,7 +7672,7 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -7683,7 +7683,7 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7699,7 +7699,7 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -7710,7 +7710,7 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7819,7 +7819,7 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_7_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7848,7 +7848,7 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7863,7 +7863,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -7874,7 +7874,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7882,7 +7882,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -7890,7 +7890,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -7901,7 +7901,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -7909,7 +7909,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -7932,7 +7932,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -7954,7 +7954,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_7_v4i32:
@@ -7973,7 +7973,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_7_v4i32:
@@ -8008,7 +8008,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_7_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8037,7 +8037,7 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8052,7 +8052,7 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -8063,7 +8063,7 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8079,7 +8079,7 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -8090,7 +8090,7 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8199,7 +8199,7 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_8_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8228,7 +8228,7 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8243,7 +8243,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -8254,7 +8254,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8262,7 +8262,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -8270,7 +8270,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -8281,7 +8281,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8289,7 +8289,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -8312,7 +8312,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -8334,7 +8334,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_8_v4i32:
@@ -8353,7 +8353,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_8_v4i32:
@@ -8388,7 +8388,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_8_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8417,7 +8417,7 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8432,7 +8432,7 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -8443,7 +8443,7 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8459,7 +8459,7 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -8470,7 +8470,7 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8579,7 +8579,7 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_9_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8608,7 +8608,7 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8623,7 +8623,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -8634,7 +8634,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8642,7 +8642,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -8650,7 +8650,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -8661,7 +8661,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8669,7 +8669,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -8692,7 +8692,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -8714,7 +8714,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_9_v4i32:
@@ -8733,7 +8733,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_9_v4i32:
@@ -8768,7 +8768,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_9_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8797,7 +8797,7 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8812,7 +8812,7 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -8823,7 +8823,7 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8839,7 +8839,7 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -8850,7 +8850,7 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -8959,7 +8959,7 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_10_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8988,7 +8988,7 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9003,7 +9003,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -9014,7 +9014,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9022,7 +9022,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -9030,7 +9030,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -9041,7 +9041,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9049,7 +9049,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -9072,7 +9072,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -9094,7 +9094,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_10_v4i32:
@@ -9113,7 +9113,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_10_v4i32:
@@ -9148,7 +9148,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_10_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9177,7 +9177,7 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9192,7 +9192,7 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -9203,7 +9203,7 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9219,7 +9219,7 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -9230,7 +9230,7 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9339,7 +9339,7 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_11_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9368,7 +9368,7 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9383,7 +9383,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -9394,7 +9394,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9402,7 +9402,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -9410,7 +9410,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -9421,7 +9421,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9429,7 +9429,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -9452,7 +9452,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -9474,7 +9474,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_11_v4i32:
@@ -9493,7 +9493,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_11_v4i32:
@@ -9528,7 +9528,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_11_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9557,7 +9557,7 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9572,7 +9572,7 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -9583,7 +9583,7 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9599,7 +9599,7 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -9610,7 +9610,7 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9719,7 +9719,7 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_12_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9748,7 +9748,7 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9763,7 +9763,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -9774,7 +9774,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9782,7 +9782,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -9790,7 +9790,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -9801,7 +9801,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9809,7 +9809,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -9832,7 +9832,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -9854,7 +9854,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_12_v4i32:
@@ -9873,7 +9873,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_12_v4i32:
@@ -9908,7 +9908,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_12_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9937,7 +9937,7 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9952,7 +9952,7 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -9963,7 +9963,7 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -9979,7 +9979,7 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -9990,7 +9990,7 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10099,7 +10099,7 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_13_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10128,7 +10128,7 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10143,7 +10143,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -10154,7 +10154,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10162,7 +10162,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -10170,7 +10170,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -10181,7 +10181,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10189,7 +10189,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -10212,7 +10212,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -10234,7 +10234,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_13_v4i32:
@@ -10253,7 +10253,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_13_v4i32:
@@ -10288,7 +10288,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_13_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10317,7 +10317,7 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10332,7 +10332,7 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -10343,7 +10343,7 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10359,7 +10359,7 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -10370,7 +10370,7 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10479,7 +10479,7 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_14_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10508,7 +10508,7 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10523,7 +10523,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -10534,7 +10534,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10542,7 +10542,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -10550,7 +10550,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -10561,7 +10561,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10569,7 +10569,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -10592,7 +10592,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -10614,7 +10614,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_14_v4i32:
@@ -10633,7 +10633,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_14_v4i32:
@@ -10668,7 +10668,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_14_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10697,7 +10697,7 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10712,7 +10712,7 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -10723,7 +10723,7 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10739,7 +10739,7 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -10750,7 +10750,7 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10859,7 +10859,7 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_15_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10888,7 +10888,7 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10903,7 +10903,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -10914,7 +10914,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10922,7 +10922,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -10930,7 +10930,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -10941,7 +10941,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -10949,7 +10949,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -10972,7 +10972,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -10994,7 +10994,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_15_v4i32:
@@ -11013,7 +11013,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_15_v4i32:
@@ -11048,7 +11048,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_15_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11077,7 +11077,7 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11092,7 +11092,7 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -11103,7 +11103,7 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11119,7 +11119,7 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -11130,7 +11130,7 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11239,7 +11239,7 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_16_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11268,7 +11268,7 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11283,7 +11283,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -11294,7 +11294,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11302,7 +11302,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -11310,7 +11310,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -11321,7 +11321,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11329,7 +11329,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -11352,7 +11352,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -11374,7 +11374,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_16_v4i32:
@@ -11393,7 +11393,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_16_v4i32:
@@ -11428,7 +11428,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_16_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11457,7 +11457,7 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11472,7 +11472,7 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -11483,7 +11483,7 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11499,7 +11499,7 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -11510,7 +11510,7 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11619,7 +11619,7 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_17_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11648,7 +11648,7 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11663,7 +11663,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -11674,7 +11674,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11682,7 +11682,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -11690,7 +11690,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -11701,7 +11701,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11709,7 +11709,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -11732,7 +11732,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -11754,7 +11754,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_17_v4i32:
@@ -11773,7 +11773,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_17_v4i32:
@@ -11808,7 +11808,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_17_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11837,7 +11837,7 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11852,7 +11852,7 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -11863,7 +11863,7 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11879,7 +11879,7 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -11890,7 +11890,7 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -11999,7 +11999,7 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_18_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12028,7 +12028,7 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12043,7 +12043,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -12054,7 +12054,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12062,7 +12062,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -12070,7 +12070,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -12081,7 +12081,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12089,7 +12089,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -12112,7 +12112,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -12134,7 +12134,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_18_v4i32:
@@ -12153,7 +12153,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_18_v4i32:
@@ -12188,7 +12188,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_18_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12217,7 +12217,7 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12232,7 +12232,7 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -12243,7 +12243,7 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12259,7 +12259,7 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -12270,7 +12270,7 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12379,7 +12379,7 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_19_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12408,7 +12408,7 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12423,7 +12423,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -12434,7 +12434,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12442,7 +12442,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -12450,7 +12450,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -12461,7 +12461,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12469,7 +12469,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -12492,7 +12492,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -12514,7 +12514,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_19_v4i32:
@@ -12533,7 +12533,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_19_v4i32:
@@ -12568,7 +12568,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_19_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12597,7 +12597,7 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12612,7 +12612,7 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -12623,7 +12623,7 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12639,7 +12639,7 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -12650,7 +12650,7 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12759,7 +12759,7 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_20_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12788,7 +12788,7 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12803,7 +12803,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -12814,7 +12814,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12822,7 +12822,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -12830,7 +12830,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -12841,7 +12841,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -12849,7 +12849,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -12872,7 +12872,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -12894,7 +12894,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_20_v4i32:
@@ -12913,7 +12913,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_20_v4i32:
@@ -12948,7 +12948,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_20_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12977,7 +12977,7 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12992,7 +12992,7 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -13003,7 +13003,7 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13019,7 +13019,7 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -13030,7 +13030,7 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13139,7 +13139,7 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_21_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13168,7 +13168,7 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13183,7 +13183,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -13194,7 +13194,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13202,7 +13202,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -13210,7 +13210,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -13221,7 +13221,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13229,7 +13229,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -13252,7 +13252,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -13274,7 +13274,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_21_v4i32:
@@ -13293,7 +13293,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_21_v4i32:
@@ -13328,7 +13328,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_21_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13357,7 +13357,7 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13372,7 +13372,7 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -13383,7 +13383,7 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13399,7 +13399,7 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -13410,7 +13410,7 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13519,7 +13519,7 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_22_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13548,7 +13548,7 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13563,7 +13563,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -13574,7 +13574,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13582,7 +13582,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -13590,7 +13590,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -13601,7 +13601,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13609,7 +13609,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -13632,7 +13632,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -13654,7 +13654,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_22_v4i32:
@@ -13673,7 +13673,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_22_v4i32:
@@ -13708,7 +13708,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_22_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13737,7 +13737,7 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13752,7 +13752,7 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -13763,7 +13763,7 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13779,7 +13779,7 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -13790,7 +13790,7 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13899,7 +13899,7 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_23_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13928,7 +13928,7 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13943,7 +13943,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -13954,7 +13954,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13962,7 +13962,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -13970,7 +13970,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -13981,7 +13981,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -13989,7 +13989,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -14012,7 +14012,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -14034,7 +14034,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_23_v4i32:
@@ -14053,7 +14053,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_23_v4i32:
@@ -14088,7 +14088,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_23_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14117,7 +14117,7 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14132,7 +14132,7 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -14143,7 +14143,7 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14159,7 +14159,7 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -14170,7 +14170,7 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14279,7 +14279,7 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_24_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14308,7 +14308,7 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14323,7 +14323,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -14334,7 +14334,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14342,7 +14342,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -14350,7 +14350,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -14361,7 +14361,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14369,7 +14369,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -14392,7 +14392,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -14414,7 +14414,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_24_v4i32:
@@ -14433,7 +14433,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_24_v4i32:
@@ -14468,7 +14468,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_24_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14497,7 +14497,7 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14512,7 +14512,7 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -14523,7 +14523,7 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14539,7 +14539,7 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -14550,7 +14550,7 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14659,7 +14659,7 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_25_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14688,7 +14688,7 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14703,7 +14703,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -14714,7 +14714,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14722,7 +14722,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -14730,7 +14730,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -14741,7 +14741,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14749,7 +14749,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -14772,7 +14772,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -14794,7 +14794,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_25_v4i32:
@@ -14813,7 +14813,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_25_v4i32:
@@ -14848,7 +14848,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_25_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14877,7 +14877,7 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14892,7 +14892,7 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -14903,7 +14903,7 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -14919,7 +14919,7 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -14930,7 +14930,7 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15039,7 +15039,7 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_26_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15068,7 +15068,7 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15083,7 +15083,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -15094,7 +15094,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15102,7 +15102,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -15110,7 +15110,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -15121,7 +15121,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15129,7 +15129,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -15152,7 +15152,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -15174,7 +15174,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_26_v4i32:
@@ -15193,7 +15193,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_26_v4i32:
@@ -15228,7 +15228,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_26_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15257,7 +15257,7 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15272,7 +15272,7 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -15283,7 +15283,7 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15299,7 +15299,7 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -15310,7 +15310,7 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15419,7 +15419,7 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_27_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15448,7 +15448,7 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15463,7 +15463,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -15474,7 +15474,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15482,7 +15482,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -15490,7 +15490,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -15501,7 +15501,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15509,7 +15509,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -15532,7 +15532,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -15554,7 +15554,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_27_v4i32:
@@ -15573,7 +15573,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_27_v4i32:
@@ -15608,7 +15608,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_27_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15637,7 +15637,7 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15652,7 +15652,7 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -15663,7 +15663,7 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15679,7 +15679,7 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -15690,7 +15690,7 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15799,7 +15799,7 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_28_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15828,7 +15828,7 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15843,7 +15843,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -15854,7 +15854,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15862,7 +15862,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -15870,7 +15870,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -15881,7 +15881,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -15889,7 +15889,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -15912,7 +15912,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -15934,7 +15934,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_28_v4i32:
@@ -15953,7 +15953,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_28_v4i32:
@@ -15988,7 +15988,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_28_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16017,7 +16017,7 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16032,7 +16032,7 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -16043,7 +16043,7 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16059,7 +16059,7 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -16070,7 +16070,7 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16179,7 +16179,7 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_29_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16208,7 +16208,7 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16223,7 +16223,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -16234,7 +16234,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16242,7 +16242,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -16250,7 +16250,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -16261,7 +16261,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16269,7 +16269,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -16292,7 +16292,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -16314,7 +16314,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_29_v4i32:
@@ -16333,7 +16333,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_29_v4i32:
@@ -16368,7 +16368,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_29_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16397,7 +16397,7 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16412,7 +16412,7 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -16423,7 +16423,7 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16439,7 +16439,7 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -16450,7 +16450,7 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16559,7 +16559,7 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_30_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16588,7 +16588,7 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16603,7 +16603,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -16614,7 +16614,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16622,7 +16622,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: packuswb %xmm2, %xmm1
-; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -16630,7 +16630,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -16641,7 +16641,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16649,7 +16649,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: packuswb %xmm2, %xmm1
-; SSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -16672,7 +16672,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSSE3-NEXT: psadbw %xmm0, %xmm1
; SSSE3-NEXT: packuswb %xmm2, %xmm1
-; SSSE3-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
+; SSSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: retq
;
@@ -16694,7 +16694,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; SSE41-NEXT: psadbw %xmm1, %xmm3
; SSE41-NEXT: psadbw %xmm1, %xmm0
; SSE41-NEXT: packuswb %xmm3, %xmm0
-; SSE41-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: ugt_30_v4i32:
@@ -16713,7 +16713,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_30_v4i32:
@@ -16748,7 +16748,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_30_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16777,7 +16777,7 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16792,7 +16792,7 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -16803,7 +16803,7 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16819,7 +16819,7 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -16830,7 +16830,7 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -16939,7 +16939,7 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_31_v4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16968,7 +16968,7 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
; BITALG-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; BITALG-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to4}, %xmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17054,14 +17054,14 @@ define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17166,7 +17166,7 @@ define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_2_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17199,7 +17199,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -17210,10 +17210,10 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483650,2147483650]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17229,7 +17229,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -17240,10 +17240,10 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483650,2147483650]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17269,7 +17269,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483650,2147483650]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17295,7 +17295,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483650,2147483650]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17319,7 +17319,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_2_v2i64:
@@ -17334,21 +17334,21 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_2_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_2_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17359,7 +17359,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -17368,7 +17368,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17383,7 +17383,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -17394,10 +17394,10 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17413,7 +17413,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -17424,10 +17424,10 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17453,7 +17453,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17479,7 +17479,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17535,7 +17535,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_3_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17556,7 +17556,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17571,7 +17571,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -17582,10 +17582,10 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17601,7 +17601,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -17612,10 +17612,10 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17641,7 +17641,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17667,7 +17667,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483651,2147483651]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17691,7 +17691,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_3_v2i64:
@@ -17706,21 +17706,21 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_3_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_3_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17731,7 +17731,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -17740,7 +17740,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17755,7 +17755,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -17766,10 +17766,10 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17785,7 +17785,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -17796,10 +17796,10 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17825,7 +17825,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17851,7 +17851,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -17907,7 +17907,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_4_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17928,7 +17928,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17943,7 +17943,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -17954,10 +17954,10 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -17973,7 +17973,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -17984,10 +17984,10 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18013,7 +18013,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18039,7 +18039,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483652,2147483652]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18063,7 +18063,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_4_v2i64:
@@ -18078,21 +18078,21 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_4_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_4_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18103,7 +18103,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -18112,7 +18112,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18127,7 +18127,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -18138,10 +18138,10 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18157,7 +18157,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -18168,10 +18168,10 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18197,7 +18197,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18223,7 +18223,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18279,7 +18279,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_5_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18300,7 +18300,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18315,7 +18315,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -18326,10 +18326,10 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18345,7 +18345,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -18356,10 +18356,10 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18385,7 +18385,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18411,7 +18411,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483653,2147483653]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18435,7 +18435,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_5_v2i64:
@@ -18450,21 +18450,21 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_5_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_5_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18475,7 +18475,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -18484,7 +18484,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18499,7 +18499,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -18510,10 +18510,10 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18529,7 +18529,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -18540,10 +18540,10 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18569,7 +18569,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18595,7 +18595,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18651,7 +18651,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_6_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18672,7 +18672,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18687,7 +18687,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -18698,10 +18698,10 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18717,7 +18717,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -18728,10 +18728,10 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18757,7 +18757,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18783,7 +18783,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483654,2147483654]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -18807,7 +18807,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_6_v2i64:
@@ -18822,21 +18822,21 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_6_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_6_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18847,7 +18847,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -18856,7 +18856,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18871,7 +18871,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -18882,10 +18882,10 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18901,7 +18901,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -18912,10 +18912,10 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18941,7 +18941,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -18967,7 +18967,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19023,7 +19023,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_7_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19044,7 +19044,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19059,7 +19059,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -19070,10 +19070,10 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19089,7 +19089,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -19100,10 +19100,10 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19129,7 +19129,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19155,7 +19155,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483655]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19179,7 +19179,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_7_v2i64:
@@ -19194,21 +19194,21 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_7_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_7_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19219,7 +19219,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -19228,7 +19228,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19243,7 +19243,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -19254,10 +19254,10 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19273,7 +19273,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -19284,10 +19284,10 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19313,7 +19313,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19339,7 +19339,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19395,7 +19395,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_8_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19416,7 +19416,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19431,7 +19431,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -19442,10 +19442,10 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19461,7 +19461,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -19472,10 +19472,10 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19501,7 +19501,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19527,7 +19527,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483656,2147483656]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19551,7 +19551,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_8_v2i64:
@@ -19566,21 +19566,21 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_8_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_8_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19591,7 +19591,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -19600,7 +19600,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19615,7 +19615,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -19626,10 +19626,10 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19645,7 +19645,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -19656,10 +19656,10 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19685,7 +19685,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19711,7 +19711,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -19767,7 +19767,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_9_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19788,7 +19788,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19803,7 +19803,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -19814,10 +19814,10 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19833,7 +19833,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -19844,10 +19844,10 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19873,7 +19873,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19899,7 +19899,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483657,2147483657]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -19923,7 +19923,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_9_v2i64:
@@ -19938,21 +19938,21 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_9_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_9_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19963,7 +19963,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -19972,7 +19972,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19987,7 +19987,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -19998,10 +19998,10 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20017,7 +20017,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -20028,10 +20028,10 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20057,7 +20057,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20083,7 +20083,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20139,7 +20139,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_10_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20160,7 +20160,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20175,7 +20175,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -20186,10 +20186,10 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20205,7 +20205,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -20216,10 +20216,10 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20245,7 +20245,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20271,7 +20271,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483658,2147483658]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20295,7 +20295,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_10_v2i64:
@@ -20310,21 +20310,21 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_10_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_10_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20335,7 +20335,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -20344,7 +20344,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20359,7 +20359,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -20370,10 +20370,10 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20389,7 +20389,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -20400,10 +20400,10 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20429,7 +20429,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20455,7 +20455,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20511,7 +20511,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_11_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20532,7 +20532,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20547,7 +20547,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -20558,10 +20558,10 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20577,7 +20577,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -20588,10 +20588,10 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20617,7 +20617,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20643,7 +20643,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483659,2147483659]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20667,7 +20667,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_11_v2i64:
@@ -20682,21 +20682,21 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_11_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_11_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20707,7 +20707,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -20716,7 +20716,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20731,7 +20731,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -20742,10 +20742,10 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20761,7 +20761,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -20772,10 +20772,10 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20801,7 +20801,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20827,7 +20827,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -20883,7 +20883,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_12_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20904,7 +20904,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20919,7 +20919,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -20930,10 +20930,10 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20949,7 +20949,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -20960,10 +20960,10 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -20989,7 +20989,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21015,7 +21015,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483660,2147483660]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21039,7 +21039,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_12_v2i64:
@@ -21054,21 +21054,21 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_12_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_12_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21079,7 +21079,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -21088,7 +21088,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21103,7 +21103,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -21114,10 +21114,10 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21133,7 +21133,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -21144,10 +21144,10 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21173,7 +21173,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21199,7 +21199,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21255,7 +21255,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_13_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21276,7 +21276,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21291,7 +21291,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -21302,10 +21302,10 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21321,7 +21321,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -21332,10 +21332,10 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21361,7 +21361,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21387,7 +21387,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483661,2147483661]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21411,7 +21411,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_13_v2i64:
@@ -21426,21 +21426,21 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_13_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_13_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21451,7 +21451,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -21460,7 +21460,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21475,7 +21475,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -21486,10 +21486,10 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21505,7 +21505,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -21516,10 +21516,10 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21545,7 +21545,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21571,7 +21571,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21627,7 +21627,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_14_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21648,7 +21648,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21663,7 +21663,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -21674,10 +21674,10 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21693,7 +21693,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -21704,10 +21704,10 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21733,7 +21733,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21759,7 +21759,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483662,2147483662]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -21783,7 +21783,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_14_v2i64:
@@ -21798,21 +21798,21 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_14_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_14_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21823,7 +21823,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -21832,7 +21832,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21847,7 +21847,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -21858,10 +21858,10 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21877,7 +21877,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -21888,10 +21888,10 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21917,7 +21917,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21943,7 +21943,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -21999,7 +21999,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_15_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22020,7 +22020,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22035,7 +22035,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -22046,10 +22046,10 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22065,7 +22065,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -22076,10 +22076,10 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22105,7 +22105,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22131,7 +22131,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483663,2147483663]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22155,7 +22155,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_15_v2i64:
@@ -22170,21 +22170,21 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_15_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_15_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22195,7 +22195,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -22204,7 +22204,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22219,7 +22219,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -22230,10 +22230,10 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22249,7 +22249,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -22260,10 +22260,10 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22289,7 +22289,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22315,7 +22315,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22371,7 +22371,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_16_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22392,7 +22392,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22407,7 +22407,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -22418,10 +22418,10 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22437,7 +22437,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -22448,10 +22448,10 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22477,7 +22477,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22503,7 +22503,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483664,2147483664]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22527,7 +22527,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_16_v2i64:
@@ -22542,21 +22542,21 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_16_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_16_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22567,7 +22567,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -22576,7 +22576,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22591,7 +22591,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -22602,10 +22602,10 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22621,7 +22621,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -22632,10 +22632,10 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22661,7 +22661,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22687,7 +22687,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22743,7 +22743,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_17_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22764,7 +22764,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22779,7 +22779,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -22790,10 +22790,10 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22809,7 +22809,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -22820,10 +22820,10 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22849,7 +22849,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22875,7 +22875,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483665,2147483665]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -22899,7 +22899,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_17_v2i64:
@@ -22914,21 +22914,21 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_17_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_17_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22939,7 +22939,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -22948,7 +22948,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22963,7 +22963,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -22974,10 +22974,10 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -22993,7 +22993,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -23004,10 +23004,10 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23033,7 +23033,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23059,7 +23059,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23115,7 +23115,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_18_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23136,7 +23136,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23151,7 +23151,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -23162,10 +23162,10 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23181,7 +23181,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -23192,10 +23192,10 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23221,7 +23221,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23247,7 +23247,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483666,2147483666]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23271,7 +23271,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_18_v2i64:
@@ -23286,21 +23286,21 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_18_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_18_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23311,7 +23311,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -23320,7 +23320,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23335,7 +23335,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -23346,10 +23346,10 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23365,7 +23365,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -23376,10 +23376,10 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23405,7 +23405,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23431,7 +23431,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23487,7 +23487,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_19_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23508,7 +23508,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23523,7 +23523,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -23534,10 +23534,10 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23553,7 +23553,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -23564,10 +23564,10 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23593,7 +23593,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23619,7 +23619,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483667,2147483667]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23643,7 +23643,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_19_v2i64:
@@ -23658,21 +23658,21 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_19_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_19_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23683,7 +23683,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -23692,7 +23692,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23707,7 +23707,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -23718,10 +23718,10 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23737,7 +23737,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -23748,10 +23748,10 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23777,7 +23777,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23803,7 +23803,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -23859,7 +23859,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_20_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23880,7 +23880,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23895,7 +23895,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -23906,10 +23906,10 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23925,7 +23925,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -23936,10 +23936,10 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23965,7 +23965,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -23991,7 +23991,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483668,2147483668]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24015,7 +24015,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_20_v2i64:
@@ -24030,21 +24030,21 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_20_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_20_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24055,7 +24055,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -24064,7 +24064,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24079,7 +24079,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -24090,10 +24090,10 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24109,7 +24109,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -24120,10 +24120,10 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24149,7 +24149,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24175,7 +24175,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24231,7 +24231,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_21_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24252,7 +24252,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24267,7 +24267,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -24278,10 +24278,10 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24297,7 +24297,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -24308,10 +24308,10 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24337,7 +24337,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24363,7 +24363,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483669,2147483669]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24387,7 +24387,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_21_v2i64:
@@ -24402,21 +24402,21 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_21_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_21_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24427,7 +24427,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -24436,7 +24436,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24451,7 +24451,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -24462,10 +24462,10 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24481,7 +24481,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -24492,10 +24492,10 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24521,7 +24521,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24547,7 +24547,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24603,7 +24603,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_22_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24624,7 +24624,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24639,7 +24639,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -24650,10 +24650,10 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24669,7 +24669,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -24680,10 +24680,10 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24709,7 +24709,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24735,7 +24735,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483670,2147483670]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -24759,7 +24759,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_22_v2i64:
@@ -24774,21 +24774,21 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_22_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_22_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24799,7 +24799,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -24808,7 +24808,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24823,7 +24823,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -24834,10 +24834,10 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24853,7 +24853,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -24864,10 +24864,10 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24893,7 +24893,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24919,7 +24919,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -24975,7 +24975,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_23_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24996,7 +24996,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25011,7 +25011,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -25022,10 +25022,10 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25041,7 +25041,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -25052,10 +25052,10 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25081,7 +25081,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25107,7 +25107,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483671,2147483671]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25131,7 +25131,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_23_v2i64:
@@ -25146,21 +25146,21 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_23_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_23_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25171,7 +25171,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -25180,7 +25180,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25195,7 +25195,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -25206,10 +25206,10 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25225,7 +25225,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -25236,10 +25236,10 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25265,7 +25265,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25291,7 +25291,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25347,7 +25347,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_24_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25368,7 +25368,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25383,7 +25383,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -25394,10 +25394,10 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25413,7 +25413,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -25424,10 +25424,10 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25453,7 +25453,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25479,7 +25479,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483672,2147483672]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25503,7 +25503,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_24_v2i64:
@@ -25518,21 +25518,21 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_24_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_24_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25543,7 +25543,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -25552,7 +25552,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25567,7 +25567,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -25578,10 +25578,10 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25597,7 +25597,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -25608,10 +25608,10 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25637,7 +25637,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25663,7 +25663,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25719,7 +25719,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_25_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25740,7 +25740,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25755,7 +25755,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -25766,10 +25766,10 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25785,7 +25785,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -25796,10 +25796,10 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25825,7 +25825,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25851,7 +25851,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483673,2147483673]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -25875,7 +25875,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_25_v2i64:
@@ -25890,21 +25890,21 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_25_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_25_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25915,7 +25915,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -25924,7 +25924,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25939,7 +25939,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -25950,10 +25950,10 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -25969,7 +25969,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -25980,10 +25980,10 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26009,7 +26009,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26035,7 +26035,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26091,7 +26091,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_26_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26112,7 +26112,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26127,7 +26127,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -26138,10 +26138,10 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26157,7 +26157,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -26168,10 +26168,10 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26197,7 +26197,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26223,7 +26223,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483674,2147483674]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26247,7 +26247,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_26_v2i64:
@@ -26262,21 +26262,21 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_26_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_26_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26287,7 +26287,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -26296,7 +26296,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26311,7 +26311,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -26322,10 +26322,10 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26341,7 +26341,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -26352,10 +26352,10 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26381,7 +26381,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26407,7 +26407,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26463,7 +26463,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_27_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26484,7 +26484,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26499,7 +26499,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -26510,10 +26510,10 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26529,7 +26529,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -26540,10 +26540,10 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26569,7 +26569,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26595,7 +26595,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483675,2147483675]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26619,7 +26619,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_27_v2i64:
@@ -26634,21 +26634,21 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_27_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_27_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26659,7 +26659,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -26668,7 +26668,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26683,7 +26683,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -26694,10 +26694,10 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26713,7 +26713,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -26724,10 +26724,10 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26753,7 +26753,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26779,7 +26779,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -26835,7 +26835,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_28_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26856,7 +26856,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26871,7 +26871,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -26882,10 +26882,10 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26901,7 +26901,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -26912,10 +26912,10 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26941,7 +26941,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26967,7 +26967,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483676,2147483676]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -26991,7 +26991,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_28_v2i64:
@@ -27006,21 +27006,21 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_28_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_28_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27031,7 +27031,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -27040,7 +27040,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27055,7 +27055,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -27066,10 +27066,10 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27085,7 +27085,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -27096,10 +27096,10 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27125,7 +27125,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27151,7 +27151,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27207,7 +27207,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_29_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27228,7 +27228,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27243,7 +27243,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -27254,10 +27254,10 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27273,7 +27273,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -27284,10 +27284,10 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27313,7 +27313,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27339,7 +27339,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483677,2147483677]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27363,7 +27363,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_29_v2i64:
@@ -27378,21 +27378,21 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_29_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_29_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27403,7 +27403,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -27412,7 +27412,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27427,7 +27427,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -27438,10 +27438,10 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27457,7 +27457,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -27468,10 +27468,10 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27497,7 +27497,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27523,7 +27523,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27579,7 +27579,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_30_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27600,7 +27600,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27615,7 +27615,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -27626,10 +27626,10 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27645,7 +27645,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -27656,10 +27656,10 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27685,7 +27685,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27711,7 +27711,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483678,2147483678]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -27735,7 +27735,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_30_v2i64:
@@ -27750,21 +27750,21 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_30_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_30_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27775,7 +27775,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -27784,7 +27784,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27799,7 +27799,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -27810,10 +27810,10 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27829,7 +27829,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -27840,10 +27840,10 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27869,7 +27869,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27895,7 +27895,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -27951,7 +27951,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_31_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27972,7 +27972,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27987,7 +27987,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -27998,10 +27998,10 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28017,7 +28017,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -28028,10 +28028,10 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28057,7 +28057,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28083,7 +28083,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483679,2147483679]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28107,7 +28107,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_31_v2i64:
@@ -28122,21 +28122,21 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_31_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_31_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28147,7 +28147,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -28156,7 +28156,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28171,7 +28171,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -28182,10 +28182,10 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28201,7 +28201,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -28212,10 +28212,10 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28241,7 +28241,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28267,7 +28267,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28323,7 +28323,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_32_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28344,7 +28344,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28359,7 +28359,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -28370,10 +28370,10 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28389,7 +28389,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -28400,10 +28400,10 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28429,7 +28429,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28455,7 +28455,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483680,2147483680]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28479,7 +28479,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_32_v2i64:
@@ -28494,21 +28494,21 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_32_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_32_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28519,7 +28519,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -28528,7 +28528,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28543,7 +28543,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -28554,10 +28554,10 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28573,7 +28573,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -28584,10 +28584,10 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28613,7 +28613,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28639,7 +28639,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28695,7 +28695,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_33_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28716,7 +28716,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28731,7 +28731,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -28742,10 +28742,10 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28761,7 +28761,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -28772,10 +28772,10 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28801,7 +28801,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28827,7 +28827,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483681,2147483681]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -28851,7 +28851,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_33_v2i64:
@@ -28866,21 +28866,21 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_33_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_33_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28891,7 +28891,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -28900,7 +28900,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28915,7 +28915,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -28926,10 +28926,10 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28945,7 +28945,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -28956,10 +28956,10 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -28985,7 +28985,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29011,7 +29011,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29067,7 +29067,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_34_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29088,7 +29088,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29103,7 +29103,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -29114,10 +29114,10 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29133,7 +29133,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -29144,10 +29144,10 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29173,7 +29173,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29199,7 +29199,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483682,2147483682]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29223,7 +29223,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_34_v2i64:
@@ -29238,21 +29238,21 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_34_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_34_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29263,7 +29263,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -29272,7 +29272,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29287,7 +29287,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -29298,10 +29298,10 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29317,7 +29317,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -29328,10 +29328,10 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29357,7 +29357,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29383,7 +29383,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29439,7 +29439,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_35_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29460,7 +29460,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29475,7 +29475,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -29486,10 +29486,10 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29505,7 +29505,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -29516,10 +29516,10 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29545,7 +29545,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29571,7 +29571,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483683,2147483683]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29595,7 +29595,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_35_v2i64:
@@ -29610,21 +29610,21 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_35_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_35_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29635,7 +29635,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -29644,7 +29644,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29659,7 +29659,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -29670,10 +29670,10 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29689,7 +29689,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -29700,10 +29700,10 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29729,7 +29729,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29755,7 +29755,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -29811,7 +29811,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_36_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29832,7 +29832,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29847,7 +29847,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -29858,10 +29858,10 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29877,7 +29877,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -29888,10 +29888,10 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29917,7 +29917,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29943,7 +29943,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483684,2147483684]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -29967,7 +29967,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_36_v2i64:
@@ -29982,21 +29982,21 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_36_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_36_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30007,7 +30007,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -30016,7 +30016,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30031,7 +30031,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -30042,10 +30042,10 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30061,7 +30061,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -30072,10 +30072,10 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30101,7 +30101,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30127,7 +30127,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30183,7 +30183,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_37_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30204,7 +30204,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30219,7 +30219,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -30230,10 +30230,10 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30249,7 +30249,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -30260,10 +30260,10 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30289,7 +30289,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30315,7 +30315,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483685,2147483685]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30339,7 +30339,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_37_v2i64:
@@ -30354,21 +30354,21 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_37_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_37_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30379,7 +30379,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -30388,7 +30388,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30403,7 +30403,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -30414,10 +30414,10 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30433,7 +30433,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -30444,10 +30444,10 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30473,7 +30473,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30499,7 +30499,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30555,7 +30555,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_38_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30576,7 +30576,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30591,7 +30591,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -30602,10 +30602,10 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30621,7 +30621,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -30632,10 +30632,10 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30661,7 +30661,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30687,7 +30687,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483686,2147483686]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30711,7 +30711,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_38_v2i64:
@@ -30726,21 +30726,21 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_38_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_38_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30751,7 +30751,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -30760,7 +30760,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30775,7 +30775,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -30786,10 +30786,10 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30805,7 +30805,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -30816,10 +30816,10 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30845,7 +30845,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30871,7 +30871,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -30927,7 +30927,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_39_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30948,7 +30948,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30963,7 +30963,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -30974,10 +30974,10 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -30993,7 +30993,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -31004,10 +31004,10 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31033,7 +31033,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31059,7 +31059,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483687,2147483687]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31083,7 +31083,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_39_v2i64:
@@ -31098,21 +31098,21 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_39_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_39_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31123,7 +31123,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -31132,7 +31132,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31147,7 +31147,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -31158,10 +31158,10 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31177,7 +31177,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -31188,10 +31188,10 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31217,7 +31217,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31243,7 +31243,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31299,7 +31299,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_40_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31320,7 +31320,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31335,7 +31335,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -31346,10 +31346,10 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31365,7 +31365,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -31376,10 +31376,10 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31405,7 +31405,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31431,7 +31431,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483688,2147483688]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31455,7 +31455,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_40_v2i64:
@@ -31470,21 +31470,21 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_40_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_40_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31495,7 +31495,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -31504,7 +31504,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31519,7 +31519,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -31530,10 +31530,10 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31549,7 +31549,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -31560,10 +31560,10 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31589,7 +31589,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31615,7 +31615,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31671,7 +31671,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_41_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31692,7 +31692,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31707,7 +31707,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -31718,10 +31718,10 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31737,7 +31737,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -31748,10 +31748,10 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31777,7 +31777,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31803,7 +31803,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483689,2147483689]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -31827,7 +31827,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_41_v2i64:
@@ -31842,21 +31842,21 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_41_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_41_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31867,7 +31867,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -31876,7 +31876,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31891,7 +31891,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -31902,10 +31902,10 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31921,7 +31921,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -31932,10 +31932,10 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31961,7 +31961,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -31987,7 +31987,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32043,7 +32043,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_42_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32064,7 +32064,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32079,7 +32079,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -32090,10 +32090,10 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32109,7 +32109,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -32120,10 +32120,10 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32149,7 +32149,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32175,7 +32175,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483690,2147483690]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32199,7 +32199,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_42_v2i64:
@@ -32214,21 +32214,21 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_42_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_42_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32239,7 +32239,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -32248,7 +32248,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32263,7 +32263,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -32274,10 +32274,10 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32293,7 +32293,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -32304,10 +32304,10 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32333,7 +32333,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32359,7 +32359,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32415,7 +32415,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_43_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32436,7 +32436,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32451,7 +32451,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -32462,10 +32462,10 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32481,7 +32481,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -32492,10 +32492,10 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32521,7 +32521,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32547,7 +32547,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483691,2147483691]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32571,7 +32571,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_43_v2i64:
@@ -32586,21 +32586,21 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_43_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_43_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32611,7 +32611,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -32620,7 +32620,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32635,7 +32635,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -32646,10 +32646,10 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32665,7 +32665,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -32676,10 +32676,10 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32705,7 +32705,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32731,7 +32731,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -32787,7 +32787,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_44_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32808,7 +32808,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32823,7 +32823,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -32834,10 +32834,10 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32853,7 +32853,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -32864,10 +32864,10 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32893,7 +32893,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32919,7 +32919,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483692,2147483692]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -32943,7 +32943,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_44_v2i64:
@@ -32958,21 +32958,21 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_44_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_44_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32983,7 +32983,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -32992,7 +32992,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33007,7 +33007,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -33018,10 +33018,10 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33037,7 +33037,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -33048,10 +33048,10 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33077,7 +33077,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33103,7 +33103,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33159,7 +33159,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_45_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33180,7 +33180,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33195,7 +33195,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -33206,10 +33206,10 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33225,7 +33225,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -33236,10 +33236,10 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33265,7 +33265,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33291,7 +33291,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483693,2147483693]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33315,7 +33315,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_45_v2i64:
@@ -33330,21 +33330,21 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_45_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_45_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33355,7 +33355,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -33364,7 +33364,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33379,7 +33379,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -33390,10 +33390,10 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33409,7 +33409,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -33420,10 +33420,10 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33449,7 +33449,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33475,7 +33475,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33531,7 +33531,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_46_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33552,7 +33552,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33567,7 +33567,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -33578,10 +33578,10 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33597,7 +33597,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -33608,10 +33608,10 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33637,7 +33637,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33663,7 +33663,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483694,2147483694]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33687,7 +33687,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_46_v2i64:
@@ -33702,21 +33702,21 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_46_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_46_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33727,7 +33727,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -33736,7 +33736,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33751,7 +33751,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -33762,10 +33762,10 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33781,7 +33781,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -33792,10 +33792,10 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33821,7 +33821,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33847,7 +33847,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -33903,7 +33903,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_47_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33924,7 +33924,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33939,7 +33939,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -33950,10 +33950,10 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -33969,7 +33969,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -33980,10 +33980,10 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34009,7 +34009,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34035,7 +34035,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483695,2147483695]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34059,7 +34059,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_47_v2i64:
@@ -34074,21 +34074,21 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_47_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_47_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34099,7 +34099,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -34108,7 +34108,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34123,7 +34123,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -34134,10 +34134,10 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34153,7 +34153,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -34164,10 +34164,10 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34193,7 +34193,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34219,7 +34219,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34275,7 +34275,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_48_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34296,7 +34296,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34311,7 +34311,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -34322,10 +34322,10 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34341,7 +34341,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -34352,10 +34352,10 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34381,7 +34381,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34407,7 +34407,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483696,2147483696]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34431,7 +34431,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_48_v2i64:
@@ -34446,21 +34446,21 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_48_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_48_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34471,7 +34471,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -34480,7 +34480,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34495,7 +34495,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -34506,10 +34506,10 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34525,7 +34525,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -34536,10 +34536,10 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34565,7 +34565,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34591,7 +34591,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34647,7 +34647,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_49_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34668,7 +34668,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34683,7 +34683,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -34694,10 +34694,10 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34713,7 +34713,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -34724,10 +34724,10 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34753,7 +34753,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34779,7 +34779,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483697,2147483697]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -34803,7 +34803,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_49_v2i64:
@@ -34818,21 +34818,21 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_49_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_49_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34843,7 +34843,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -34852,7 +34852,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34867,7 +34867,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -34878,10 +34878,10 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34897,7 +34897,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -34908,10 +34908,10 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34937,7 +34937,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -34963,7 +34963,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35019,7 +35019,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_50_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35040,7 +35040,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35055,7 +35055,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -35066,10 +35066,10 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35085,7 +35085,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -35096,10 +35096,10 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35125,7 +35125,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35151,7 +35151,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483698,2147483698]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35175,7 +35175,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_50_v2i64:
@@ -35190,21 +35190,21 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_50_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_50_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35215,7 +35215,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -35224,7 +35224,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35239,7 +35239,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -35250,10 +35250,10 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35269,7 +35269,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -35280,10 +35280,10 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35309,7 +35309,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35335,7 +35335,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35391,7 +35391,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_51_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35412,7 +35412,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35427,7 +35427,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -35438,10 +35438,10 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35457,7 +35457,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -35468,10 +35468,10 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35497,7 +35497,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35523,7 +35523,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483699,2147483699]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35547,7 +35547,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_51_v2i64:
@@ -35562,21 +35562,21 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_51_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_51_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35587,7 +35587,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -35596,7 +35596,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35611,7 +35611,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -35622,10 +35622,10 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35641,7 +35641,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -35652,10 +35652,10 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35681,7 +35681,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35707,7 +35707,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -35763,7 +35763,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_52_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35784,7 +35784,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35799,7 +35799,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -35810,10 +35810,10 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35829,7 +35829,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -35840,10 +35840,10 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35869,7 +35869,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35895,7 +35895,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483700,2147483700]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -35919,7 +35919,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_52_v2i64:
@@ -35934,21 +35934,21 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_52_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_52_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35959,7 +35959,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -35968,7 +35968,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35983,7 +35983,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -35994,10 +35994,10 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36013,7 +36013,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -36024,10 +36024,10 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36053,7 +36053,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36079,7 +36079,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36135,7 +36135,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_53_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36156,7 +36156,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36171,7 +36171,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -36182,10 +36182,10 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36201,7 +36201,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -36212,10 +36212,10 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36241,7 +36241,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36267,7 +36267,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483701,2147483701]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36291,7 +36291,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_53_v2i64:
@@ -36306,21 +36306,21 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_53_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_53_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36331,7 +36331,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -36340,7 +36340,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36355,7 +36355,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -36366,10 +36366,10 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36385,7 +36385,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -36396,10 +36396,10 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36425,7 +36425,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36451,7 +36451,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36507,7 +36507,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_54_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36528,7 +36528,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36543,7 +36543,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -36554,10 +36554,10 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36573,7 +36573,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -36584,10 +36584,10 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36613,7 +36613,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36639,7 +36639,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483702,2147483702]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36663,7 +36663,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_54_v2i64:
@@ -36678,21 +36678,21 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_54_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_54_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36703,7 +36703,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -36712,7 +36712,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36727,7 +36727,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -36738,10 +36738,10 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36757,7 +36757,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -36768,10 +36768,10 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36797,7 +36797,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36823,7 +36823,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -36879,7 +36879,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_55_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36900,7 +36900,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36915,7 +36915,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -36926,10 +36926,10 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36945,7 +36945,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -36956,10 +36956,10 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -36985,7 +36985,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37011,7 +37011,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483703,2147483703]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37035,7 +37035,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_55_v2i64:
@@ -37050,21 +37050,21 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_55_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_55_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37075,7 +37075,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -37084,7 +37084,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37099,7 +37099,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -37110,10 +37110,10 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37129,7 +37129,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -37140,10 +37140,10 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37169,7 +37169,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37195,7 +37195,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37251,7 +37251,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_56_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37272,7 +37272,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37287,7 +37287,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -37298,10 +37298,10 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37317,7 +37317,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -37328,10 +37328,10 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37357,7 +37357,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37383,7 +37383,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483704,2147483704]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37407,7 +37407,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_56_v2i64:
@@ -37422,21 +37422,21 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_56_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_56_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37447,7 +37447,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -37456,7 +37456,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37471,7 +37471,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -37482,10 +37482,10 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37501,7 +37501,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -37512,10 +37512,10 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37541,7 +37541,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37567,7 +37567,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37623,7 +37623,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_57_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37644,7 +37644,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37659,7 +37659,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -37670,10 +37670,10 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37689,7 +37689,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -37700,10 +37700,10 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37729,7 +37729,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37755,7 +37755,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483705,2147483705]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -37779,7 +37779,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_57_v2i64:
@@ -37794,21 +37794,21 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_57_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_57_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37819,7 +37819,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -37828,7 +37828,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37843,7 +37843,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -37854,10 +37854,10 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37873,7 +37873,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -37884,10 +37884,10 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37913,7 +37913,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37939,7 +37939,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -37995,7 +37995,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_58_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38016,7 +38016,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38031,7 +38031,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -38042,10 +38042,10 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38061,7 +38061,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -38072,10 +38072,10 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38101,7 +38101,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38127,7 +38127,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483706,2147483706]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38151,7 +38151,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_58_v2i64:
@@ -38166,21 +38166,21 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_58_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_58_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38191,7 +38191,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -38200,7 +38200,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38215,7 +38215,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -38226,10 +38226,10 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38245,7 +38245,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -38256,10 +38256,10 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38285,7 +38285,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38311,7 +38311,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38367,7 +38367,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_59_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38388,7 +38388,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38403,7 +38403,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -38414,10 +38414,10 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38433,7 +38433,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -38444,10 +38444,10 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38473,7 +38473,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38499,7 +38499,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483707,2147483707]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38523,7 +38523,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_59_v2i64:
@@ -38538,21 +38538,21 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_59_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_59_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38563,7 +38563,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -38572,7 +38572,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38587,7 +38587,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -38598,10 +38598,10 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38617,7 +38617,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -38628,10 +38628,10 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38657,7 +38657,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38683,7 +38683,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38739,7 +38739,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_60_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38760,7 +38760,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38775,7 +38775,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -38786,10 +38786,10 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38805,7 +38805,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -38816,10 +38816,10 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38845,7 +38845,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38871,7 +38871,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483708,2147483708]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -38895,7 +38895,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_60_v2i64:
@@ -38910,21 +38910,21 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_60_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_60_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38935,7 +38935,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -38944,7 +38944,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38959,7 +38959,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -38970,10 +38970,10 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -38989,7 +38989,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -39000,10 +39000,10 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39029,7 +39029,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39055,7 +39055,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39111,7 +39111,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_61_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39132,7 +39132,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39147,7 +39147,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -39158,10 +39158,10 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39177,7 +39177,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -39188,10 +39188,10 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39217,7 +39217,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39243,7 +39243,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483709,2147483709]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39267,7 +39267,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_61_v2i64:
@@ -39282,21 +39282,21 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_61_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_61_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39307,7 +39307,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -39316,7 +39316,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39331,7 +39331,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -39342,10 +39342,10 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39361,7 +39361,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -39372,10 +39372,10 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39401,7 +39401,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39427,7 +39427,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39483,7 +39483,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_62_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39504,7 +39504,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39519,7 +39519,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -39530,10 +39530,10 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39549,7 +39549,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -39560,10 +39560,10 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39589,7 +39589,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39615,7 +39615,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483710,2147483710]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
@@ -39639,7 +39639,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: ugt_62_v2i64:
@@ -39654,21 +39654,21 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_62_v2i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_62_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39679,7 +39679,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
; BITALG_NOVLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG_NOVLX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG_NOVLX-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
@@ -39688,7 +39688,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39703,7 +39703,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -39714,10 +39714,10 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm1, %xmm0
-; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483711,2147483711]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39733,7 +39733,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -39744,10 +39744,10 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm1, %xmm0
-; SSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483711,2147483711]
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39773,7 +39773,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; SSSE3-NEXT: paddb %xmm4, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: psadbw %xmm3, %xmm0
-; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483711,2147483711]
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39799,7 +39799,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: psadbw %xmm3, %xmm0
-; SSE41-NEXT: por {{.*}}(%rip), %xmm0
+; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2147483711,2147483711]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
@@ -39855,7 +39855,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_63_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39876,7 +39876,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-128.ll b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
index bb08e70a36830..07f192793afc2 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
@@ -15,7 +15,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -26,7 +26,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
@@ -36,7 +36,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -47,7 +47,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
@@ -150,7 +150,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -161,7 +161,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -176,7 +176,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -187,7 +187,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -321,7 +321,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -332,7 +332,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
@@ -343,7 +343,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -354,7 +354,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
@@ -465,7 +465,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -476,7 +476,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -484,7 +484,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -495,7 +495,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -764,14 +764,14 @@ define <2 x i64> @eq_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: eq_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: eq_1_v2i64:
@@ -895,7 +895,7 @@ define <2 x i64> @ne_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQ-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512VPOPCNTDQ-NEXT: vzeroupper
@@ -904,7 +904,7 @@ define <2 x i64> @ne_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ne_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -1128,14 +1128,14 @@ define <8 x i16> @eq_1_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: eq_1_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
%3 = icmp eq <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1210,7 +1210,7 @@ define <8 x i16> @ne_1_v8i16(<8 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; BITALG_NOVLX-NEXT: vzeroupper
@@ -1219,7 +1219,7 @@ define <8 x i16> @ne_1_v8i16(<8 x i16> %0) {
; BITALG-LABEL: ne_1_v8i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %xmm0, %xmm0
-; BITALG-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
+; BITALG-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
@@ -1255,14 +1255,14 @@ define <16 x i8> @eq_1_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vzeroupper
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: eq_1_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpeqb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp eq <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1337,7 +1337,7 @@ define <16 x i8> @ne_1_v16i8(<16 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG_NOVLX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG_NOVLX-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0
; BITALG_NOVLX-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; BITALG_NOVLX-NEXT: vzeroupper
@@ -1346,7 +1346,7 @@ define <16 x i8> @ne_1_v16i8(<16 x i8> %0) {
; BITALG-LABEL: ne_1_v16i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
-; BITALG-NEXT: vpcmpeqb {{.*}}(%rip), %xmm0, %xmm0
+; BITALG-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; BITALG-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
; BITALG-NEXT: retq
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll b/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
index 3c81a2d6c5c12..17fb2bfe197d9 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
@@ -59,13 +59,13 @@ define <32 x i8> @ugt_1_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_1_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -127,7 +127,7 @@ define <32 x i8> @ult_2_v32i8(<32 x i8> %0) {
; BITALG-LABEL: ult_2_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -172,7 +172,7 @@ define <32 x i8> @ugt_2_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -186,7 +186,7 @@ define <32 x i8> @ugt_2_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -200,7 +200,7 @@ define <32 x i8> @ugt_2_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -208,13 +208,13 @@ define <32 x i8> @ugt_2_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_2_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -259,7 +259,7 @@ define <32 x i8> @ult_3_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -273,7 +273,7 @@ define <32 x i8> @ult_3_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -287,7 +287,7 @@ define <32 x i8> @ult_3_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -302,7 +302,7 @@ define <32 x i8> @ult_3_v32i8(<32 x i8> %0) {
; BITALG-LABEL: ult_3_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -347,7 +347,7 @@ define <32 x i8> @ugt_3_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -361,7 +361,7 @@ define <32 x i8> @ugt_3_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -375,7 +375,7 @@ define <32 x i8> @ugt_3_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -383,13 +383,13 @@ define <32 x i8> @ugt_3_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_3_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -434,7 +434,7 @@ define <32 x i8> @ult_4_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -448,7 +448,7 @@ define <32 x i8> @ult_4_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -462,7 +462,7 @@ define <32 x i8> @ult_4_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -477,7 +477,7 @@ define <32 x i8> @ult_4_v32i8(<32 x i8> %0) {
; BITALG-LABEL: ult_4_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -522,7 +522,7 @@ define <32 x i8> @ugt_4_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -536,7 +536,7 @@ define <32 x i8> @ugt_4_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -550,7 +550,7 @@ define <32 x i8> @ugt_4_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -558,13 +558,13 @@ define <32 x i8> @ugt_4_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_4_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -609,7 +609,7 @@ define <32 x i8> @ult_5_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -623,7 +623,7 @@ define <32 x i8> @ult_5_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -637,7 +637,7 @@ define <32 x i8> @ult_5_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -652,7 +652,7 @@ define <32 x i8> @ult_5_v32i8(<32 x i8> %0) {
; BITALG-LABEL: ult_5_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -697,7 +697,7 @@ define <32 x i8> @ugt_5_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -711,7 +711,7 @@ define <32 x i8> @ugt_5_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -725,7 +725,7 @@ define <32 x i8> @ugt_5_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -733,13 +733,13 @@ define <32 x i8> @ugt_5_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_5_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -784,7 +784,7 @@ define <32 x i8> @ult_6_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -798,7 +798,7 @@ define <32 x i8> @ult_6_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -812,7 +812,7 @@ define <32 x i8> @ult_6_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -827,7 +827,7 @@ define <32 x i8> @ult_6_v32i8(<32 x i8> %0) {
; BITALG-LABEL: ult_6_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -872,7 +872,7 @@ define <32 x i8> @ugt_6_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -886,7 +886,7 @@ define <32 x i8> @ugt_6_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -900,7 +900,7 @@ define <32 x i8> @ugt_6_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -908,13 +908,13 @@ define <32 x i8> @ugt_6_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_6_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -959,7 +959,7 @@ define <32 x i8> @ult_7_v32i8(<32 x i8> %0) {
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -973,7 +973,7 @@ define <32 x i8> @ult_7_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQ-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -987,7 +987,7 @@ define <32 x i8> @ult_7_v32i8(<32 x i8> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpminub {{.*}}(%rip), %ymm0, %ymm1
+; AVX512VPOPCNTDQVL-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
@@ -1002,7 +1002,7 @@ define <32 x i8> @ult_7_v32i8(<32 x i8> %0) {
; BITALG-LABEL: ult_7_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
@@ -1063,13 +1063,13 @@ define <16 x i16> @ugt_1_v16i16(<16 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_1_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1131,7 +1131,7 @@ define <16 x i16> @ult_2_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_2_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1183,7 +1183,7 @@ define <16 x i16> @ugt_2_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_2_v16i16:
@@ -1191,7 +1191,7 @@ define <16 x i16> @ugt_2_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_2_v16i16:
@@ -1199,20 +1199,20 @@ define <16 x i16> @ugt_2_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_2_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_2_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1297,7 +1297,7 @@ define <16 x i16> @ult_3_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_3_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1349,7 +1349,7 @@ define <16 x i16> @ugt_3_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_3_v16i16:
@@ -1357,7 +1357,7 @@ define <16 x i16> @ugt_3_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_3_v16i16:
@@ -1365,20 +1365,20 @@ define <16 x i16> @ugt_3_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_3_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_3_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1463,7 +1463,7 @@ define <16 x i16> @ult_4_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_4_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1515,7 +1515,7 @@ define <16 x i16> @ugt_4_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_4_v16i16:
@@ -1523,7 +1523,7 @@ define <16 x i16> @ugt_4_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_4_v16i16:
@@ -1531,20 +1531,20 @@ define <16 x i16> @ugt_4_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_4_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_4_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1629,7 +1629,7 @@ define <16 x i16> @ult_5_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_5_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1681,7 +1681,7 @@ define <16 x i16> @ugt_5_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_5_v16i16:
@@ -1689,7 +1689,7 @@ define <16 x i16> @ugt_5_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_5_v16i16:
@@ -1697,20 +1697,20 @@ define <16 x i16> @ugt_5_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_5_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_5_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1795,7 +1795,7 @@ define <16 x i16> @ult_6_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_6_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1847,7 +1847,7 @@ define <16 x i16> @ugt_6_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_6_v16i16:
@@ -1855,7 +1855,7 @@ define <16 x i16> @ugt_6_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_6_v16i16:
@@ -1863,20 +1863,20 @@ define <16 x i16> @ugt_6_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_6_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_6_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -1961,7 +1961,7 @@ define <16 x i16> @ult_7_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_7_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2013,7 +2013,7 @@ define <16 x i16> @ugt_7_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_7_v16i16:
@@ -2021,7 +2021,7 @@ define <16 x i16> @ugt_7_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_7_v16i16:
@@ -2029,20 +2029,20 @@ define <16 x i16> @ugt_7_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_7_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_7_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2127,7 +2127,7 @@ define <16 x i16> @ult_8_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_8_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2179,7 +2179,7 @@ define <16 x i16> @ugt_8_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_8_v16i16:
@@ -2187,7 +2187,7 @@ define <16 x i16> @ugt_8_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_8_v16i16:
@@ -2195,20 +2195,20 @@ define <16 x i16> @ugt_8_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_8_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_8_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2293,7 +2293,7 @@ define <16 x i16> @ult_9_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_9_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2345,7 +2345,7 @@ define <16 x i16> @ugt_9_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_9_v16i16:
@@ -2353,7 +2353,7 @@ define <16 x i16> @ugt_9_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_9_v16i16:
@@ -2361,20 +2361,20 @@ define <16 x i16> @ugt_9_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_9_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_9_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2459,7 +2459,7 @@ define <16 x i16> @ult_10_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_10_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2511,7 +2511,7 @@ define <16 x i16> @ugt_10_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_10_v16i16:
@@ -2519,7 +2519,7 @@ define <16 x i16> @ugt_10_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_10_v16i16:
@@ -2527,20 +2527,20 @@ define <16 x i16> @ugt_10_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_10_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_10_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2625,7 +2625,7 @@ define <16 x i16> @ult_11_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_11_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2677,7 +2677,7 @@ define <16 x i16> @ugt_11_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_11_v16i16:
@@ -2685,7 +2685,7 @@ define <16 x i16> @ugt_11_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_11_v16i16:
@@ -2693,20 +2693,20 @@ define <16 x i16> @ugt_11_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_11_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_11_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2791,7 +2791,7 @@ define <16 x i16> @ult_12_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_12_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2843,7 +2843,7 @@ define <16 x i16> @ugt_12_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_12_v16i16:
@@ -2851,7 +2851,7 @@ define <16 x i16> @ugt_12_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_12_v16i16:
@@ -2859,20 +2859,20 @@ define <16 x i16> @ugt_12_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_12_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_12_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -2957,7 +2957,7 @@ define <16 x i16> @ult_13_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_13_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -3009,7 +3009,7 @@ define <16 x i16> @ugt_13_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_13_v16i16:
@@ -3017,7 +3017,7 @@ define <16 x i16> @ugt_13_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_13_v16i16:
@@ -3025,20 +3025,20 @@ define <16 x i16> @ugt_13_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_13_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_13_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -3123,7 +3123,7 @@ define <16 x i16> @ult_14_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_14_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -3175,7 +3175,7 @@ define <16 x i16> @ugt_14_v16i16(<16 x i16> %0) {
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_14_v16i16:
@@ -3183,7 +3183,7 @@ define <16 x i16> @ugt_14_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQ-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: ugt_14_v16i16:
@@ -3191,20 +3191,20 @@ define <16 x i16> @ugt_14_v16i16(<16 x i16> %0) {
; AVX512VPOPCNTDQVL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQVL-NEXT: vpmovdw %zmm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VPOPCNTDQVL-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: ugt_14_v16i16:
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpgtw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: ugt_14_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -3289,7 +3289,7 @@ define <16 x i16> @ult_15_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ult_15_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %ymm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -3336,7 +3336,7 @@ define <8 x i32> @ugt_1_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_1_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -3402,7 +3402,7 @@ define <8 x i32> @ult_2_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_2_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -3496,7 +3496,7 @@ define <8 x i32> @ugt_2_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_2_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -3524,7 +3524,7 @@ define <8 x i32> @ugt_2_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -3600,7 +3600,7 @@ define <8 x i32> @ult_3_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_3_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -3628,7 +3628,7 @@ define <8 x i32> @ult_3_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -3704,7 +3704,7 @@ define <8 x i32> @ugt_3_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_3_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -3732,7 +3732,7 @@ define <8 x i32> @ugt_3_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -3808,7 +3808,7 @@ define <8 x i32> @ult_4_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_4_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -3836,7 +3836,7 @@ define <8 x i32> @ult_4_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -3912,7 +3912,7 @@ define <8 x i32> @ugt_4_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_4_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -3940,7 +3940,7 @@ define <8 x i32> @ugt_4_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4016,7 +4016,7 @@ define <8 x i32> @ult_5_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_5_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4044,7 +4044,7 @@ define <8 x i32> @ult_5_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4120,7 +4120,7 @@ define <8 x i32> @ugt_5_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_5_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4148,7 +4148,7 @@ define <8 x i32> @ugt_5_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4224,7 +4224,7 @@ define <8 x i32> @ult_6_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_6_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4252,7 +4252,7 @@ define <8 x i32> @ult_6_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4328,7 +4328,7 @@ define <8 x i32> @ugt_6_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_6_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4356,7 +4356,7 @@ define <8 x i32> @ugt_6_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4432,7 +4432,7 @@ define <8 x i32> @ult_7_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_7_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4460,7 +4460,7 @@ define <8 x i32> @ult_7_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4536,7 +4536,7 @@ define <8 x i32> @ugt_7_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_7_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4564,7 +4564,7 @@ define <8 x i32> @ugt_7_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4640,7 +4640,7 @@ define <8 x i32> @ult_8_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_8_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4668,7 +4668,7 @@ define <8 x i32> @ult_8_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4744,7 +4744,7 @@ define <8 x i32> @ugt_8_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_8_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4772,7 +4772,7 @@ define <8 x i32> @ugt_8_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4848,7 +4848,7 @@ define <8 x i32> @ult_9_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_9_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4876,7 +4876,7 @@ define <8 x i32> @ult_9_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -4952,7 +4952,7 @@ define <8 x i32> @ugt_9_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_9_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -4980,7 +4980,7 @@ define <8 x i32> @ugt_9_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5056,7 +5056,7 @@ define <8 x i32> @ult_10_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_10_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5084,7 +5084,7 @@ define <8 x i32> @ult_10_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5160,7 +5160,7 @@ define <8 x i32> @ugt_10_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_10_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5188,7 +5188,7 @@ define <8 x i32> @ugt_10_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5264,7 +5264,7 @@ define <8 x i32> @ult_11_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_11_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5292,7 +5292,7 @@ define <8 x i32> @ult_11_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5368,7 +5368,7 @@ define <8 x i32> @ugt_11_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_11_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5396,7 +5396,7 @@ define <8 x i32> @ugt_11_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5472,7 +5472,7 @@ define <8 x i32> @ult_12_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_12_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5500,7 +5500,7 @@ define <8 x i32> @ult_12_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5576,7 +5576,7 @@ define <8 x i32> @ugt_12_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_12_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5604,7 +5604,7 @@ define <8 x i32> @ugt_12_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5680,7 +5680,7 @@ define <8 x i32> @ult_13_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_13_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5708,7 +5708,7 @@ define <8 x i32> @ult_13_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5784,7 +5784,7 @@ define <8 x i32> @ugt_13_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_13_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5812,7 +5812,7 @@ define <8 x i32> @ugt_13_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5888,7 +5888,7 @@ define <8 x i32> @ult_14_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_14_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -5916,7 +5916,7 @@ define <8 x i32> @ult_14_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -5992,7 +5992,7 @@ define <8 x i32> @ugt_14_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_14_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6020,7 +6020,7 @@ define <8 x i32> @ugt_14_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6096,7 +6096,7 @@ define <8 x i32> @ult_15_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_15_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6124,7 +6124,7 @@ define <8 x i32> @ult_15_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6200,7 +6200,7 @@ define <8 x i32> @ugt_15_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_15_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6228,7 +6228,7 @@ define <8 x i32> @ugt_15_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6304,7 +6304,7 @@ define <8 x i32> @ult_16_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_16_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6332,7 +6332,7 @@ define <8 x i32> @ult_16_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6408,7 +6408,7 @@ define <8 x i32> @ugt_16_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_16_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6436,7 +6436,7 @@ define <8 x i32> @ugt_16_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6512,7 +6512,7 @@ define <8 x i32> @ult_17_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_17_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6540,7 +6540,7 @@ define <8 x i32> @ult_17_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6616,7 +6616,7 @@ define <8 x i32> @ugt_17_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_17_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6644,7 +6644,7 @@ define <8 x i32> @ugt_17_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6720,7 +6720,7 @@ define <8 x i32> @ult_18_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_18_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6748,7 +6748,7 @@ define <8 x i32> @ult_18_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6824,7 +6824,7 @@ define <8 x i32> @ugt_18_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_18_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6852,7 +6852,7 @@ define <8 x i32> @ugt_18_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -6928,7 +6928,7 @@ define <8 x i32> @ult_19_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_19_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -6956,7 +6956,7 @@ define <8 x i32> @ult_19_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7032,7 +7032,7 @@ define <8 x i32> @ugt_19_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_19_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7060,7 +7060,7 @@ define <8 x i32> @ugt_19_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7136,7 +7136,7 @@ define <8 x i32> @ult_20_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_20_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7164,7 +7164,7 @@ define <8 x i32> @ult_20_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7240,7 +7240,7 @@ define <8 x i32> @ugt_20_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_20_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7268,7 +7268,7 @@ define <8 x i32> @ugt_20_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7344,7 +7344,7 @@ define <8 x i32> @ult_21_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_21_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7372,7 +7372,7 @@ define <8 x i32> @ult_21_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7448,7 +7448,7 @@ define <8 x i32> @ugt_21_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_21_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7476,7 +7476,7 @@ define <8 x i32> @ugt_21_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7552,7 +7552,7 @@ define <8 x i32> @ult_22_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_22_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7580,7 +7580,7 @@ define <8 x i32> @ult_22_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7656,7 +7656,7 @@ define <8 x i32> @ugt_22_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_22_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7684,7 +7684,7 @@ define <8 x i32> @ugt_22_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7760,7 +7760,7 @@ define <8 x i32> @ult_23_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_23_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7788,7 +7788,7 @@ define <8 x i32> @ult_23_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7864,7 +7864,7 @@ define <8 x i32> @ugt_23_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_23_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7892,7 +7892,7 @@ define <8 x i32> @ugt_23_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -7968,7 +7968,7 @@ define <8 x i32> @ult_24_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_24_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -7996,7 +7996,7 @@ define <8 x i32> @ult_24_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8072,7 +8072,7 @@ define <8 x i32> @ugt_24_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_24_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8100,7 +8100,7 @@ define <8 x i32> @ugt_24_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8176,7 +8176,7 @@ define <8 x i32> @ult_25_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_25_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8204,7 +8204,7 @@ define <8 x i32> @ult_25_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8280,7 +8280,7 @@ define <8 x i32> @ugt_25_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_25_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8308,7 +8308,7 @@ define <8 x i32> @ugt_25_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8384,7 +8384,7 @@ define <8 x i32> @ult_26_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_26_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8412,7 +8412,7 @@ define <8 x i32> @ult_26_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8488,7 +8488,7 @@ define <8 x i32> @ugt_26_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_26_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8516,7 +8516,7 @@ define <8 x i32> @ugt_26_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8592,7 +8592,7 @@ define <8 x i32> @ult_27_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_27_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8620,7 +8620,7 @@ define <8 x i32> @ult_27_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8696,7 +8696,7 @@ define <8 x i32> @ugt_27_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_27_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8724,7 +8724,7 @@ define <8 x i32> @ugt_27_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8800,7 +8800,7 @@ define <8 x i32> @ult_28_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_28_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8828,7 +8828,7 @@ define <8 x i32> @ult_28_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -8904,7 +8904,7 @@ define <8 x i32> @ugt_28_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_28_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -8932,7 +8932,7 @@ define <8 x i32> @ugt_28_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9008,7 +9008,7 @@ define <8 x i32> @ult_29_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_29_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9036,7 +9036,7 @@ define <8 x i32> @ult_29_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9112,7 +9112,7 @@ define <8 x i32> @ugt_29_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_29_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9140,7 +9140,7 @@ define <8 x i32> @ugt_29_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9216,7 +9216,7 @@ define <8 x i32> @ult_30_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_30_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9244,7 +9244,7 @@ define <8 x i32> @ult_30_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9320,7 +9320,7 @@ define <8 x i32> @ugt_30_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_30_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9348,7 +9348,7 @@ define <8 x i32> @ugt_30_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9424,7 +9424,7 @@ define <8 x i32> @ult_31_v8i32(<8 x i32> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_31_v8i32:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntd %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9452,7 +9452,7 @@ define <8 x i32> @ult_31_v8i32(<8 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to8}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9500,7 +9500,7 @@ define <4 x i64> @ugt_1_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_1_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9566,7 +9566,7 @@ define <4 x i64> @ult_2_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_2_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9648,7 +9648,7 @@ define <4 x i64> @ugt_2_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_2_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9668,7 +9668,7 @@ define <4 x i64> @ugt_2_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9732,7 +9732,7 @@ define <4 x i64> @ult_3_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_3_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9752,7 +9752,7 @@ define <4 x i64> @ult_3_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9816,7 +9816,7 @@ define <4 x i64> @ugt_3_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_3_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9836,7 +9836,7 @@ define <4 x i64> @ugt_3_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9900,7 +9900,7 @@ define <4 x i64> @ult_4_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_4_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -9920,7 +9920,7 @@ define <4 x i64> @ult_4_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -9984,7 +9984,7 @@ define <4 x i64> @ugt_4_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_4_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10004,7 +10004,7 @@ define <4 x i64> @ugt_4_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10068,7 +10068,7 @@ define <4 x i64> @ult_5_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_5_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10088,7 +10088,7 @@ define <4 x i64> @ult_5_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10152,7 +10152,7 @@ define <4 x i64> @ugt_5_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_5_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10172,7 +10172,7 @@ define <4 x i64> @ugt_5_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10236,7 +10236,7 @@ define <4 x i64> @ult_6_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_6_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10256,7 +10256,7 @@ define <4 x i64> @ult_6_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10320,7 +10320,7 @@ define <4 x i64> @ugt_6_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_6_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10340,7 +10340,7 @@ define <4 x i64> @ugt_6_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10404,7 +10404,7 @@ define <4 x i64> @ult_7_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_7_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10424,7 +10424,7 @@ define <4 x i64> @ult_7_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10488,7 +10488,7 @@ define <4 x i64> @ugt_7_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_7_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10508,7 +10508,7 @@ define <4 x i64> @ugt_7_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10572,7 +10572,7 @@ define <4 x i64> @ult_8_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_8_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10592,7 +10592,7 @@ define <4 x i64> @ult_8_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10656,7 +10656,7 @@ define <4 x i64> @ugt_8_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_8_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10676,7 +10676,7 @@ define <4 x i64> @ugt_8_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10740,7 +10740,7 @@ define <4 x i64> @ult_9_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_9_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10760,7 +10760,7 @@ define <4 x i64> @ult_9_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10824,7 +10824,7 @@ define <4 x i64> @ugt_9_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_9_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10844,7 +10844,7 @@ define <4 x i64> @ugt_9_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10908,7 +10908,7 @@ define <4 x i64> @ult_10_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_10_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -10928,7 +10928,7 @@ define <4 x i64> @ult_10_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -10992,7 +10992,7 @@ define <4 x i64> @ugt_10_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_10_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11012,7 +11012,7 @@ define <4 x i64> @ugt_10_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11076,7 +11076,7 @@ define <4 x i64> @ult_11_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_11_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11096,7 +11096,7 @@ define <4 x i64> @ult_11_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11160,7 +11160,7 @@ define <4 x i64> @ugt_11_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_11_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11180,7 +11180,7 @@ define <4 x i64> @ugt_11_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11244,7 +11244,7 @@ define <4 x i64> @ult_12_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_12_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11264,7 +11264,7 @@ define <4 x i64> @ult_12_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11328,7 +11328,7 @@ define <4 x i64> @ugt_12_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_12_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11348,7 +11348,7 @@ define <4 x i64> @ugt_12_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11412,7 +11412,7 @@ define <4 x i64> @ult_13_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_13_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11432,7 +11432,7 @@ define <4 x i64> @ult_13_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11496,7 +11496,7 @@ define <4 x i64> @ugt_13_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_13_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11516,7 +11516,7 @@ define <4 x i64> @ugt_13_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11580,7 +11580,7 @@ define <4 x i64> @ult_14_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_14_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11600,7 +11600,7 @@ define <4 x i64> @ult_14_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11664,7 +11664,7 @@ define <4 x i64> @ugt_14_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_14_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11684,7 +11684,7 @@ define <4 x i64> @ugt_14_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11748,7 +11748,7 @@ define <4 x i64> @ult_15_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_15_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11768,7 +11768,7 @@ define <4 x i64> @ult_15_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11832,7 +11832,7 @@ define <4 x i64> @ugt_15_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_15_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11852,7 +11852,7 @@ define <4 x i64> @ugt_15_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -11916,7 +11916,7 @@ define <4 x i64> @ult_16_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_16_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -11936,7 +11936,7 @@ define <4 x i64> @ult_16_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12000,7 +12000,7 @@ define <4 x i64> @ugt_16_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_16_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12020,7 +12020,7 @@ define <4 x i64> @ugt_16_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12084,7 +12084,7 @@ define <4 x i64> @ult_17_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_17_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12104,7 +12104,7 @@ define <4 x i64> @ult_17_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12168,7 +12168,7 @@ define <4 x i64> @ugt_17_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_17_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12188,7 +12188,7 @@ define <4 x i64> @ugt_17_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12252,7 +12252,7 @@ define <4 x i64> @ult_18_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_18_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12272,7 +12272,7 @@ define <4 x i64> @ult_18_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12336,7 +12336,7 @@ define <4 x i64> @ugt_18_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_18_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12356,7 +12356,7 @@ define <4 x i64> @ugt_18_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12420,7 +12420,7 @@ define <4 x i64> @ult_19_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_19_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12440,7 +12440,7 @@ define <4 x i64> @ult_19_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12504,7 +12504,7 @@ define <4 x i64> @ugt_19_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_19_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12524,7 +12524,7 @@ define <4 x i64> @ugt_19_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12588,7 +12588,7 @@ define <4 x i64> @ult_20_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_20_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12608,7 +12608,7 @@ define <4 x i64> @ult_20_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12672,7 +12672,7 @@ define <4 x i64> @ugt_20_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_20_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12692,7 +12692,7 @@ define <4 x i64> @ugt_20_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12756,7 +12756,7 @@ define <4 x i64> @ult_21_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_21_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12776,7 +12776,7 @@ define <4 x i64> @ult_21_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12840,7 +12840,7 @@ define <4 x i64> @ugt_21_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_21_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12860,7 +12860,7 @@ define <4 x i64> @ugt_21_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -12924,7 +12924,7 @@ define <4 x i64> @ult_22_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_22_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -12944,7 +12944,7 @@ define <4 x i64> @ult_22_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13008,7 +13008,7 @@ define <4 x i64> @ugt_22_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_22_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13028,7 +13028,7 @@ define <4 x i64> @ugt_22_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13092,7 +13092,7 @@ define <4 x i64> @ult_23_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_23_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13112,7 +13112,7 @@ define <4 x i64> @ult_23_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13176,7 +13176,7 @@ define <4 x i64> @ugt_23_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_23_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13196,7 +13196,7 @@ define <4 x i64> @ugt_23_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13260,7 +13260,7 @@ define <4 x i64> @ult_24_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_24_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13280,7 +13280,7 @@ define <4 x i64> @ult_24_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13344,7 +13344,7 @@ define <4 x i64> @ugt_24_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_24_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13364,7 +13364,7 @@ define <4 x i64> @ugt_24_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13428,7 +13428,7 @@ define <4 x i64> @ult_25_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_25_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13448,7 +13448,7 @@ define <4 x i64> @ult_25_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13512,7 +13512,7 @@ define <4 x i64> @ugt_25_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_25_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13532,7 +13532,7 @@ define <4 x i64> @ugt_25_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13596,7 +13596,7 @@ define <4 x i64> @ult_26_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_26_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13616,7 +13616,7 @@ define <4 x i64> @ult_26_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13680,7 +13680,7 @@ define <4 x i64> @ugt_26_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_26_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13700,7 +13700,7 @@ define <4 x i64> @ugt_26_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13764,7 +13764,7 @@ define <4 x i64> @ult_27_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_27_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13784,7 +13784,7 @@ define <4 x i64> @ult_27_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13848,7 +13848,7 @@ define <4 x i64> @ugt_27_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_27_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13868,7 +13868,7 @@ define <4 x i64> @ugt_27_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -13932,7 +13932,7 @@ define <4 x i64> @ult_28_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_28_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -13952,7 +13952,7 @@ define <4 x i64> @ult_28_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14016,7 +14016,7 @@ define <4 x i64> @ugt_28_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_28_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14036,7 +14036,7 @@ define <4 x i64> @ugt_28_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14100,7 +14100,7 @@ define <4 x i64> @ult_29_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_29_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14120,7 +14120,7 @@ define <4 x i64> @ult_29_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14184,7 +14184,7 @@ define <4 x i64> @ugt_29_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_29_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14204,7 +14204,7 @@ define <4 x i64> @ugt_29_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14268,7 +14268,7 @@ define <4 x i64> @ult_30_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_30_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14288,7 +14288,7 @@ define <4 x i64> @ult_30_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14352,7 +14352,7 @@ define <4 x i64> @ugt_30_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_30_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14372,7 +14372,7 @@ define <4 x i64> @ugt_30_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14436,7 +14436,7 @@ define <4 x i64> @ult_31_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_31_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14456,7 +14456,7 @@ define <4 x i64> @ult_31_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14520,7 +14520,7 @@ define <4 x i64> @ugt_31_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_31_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14540,7 +14540,7 @@ define <4 x i64> @ugt_31_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14604,7 +14604,7 @@ define <4 x i64> @ult_32_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_32_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14624,7 +14624,7 @@ define <4 x i64> @ult_32_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14688,7 +14688,7 @@ define <4 x i64> @ugt_32_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_32_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14708,7 +14708,7 @@ define <4 x i64> @ugt_32_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14772,7 +14772,7 @@ define <4 x i64> @ult_33_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_33_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14792,7 +14792,7 @@ define <4 x i64> @ult_33_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14856,7 +14856,7 @@ define <4 x i64> @ugt_33_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_33_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14876,7 +14876,7 @@ define <4 x i64> @ugt_33_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -14940,7 +14940,7 @@ define <4 x i64> @ult_34_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_34_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -14960,7 +14960,7 @@ define <4 x i64> @ult_34_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15024,7 +15024,7 @@ define <4 x i64> @ugt_34_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_34_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15044,7 +15044,7 @@ define <4 x i64> @ugt_34_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15108,7 +15108,7 @@ define <4 x i64> @ult_35_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_35_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15128,7 +15128,7 @@ define <4 x i64> @ult_35_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15192,7 +15192,7 @@ define <4 x i64> @ugt_35_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_35_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15212,7 +15212,7 @@ define <4 x i64> @ugt_35_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15276,7 +15276,7 @@ define <4 x i64> @ult_36_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_36_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15296,7 +15296,7 @@ define <4 x i64> @ult_36_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15360,7 +15360,7 @@ define <4 x i64> @ugt_36_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_36_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15380,7 +15380,7 @@ define <4 x i64> @ugt_36_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15444,7 +15444,7 @@ define <4 x i64> @ult_37_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_37_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15464,7 +15464,7 @@ define <4 x i64> @ult_37_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15528,7 +15528,7 @@ define <4 x i64> @ugt_37_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_37_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15548,7 +15548,7 @@ define <4 x i64> @ugt_37_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15612,7 +15612,7 @@ define <4 x i64> @ult_38_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_38_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15632,7 +15632,7 @@ define <4 x i64> @ult_38_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15696,7 +15696,7 @@ define <4 x i64> @ugt_38_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_38_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15716,7 +15716,7 @@ define <4 x i64> @ugt_38_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15780,7 +15780,7 @@ define <4 x i64> @ult_39_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_39_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15800,7 +15800,7 @@ define <4 x i64> @ult_39_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15864,7 +15864,7 @@ define <4 x i64> @ugt_39_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_39_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15884,7 +15884,7 @@ define <4 x i64> @ugt_39_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -15948,7 +15948,7 @@ define <4 x i64> @ult_40_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_40_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -15968,7 +15968,7 @@ define <4 x i64> @ult_40_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16032,7 +16032,7 @@ define <4 x i64> @ugt_40_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_40_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16052,7 +16052,7 @@ define <4 x i64> @ugt_40_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16116,7 +16116,7 @@ define <4 x i64> @ult_41_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_41_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16136,7 +16136,7 @@ define <4 x i64> @ult_41_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16200,7 +16200,7 @@ define <4 x i64> @ugt_41_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_41_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16220,7 +16220,7 @@ define <4 x i64> @ugt_41_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16284,7 +16284,7 @@ define <4 x i64> @ult_42_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_42_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16304,7 +16304,7 @@ define <4 x i64> @ult_42_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16368,7 +16368,7 @@ define <4 x i64> @ugt_42_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_42_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16388,7 +16388,7 @@ define <4 x i64> @ugt_42_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16452,7 +16452,7 @@ define <4 x i64> @ult_43_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_43_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16472,7 +16472,7 @@ define <4 x i64> @ult_43_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16536,7 +16536,7 @@ define <4 x i64> @ugt_43_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_43_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16556,7 +16556,7 @@ define <4 x i64> @ugt_43_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16620,7 +16620,7 @@ define <4 x i64> @ult_44_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_44_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16640,7 +16640,7 @@ define <4 x i64> @ult_44_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16704,7 +16704,7 @@ define <4 x i64> @ugt_44_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_44_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16724,7 +16724,7 @@ define <4 x i64> @ugt_44_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16788,7 +16788,7 @@ define <4 x i64> @ult_45_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_45_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16808,7 +16808,7 @@ define <4 x i64> @ult_45_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16872,7 +16872,7 @@ define <4 x i64> @ugt_45_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_45_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16892,7 +16892,7 @@ define <4 x i64> @ugt_45_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -16956,7 +16956,7 @@ define <4 x i64> @ult_46_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_46_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -16976,7 +16976,7 @@ define <4 x i64> @ult_46_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17040,7 +17040,7 @@ define <4 x i64> @ugt_46_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_46_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17060,7 +17060,7 @@ define <4 x i64> @ugt_46_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17124,7 +17124,7 @@ define <4 x i64> @ult_47_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_47_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17144,7 +17144,7 @@ define <4 x i64> @ult_47_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17208,7 +17208,7 @@ define <4 x i64> @ugt_47_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_47_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17228,7 +17228,7 @@ define <4 x i64> @ugt_47_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17292,7 +17292,7 @@ define <4 x i64> @ult_48_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_48_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17312,7 +17312,7 @@ define <4 x i64> @ult_48_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17376,7 +17376,7 @@ define <4 x i64> @ugt_48_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_48_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17396,7 +17396,7 @@ define <4 x i64> @ugt_48_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17460,7 +17460,7 @@ define <4 x i64> @ult_49_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_49_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17480,7 +17480,7 @@ define <4 x i64> @ult_49_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17544,7 +17544,7 @@ define <4 x i64> @ugt_49_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_49_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17564,7 +17564,7 @@ define <4 x i64> @ugt_49_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17628,7 +17628,7 @@ define <4 x i64> @ult_50_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_50_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17648,7 +17648,7 @@ define <4 x i64> @ult_50_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17712,7 +17712,7 @@ define <4 x i64> @ugt_50_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_50_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17732,7 +17732,7 @@ define <4 x i64> @ugt_50_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17796,7 +17796,7 @@ define <4 x i64> @ult_51_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_51_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17816,7 +17816,7 @@ define <4 x i64> @ult_51_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17880,7 +17880,7 @@ define <4 x i64> @ugt_51_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_51_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17900,7 +17900,7 @@ define <4 x i64> @ugt_51_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17964,7 +17964,7 @@ define <4 x i64> @ult_52_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_52_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17984,7 +17984,7 @@ define <4 x i64> @ult_52_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18048,7 +18048,7 @@ define <4 x i64> @ugt_52_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_52_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18068,7 +18068,7 @@ define <4 x i64> @ugt_52_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18132,7 +18132,7 @@ define <4 x i64> @ult_53_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_53_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18152,7 +18152,7 @@ define <4 x i64> @ult_53_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18216,7 +18216,7 @@ define <4 x i64> @ugt_53_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_53_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18236,7 +18236,7 @@ define <4 x i64> @ugt_53_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18300,7 +18300,7 @@ define <4 x i64> @ult_54_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_54_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18320,7 +18320,7 @@ define <4 x i64> @ult_54_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18384,7 +18384,7 @@ define <4 x i64> @ugt_54_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_54_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18404,7 +18404,7 @@ define <4 x i64> @ugt_54_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18468,7 +18468,7 @@ define <4 x i64> @ult_55_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_55_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18488,7 +18488,7 @@ define <4 x i64> @ult_55_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18552,7 +18552,7 @@ define <4 x i64> @ugt_55_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_55_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18572,7 +18572,7 @@ define <4 x i64> @ugt_55_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18636,7 +18636,7 @@ define <4 x i64> @ult_56_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_56_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18656,7 +18656,7 @@ define <4 x i64> @ult_56_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18720,7 +18720,7 @@ define <4 x i64> @ugt_56_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_56_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18740,7 +18740,7 @@ define <4 x i64> @ugt_56_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18804,7 +18804,7 @@ define <4 x i64> @ult_57_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_57_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18824,7 +18824,7 @@ define <4 x i64> @ult_57_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18888,7 +18888,7 @@ define <4 x i64> @ugt_57_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_57_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18908,7 +18908,7 @@ define <4 x i64> @ugt_57_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18972,7 +18972,7 @@ define <4 x i64> @ult_58_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_58_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18992,7 +18992,7 @@ define <4 x i64> @ult_58_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19056,7 +19056,7 @@ define <4 x i64> @ugt_58_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_58_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19076,7 +19076,7 @@ define <4 x i64> @ugt_58_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19140,7 +19140,7 @@ define <4 x i64> @ult_59_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_59_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19160,7 +19160,7 @@ define <4 x i64> @ult_59_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19224,7 +19224,7 @@ define <4 x i64> @ugt_59_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_59_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19244,7 +19244,7 @@ define <4 x i64> @ugt_59_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19308,7 +19308,7 @@ define <4 x i64> @ult_60_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_60_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19328,7 +19328,7 @@ define <4 x i64> @ult_60_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19392,7 +19392,7 @@ define <4 x i64> @ugt_60_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_60_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19412,7 +19412,7 @@ define <4 x i64> @ugt_60_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19476,7 +19476,7 @@ define <4 x i64> @ult_61_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_61_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19496,7 +19496,7 @@ define <4 x i64> @ult_61_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19560,7 +19560,7 @@ define <4 x i64> @ugt_61_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_61_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19580,7 +19580,7 @@ define <4 x i64> @ugt_61_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19644,7 +19644,7 @@ define <4 x i64> @ult_62_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_62_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19664,7 +19664,7 @@ define <4 x i64> @ult_62_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19728,7 +19728,7 @@ define <4 x i64> @ugt_62_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_62_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19748,7 +19748,7 @@ define <4 x i64> @ugt_62_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19812,7 +19812,7 @@ define <4 x i64> @ult_63_v4i64(<4 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_63_v4i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %ymm0, %ymm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19832,7 +19832,7 @@ define <4 x i64> @ult_63_v4i64(<4 x i64> %0) {
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to4}, %ymm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; BITALG-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; BITALG-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; BITALG-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-256.ll b/llvm/test/CodeGen/X86/vector-popcnt-256.ll
index e42cb059eb0cb..500cc8e06b624 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-256.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-256.ll
@@ -699,13 +699,13 @@ define <16 x i16> @eq_1_v16i16(<16 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: eq_1_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpeqw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
%3 = icmp eq <16 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -773,7 +773,7 @@ define <16 x i16> @ne_1_v16i16(<16 x i16> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; BITALG_NOVLX-NEXT: retq
@@ -781,7 +781,7 @@ define <16 x i16> @ne_1_v16i16(<16 x i16> %0) {
; BITALG-LABEL: ne_1_v16i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %ymm0, %ymm0
-; BITALG-NEXT: vpcmpeqw {{.*}}(%rip), %ymm0, %ymm0
+; BITALG-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG-NEXT: vpternlogq $15, %ymm0, %ymm0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %0)
@@ -846,13 +846,13 @@ define <32 x i8> @eq_1_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: eq_1_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpeqb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
%3 = icmp eq <32 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -920,7 +920,7 @@ define <32 x i8> @ne_1_v32i8(<32 x i8> %0) {
; BITALG_NOVLX: # %bb.0:
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG_NOVLX-NEXT: vpcmpeqb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG_NOVLX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG_NOVLX-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0
; BITALG_NOVLX-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; BITALG_NOVLX-NEXT: retq
@@ -928,7 +928,7 @@ define <32 x i8> @ne_1_v32i8(<32 x i8> %0) {
; BITALG-LABEL: ne_1_v32i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %ymm0, %ymm0
-; BITALG-NEXT: vpcmpeqb {{.*}}(%rip), %ymm0, %ymm0
+; BITALG-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; BITALG-NEXT: vpternlogq $15, %ymm0, %ymm0, %ymm0
; BITALG-NEXT: retq
%2 = tail call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %0)
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll b/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
index 6217d031be0ad..820f0f0b723e5 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
@@ -56,7 +56,7 @@ define <64 x i8> @ugt_1_v64i8(<64 x i8> %0) {
; BITALG-LABEL: ugt_1_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -113,7 +113,7 @@ define <64 x i8> @ult_2_v64i8(<64 x i8> %0) {
; BITALG-LABEL: ult_2_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -158,7 +158,7 @@ define <64 x i8> @ugt_2_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -197,14 +197,14 @@ define <64 x i8> @ugt_2_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_2_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -249,7 +249,7 @@ define <64 x i8> @ult_3_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -288,14 +288,14 @@ define <64 x i8> @ult_3_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_3_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -340,7 +340,7 @@ define <64 x i8> @ugt_3_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -379,14 +379,14 @@ define <64 x i8> @ugt_3_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_3_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -431,7 +431,7 @@ define <64 x i8> @ult_4_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -470,14 +470,14 @@ define <64 x i8> @ult_4_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_4_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -522,7 +522,7 @@ define <64 x i8> @ugt_4_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -561,14 +561,14 @@ define <64 x i8> @ugt_4_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_4_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -613,7 +613,7 @@ define <64 x i8> @ult_5_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -652,14 +652,14 @@ define <64 x i8> @ult_5_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_5_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -704,7 +704,7 @@ define <64 x i8> @ugt_5_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -743,14 +743,14 @@ define <64 x i8> @ugt_5_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_5_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -795,7 +795,7 @@ define <64 x i8> @ult_6_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -834,14 +834,14 @@ define <64 x i8> @ult_6_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_6_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -886,7 +886,7 @@ define <64 x i8> @ugt_6_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -925,14 +925,14 @@ define <64 x i8> @ugt_6_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_6_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -977,7 +977,7 @@ define <64 x i8> @ult_7_v64i8(<64 x i8> %0) {
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1016,14 +1016,14 @@ define <64 x i8> @ult_7_v64i8(<64 x i8> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_7_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltub {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -1082,7 +1082,7 @@ define <32 x i16> @ugt_1_v32i16(<32 x i16> %0) {
; BITALG-LABEL: ugt_1_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1139,7 +1139,7 @@ define <32 x i16> @ult_2_v32i16(<32 x i16> %0) {
; BITALG-LABEL: ult_2_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1191,7 +1191,7 @@ define <32 x i16> @ugt_2_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1223,14 +1223,14 @@ define <32 x i16> @ugt_2_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_2_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1282,7 +1282,7 @@ define <32 x i16> @ult_3_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1314,14 +1314,14 @@ define <32 x i16> @ult_3_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_3_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1373,7 +1373,7 @@ define <32 x i16> @ugt_3_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1405,14 +1405,14 @@ define <32 x i16> @ugt_3_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_3_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1464,7 +1464,7 @@ define <32 x i16> @ult_4_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1496,14 +1496,14 @@ define <32 x i16> @ult_4_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_4_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1555,7 +1555,7 @@ define <32 x i16> @ugt_4_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1587,14 +1587,14 @@ define <32 x i16> @ugt_4_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_4_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1646,7 +1646,7 @@ define <32 x i16> @ult_5_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1678,14 +1678,14 @@ define <32 x i16> @ult_5_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_5_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1737,7 +1737,7 @@ define <32 x i16> @ugt_5_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1769,14 +1769,14 @@ define <32 x i16> @ugt_5_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_5_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1828,7 +1828,7 @@ define <32 x i16> @ult_6_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1860,14 +1860,14 @@ define <32 x i16> @ult_6_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_6_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -1919,7 +1919,7 @@ define <32 x i16> @ugt_6_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -1951,14 +1951,14 @@ define <32 x i16> @ugt_6_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_6_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2010,7 +2010,7 @@ define <32 x i16> @ult_7_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2042,14 +2042,14 @@ define <32 x i16> @ult_7_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_7_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2101,7 +2101,7 @@ define <32 x i16> @ugt_7_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2133,14 +2133,14 @@ define <32 x i16> @ugt_7_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_7_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2192,7 +2192,7 @@ define <32 x i16> @ult_8_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2224,14 +2224,14 @@ define <32 x i16> @ult_8_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_8_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2283,7 +2283,7 @@ define <32 x i16> @ugt_8_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2315,14 +2315,14 @@ define <32 x i16> @ugt_8_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_8_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2374,7 +2374,7 @@ define <32 x i16> @ult_9_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2406,14 +2406,14 @@ define <32 x i16> @ult_9_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_9_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2465,7 +2465,7 @@ define <32 x i16> @ugt_9_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2497,14 +2497,14 @@ define <32 x i16> @ugt_9_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_9_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2556,7 +2556,7 @@ define <32 x i16> @ult_10_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2588,14 +2588,14 @@ define <32 x i16> @ult_10_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_10_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2647,7 +2647,7 @@ define <32 x i16> @ugt_10_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2679,14 +2679,14 @@ define <32 x i16> @ugt_10_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_10_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2738,7 +2738,7 @@ define <32 x i16> @ult_11_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2770,14 +2770,14 @@ define <32 x i16> @ult_11_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_11_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2829,7 +2829,7 @@ define <32 x i16> @ugt_11_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2861,14 +2861,14 @@ define <32 x i16> @ugt_11_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_11_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -2920,7 +2920,7 @@ define <32 x i16> @ult_12_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -2952,14 +2952,14 @@ define <32 x i16> @ult_12_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_12_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -3011,7 +3011,7 @@ define <32 x i16> @ugt_12_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -3043,14 +3043,14 @@ define <32 x i16> @ugt_12_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_12_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -3102,7 +3102,7 @@ define <32 x i16> @ult_13_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -3134,14 +3134,14 @@ define <32 x i16> @ult_13_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_13_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -3193,7 +3193,7 @@ define <32 x i16> @ugt_13_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -3225,14 +3225,14 @@ define <32 x i16> @ugt_13_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_13_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -3284,7 +3284,7 @@ define <32 x i16> @ult_14_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -3316,14 +3316,14 @@ define <32 x i16> @ult_14_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_14_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -3375,7 +3375,7 @@ define <32 x i16> @ugt_14_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -3407,14 +3407,14 @@ define <32 x i16> @ugt_14_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ugt_14_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpnleuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -3466,7 +3466,7 @@ define <32 x i16> @ult_15_v32i16(<32 x i16> %0) {
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: retq
;
@@ -3498,14 +3498,14 @@ define <32 x i16> @ult_15_v32i16(<32 x i16> %0) {
; AVX512VPOPCNTDQ-BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512VPOPCNTDQ-BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; AVX512VPOPCNTDQ-BW-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; AVX512VPOPCNTDQ-BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512VPOPCNTDQ-BW-NEXT: retq
;
; BITALG-LABEL: ult_15_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpltuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -3534,7 +3534,7 @@ define <16 x i32> @ugt_1_v16i32(<16 x i32> %0) {
; AVX512VPOPCNTDQ-LABEL: ugt_1_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3571,7 +3571,7 @@ define <16 x i32> @ult_2_v16i32(<16 x i32> %0) {
; AVX512VPOPCNTDQ-LABEL: ult_2_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3618,7 +3618,7 @@ define <16 x i32> @ugt_2_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -3638,14 +3638,14 @@ define <16 x i32> @ugt_2_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_2_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3658,7 +3658,7 @@ define <16 x i32> @ugt_2_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -3697,7 +3697,7 @@ define <16 x i32> @ult_3_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -3717,14 +3717,14 @@ define <16 x i32> @ult_3_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_3_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3737,7 +3737,7 @@ define <16 x i32> @ult_3_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -3776,7 +3776,7 @@ define <16 x i32> @ugt_3_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -3796,14 +3796,14 @@ define <16 x i32> @ugt_3_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_3_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3816,7 +3816,7 @@ define <16 x i32> @ugt_3_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -3855,7 +3855,7 @@ define <16 x i32> @ult_4_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -3875,14 +3875,14 @@ define <16 x i32> @ult_4_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_4_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3895,7 +3895,7 @@ define <16 x i32> @ult_4_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -3934,7 +3934,7 @@ define <16 x i32> @ugt_4_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -3954,14 +3954,14 @@ define <16 x i32> @ugt_4_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_4_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -3974,7 +3974,7 @@ define <16 x i32> @ugt_4_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4013,7 +4013,7 @@ define <16 x i32> @ult_5_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4033,14 +4033,14 @@ define <16 x i32> @ult_5_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_5_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4053,7 +4053,7 @@ define <16 x i32> @ult_5_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4092,7 +4092,7 @@ define <16 x i32> @ugt_5_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4112,14 +4112,14 @@ define <16 x i32> @ugt_5_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_5_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4132,7 +4132,7 @@ define <16 x i32> @ugt_5_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4171,7 +4171,7 @@ define <16 x i32> @ult_6_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4191,14 +4191,14 @@ define <16 x i32> @ult_6_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_6_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4211,7 +4211,7 @@ define <16 x i32> @ult_6_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4250,7 +4250,7 @@ define <16 x i32> @ugt_6_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4270,14 +4270,14 @@ define <16 x i32> @ugt_6_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_6_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4290,7 +4290,7 @@ define <16 x i32> @ugt_6_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4329,7 +4329,7 @@ define <16 x i32> @ult_7_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4349,14 +4349,14 @@ define <16 x i32> @ult_7_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_7_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4369,7 +4369,7 @@ define <16 x i32> @ult_7_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4408,7 +4408,7 @@ define <16 x i32> @ugt_7_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4428,14 +4428,14 @@ define <16 x i32> @ugt_7_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_7_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4448,7 +4448,7 @@ define <16 x i32> @ugt_7_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4487,7 +4487,7 @@ define <16 x i32> @ult_8_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4507,14 +4507,14 @@ define <16 x i32> @ult_8_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_8_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4527,7 +4527,7 @@ define <16 x i32> @ult_8_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4566,7 +4566,7 @@ define <16 x i32> @ugt_8_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4586,14 +4586,14 @@ define <16 x i32> @ugt_8_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_8_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4606,7 +4606,7 @@ define <16 x i32> @ugt_8_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4645,7 +4645,7 @@ define <16 x i32> @ult_9_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4665,14 +4665,14 @@ define <16 x i32> @ult_9_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_9_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4685,7 +4685,7 @@ define <16 x i32> @ult_9_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4724,7 +4724,7 @@ define <16 x i32> @ugt_9_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4744,14 +4744,14 @@ define <16 x i32> @ugt_9_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_9_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4764,7 +4764,7 @@ define <16 x i32> @ugt_9_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4803,7 +4803,7 @@ define <16 x i32> @ult_10_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4823,14 +4823,14 @@ define <16 x i32> @ult_10_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_10_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4843,7 +4843,7 @@ define <16 x i32> @ult_10_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4882,7 +4882,7 @@ define <16 x i32> @ugt_10_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4902,14 +4902,14 @@ define <16 x i32> @ugt_10_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_10_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -4922,7 +4922,7 @@ define <16 x i32> @ugt_10_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -4961,7 +4961,7 @@ define <16 x i32> @ult_11_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -4981,14 +4981,14 @@ define <16 x i32> @ult_11_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_11_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5001,7 +5001,7 @@ define <16 x i32> @ult_11_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5040,7 +5040,7 @@ define <16 x i32> @ugt_11_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5060,14 +5060,14 @@ define <16 x i32> @ugt_11_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_11_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5080,7 +5080,7 @@ define <16 x i32> @ugt_11_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5119,7 +5119,7 @@ define <16 x i32> @ult_12_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5139,14 +5139,14 @@ define <16 x i32> @ult_12_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_12_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5159,7 +5159,7 @@ define <16 x i32> @ult_12_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5198,7 +5198,7 @@ define <16 x i32> @ugt_12_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5218,14 +5218,14 @@ define <16 x i32> @ugt_12_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_12_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5238,7 +5238,7 @@ define <16 x i32> @ugt_12_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5277,7 +5277,7 @@ define <16 x i32> @ult_13_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5297,14 +5297,14 @@ define <16 x i32> @ult_13_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_13_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5317,7 +5317,7 @@ define <16 x i32> @ult_13_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5356,7 +5356,7 @@ define <16 x i32> @ugt_13_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5376,14 +5376,14 @@ define <16 x i32> @ugt_13_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_13_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5396,7 +5396,7 @@ define <16 x i32> @ugt_13_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5435,7 +5435,7 @@ define <16 x i32> @ult_14_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5455,14 +5455,14 @@ define <16 x i32> @ult_14_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_14_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5475,7 +5475,7 @@ define <16 x i32> @ult_14_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5514,7 +5514,7 @@ define <16 x i32> @ugt_14_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5534,14 +5534,14 @@ define <16 x i32> @ugt_14_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_14_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5554,7 +5554,7 @@ define <16 x i32> @ugt_14_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5593,7 +5593,7 @@ define <16 x i32> @ult_15_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5613,14 +5613,14 @@ define <16 x i32> @ult_15_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_15_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5633,7 +5633,7 @@ define <16 x i32> @ult_15_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5672,7 +5672,7 @@ define <16 x i32> @ugt_15_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5692,14 +5692,14 @@ define <16 x i32> @ugt_15_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_15_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5712,7 +5712,7 @@ define <16 x i32> @ugt_15_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5751,7 +5751,7 @@ define <16 x i32> @ult_16_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5771,14 +5771,14 @@ define <16 x i32> @ult_16_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_16_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5791,7 +5791,7 @@ define <16 x i32> @ult_16_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5830,7 +5830,7 @@ define <16 x i32> @ugt_16_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5850,14 +5850,14 @@ define <16 x i32> @ugt_16_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_16_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5870,7 +5870,7 @@ define <16 x i32> @ugt_16_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5909,7 +5909,7 @@ define <16 x i32> @ult_17_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -5929,14 +5929,14 @@ define <16 x i32> @ult_17_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_17_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -5949,7 +5949,7 @@ define <16 x i32> @ult_17_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -5988,7 +5988,7 @@ define <16 x i32> @ugt_17_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6008,14 +6008,14 @@ define <16 x i32> @ugt_17_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_17_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6028,7 +6028,7 @@ define <16 x i32> @ugt_17_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6067,7 +6067,7 @@ define <16 x i32> @ult_18_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6087,14 +6087,14 @@ define <16 x i32> @ult_18_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_18_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6107,7 +6107,7 @@ define <16 x i32> @ult_18_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6146,7 +6146,7 @@ define <16 x i32> @ugt_18_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6166,14 +6166,14 @@ define <16 x i32> @ugt_18_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_18_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6186,7 +6186,7 @@ define <16 x i32> @ugt_18_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6225,7 +6225,7 @@ define <16 x i32> @ult_19_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6245,14 +6245,14 @@ define <16 x i32> @ult_19_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_19_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6265,7 +6265,7 @@ define <16 x i32> @ult_19_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6304,7 +6304,7 @@ define <16 x i32> @ugt_19_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6324,14 +6324,14 @@ define <16 x i32> @ugt_19_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_19_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6344,7 +6344,7 @@ define <16 x i32> @ugt_19_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6383,7 +6383,7 @@ define <16 x i32> @ult_20_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6403,14 +6403,14 @@ define <16 x i32> @ult_20_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_20_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6423,7 +6423,7 @@ define <16 x i32> @ult_20_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6462,7 +6462,7 @@ define <16 x i32> @ugt_20_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6482,14 +6482,14 @@ define <16 x i32> @ugt_20_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_20_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6502,7 +6502,7 @@ define <16 x i32> @ugt_20_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6541,7 +6541,7 @@ define <16 x i32> @ult_21_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6561,14 +6561,14 @@ define <16 x i32> @ult_21_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_21_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6581,7 +6581,7 @@ define <16 x i32> @ult_21_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6620,7 +6620,7 @@ define <16 x i32> @ugt_21_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6640,14 +6640,14 @@ define <16 x i32> @ugt_21_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_21_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6660,7 +6660,7 @@ define <16 x i32> @ugt_21_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6699,7 +6699,7 @@ define <16 x i32> @ult_22_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6719,14 +6719,14 @@ define <16 x i32> @ult_22_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_22_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6739,7 +6739,7 @@ define <16 x i32> @ult_22_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6778,7 +6778,7 @@ define <16 x i32> @ugt_22_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6798,14 +6798,14 @@ define <16 x i32> @ugt_22_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_22_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6818,7 +6818,7 @@ define <16 x i32> @ugt_22_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6857,7 +6857,7 @@ define <16 x i32> @ult_23_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6877,14 +6877,14 @@ define <16 x i32> @ult_23_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_23_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6897,7 +6897,7 @@ define <16 x i32> @ult_23_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -6936,7 +6936,7 @@ define <16 x i32> @ugt_23_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -6956,14 +6956,14 @@ define <16 x i32> @ugt_23_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_23_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -6976,7 +6976,7 @@ define <16 x i32> @ugt_23_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7015,7 +7015,7 @@ define <16 x i32> @ult_24_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7035,14 +7035,14 @@ define <16 x i32> @ult_24_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_24_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7055,7 +7055,7 @@ define <16 x i32> @ult_24_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7094,7 +7094,7 @@ define <16 x i32> @ugt_24_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7114,14 +7114,14 @@ define <16 x i32> @ugt_24_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_24_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7134,7 +7134,7 @@ define <16 x i32> @ugt_24_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7173,7 +7173,7 @@ define <16 x i32> @ult_25_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7193,14 +7193,14 @@ define <16 x i32> @ult_25_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_25_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7213,7 +7213,7 @@ define <16 x i32> @ult_25_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7252,7 +7252,7 @@ define <16 x i32> @ugt_25_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7272,14 +7272,14 @@ define <16 x i32> @ugt_25_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_25_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7292,7 +7292,7 @@ define <16 x i32> @ugt_25_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7331,7 +7331,7 @@ define <16 x i32> @ult_26_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7351,14 +7351,14 @@ define <16 x i32> @ult_26_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_26_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7371,7 +7371,7 @@ define <16 x i32> @ult_26_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7410,7 +7410,7 @@ define <16 x i32> @ugt_26_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7430,14 +7430,14 @@ define <16 x i32> @ugt_26_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_26_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7450,7 +7450,7 @@ define <16 x i32> @ugt_26_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7489,7 +7489,7 @@ define <16 x i32> @ult_27_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7509,14 +7509,14 @@ define <16 x i32> @ult_27_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_27_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7529,7 +7529,7 @@ define <16 x i32> @ult_27_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7568,7 +7568,7 @@ define <16 x i32> @ugt_27_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7588,14 +7588,14 @@ define <16 x i32> @ugt_27_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_27_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7608,7 +7608,7 @@ define <16 x i32> @ugt_27_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7647,7 +7647,7 @@ define <16 x i32> @ult_28_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7667,14 +7667,14 @@ define <16 x i32> @ult_28_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_28_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7687,7 +7687,7 @@ define <16 x i32> @ult_28_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7726,7 +7726,7 @@ define <16 x i32> @ugt_28_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7746,14 +7746,14 @@ define <16 x i32> @ugt_28_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_28_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7766,7 +7766,7 @@ define <16 x i32> @ugt_28_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7805,7 +7805,7 @@ define <16 x i32> @ult_29_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7825,14 +7825,14 @@ define <16 x i32> @ult_29_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_29_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7845,7 +7845,7 @@ define <16 x i32> @ult_29_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7884,7 +7884,7 @@ define <16 x i32> @ugt_29_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7904,14 +7904,14 @@ define <16 x i32> @ugt_29_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_29_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -7924,7 +7924,7 @@ define <16 x i32> @ugt_29_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -7963,7 +7963,7 @@ define <16 x i32> @ult_30_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -7983,14 +7983,14 @@ define <16 x i32> @ult_30_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_30_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8003,7 +8003,7 @@ define <16 x i32> @ult_30_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -8042,7 +8042,7 @@ define <16 x i32> @ugt_30_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8062,14 +8062,14 @@ define <16 x i32> @ugt_30_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_30_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8082,7 +8082,7 @@ define <16 x i32> @ugt_30_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -8121,7 +8121,7 @@ define <16 x i32> @ult_31_v16i32(<16 x i32> %0) {
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8141,14 +8141,14 @@ define <16 x i32> @ult_31_v16i32(<16 x i32> %0) {
; AVX512BW-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_31_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8161,7 +8161,7 @@ define <16 x i32> @ult_31_v16i32(<16 x i32> %0) {
; BITALG-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
; BITALG-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltud {{.*}}(%rip){1to16}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; BITALG-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %0)
@@ -8190,7 +8190,7 @@ define <8 x i64> @ugt_1_v8i64(<8 x i64> %0) {
; AVX512VPOPCNTDQ-LABEL: ugt_1_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8227,7 +8227,7 @@ define <8 x i64> @ult_2_v8i64(<8 x i64> %0) {
; AVX512VPOPCNTDQ-LABEL: ult_2_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8266,7 +8266,7 @@ define <8 x i64> @ugt_2_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8282,14 +8282,14 @@ define <8 x i64> @ugt_2_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_2_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8298,7 +8298,7 @@ define <8 x i64> @ugt_2_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8329,7 +8329,7 @@ define <8 x i64> @ult_3_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8345,14 +8345,14 @@ define <8 x i64> @ult_3_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_3_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8361,7 +8361,7 @@ define <8 x i64> @ult_3_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8392,7 +8392,7 @@ define <8 x i64> @ugt_3_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8408,14 +8408,14 @@ define <8 x i64> @ugt_3_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_3_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8424,7 +8424,7 @@ define <8 x i64> @ugt_3_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8455,7 +8455,7 @@ define <8 x i64> @ult_4_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8471,14 +8471,14 @@ define <8 x i64> @ult_4_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_4_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8487,7 +8487,7 @@ define <8 x i64> @ult_4_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8518,7 +8518,7 @@ define <8 x i64> @ugt_4_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8534,14 +8534,14 @@ define <8 x i64> @ugt_4_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_4_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8550,7 +8550,7 @@ define <8 x i64> @ugt_4_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8581,7 +8581,7 @@ define <8 x i64> @ult_5_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8597,14 +8597,14 @@ define <8 x i64> @ult_5_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_5_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8613,7 +8613,7 @@ define <8 x i64> @ult_5_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8644,7 +8644,7 @@ define <8 x i64> @ugt_5_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8660,14 +8660,14 @@ define <8 x i64> @ugt_5_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_5_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8676,7 +8676,7 @@ define <8 x i64> @ugt_5_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8707,7 +8707,7 @@ define <8 x i64> @ult_6_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8723,14 +8723,14 @@ define <8 x i64> @ult_6_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_6_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8739,7 +8739,7 @@ define <8 x i64> @ult_6_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8770,7 +8770,7 @@ define <8 x i64> @ugt_6_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8786,14 +8786,14 @@ define <8 x i64> @ugt_6_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_6_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8802,7 +8802,7 @@ define <8 x i64> @ugt_6_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8833,7 +8833,7 @@ define <8 x i64> @ult_7_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8849,14 +8849,14 @@ define <8 x i64> @ult_7_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_7_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8865,7 +8865,7 @@ define <8 x i64> @ult_7_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8896,7 +8896,7 @@ define <8 x i64> @ugt_7_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8912,14 +8912,14 @@ define <8 x i64> @ugt_7_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_7_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8928,7 +8928,7 @@ define <8 x i64> @ugt_7_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -8959,7 +8959,7 @@ define <8 x i64> @ult_8_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -8975,14 +8975,14 @@ define <8 x i64> @ult_8_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_8_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -8991,7 +8991,7 @@ define <8 x i64> @ult_8_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9022,7 +9022,7 @@ define <8 x i64> @ugt_8_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9038,14 +9038,14 @@ define <8 x i64> @ugt_8_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_8_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9054,7 +9054,7 @@ define <8 x i64> @ugt_8_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9085,7 +9085,7 @@ define <8 x i64> @ult_9_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9101,14 +9101,14 @@ define <8 x i64> @ult_9_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_9_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9117,7 +9117,7 @@ define <8 x i64> @ult_9_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9148,7 +9148,7 @@ define <8 x i64> @ugt_9_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9164,14 +9164,14 @@ define <8 x i64> @ugt_9_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_9_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9180,7 +9180,7 @@ define <8 x i64> @ugt_9_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9211,7 +9211,7 @@ define <8 x i64> @ult_10_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9227,14 +9227,14 @@ define <8 x i64> @ult_10_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_10_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9243,7 +9243,7 @@ define <8 x i64> @ult_10_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9274,7 +9274,7 @@ define <8 x i64> @ugt_10_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9290,14 +9290,14 @@ define <8 x i64> @ugt_10_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_10_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9306,7 +9306,7 @@ define <8 x i64> @ugt_10_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9337,7 +9337,7 @@ define <8 x i64> @ult_11_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9353,14 +9353,14 @@ define <8 x i64> @ult_11_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_11_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9369,7 +9369,7 @@ define <8 x i64> @ult_11_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9400,7 +9400,7 @@ define <8 x i64> @ugt_11_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9416,14 +9416,14 @@ define <8 x i64> @ugt_11_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_11_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9432,7 +9432,7 @@ define <8 x i64> @ugt_11_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9463,7 +9463,7 @@ define <8 x i64> @ult_12_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9479,14 +9479,14 @@ define <8 x i64> @ult_12_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_12_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9495,7 +9495,7 @@ define <8 x i64> @ult_12_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9526,7 +9526,7 @@ define <8 x i64> @ugt_12_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9542,14 +9542,14 @@ define <8 x i64> @ugt_12_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_12_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9558,7 +9558,7 @@ define <8 x i64> @ugt_12_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9589,7 +9589,7 @@ define <8 x i64> @ult_13_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9605,14 +9605,14 @@ define <8 x i64> @ult_13_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_13_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9621,7 +9621,7 @@ define <8 x i64> @ult_13_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9652,7 +9652,7 @@ define <8 x i64> @ugt_13_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9668,14 +9668,14 @@ define <8 x i64> @ugt_13_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_13_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9684,7 +9684,7 @@ define <8 x i64> @ugt_13_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9715,7 +9715,7 @@ define <8 x i64> @ult_14_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9731,14 +9731,14 @@ define <8 x i64> @ult_14_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_14_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9747,7 +9747,7 @@ define <8 x i64> @ult_14_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9778,7 +9778,7 @@ define <8 x i64> @ugt_14_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9794,14 +9794,14 @@ define <8 x i64> @ugt_14_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_14_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9810,7 +9810,7 @@ define <8 x i64> @ugt_14_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9841,7 +9841,7 @@ define <8 x i64> @ult_15_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9857,14 +9857,14 @@ define <8 x i64> @ult_15_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_15_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9873,7 +9873,7 @@ define <8 x i64> @ult_15_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9904,7 +9904,7 @@ define <8 x i64> @ugt_15_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9920,14 +9920,14 @@ define <8 x i64> @ugt_15_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_15_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9936,7 +9936,7 @@ define <8 x i64> @ugt_15_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -9967,7 +9967,7 @@ define <8 x i64> @ult_16_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -9983,14 +9983,14 @@ define <8 x i64> @ult_16_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_16_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -9999,7 +9999,7 @@ define <8 x i64> @ult_16_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10030,7 +10030,7 @@ define <8 x i64> @ugt_16_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10046,14 +10046,14 @@ define <8 x i64> @ugt_16_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_16_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10062,7 +10062,7 @@ define <8 x i64> @ugt_16_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10093,7 +10093,7 @@ define <8 x i64> @ult_17_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10109,14 +10109,14 @@ define <8 x i64> @ult_17_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_17_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10125,7 +10125,7 @@ define <8 x i64> @ult_17_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10156,7 +10156,7 @@ define <8 x i64> @ugt_17_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10172,14 +10172,14 @@ define <8 x i64> @ugt_17_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_17_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10188,7 +10188,7 @@ define <8 x i64> @ugt_17_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10219,7 +10219,7 @@ define <8 x i64> @ult_18_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10235,14 +10235,14 @@ define <8 x i64> @ult_18_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_18_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10251,7 +10251,7 @@ define <8 x i64> @ult_18_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10282,7 +10282,7 @@ define <8 x i64> @ugt_18_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10298,14 +10298,14 @@ define <8 x i64> @ugt_18_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_18_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10314,7 +10314,7 @@ define <8 x i64> @ugt_18_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10345,7 +10345,7 @@ define <8 x i64> @ult_19_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10361,14 +10361,14 @@ define <8 x i64> @ult_19_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_19_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10377,7 +10377,7 @@ define <8 x i64> @ult_19_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10408,7 +10408,7 @@ define <8 x i64> @ugt_19_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10424,14 +10424,14 @@ define <8 x i64> @ugt_19_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_19_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10440,7 +10440,7 @@ define <8 x i64> @ugt_19_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10471,7 +10471,7 @@ define <8 x i64> @ult_20_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10487,14 +10487,14 @@ define <8 x i64> @ult_20_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_20_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10503,7 +10503,7 @@ define <8 x i64> @ult_20_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10534,7 +10534,7 @@ define <8 x i64> @ugt_20_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10550,14 +10550,14 @@ define <8 x i64> @ugt_20_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_20_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10566,7 +10566,7 @@ define <8 x i64> @ugt_20_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10597,7 +10597,7 @@ define <8 x i64> @ult_21_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10613,14 +10613,14 @@ define <8 x i64> @ult_21_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_21_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10629,7 +10629,7 @@ define <8 x i64> @ult_21_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10660,7 +10660,7 @@ define <8 x i64> @ugt_21_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10676,14 +10676,14 @@ define <8 x i64> @ugt_21_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_21_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10692,7 +10692,7 @@ define <8 x i64> @ugt_21_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10723,7 +10723,7 @@ define <8 x i64> @ult_22_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10739,14 +10739,14 @@ define <8 x i64> @ult_22_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_22_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10755,7 +10755,7 @@ define <8 x i64> @ult_22_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10786,7 +10786,7 @@ define <8 x i64> @ugt_22_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10802,14 +10802,14 @@ define <8 x i64> @ugt_22_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_22_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10818,7 +10818,7 @@ define <8 x i64> @ugt_22_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10849,7 +10849,7 @@ define <8 x i64> @ult_23_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10865,14 +10865,14 @@ define <8 x i64> @ult_23_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_23_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10881,7 +10881,7 @@ define <8 x i64> @ult_23_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10912,7 +10912,7 @@ define <8 x i64> @ugt_23_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10928,14 +10928,14 @@ define <8 x i64> @ugt_23_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_23_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -10944,7 +10944,7 @@ define <8 x i64> @ugt_23_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -10975,7 +10975,7 @@ define <8 x i64> @ult_24_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -10991,14 +10991,14 @@ define <8 x i64> @ult_24_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_24_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11007,7 +11007,7 @@ define <8 x i64> @ult_24_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11038,7 +11038,7 @@ define <8 x i64> @ugt_24_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11054,14 +11054,14 @@ define <8 x i64> @ugt_24_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_24_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11070,7 +11070,7 @@ define <8 x i64> @ugt_24_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11101,7 +11101,7 @@ define <8 x i64> @ult_25_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11117,14 +11117,14 @@ define <8 x i64> @ult_25_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_25_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11133,7 +11133,7 @@ define <8 x i64> @ult_25_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11164,7 +11164,7 @@ define <8 x i64> @ugt_25_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11180,14 +11180,14 @@ define <8 x i64> @ugt_25_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_25_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11196,7 +11196,7 @@ define <8 x i64> @ugt_25_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11227,7 +11227,7 @@ define <8 x i64> @ult_26_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11243,14 +11243,14 @@ define <8 x i64> @ult_26_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_26_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11259,7 +11259,7 @@ define <8 x i64> @ult_26_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11290,7 +11290,7 @@ define <8 x i64> @ugt_26_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11306,14 +11306,14 @@ define <8 x i64> @ugt_26_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_26_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11322,7 +11322,7 @@ define <8 x i64> @ugt_26_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11353,7 +11353,7 @@ define <8 x i64> @ult_27_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11369,14 +11369,14 @@ define <8 x i64> @ult_27_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_27_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11385,7 +11385,7 @@ define <8 x i64> @ult_27_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11416,7 +11416,7 @@ define <8 x i64> @ugt_27_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11432,14 +11432,14 @@ define <8 x i64> @ugt_27_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_27_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11448,7 +11448,7 @@ define <8 x i64> @ugt_27_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11479,7 +11479,7 @@ define <8 x i64> @ult_28_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11495,14 +11495,14 @@ define <8 x i64> @ult_28_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_28_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11511,7 +11511,7 @@ define <8 x i64> @ult_28_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11542,7 +11542,7 @@ define <8 x i64> @ugt_28_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11558,14 +11558,14 @@ define <8 x i64> @ugt_28_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_28_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11574,7 +11574,7 @@ define <8 x i64> @ugt_28_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11605,7 +11605,7 @@ define <8 x i64> @ult_29_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11621,14 +11621,14 @@ define <8 x i64> @ult_29_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_29_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11637,7 +11637,7 @@ define <8 x i64> @ult_29_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11668,7 +11668,7 @@ define <8 x i64> @ugt_29_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11684,14 +11684,14 @@ define <8 x i64> @ugt_29_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_29_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11700,7 +11700,7 @@ define <8 x i64> @ugt_29_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11731,7 +11731,7 @@ define <8 x i64> @ult_30_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11747,14 +11747,14 @@ define <8 x i64> @ult_30_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_30_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11763,7 +11763,7 @@ define <8 x i64> @ult_30_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11794,7 +11794,7 @@ define <8 x i64> @ugt_30_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11810,14 +11810,14 @@ define <8 x i64> @ugt_30_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_30_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11826,7 +11826,7 @@ define <8 x i64> @ugt_30_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11857,7 +11857,7 @@ define <8 x i64> @ult_31_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11873,14 +11873,14 @@ define <8 x i64> @ult_31_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_31_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11889,7 +11889,7 @@ define <8 x i64> @ult_31_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11920,7 +11920,7 @@ define <8 x i64> @ugt_31_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11936,14 +11936,14 @@ define <8 x i64> @ugt_31_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_31_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -11952,7 +11952,7 @@ define <8 x i64> @ugt_31_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -11983,7 +11983,7 @@ define <8 x i64> @ult_32_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -11999,14 +11999,14 @@ define <8 x i64> @ult_32_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_32_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12015,7 +12015,7 @@ define <8 x i64> @ult_32_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12046,7 +12046,7 @@ define <8 x i64> @ugt_32_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12062,14 +12062,14 @@ define <8 x i64> @ugt_32_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_32_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12078,7 +12078,7 @@ define <8 x i64> @ugt_32_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12109,7 +12109,7 @@ define <8 x i64> @ult_33_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12125,14 +12125,14 @@ define <8 x i64> @ult_33_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_33_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12141,7 +12141,7 @@ define <8 x i64> @ult_33_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12172,7 +12172,7 @@ define <8 x i64> @ugt_33_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12188,14 +12188,14 @@ define <8 x i64> @ugt_33_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_33_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12204,7 +12204,7 @@ define <8 x i64> @ugt_33_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12235,7 +12235,7 @@ define <8 x i64> @ult_34_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12251,14 +12251,14 @@ define <8 x i64> @ult_34_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_34_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12267,7 +12267,7 @@ define <8 x i64> @ult_34_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12298,7 +12298,7 @@ define <8 x i64> @ugt_34_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12314,14 +12314,14 @@ define <8 x i64> @ugt_34_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_34_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12330,7 +12330,7 @@ define <8 x i64> @ugt_34_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12361,7 +12361,7 @@ define <8 x i64> @ult_35_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12377,14 +12377,14 @@ define <8 x i64> @ult_35_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_35_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12393,7 +12393,7 @@ define <8 x i64> @ult_35_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12424,7 +12424,7 @@ define <8 x i64> @ugt_35_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12440,14 +12440,14 @@ define <8 x i64> @ugt_35_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_35_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12456,7 +12456,7 @@ define <8 x i64> @ugt_35_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12487,7 +12487,7 @@ define <8 x i64> @ult_36_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12503,14 +12503,14 @@ define <8 x i64> @ult_36_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_36_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12519,7 +12519,7 @@ define <8 x i64> @ult_36_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12550,7 +12550,7 @@ define <8 x i64> @ugt_36_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12566,14 +12566,14 @@ define <8 x i64> @ugt_36_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_36_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12582,7 +12582,7 @@ define <8 x i64> @ugt_36_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12613,7 +12613,7 @@ define <8 x i64> @ult_37_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12629,14 +12629,14 @@ define <8 x i64> @ult_37_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_37_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12645,7 +12645,7 @@ define <8 x i64> @ult_37_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12676,7 +12676,7 @@ define <8 x i64> @ugt_37_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12692,14 +12692,14 @@ define <8 x i64> @ugt_37_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_37_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12708,7 +12708,7 @@ define <8 x i64> @ugt_37_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12739,7 +12739,7 @@ define <8 x i64> @ult_38_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12755,14 +12755,14 @@ define <8 x i64> @ult_38_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_38_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12771,7 +12771,7 @@ define <8 x i64> @ult_38_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12802,7 +12802,7 @@ define <8 x i64> @ugt_38_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12818,14 +12818,14 @@ define <8 x i64> @ugt_38_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_38_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12834,7 +12834,7 @@ define <8 x i64> @ugt_38_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12865,7 +12865,7 @@ define <8 x i64> @ult_39_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12881,14 +12881,14 @@ define <8 x i64> @ult_39_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_39_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12897,7 +12897,7 @@ define <8 x i64> @ult_39_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12928,7 +12928,7 @@ define <8 x i64> @ugt_39_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -12944,14 +12944,14 @@ define <8 x i64> @ugt_39_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_39_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -12960,7 +12960,7 @@ define <8 x i64> @ugt_39_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -12991,7 +12991,7 @@ define <8 x i64> @ult_40_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13007,14 +13007,14 @@ define <8 x i64> @ult_40_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_40_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13023,7 +13023,7 @@ define <8 x i64> @ult_40_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13054,7 +13054,7 @@ define <8 x i64> @ugt_40_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13070,14 +13070,14 @@ define <8 x i64> @ugt_40_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_40_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13086,7 +13086,7 @@ define <8 x i64> @ugt_40_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13117,7 +13117,7 @@ define <8 x i64> @ult_41_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13133,14 +13133,14 @@ define <8 x i64> @ult_41_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_41_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13149,7 +13149,7 @@ define <8 x i64> @ult_41_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13180,7 +13180,7 @@ define <8 x i64> @ugt_41_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13196,14 +13196,14 @@ define <8 x i64> @ugt_41_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_41_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13212,7 +13212,7 @@ define <8 x i64> @ugt_41_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13243,7 +13243,7 @@ define <8 x i64> @ult_42_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13259,14 +13259,14 @@ define <8 x i64> @ult_42_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_42_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13275,7 +13275,7 @@ define <8 x i64> @ult_42_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13306,7 +13306,7 @@ define <8 x i64> @ugt_42_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13322,14 +13322,14 @@ define <8 x i64> @ugt_42_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_42_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13338,7 +13338,7 @@ define <8 x i64> @ugt_42_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13369,7 +13369,7 @@ define <8 x i64> @ult_43_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13385,14 +13385,14 @@ define <8 x i64> @ult_43_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_43_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13401,7 +13401,7 @@ define <8 x i64> @ult_43_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13432,7 +13432,7 @@ define <8 x i64> @ugt_43_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13448,14 +13448,14 @@ define <8 x i64> @ugt_43_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_43_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13464,7 +13464,7 @@ define <8 x i64> @ugt_43_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13495,7 +13495,7 @@ define <8 x i64> @ult_44_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13511,14 +13511,14 @@ define <8 x i64> @ult_44_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_44_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13527,7 +13527,7 @@ define <8 x i64> @ult_44_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13558,7 +13558,7 @@ define <8 x i64> @ugt_44_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13574,14 +13574,14 @@ define <8 x i64> @ugt_44_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_44_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13590,7 +13590,7 @@ define <8 x i64> @ugt_44_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13621,7 +13621,7 @@ define <8 x i64> @ult_45_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13637,14 +13637,14 @@ define <8 x i64> @ult_45_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_45_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13653,7 +13653,7 @@ define <8 x i64> @ult_45_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13684,7 +13684,7 @@ define <8 x i64> @ugt_45_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13700,14 +13700,14 @@ define <8 x i64> @ugt_45_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_45_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13716,7 +13716,7 @@ define <8 x i64> @ugt_45_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13747,7 +13747,7 @@ define <8 x i64> @ult_46_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13763,14 +13763,14 @@ define <8 x i64> @ult_46_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_46_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13779,7 +13779,7 @@ define <8 x i64> @ult_46_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13810,7 +13810,7 @@ define <8 x i64> @ugt_46_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13826,14 +13826,14 @@ define <8 x i64> @ugt_46_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_46_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13842,7 +13842,7 @@ define <8 x i64> @ugt_46_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13873,7 +13873,7 @@ define <8 x i64> @ult_47_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13889,14 +13889,14 @@ define <8 x i64> @ult_47_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_47_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13905,7 +13905,7 @@ define <8 x i64> @ult_47_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13936,7 +13936,7 @@ define <8 x i64> @ugt_47_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -13952,14 +13952,14 @@ define <8 x i64> @ugt_47_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_47_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -13968,7 +13968,7 @@ define <8 x i64> @ugt_47_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -13999,7 +13999,7 @@ define <8 x i64> @ult_48_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14015,14 +14015,14 @@ define <8 x i64> @ult_48_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_48_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14031,7 +14031,7 @@ define <8 x i64> @ult_48_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14062,7 +14062,7 @@ define <8 x i64> @ugt_48_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14078,14 +14078,14 @@ define <8 x i64> @ugt_48_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_48_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14094,7 +14094,7 @@ define <8 x i64> @ugt_48_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14125,7 +14125,7 @@ define <8 x i64> @ult_49_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14141,14 +14141,14 @@ define <8 x i64> @ult_49_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_49_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14157,7 +14157,7 @@ define <8 x i64> @ult_49_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14188,7 +14188,7 @@ define <8 x i64> @ugt_49_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14204,14 +14204,14 @@ define <8 x i64> @ugt_49_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_49_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14220,7 +14220,7 @@ define <8 x i64> @ugt_49_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14251,7 +14251,7 @@ define <8 x i64> @ult_50_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14267,14 +14267,14 @@ define <8 x i64> @ult_50_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_50_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14283,7 +14283,7 @@ define <8 x i64> @ult_50_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14314,7 +14314,7 @@ define <8 x i64> @ugt_50_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14330,14 +14330,14 @@ define <8 x i64> @ugt_50_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_50_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14346,7 +14346,7 @@ define <8 x i64> @ugt_50_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14377,7 +14377,7 @@ define <8 x i64> @ult_51_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14393,14 +14393,14 @@ define <8 x i64> @ult_51_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_51_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14409,7 +14409,7 @@ define <8 x i64> @ult_51_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14440,7 +14440,7 @@ define <8 x i64> @ugt_51_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14456,14 +14456,14 @@ define <8 x i64> @ugt_51_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_51_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14472,7 +14472,7 @@ define <8 x i64> @ugt_51_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14503,7 +14503,7 @@ define <8 x i64> @ult_52_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14519,14 +14519,14 @@ define <8 x i64> @ult_52_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_52_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14535,7 +14535,7 @@ define <8 x i64> @ult_52_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14566,7 +14566,7 @@ define <8 x i64> @ugt_52_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14582,14 +14582,14 @@ define <8 x i64> @ugt_52_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_52_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14598,7 +14598,7 @@ define <8 x i64> @ugt_52_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14629,7 +14629,7 @@ define <8 x i64> @ult_53_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14645,14 +14645,14 @@ define <8 x i64> @ult_53_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_53_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14661,7 +14661,7 @@ define <8 x i64> @ult_53_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14692,7 +14692,7 @@ define <8 x i64> @ugt_53_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14708,14 +14708,14 @@ define <8 x i64> @ugt_53_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_53_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14724,7 +14724,7 @@ define <8 x i64> @ugt_53_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14755,7 +14755,7 @@ define <8 x i64> @ult_54_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14771,14 +14771,14 @@ define <8 x i64> @ult_54_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_54_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14787,7 +14787,7 @@ define <8 x i64> @ult_54_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14818,7 +14818,7 @@ define <8 x i64> @ugt_54_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14834,14 +14834,14 @@ define <8 x i64> @ugt_54_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_54_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14850,7 +14850,7 @@ define <8 x i64> @ugt_54_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14881,7 +14881,7 @@ define <8 x i64> @ult_55_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14897,14 +14897,14 @@ define <8 x i64> @ult_55_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_55_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14913,7 +14913,7 @@ define <8 x i64> @ult_55_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -14944,7 +14944,7 @@ define <8 x i64> @ugt_55_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -14960,14 +14960,14 @@ define <8 x i64> @ugt_55_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_55_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -14976,7 +14976,7 @@ define <8 x i64> @ugt_55_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15007,7 +15007,7 @@ define <8 x i64> @ult_56_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15023,14 +15023,14 @@ define <8 x i64> @ult_56_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_56_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15039,7 +15039,7 @@ define <8 x i64> @ult_56_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15070,7 +15070,7 @@ define <8 x i64> @ugt_56_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15086,14 +15086,14 @@ define <8 x i64> @ugt_56_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_56_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15102,7 +15102,7 @@ define <8 x i64> @ugt_56_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15133,7 +15133,7 @@ define <8 x i64> @ult_57_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15149,14 +15149,14 @@ define <8 x i64> @ult_57_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_57_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15165,7 +15165,7 @@ define <8 x i64> @ult_57_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15196,7 +15196,7 @@ define <8 x i64> @ugt_57_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15212,14 +15212,14 @@ define <8 x i64> @ugt_57_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_57_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15228,7 +15228,7 @@ define <8 x i64> @ugt_57_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15259,7 +15259,7 @@ define <8 x i64> @ult_58_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15275,14 +15275,14 @@ define <8 x i64> @ult_58_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_58_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15291,7 +15291,7 @@ define <8 x i64> @ult_58_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15322,7 +15322,7 @@ define <8 x i64> @ugt_58_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15338,14 +15338,14 @@ define <8 x i64> @ugt_58_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_58_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15354,7 +15354,7 @@ define <8 x i64> @ugt_58_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15385,7 +15385,7 @@ define <8 x i64> @ult_59_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15401,14 +15401,14 @@ define <8 x i64> @ult_59_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_59_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15417,7 +15417,7 @@ define <8 x i64> @ult_59_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15448,7 +15448,7 @@ define <8 x i64> @ugt_59_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15464,14 +15464,14 @@ define <8 x i64> @ugt_59_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_59_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15480,7 +15480,7 @@ define <8 x i64> @ugt_59_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15511,7 +15511,7 @@ define <8 x i64> @ult_60_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15527,14 +15527,14 @@ define <8 x i64> @ult_60_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_60_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15543,7 +15543,7 @@ define <8 x i64> @ult_60_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15574,7 +15574,7 @@ define <8 x i64> @ugt_60_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15590,14 +15590,14 @@ define <8 x i64> @ugt_60_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_60_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15606,7 +15606,7 @@ define <8 x i64> @ugt_60_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15637,7 +15637,7 @@ define <8 x i64> @ult_61_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15653,14 +15653,14 @@ define <8 x i64> @ult_61_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_61_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15669,7 +15669,7 @@ define <8 x i64> @ult_61_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15700,7 +15700,7 @@ define <8 x i64> @ugt_61_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15716,14 +15716,14 @@ define <8 x i64> @ugt_61_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_61_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15732,7 +15732,7 @@ define <8 x i64> @ugt_61_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15763,7 +15763,7 @@ define <8 x i64> @ult_62_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15779,14 +15779,14 @@ define <8 x i64> @ult_62_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_62_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15795,7 +15795,7 @@ define <8 x i64> @ult_62_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15826,7 +15826,7 @@ define <8 x i64> @ugt_62_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15842,14 +15842,14 @@ define <8 x i64> @ugt_62_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ugt_62_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15858,7 +15858,7 @@ define <8 x i64> @ugt_62_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpnleuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
@@ -15889,7 +15889,7 @@ define <8 x i64> @ult_63_v8i64(<8 x i64> %0) {
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512F-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
@@ -15905,14 +15905,14 @@ define <8 x i64> @ult_63_v8i64(<8 x i64> %0) {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512BW-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: ult_63_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -15921,7 +15921,7 @@ define <8 x i64> @ult_63_v8i64(<8 x i64> %0) {
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %zmm1, %zmm0, %zmm0
-; BITALG-NEXT: vpcmpltuq {{.*}}(%rip){1to8}, %zmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; BITALG-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; BITALG-NEXT: retq
%2 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %0)
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-512.ll b/llvm/test/CodeGen/X86/vector-popcnt-512.ll
index c329b64fc3462..552a27daf971a 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-512.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-512.ll
@@ -299,7 +299,7 @@ define <8 x i64> @eq_1_v8i64(<8 x i64> %0) {
; AVX512VPOPCNTDQ-LABEL: eq_1_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpeqq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -341,7 +341,7 @@ define <8 x i64> @ne_1_v8i64(<8 x i64> %0) {
; AVX512VPOPCNTDQ-LABEL: ne_1_v8i64:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpneqq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpneqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -382,7 +382,7 @@ define <16 x i32> @eq_1_v16i32(<16 x i32> %0) {
; AVX512VPOPCNTDQ-LABEL: eq_1_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpeqd {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -424,7 +424,7 @@ define <16 x i32> @ne_1_v16i32(<16 x i32> %0) {
; AVX512VPOPCNTDQ-LABEL: ne_1_v16i32:
; AVX512VPOPCNTDQ: # %bb.0:
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
-; AVX512VPOPCNTDQ-NEXT: vpcmpneqd {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512VPOPCNTDQ-NEXT: vpcmpneqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512VPOPCNTDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VPOPCNTDQ-NEXT: retq
;
@@ -501,7 +501,7 @@ define <32 x i16> @eq_1_v32i16(<32 x i16> %0) {
; BITALG-LABEL: eq_1_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpeqw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -572,7 +572,7 @@ define <32 x i16> @ne_1_v32i16(<32 x i16> %0) {
; BITALG-LABEL: ne_1_v32i16:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntw %zmm0, %zmm0
-; BITALG-NEXT: vpcmpneqw {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpneqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2w %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %0)
@@ -639,7 +639,7 @@ define <64 x i8> @eq_1_v64i8(<64 x i8> %0) {
; BITALG-LABEL: eq_1_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpeqb {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
@@ -710,7 +710,7 @@ define <64 x i8> @ne_1_v64i8(<64 x i8> %0) {
; BITALG-LABEL: ne_1_v64i8:
; BITALG: # %bb.0:
; BITALG-NEXT: vpopcntb %zmm0, %zmm0
-; BITALG-NEXT: vpcmpneqb {{.*}}(%rip), %zmm0, %k0
+; BITALG-NEXT: vpcmpneqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k0
; BITALG-NEXT: vpmovm2b %k0, %zmm0
; BITALG-NEXT: retq
%2 = tail call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %0)
diff --git a/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll b/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
index 50aad826e7307..068148d69498d 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
@@ -367,7 +367,7 @@ define i1 @trunc_v16i16_v16i1(<16 x i16>) {
;
; AVX1-LABEL: trunc_v16i16_v16i1:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
@@ -379,7 +379,7 @@ define i1 @trunc_v16i16_v16i1(<16 x i16>) {
;
; AVX2-LABEL: trunc_v16i16_v16i1:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsllw $7, %xmm0, %xmm0
@@ -691,7 +691,7 @@ define i1 @trunc_v32i16_v32i1(<32 x i16>) {
; AVX1-LABEL: trunc_v32i16_v32i1:
; AVX1: # %bb.0:
; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fadd.ll b/llvm/test/CodeGen/X86/vector-reduce-fadd.ll
index 0ca7d70736618..f81b841824992 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fadd.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fadd.ll
@@ -783,25 +783,25 @@ define float @test_v2f32_undef(<2 x float> %a0) {
; SSE2-LABEL: test_v2f32_undef:
; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE2-NEXT: addss {{.*}}(%rip), %xmm0
+; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: test_v2f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE41-NEXT: addss {{.*}}(%rip), %xmm0
+; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX-LABEL: test_v2f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX512-LABEL: test_v2f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX512-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = call float @llvm.vector.reduce.fadd.f32.v2f32(float undef, <2 x float> %a0)
ret float %1
@@ -812,7 +812,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
-; SSE2-NEXT: addss {{.*}}(%rip), %xmm1
+; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: addss %xmm1, %xmm2
@@ -823,7 +823,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; SSE41-NEXT: addss {{.*}}(%rip), %xmm1
+; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movaps %xmm0, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE41-NEXT: addss %xmm1, %xmm2
@@ -834,7 +834,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; AVX-LABEL: test_v4f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vaddss %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3]
@@ -844,7 +844,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; AVX512-LABEL: test_v4f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-NEXT: vaddss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3]
@@ -859,7 +859,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
-; SSE2-NEXT: addss {{.*}}(%rip), %xmm2
+; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: addss %xmm2, %xmm3
@@ -879,7 +879,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; SSE41-NEXT: addss {{.*}}(%rip), %xmm2
+; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movaps %xmm0, %xmm3
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE41-NEXT: addss %xmm2, %xmm3
@@ -898,7 +898,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; AVX-LABEL: test_v8f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vaddss %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
@@ -917,7 +917,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; AVX512-LABEL: test_v8f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-NEXT: vaddss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
@@ -941,7 +941,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
-; SSE2-NEXT: addss {{.*}}(%rip), %xmm4
+; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: movaps %xmm0, %xmm5
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE2-NEXT: addss %xmm4, %xmm5
@@ -979,7 +979,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE41-NEXT: addss {{.*}}(%rip), %xmm4
+; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: movaps %xmm0, %xmm5
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE41-NEXT: addss %xmm4, %xmm5
@@ -1014,7 +1014,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; AVX-LABEL: test_v16f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; AVX-NEXT: vaddss {{.*}}(%rip), %xmm2, %xmm2
+; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,3,3,3]
@@ -1048,7 +1048,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; AVX512-LABEL: test_v16f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-NEXT: vaddss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
@@ -1696,19 +1696,19 @@ define double @test_v2f64_undef(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_v2f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX512-LABEL: test_v2f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fadd.f64.v2f64(double undef, <2 x double> %a0)
ret double %1
@@ -1718,7 +1718,7 @@ define double @test_v4f64_undef(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0
@@ -1727,7 +1727,7 @@ define double @test_v4f64_undef(<4 x double> %a0) {
; AVX-LABEL: test_v4f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1738,7 +1738,7 @@ define double @test_v4f64_undef(<4 x double> %a0) {
; AVX512-LABEL: test_v4f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX512-NEXT: vaddsd {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vaddsd %xmm0, %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1753,7 +1753,7 @@ define double @test_v8f64_undef(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0
@@ -1768,7 +1768,7 @@ define double @test_v8f64_undef(<8 x double> %a0) {
; AVX-LABEL: test_v8f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm2, %xmm2
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vaddsd %xmm0, %xmm2, %xmm2
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1786,7 +1786,7 @@ define double @test_v8f64_undef(<8 x double> %a0) {
; AVX512-LABEL: test_v8f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX512-NEXT: vaddsd {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX512-NEXT: vaddsd %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
@@ -1809,7 +1809,7 @@ define double @test_v16f64_undef(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0
@@ -1836,7 +1836,7 @@ define double @test_v16f64_undef(<16 x double> %a0) {
; AVX-LABEL: test_v16f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm4, %xmm4
+; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vaddsd %xmm0, %xmm4, %xmm4
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1868,7 +1868,7 @@ define double @test_v16f64_undef(<16 x double> %a0) {
; AVX512-LABEL: test_v16f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX512-NEXT: vaddsd {{.*}}(%rip), %xmm2, %xmm2
+; AVX512-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX512-NEXT: vaddsd %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vpermilpd {{.*#+}} xmm3 = xmm3[1,0]
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmul.ll b/llvm/test/CodeGen/X86/vector-reduce-fmul.ll
index 7e1d6afa57cc7..9fbe21cfaa1aa 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fmul.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fmul.ll
@@ -648,25 +648,25 @@ define float @test_v2f32_undef(<2 x float> %a0) {
; SSE2-LABEL: test_v2f32_undef:
; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE2-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: test_v2f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE41-NEXT: mulss {{.*}}(%rip), %xmm0
+; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX-LABEL: test_v2f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX512-LABEL: test_v2f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = call float @llvm.vector.reduce.fmul.f32.v2f32(float undef, <2 x float> %a0)
ret float %1
@@ -677,7 +677,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
-; SSE2-NEXT: mulss {{.*}}(%rip), %xmm1
+; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: mulss %xmm1, %xmm2
@@ -688,7 +688,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; SSE41-NEXT: mulss {{.*}}(%rip), %xmm1
+; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movaps %xmm0, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE41-NEXT: mulss %xmm1, %xmm2
@@ -699,7 +699,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; AVX-LABEL: test_v4f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3]
@@ -709,7 +709,7 @@ define float @test_v4f32_undef(<4 x float> %a0) {
; AVX512-LABEL: test_v4f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3]
@@ -724,7 +724,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
-; SSE2-NEXT: mulss {{.*}}(%rip), %xmm2
+; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: mulss %xmm2, %xmm3
@@ -744,7 +744,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; SSE41-NEXT: mulss {{.*}}(%rip), %xmm2
+; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movaps %xmm0, %xmm3
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE41-NEXT: mulss %xmm2, %xmm3
@@ -763,7 +763,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; AVX-LABEL: test_v8f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
@@ -782,7 +782,7 @@ define float @test_v8f32_undef(<8 x float> %a0) {
; AVX512-LABEL: test_v8f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
@@ -806,7 +806,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
-; SSE2-NEXT: mulss {{.*}}(%rip), %xmm4
+; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: movaps %xmm0, %xmm5
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE2-NEXT: mulss %xmm4, %xmm5
@@ -844,7 +844,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE41-NEXT: mulss {{.*}}(%rip), %xmm4
+; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: movaps %xmm0, %xmm5
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE41-NEXT: mulss %xmm4, %xmm5
@@ -879,7 +879,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; AVX-LABEL: test_v16f32_undef:
; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; AVX-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
+; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
; AVX-NEXT: vmulss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,3,3,3]
@@ -913,7 +913,7 @@ define float @test_v16f32_undef(<16 x float> %a0) {
; AVX512-LABEL: test_v16f32_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
@@ -1431,19 +1431,19 @@ define double @test_v2f64_undef(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: mulsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test_v2f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX-NEXT: vmulsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
; AVX512-LABEL: test_v2f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT: vmulsd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fmul.f64.v2f64(double undef, <2 x double> %a0)
ret double %1
@@ -1453,7 +1453,7 @@ define double @test_v4f64_undef(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: mulsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0
@@ -1462,7 +1462,7 @@ define double @test_v4f64_undef(<4 x double> %a0) {
; AVX-LABEL: test_v4f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vmulsd {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmulsd %xmm0, %xmm1, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1473,7 +1473,7 @@ define double @test_v4f64_undef(<4 x double> %a0) {
; AVX512-LABEL: test_v4f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX512-NEXT: vmulsd {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vmulsd %xmm0, %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1488,7 +1488,7 @@ define double @test_v8f64_undef(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: mulsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0
@@ -1503,7 +1503,7 @@ define double @test_v8f64_undef(<8 x double> %a0) {
; AVX-LABEL: test_v8f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX-NEXT: vmulsd {{.*}}(%rip), %xmm2, %xmm2
+; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmulsd %xmm0, %xmm2, %xmm2
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1521,7 +1521,7 @@ define double @test_v8f64_undef(<8 x double> %a0) {
; AVX512-LABEL: test_v8f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX512-NEXT: vmulsd {{.*}}(%rip), %xmm1, %xmm1
+; AVX512-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX512-NEXT: vmulsd %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
@@ -1544,7 +1544,7 @@ define double @test_v16f64_undef(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
-; SSE-NEXT: mulsd {{.*}}(%rip), %xmm0
+; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0
@@ -1571,7 +1571,7 @@ define double @test_v16f64_undef(<16 x double> %a0) {
; AVX-LABEL: test_v16f64_undef:
; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX-NEXT: vmulsd {{.*}}(%rip), %xmm4, %xmm4
+; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmulsd %xmm0, %xmm4, %xmm4
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
@@ -1603,7 +1603,7 @@ define double @test_v16f64_undef(<16 x double> %a0) {
; AVX512-LABEL: test_v16f64_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX512-NEXT: vmulsd {{.*}}(%rip), %xmm2, %xmm2
+; AVX512-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX512-NEXT: vmulsd %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vpermilpd {{.*#+}} xmm3 = xmm3[1,0]
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-bool.ll b/llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
index fea4d6af55062..6269cd4df1119 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
@@ -362,7 +362,7 @@ define i1 @trunc_v16i16_v16i1(<16 x i16>) {
;
; AVX1-LABEL: trunc_v16i16_v16i1:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
@@ -374,7 +374,7 @@ define i1 @trunc_v16i16_v16i1(<16 x i16>) {
;
; AVX2-LABEL: trunc_v16i16_v16i1:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsllw $7, %xmm0, %xmm0
@@ -684,7 +684,7 @@ define i1 @trunc_v32i16_v32i1(<32 x i16>) {
; AVX1-LABEL: trunc_v32i16_v32i1:
; AVX1: # %bb.0:
; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
index a06c7052044e6..31cbb9a1afefa 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
@@ -832,13 +832,13 @@ define i1 @trunc_v2i64(<2 x i64> %a0) {
;
; SSE41-LABEL: trunc_v2i64:
; SSE41: # %bb.0:
-; SSE41-NEXT: ptest {{.*}}(%rip), %xmm0
+; SSE41-NEXT: ptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX-LABEL: trunc_v2i64:
; AVX: # %bb.0:
-; AVX-NEXT: vptest {{.*}}(%rip), %xmm0
+; AVX-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX-NEXT: sete %al
; AVX-NEXT: retq
%1 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a0)
@@ -851,7 +851,7 @@ define i1 @mask_v8i32(<8 x i32> %a0) {
; SSE2-LABEL: mask_v8i32:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
@@ -862,13 +862,13 @@ define i1 @mask_v8i32(<8 x i32> %a0) {
; SSE41-LABEL: mask_v8i32:
; SSE41: # %bb.0:
; SSE41-NEXT: por %xmm1, %xmm0
-; SSE41-NEXT: ptest {{.*}}(%rip), %xmm0
+; SSE41-NEXT: ptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX1-LABEL: mask_v8i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vptest {{.*}}(%rip), %ymm0
+; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -898,7 +898,7 @@ define i1 @trunc_v16i16(<16 x i16> %a0) {
; SSE2-LABEL: trunc_v16i16:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
@@ -909,13 +909,13 @@ define i1 @trunc_v16i16(<16 x i16> %a0) {
; SSE41-LABEL: trunc_v16i16:
; SSE41: # %bb.0:
; SSE41-NEXT: por %xmm1, %xmm0
-; SSE41-NEXT: ptest {{.*}}(%rip), %xmm0
+; SSE41-NEXT: ptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: setne %al
; SSE41-NEXT: retq
;
; AVX1-LABEL: trunc_v16i16:
; AVX1: # %bb.0:
-; AVX1-NEXT: vptest {{.*}}(%rip), %ymm0
+; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0
; AVX1-NEXT: setne %al
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -951,7 +951,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) {
; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: por %xmm3, %xmm2
; SSE2-NEXT: por %xmm0, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: pcmpeqb %xmm2, %xmm0
; SSE2-NEXT: pmovmskb %xmm0, %eax
@@ -968,7 +968,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) {
; SSE41-NEXT: por %xmm4, %xmm2
; SSE41-NEXT: por %xmm3, %xmm2
; SSE41-NEXT: por %xmm0, %xmm2
-; SSE41-NEXT: ptest {{.*}}(%rip), %xmm2
+; SSE41-NEXT: ptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
@@ -977,7 +977,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) {
; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vorps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vptest {{.*}}(%rip), %ymm0
+; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -1014,7 +1014,7 @@ define zeroext i1 @PR44781(%struct.Box* %0) {
; SSE2-LABEL: PR44781:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqu (%rdi), %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
@@ -1025,14 +1025,14 @@ define zeroext i1 @PR44781(%struct.Box* %0) {
; SSE41-LABEL: PR44781:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqu (%rdi), %xmm0
-; SSE41-NEXT: ptest {{.*}}(%rip), %xmm0
+; SSE41-NEXT: ptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX-LABEL: PR44781:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqu (%rdi), %xmm0
-; AVX-NEXT: vptest {{.*}}(%rip), %xmm0
+; AVX-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX-NEXT: sete %al
; AVX-NEXT: retq
%2 = bitcast %struct.Box* %0 to <4 x i32>*
diff --git a/llvm/test/CodeGen/X86/vector-reduce-smax.ll b/llvm/test/CodeGen/X86/vector-reduce-smax.ll
index ccbbe53db84be..c09791787d518 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-smax.ll
@@ -1192,7 +1192,7 @@ define i16 @test_v8i16(<8 x i16> %a0) {
;
; SSE4-LABEL: test_v8i16:
; SSE4: # %bb.0:
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: phminposuw %xmm0, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1201,7 +1201,7 @@ define i16 @test_v8i16(<8 x i16> %a0) {
;
; AVX-LABEL: test_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vphminposuw %xmm0, %xmm0
; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1210,7 +1210,7 @@ define i16 @test_v8i16(<8 x i16> %a0) {
;
; AVX512-LABEL: test_v8i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1238,7 +1238,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; SSE4-LABEL: test_v16i16:
; SSE4: # %bb.0:
; SSE4-NEXT: pmaxsw %xmm1, %xmm0
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: phminposuw %xmm0, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1249,7 +1249,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1261,7 +1261,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1273,7 +1273,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1306,7 +1306,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; SSE4-NEXT: pmaxsw %xmm3, %xmm1
; SSE4-NEXT: pmaxsw %xmm2, %xmm1
; SSE4-NEXT: pmaxsw %xmm0, %xmm1
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm1
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: phminposuw %xmm1, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1320,7 +1320,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpmaxsw %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1333,7 +1333,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1347,7 +1347,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1388,7 +1388,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; SSE4-NEXT: pmaxsw %xmm4, %xmm2
; SSE4-NEXT: pmaxsw %xmm3, %xmm2
; SSE4-NEXT: pmaxsw %xmm0, %xmm2
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm2
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE4-NEXT: phminposuw %xmm2, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1408,7 +1408,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; AVX1-NEXT: vpmaxsw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpmaxsw %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1423,7 +1423,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1438,7 +1438,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32767, %eax # imm = 0x7FFF
@@ -1654,7 +1654,7 @@ define i8 @test_v16i8(<16 x i8> %a0) {
;
; SSE4-LABEL: test_v16i8:
; SSE4: # %bb.0:
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: movdqa %xmm0, %xmm1
; SSE4-NEXT: psrlw $8, %xmm1
; SSE4-NEXT: pminub %xmm0, %xmm1
@@ -1666,7 +1666,7 @@ define i8 @test_v16i8(<16 x i8> %a0) {
;
; AVX-LABEL: test_v16i8:
; AVX: # %bb.0:
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -1677,7 +1677,7 @@ define i8 @test_v16i8(<16 x i8> %a0) {
;
; AVX512-LABEL: test_v16i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1730,7 +1730,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; SSE4-LABEL: test_v32i8:
; SSE4: # %bb.0:
; SSE4-NEXT: pmaxsb %xmm1, %xmm0
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: movdqa %xmm0, %xmm1
; SSE4-NEXT: psrlw $8, %xmm1
; SSE4-NEXT: pminub %xmm0, %xmm1
@@ -1744,7 +1744,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1758,7 +1758,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1772,7 +1772,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1838,7 +1838,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; SSE4-NEXT: pmaxsb %xmm3, %xmm1
; SSE4-NEXT: pmaxsb %xmm2, %xmm1
; SSE4-NEXT: pmaxsb %xmm0, %xmm1
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm1
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: movdqa %xmm1, %xmm0
; SSE4-NEXT: psrlw $8, %xmm0
; SSE4-NEXT: pminub %xmm1, %xmm0
@@ -1855,7 +1855,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpmaxsb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1870,7 +1870,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1886,7 +1886,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1976,7 +1976,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; SSE4-NEXT: pmaxsb %xmm4, %xmm2
; SSE4-NEXT: pmaxsb %xmm3, %xmm2
; SSE4-NEXT: pmaxsb %xmm0, %xmm2
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm2
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE4-NEXT: movdqa %xmm2, %xmm0
; SSE4-NEXT: psrlw $8, %xmm0
; SSE4-NEXT: pminub %xmm2, %xmm0
@@ -1999,7 +1999,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX1-NEXT: vpmaxsb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpmaxsb %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -2016,7 +2016,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -2033,7 +2033,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-reduce-smin.ll b/llvm/test/CodeGen/X86/vector-reduce-smin.ll
index 47c2a4beae353..16d58b7742ab2 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-smin.ll
@@ -1192,7 +1192,7 @@ define i16 @test_v8i16(<8 x i16> %a0) {
;
; SSE4-LABEL: test_v8i16:
; SSE4: # %bb.0:
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: phminposuw %xmm0, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1201,7 +1201,7 @@ define i16 @test_v8i16(<8 x i16> %a0) {
;
; AVX-LABEL: test_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vphminposuw %xmm0, %xmm0
; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1210,7 +1210,7 @@ define i16 @test_v8i16(<8 x i16> %a0) {
;
; AVX512-LABEL: test_v8i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1238,7 +1238,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; SSE4-LABEL: test_v16i16:
; SSE4: # %bb.0:
; SSE4-NEXT: pminsw %xmm1, %xmm0
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: phminposuw %xmm0, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1249,7 +1249,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1261,7 +1261,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1273,7 +1273,7 @@ define i16 @test_v16i16(<16 x i16> %a0) {
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1306,7 +1306,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; SSE4-NEXT: pminsw %xmm3, %xmm1
; SSE4-NEXT: pminsw %xmm2, %xmm1
; SSE4-NEXT: pminsw %xmm0, %xmm1
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm1
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: phminposuw %xmm1, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1320,7 +1320,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpminsw %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1333,7 +1333,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1347,7 +1347,7 @@ define i16 @test_v32i16(<32 x i16> %a0) {
; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1388,7 +1388,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; SSE4-NEXT: pminsw %xmm4, %xmm2
; SSE4-NEXT: pminsw %xmm3, %xmm2
; SSE4-NEXT: pminsw %xmm0, %xmm2
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm2
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE4-NEXT: phminposuw %xmm2, %xmm0
; SSE4-NEXT: movd %xmm0, %eax
; SSE4-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1408,7 +1408,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; AVX1-NEXT: vpminsw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpminsw %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1423,7 +1423,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1438,7 +1438,7 @@ define i16 @test_v64i16(<64 x i16> %a0) {
; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpminsw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: xorl $32768, %eax # imm = 0x8000
@@ -1654,7 +1654,7 @@ define i8 @test_v16i8(<16 x i8> %a0) {
;
; SSE4-LABEL: test_v16i8:
; SSE4: # %bb.0:
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: movdqa %xmm0, %xmm1
; SSE4-NEXT: psrlw $8, %xmm1
; SSE4-NEXT: pminub %xmm0, %xmm1
@@ -1666,7 +1666,7 @@ define i8 @test_v16i8(<16 x i8> %a0) {
;
; AVX-LABEL: test_v16i8:
; AVX: # %bb.0:
-; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX-NEXT: vphminposuw %xmm0, %xmm0
@@ -1677,7 +1677,7 @@ define i8 @test_v16i8(<16 x i8> %a0) {
;
; AVX512-LABEL: test_v16i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1730,7 +1730,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; SSE4-LABEL: test_v32i8:
; SSE4: # %bb.0:
; SSE4-NEXT: pminsb %xmm1, %xmm0
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm0
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: movdqa %xmm0, %xmm1
; SSE4-NEXT: psrlw $8, %xmm1
; SSE4-NEXT: pminub %xmm0, %xmm1
@@ -1744,7 +1744,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1758,7 +1758,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1772,7 +1772,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1838,7 +1838,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; SSE4-NEXT: pminsb %xmm3, %xmm1
; SSE4-NEXT: pminsb %xmm2, %xmm1
; SSE4-NEXT: pminsb %xmm0, %xmm1
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm1
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: movdqa %xmm1, %xmm0
; SSE4-NEXT: psrlw $8, %xmm0
; SSE4-NEXT: pminub %xmm1, %xmm0
@@ -1855,7 +1855,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpminsb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -1870,7 +1870,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -1886,7 +1886,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
@@ -1976,7 +1976,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; SSE4-NEXT: pminsb %xmm4, %xmm2
; SSE4-NEXT: pminsb %xmm3, %xmm2
; SSE4-NEXT: pminsb %xmm0, %xmm2
-; SSE4-NEXT: pxor {{.*}}(%rip), %xmm2
+; SSE4-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE4-NEXT: movdqa %xmm2, %xmm0
; SSE4-NEXT: psrlw $8, %xmm0
; SSE4-NEXT: pminub %xmm2, %xmm0
@@ -1999,7 +1999,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX1-NEXT: vpminsb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpminsb %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vphminposuw %xmm0, %xmm0
@@ -2016,7 +2016,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX2-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vphminposuw %xmm0, %xmm0
@@ -2033,7 +2033,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpminsb %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vphminposuw %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll b/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
index b5263772a6af1..7ef49de025531 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
@@ -367,7 +367,7 @@ define i1 @trunc_v16i16_v16i1(<16 x i16>) {
;
; AVX1-LABEL: trunc_v16i16_v16i1:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
@@ -379,7 +379,7 @@ define i1 @trunc_v16i16_v16i1(<16 x i16>) {
;
; AVX2-LABEL: trunc_v16i16_v16i1:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsllw $7, %xmm0, %xmm0
@@ -736,7 +736,7 @@ define i1 @trunc_v32i16_v32i1(<32 x i16>) {
; AVX1-LABEL: trunc_v32i16_v32i1:
; AVX1: # %bb.0:
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-rem.ll b/llvm/test/CodeGen/X86/vector-rem.ll
index 22e060719c0ab..8d32d3e39ace7 100644
--- a/llvm/test/CodeGen/X86/vector-rem.ll
+++ b/llvm/test/CodeGen/X86/vector-rem.ll
@@ -85,25 +85,25 @@ define <4 x float> @qux(<4 x float> %t, <4 x float> %u) nounwind {
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; CHECK-NEXT: callq fmodf
+; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/X86/vector-rotate-256.ll b/llvm/test/CodeGen/X86/vector-rotate-256.ll
index b1a07c91b08db..5e6e8bd7eaf34 100644
--- a/llvm/test/CodeGen/X86/vector-rotate-256.ll
+++ b/llvm/test/CodeGen/X86/vector-rotate-256.ll
@@ -265,7 +265,7 @@ define <16 x i16> @var_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; AVX2-NEXT: vpsllvd %ymm4, %ymm3, %ymm4
; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4
@@ -289,7 +289,7 @@ define <16 x i16> @var_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; AVX512F-LABEL: var_rotate_v16i16:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512F-NEXT: vpsllvd %zmm2, %zmm0, %zmm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
@@ -303,7 +303,7 @@ define <16 x i16> @var_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; AVX512VL-LABEL: var_rotate_v16i16:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512VL-NEXT: vpsllvd %zmm2, %zmm0, %zmm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
@@ -317,7 +317,7 @@ define <16 x i16> @var_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; AVX512BW-LABEL: var_rotate_v16i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm2
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512BW-NEXT: vpsubw %ymm1, %ymm3, %ymm1
@@ -327,7 +327,7 @@ define <16 x i16> @var_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
;
; AVX512VLBW-LABEL: var_rotate_v16i16:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VLBW-NEXT: vpsllvw %ymm1, %ymm0, %ymm2
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512VLBW-NEXT: vpsubw %ymm1, %ymm3, %ymm1
@@ -426,22 +426,22 @@ define <32 x i8> @var_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX2-LABEL: var_rotate_v32i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm2
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpsllw $4, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $6, %ymm0, %ymm2
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2-NEXT: vpsllw $2, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; AVX2-NEXT: vpsrlw $7, %ymm0, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpor %ymm3, %ymm2, %ymm2
; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
@@ -450,22 +450,22 @@ define <32 x i8> @var_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX512F-LABEL: var_rotate_v32i8:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm3
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpor %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $5, %ymm1, %ymm1
; AVX512F-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm2
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm3
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpor %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX512F-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm3
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpor %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX512F-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
@@ -475,17 +475,17 @@ define <32 x i8> @var_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm2
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm2, %ymm3
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; AVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm2
; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm3
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm2, %ymm3
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm2
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm3
-; AVX512VL-NEXT: vpternlogq $248, {{.*}}(%rip), %ymm2, %ymm3
+; AVX512VL-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: retq
@@ -666,7 +666,7 @@ define <8 x i32> @splatvar_rotate_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpslld %xmm3, %xmm2, %xmm4
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [32,32,32,32]
@@ -767,7 +767,7 @@ define <16 x i16> @splatvar_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind
; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX1-NEXT: vpsllw %xmm3, %xmm2, %xmm4
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [16,16,16,16,16,16,16,16]
@@ -784,7 +784,7 @@ define <16 x i16> @splatvar_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind
; AVX2-LABEL: splatvar_rotate_v16i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastw %xmm1, %xmm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX2-NEXT: vpsllw %xmm2, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
@@ -797,7 +797,7 @@ define <16 x i16> @splatvar_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind
; AVX512F-LABEL: splatvar_rotate_v16i16:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpbroadcastw %xmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512F-NEXT: vpsllw %xmm2, %ymm0, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
@@ -810,7 +810,7 @@ define <16 x i16> @splatvar_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind
; AVX512VL-LABEL: splatvar_rotate_v16i16:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpbroadcastw %xmm1, %xmm1
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512VL-NEXT: vpsllw %xmm2, %ymm0, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
@@ -823,7 +823,7 @@ define <16 x i16> @splatvar_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind
; AVX512BW-LABEL: splatvar_rotate_v16i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpbroadcastw %xmm1, %xmm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512BW-NEXT: vpsllw %xmm2, %ymm0, %ymm2
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
@@ -836,7 +836,7 @@ define <16 x i16> @splatvar_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind
; AVX512VLBW-LABEL: splatvar_rotate_v16i16:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpbroadcastw %xmm1, %xmm1
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VLBW-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512VLBW-NEXT: vpsllw %xmm2, %ymm0, %ymm2
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
@@ -891,7 +891,7 @@ define <32 x i8> @splatvar_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm3 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vpsllw %xmm3, %xmm4, %xmm5
@@ -918,7 +918,7 @@ define <32 x i8> @splatvar_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX2-LABEL: splatvar_rotate_v32i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpmovzxbq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
; AVX2-NEXT: vpsllw %xmm2, %ymm0, %ymm3
; AVX2-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
@@ -939,7 +939,7 @@ define <32 x i8> @splatvar_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX512F-LABEL: splatvar_rotate_v32i8:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpbroadcastb %xmm1, %xmm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpmovzxbq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
; AVX512F-NEXT: vpsllw %xmm2, %ymm0, %ymm3
; AVX512F-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
@@ -960,7 +960,7 @@ define <32 x i8> @splatvar_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX512VL-LABEL: splatvar_rotate_v32i8:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpbroadcastb %xmm1, %xmm1
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpmovzxbq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
; AVX512VL-NEXT: vpsllw %xmm2, %ymm0, %ymm3
; AVX512VL-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
@@ -1086,8 +1086,8 @@ define <4 x i64> @constant_rotate_v4i64(<4 x i64> %a) nounwind {
;
; AVX2-LABEL: constant_rotate_v4i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm1
-; AVX2-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
;
@@ -1101,7 +1101,7 @@ define <4 x i64> @constant_rotate_v4i64(<4 x i64> %a) nounwind {
;
; AVX512VL-LABEL: constant_rotate_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vprolvq {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vprolvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: constant_rotate_v4i64:
@@ -1114,7 +1114,7 @@ define <4 x i64> @constant_rotate_v4i64(<4 x i64> %a) nounwind {
;
; AVX512VLBW-LABEL: constant_rotate_v4i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vprolvq {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBW-NEXT: vprolvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: constant_rotate_v4i64:
@@ -1127,22 +1127,22 @@ define <4 x i64> @constant_rotate_v4i64(<4 x i64> %a) nounwind {
;
; AVX512VLVBMI2-LABEL: constant_rotate_v4i64:
; AVX512VLVBMI2: # %bb.0:
-; AVX512VLVBMI2-NEXT: vprolvq {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLVBMI2-NEXT: vprolvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: constant_rotate_v4i64:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: vprotq {{.*}}(%rip), %xmm0, %xmm1
+; XOPAVX1-NEXT: vprotq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; XOPAVX1-NEXT: vprotq {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX1-NEXT: vprotq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: constant_rotate_v4i64:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: vprotq {{.*}}(%rip), %xmm0, %xmm1
+; XOPAVX2-NEXT: vprotq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
-; XOPAVX2-NEXT: vprotq {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX2-NEXT: vprotq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; XOPAVX2-NEXT: retq
%shl = shl <4 x i64> %a, <i64 4, i64 14, i64 50, i64 60>
@@ -1180,8 +1180,8 @@ define <8 x i32> @constant_rotate_v8i32(<8 x i32> %a) nounwind {
;
; AVX2-LABEL: constant_rotate_v8i32:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm1
-; AVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
@@ -1195,7 +1195,7 @@ define <8 x i32> @constant_rotate_v8i32(<8 x i32> %a) nounwind {
;
; AVX512VL-LABEL: constant_rotate_v8i32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vprolvd {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: constant_rotate_v8i32:
@@ -1208,7 +1208,7 @@ define <8 x i32> @constant_rotate_v8i32(<8 x i32> %a) nounwind {
;
; AVX512VLBW-LABEL: constant_rotate_v8i32:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vprolvd {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBW-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: constant_rotate_v8i32:
@@ -1221,22 +1221,22 @@ define <8 x i32> @constant_rotate_v8i32(<8 x i32> %a) nounwind {
;
; AVX512VLVBMI2-LABEL: constant_rotate_v8i32:
; AVX512VLVBMI2: # %bb.0:
-; AVX512VLVBMI2-NEXT: vprolvd {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLVBMI2-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: constant_rotate_v8i32:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm1
+; XOPAVX1-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; XOPAVX1-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX1-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: constant_rotate_v8i32:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm1
+; XOPAVX2-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
-; XOPAVX2-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX2-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; XOPAVX2-NEXT: retq
%shl = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
@@ -1296,8 +1296,8 @@ define <16 x i16> @constant_rotate_v16i16(<16 x i16> %a) nounwind {
;
; AVX512VLBW-LABEL: constant_rotate_v16i16:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vpsrlvw {{.*}}(%rip), %ymm0, %ymm1
-; AVX512VLBW-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX512VLBW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512VLBW-NEXT: retq
;
@@ -1311,22 +1311,22 @@ define <16 x i16> @constant_rotate_v16i16(<16 x i16> %a) nounwind {
;
; AVX512VLVBMI2-LABEL: constant_rotate_v16i16:
; AVX512VLVBMI2: # %bb.0:
-; AVX512VLVBMI2-NEXT: vpshldvw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLVBMI2-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: constant_rotate_v16i16:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: vprotw {{.*}}(%rip), %xmm0, %xmm1
+; XOPAVX1-NEXT: vprotw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; XOPAVX1-NEXT: vprotw {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX1-NEXT: vprotw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: constant_rotate_v16i16:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: vprotw {{.*}}(%rip), %xmm0, %xmm1
+; XOPAVX2-NEXT: vprotw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
-; XOPAVX2-NEXT: vprotw {{.*}}(%rip), %xmm0, %xmm0
+; XOPAVX2-NEXT: vprotw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; XOPAVX2-NEXT: retq
%shl = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
@@ -1379,12 +1379,12 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX2-LABEL: constant_rotate_v32i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsllw $4, %ymm0, %ymm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [8192,24640,41088,57536,57344,41152,24704,8256,8192,24640,41088,57536,57344,41152,24704,8256]
; AVX2-NEXT: # ymm2 = mem[0,1,0,1]
; AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsllw $2, %ymm1, %ymm3
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX2-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm3
@@ -1392,10 +1392,10 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX2-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX2-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]
-; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm0, %ymm1, %ymm0
@@ -1404,12 +1404,12 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512F-LABEL: constant_rotate_v32i8:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [8192,24640,41088,57536,57344,41152,24704,8256,8192,24640,41088,57536,57344,41152,24704,8256]
; AVX512F-NEXT: # ymm2 = mem[0,1,0,1]
; AVX512F-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsllw $2, %ymm1, %ymm3
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm3
@@ -1417,10 +1417,10 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512F-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]
-; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512F-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm0, %ymm1, %ymm0
@@ -1429,12 +1429,12 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VL-LABEL: constant_rotate_v32i8:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm1
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VL-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [8192,24640,41088,57536,57344,41152,24704,8256,8192,24640,41088,57536,57344,41152,24704,8256]
; AVX512VL-NEXT: # ymm2 = mem[0,1,0,1]
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm1
; AVX512VL-NEXT: vpsllw $2, %ymm1, %ymm3
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm3
@@ -1442,10 +1442,10 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm3, %ymm1, %ymm1
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]
-; AVX512VL-NEXT: vpmullw {{.*}}(%rip), %ymm3, %ymm3
+; AVX512VL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
; AVX512VL-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512VL-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]
-; AVX512VL-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512VL-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: vpor %ymm0, %ymm1, %ymm0
@@ -1454,8 +1454,8 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512BW-LABEL: constant_rotate_v32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm1
-; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vporq %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: retq
@@ -1463,8 +1463,8 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VLBW-LABEL: constant_rotate_v32i8:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512VLBW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm1
-; AVX512VLBW-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VLBW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512VLBW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VLBW-NEXT: vporq %zmm0, %zmm1, %zmm0
; AVX512VLBW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512VLBW-NEXT: retq
@@ -1472,8 +1472,8 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VBMI2-LABEL: constant_rotate_v32i8:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512VBMI2-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm1
-; AVX512VBMI2-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VBMI2-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512VBMI2-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VBMI2-NEXT: vporq %zmm0, %zmm1, %zmm0
; AVX512VBMI2-NEXT: vpmovwb %zmm0, %ymm0
; AVX512VBMI2-NEXT: retq
@@ -1481,8 +1481,8 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VLVBMI2-LABEL: constant_rotate_v32i8:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
-; AVX512VLVBMI2-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm1
-; AVX512VLVBMI2-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VLVBMI2-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512VLVBMI2-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VLVBMI2-NEXT: vporq %zmm0, %zmm1, %zmm0
; AVX512VLVBMI2-NEXT: vpmovwb %zmm0, %ymm0
; AVX512VLVBMI2-NEXT: retq
@@ -1770,18 +1770,18 @@ define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX2-LABEL: splatconstant_rotate_v32i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpsllw $4, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: splatconstant_rotate_v32i8:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
@@ -1789,15 +1789,15 @@ define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_v32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsllw $4, %ymm0, %ymm1
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: vpor %ymm0, %ymm1, %ymm0
; AVX512BW-NEXT: retq
;
@@ -1805,15 +1805,15 @@ define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512VLBW-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_v32i8:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: vpsllw $4, %ymm0, %ymm1
-; AVX512VBMI2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VBMI2-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VBMI2-NEXT: vpor %ymm0, %ymm1, %ymm0
; AVX512VBMI2-NEXT: retq
;
@@ -1821,7 +1821,7 @@ define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: splatconstant_rotate_v32i8:
@@ -1856,52 +1856,52 @@ define <4 x i64> @splatconstant_rotate_mask_v4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsrlq $49, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: splatconstant_rotate_mask_v4i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlq $49, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: splatconstant_rotate_mask_v4i64:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vprolq $15, %zmm0, %zmm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: splatconstant_rotate_mask_v4i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vprolq $15, %ymm0, %ymm0
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_mask_v4i64:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512BW-NEXT: vprolq $15, %zmm0, %zmm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: retq
;
; AVX512VLBW-LABEL: splatconstant_rotate_mask_v4i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vprolq $15, %ymm0, %ymm0
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_mask_v4i64:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512VBMI2-NEXT: vprolq $15, %zmm0, %zmm0
-; AVX512VBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VBMI2-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_rotate_mask_v4i64:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vprolq $15, %ymm0, %ymm0
-; AVX512VLVBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLVBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: splatconstant_rotate_mask_v4i64:
@@ -1910,7 +1910,7 @@ define <4 x i64> @splatconstant_rotate_mask_v4i64(<4 x i64> %a) nounwind {
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; XOPAVX1-NEXT: vprotq $15, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: splatconstant_rotate_mask_v4i64:
@@ -1919,7 +1919,7 @@ define <4 x i64> @splatconstant_rotate_mask_v4i64(<4 x i64> %a) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; XOPAVX2-NEXT: vprotq $15, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%shl = shl <4 x i64> %a, <i64 15, i64 15, i64 15, i64 15>
%lshr = lshr <4 x i64> %a, <i64 49, i64 49, i64 49, i64 49>
@@ -1940,7 +1940,7 @@ define <8 x i32> @splatconstant_rotate_mask_v8i32(<8 x i32> %a) nounwind {
; AVX1-NEXT: vpslld $4, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: splatconstant_rotate_mask_v8i32:
@@ -1948,46 +1948,46 @@ define <8 x i32> @splatconstant_rotate_mask_v8i32(<8 x i32> %a) nounwind {
; AVX2-NEXT: vpsrld $28, %ymm0, %ymm1
; AVX2-NEXT: vpslld $4, %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: splatconstant_rotate_mask_v8i32:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vprold $4, %zmm0, %zmm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: splatconstant_rotate_mask_v8i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vprold $4, %ymm0, %ymm0
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_mask_v8i32:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512BW-NEXT: vprold $4, %zmm0, %zmm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: retq
;
; AVX512VLBW-LABEL: splatconstant_rotate_mask_v8i32:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vprold $4, %ymm0, %ymm0
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_mask_v8i32:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512VBMI2-NEXT: vprold $4, %zmm0, %zmm0
-; AVX512VBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VBMI2-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_rotate_mask_v8i32:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vprold $4, %ymm0, %ymm0
-; AVX512VLVBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLVBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: splatconstant_rotate_mask_v8i32:
@@ -1996,7 +1996,7 @@ define <8 x i32> @splatconstant_rotate_mask_v8i32(<8 x i32> %a) nounwind {
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; XOPAVX1-NEXT: vprotd $4, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: splatconstant_rotate_mask_v8i32:
@@ -2005,7 +2005,7 @@ define <8 x i32> @splatconstant_rotate_mask_v8i32(<8 x i32> %a) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; XOPAVX2-NEXT: vprotd $4, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%shl = shl <8 x i32> %a, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
%lshr = lshr <8 x i32> %a, <i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28>
@@ -2026,7 +2026,7 @@ define <16 x i16> @splatconstant_rotate_mask_v16i16(<16 x i16> %a) nounwind {
; AVX1-NEXT: vpsllw $5, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: splatconstant_rotate_mask_v16i16:
@@ -2034,7 +2034,7 @@ define <16 x i16> @splatconstant_rotate_mask_v16i16(<16 x i16> %a) nounwind {
; AVX2-NEXT: vpsrlw $11, %ymm0, %ymm1
; AVX2-NEXT: vpsllw $5, %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: splatconstant_rotate_mask_v16i16:
@@ -2042,14 +2042,14 @@ define <16 x i16> @splatconstant_rotate_mask_v16i16(<16 x i16> %a) nounwind {
; AVX512F-NEXT: vpsrlw $11, %ymm0, %ymm1
; AVX512F-NEXT: vpsllw $5, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: splatconstant_rotate_mask_v16i16:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $5, %ymm0, %ymm1
; AVX512VL-NEXT: vpsrlw $11, %ymm0, %ymm0
-; AVX512VL-NEXT: vpternlogq $168, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_mask_v16i16:
@@ -2057,27 +2057,27 @@ define <16 x i16> @splatconstant_rotate_mask_v16i16(<16 x i16> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $11, %ymm0, %ymm1
; AVX512BW-NEXT: vpsllw $5, %ymm0, %ymm0
; AVX512BW-NEXT: vpor %ymm1, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512BW-NEXT: retq
;
; AVX512VLBW-LABEL: splatconstant_rotate_mask_v16i16:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $5, %ymm0, %ymm1
; AVX512VLBW-NEXT: vpsrlw $11, %ymm0, %ymm0
-; AVX512VLBW-NEXT: vpternlogq $168, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VLBW-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_mask_v16i16:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512VBMI2-NEXT: vpshldw $5, %zmm0, %zmm0, %zmm0
-; AVX512VBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VBMI2-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_rotate_mask_v16i16:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpshldw $5, %ymm0, %ymm0, %ymm0
-; AVX512VLVBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VLVBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: splatconstant_rotate_mask_v16i16:
@@ -2086,7 +2086,7 @@ define <16 x i16> @splatconstant_rotate_mask_v16i16(<16 x i16> %a) nounwind {
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; XOPAVX1-NEXT: vprotw $5, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: splatconstant_rotate_mask_v16i16:
@@ -2095,7 +2095,7 @@ define <16 x i16> @splatconstant_rotate_mask_v16i16(<16 x i16> %a) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; XOPAVX2-NEXT: vprotw $5, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%shl = shl <16 x i16> %a, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
%lshr = lshr <16 x i16> %a, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
@@ -2121,43 +2121,43 @@ define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: splatconstant_rotate_mask_v32i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpsllw $4, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: splatconstant_rotate_mask_v32i8:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm1
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
-; AVX512F-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: splatconstant_rotate_mask_v32i8:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
-; AVX512VL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_mask_v32i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512BW-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512BW-NEXT: vpor %ymm0, %ymm1, %ymm0
; AVX512BW-NEXT: retq
;
@@ -2165,16 +2165,16 @@ define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512VLBW-NEXT: vpsrlw $4, %ymm0, %ymm2
-; AVX512VLBW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm0
-; AVX512VLBW-NEXT: vpternlogq $248, {{.*}}(%rip), %ymm2, %ymm0
+; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; AVX512VLBW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_mask_v32i8:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512VBMI2-NEXT: vpsrlw $4, %ymm0, %ymm0
-; AVX512VBMI2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
-; AVX512VBMI2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
+; AVX512VBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512VBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX512VBMI2-NEXT: vpor %ymm0, %ymm1, %ymm0
; AVX512VBMI2-NEXT: retq
;
@@ -2182,8 +2182,8 @@ define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %ymm0, %ymm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %ymm0, %ymm2
-; AVX512VLVBMI2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm0
-; AVX512VLVBMI2-NEXT: vpternlogq $248, {{.*}}(%rip), %ymm2, %ymm0
+; AVX512VLVBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
+; AVX512VLVBMI2-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0
; AVX512VLVBMI2-NEXT: retq
;
; XOPAVX1-LABEL: splatconstant_rotate_mask_v32i8:
@@ -2192,7 +2192,7 @@ define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind {
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; XOPAVX1-NEXT: vprotb $4, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: splatconstant_rotate_mask_v32i8:
@@ -2201,7 +2201,7 @@ define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; XOPAVX2-NEXT: vprotb $4, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%shl = shl <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
diff --git a/llvm/test/CodeGen/X86/vector-rotate-512.ll b/llvm/test/CodeGen/X86/vector-rotate-512.ll
index 8eb66d2f4e36c..0b8208930796f 100644
--- a/llvm/test/CodeGen/X86/vector-rotate-512.ll
+++ b/llvm/test/CodeGen/X86/vector-rotate-512.ll
@@ -253,12 +253,12 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm2
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm3
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsllw $5, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovb2m %zmm1, %k1
; AVX512BW-NEXT: vpblendmb %zmm3, %zmm0, %zmm3 {%k1}
; AVX512BW-NEXT: vpsllw $2, %zmm3, %zmm4
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm4, %zmm4
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm4
; AVX512BW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovb2m %zmm1, %k1
; AVX512BW-NEXT: vmovdqu8 %zmm4, %zmm3 {%k1}
@@ -270,13 +270,13 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512BW-NEXT: vpmovb2m %zmm2, %k1
; AVX512BW-NEXT: vpmovb2m %zmm1, %k2
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k2}
; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
; AVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm1
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm2, %zmm2, %zmm2
; AVX512BW-NEXT: vpmovb2m %zmm2, %k1
; AVX512BW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
@@ -288,12 +288,12 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512VLBW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX512VLBW-NEXT: vpsubb %zmm1, %zmm2, %zmm2
; AVX512VLBW-NEXT: vpsllw $4, %zmm0, %zmm3
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VLBW-NEXT: vpsllw $5, %zmm1, %zmm1
; AVX512VLBW-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLBW-NEXT: vpblendmb %zmm3, %zmm0, %zmm3 {%k1}
; AVX512VLBW-NEXT: vpsllw $2, %zmm3, %zmm4
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm4, %zmm4
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm4
; AVX512VLBW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512VLBW-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLBW-NEXT: vmovdqu8 %zmm4, %zmm3 {%k1}
@@ -305,13 +305,13 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512VLBW-NEXT: vpmovb2m %zmm2, %k1
; AVX512VLBW-NEXT: vpmovb2m %zmm1, %k2
; AVX512VLBW-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VLBW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k2}
; AVX512VLBW-NEXT: vpsrlw $2, %zmm0, %zmm1
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VLBW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
; AVX512VLBW-NEXT: vpsrlw $1, %zmm0, %zmm1
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VLBW-NEXT: vpaddb %zmm2, %zmm2, %zmm2
; AVX512VLBW-NEXT: vpmovb2m %zmm2, %k1
; AVX512VLBW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
@@ -323,12 +323,12 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512VBMI2-NEXT: vmovdqa64 {{.*#+}} zmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX512VBMI2-NEXT: vpsubb %zmm1, %zmm2, %zmm2
; AVX512VBMI2-NEXT: vpsllw $4, %zmm0, %zmm3
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VBMI2-NEXT: vpsllw $5, %zmm1, %zmm1
; AVX512VBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VBMI2-NEXT: vpblendmb %zmm3, %zmm0, %zmm3 {%k1}
; AVX512VBMI2-NEXT: vpsllw $2, %zmm3, %zmm4
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm4, %zmm4
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm4
; AVX512VBMI2-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512VBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VBMI2-NEXT: vmovdqu8 %zmm4, %zmm3 {%k1}
@@ -340,13 +340,13 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512VBMI2-NEXT: vpmovb2m %zmm2, %k1
; AVX512VBMI2-NEXT: vpmovb2m %zmm1, %k2
; AVX512VBMI2-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VBMI2-NEXT: vmovdqu8 %zmm1, %zmm0 {%k2}
; AVX512VBMI2-NEXT: vpsrlw $2, %zmm0, %zmm1
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VBMI2-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
; AVX512VBMI2-NEXT: vpsrlw $1, %zmm0, %zmm1
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VBMI2-NEXT: vpaddb %zmm2, %zmm2, %zmm2
; AVX512VBMI2-NEXT: vpmovb2m %zmm2, %k1
; AVX512VBMI2-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
@@ -358,12 +358,12 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512VLVBMI2-NEXT: vmovdqa64 {{.*#+}} zmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; AVX512VLVBMI2-NEXT: vpsubb %zmm1, %zmm2, %zmm2
; AVX512VLVBMI2-NEXT: vpsllw $4, %zmm0, %zmm3
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VLVBMI2-NEXT: vpsllw $5, %zmm1, %zmm1
; AVX512VLVBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLVBMI2-NEXT: vpblendmb %zmm3, %zmm0, %zmm3 {%k1}
; AVX512VLVBMI2-NEXT: vpsllw $2, %zmm3, %zmm4
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm4, %zmm4
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm4
; AVX512VLVBMI2-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512VLVBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLVBMI2-NEXT: vmovdqu8 %zmm4, %zmm3 {%k1}
@@ -375,13 +375,13 @@ define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512VLVBMI2-NEXT: vpmovb2m %zmm2, %k1
; AVX512VLVBMI2-NEXT: vpmovb2m %zmm1, %k2
; AVX512VLVBMI2-NEXT: vpsrlw $4, %zmm0, %zmm1
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VLVBMI2-NEXT: vmovdqu8 %zmm1, %zmm0 {%k2}
; AVX512VLVBMI2-NEXT: vpsrlw $2, %zmm0, %zmm1
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VLVBMI2-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
; AVX512VLVBMI2-NEXT: vpsrlw $1, %zmm0, %zmm1
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512VLVBMI2-NEXT: vpaddb %zmm2, %zmm2, %zmm2
; AVX512VLVBMI2-NEXT: vpmovb2m %zmm2, %k1
; AVX512VLVBMI2-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1}
@@ -637,7 +637,7 @@ define <64 x i8> @splatvar_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
define <8 x i64> @constant_rotate_v8i64(<8 x i64> %a) nounwind {
; AVX512-LABEL: constant_rotate_v8i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vprolvq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vprolvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%shl = shl <8 x i64> %a, <i64 4, i64 14, i64 50, i64 60, i64 4, i64 14, i64 50, i64 60>
%lshr = lshr <8 x i64> %a, <i64 60, i64 50, i64 14, i64 4, i64 60, i64 50, i64 14, i64 4>
@@ -648,7 +648,7 @@ define <8 x i64> @constant_rotate_v8i64(<8 x i64> %a) nounwind {
define <16 x i32> @constant_rotate_v16i32(<16 x i32> %a) nounwind {
; AVX512-LABEL: constant_rotate_v16i32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vprolvd {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%shl = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
%lshr = lshr <16 x i32> %a, <i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21>
@@ -685,26 +685,26 @@ define <32 x i16> @constant_rotate_v32i16(<32 x i16> %a) nounwind {
;
; AVX512BW-LABEL: constant_rotate_v32i16:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm1
-; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vporq %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512VLBW-LABEL: constant_rotate_v32i16:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm1
-; AVX512VLBW-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VLBW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512VLBW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VLBW-NEXT: vporq %zmm0, %zmm1, %zmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: constant_rotate_v32i16:
; AVX512VBMI2: # %bb.0:
-; AVX512VBMI2-NEXT: vpshldvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VBMI2-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VBMI2-NEXT: retq
;
; AVX512VLVBMI2-LABEL: constant_rotate_v32i16:
; AVX512VLVBMI2: # %bb.0:
-; AVX512VLVBMI2-NEXT: vpshldvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VLVBMI2-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VLVBMI2-NEXT: retq
%shl = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
%lshr = lshr <32 x i16> %a, <i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1>
@@ -817,10 +817,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; AVX512BW-NEXT: vpmovb2m %zmm1, %k1
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm2
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpblendmb %zmm2, %zmm0, %zmm2 {%k1}
; AVX512BW-NEXT: vpsllw $2, %zmm2, %zmm3
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovb2m %zmm1, %k1
; AVX512BW-NEXT: vmovdqu8 %zmm3, %zmm2 {%k1}
@@ -829,10 +829,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpaddb %zmm2, %zmm2, %zmm2 {%k1}
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm3 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: vpackuswb %zmm3, %zmm0, %zmm0
; AVX512BW-NEXT: vporq %zmm0, %zmm2, %zmm0
@@ -844,10 +844,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512VLBW-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; AVX512VLBW-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLBW-NEXT: vpsllw $4, %zmm0, %zmm2
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm2, %zmm2
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512VLBW-NEXT: vpblendmb %zmm2, %zmm0, %zmm2 {%k1}
; AVX512VLBW-NEXT: vpsllw $2, %zmm2, %zmm3
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VLBW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512VLBW-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLBW-NEXT: vmovdqu8 %zmm3, %zmm2 {%k1}
@@ -856,10 +856,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512VLBW-NEXT: vpaddb %zmm2, %zmm2, %zmm2 {%k1}
; AVX512VLBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpunpckhbw {{.*#+}} zmm3 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512VLBW-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VLBW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VLBW-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512VLBW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512VLBW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VLBW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VLBW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512VLBW-NEXT: vpackuswb %zmm3, %zmm0, %zmm0
; AVX512VLBW-NEXT: vporq %zmm0, %zmm2, %zmm0
@@ -871,10 +871,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512VBMI2-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; AVX512VBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VBMI2-NEXT: vpsllw $4, %zmm0, %zmm2
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm2, %zmm2
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512VBMI2-NEXT: vpblendmb %zmm2, %zmm0, %zmm2 {%k1}
; AVX512VBMI2-NEXT: vpsllw $2, %zmm2, %zmm3
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VBMI2-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512VBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VBMI2-NEXT: vmovdqu8 %zmm3, %zmm2 {%k1}
@@ -883,10 +883,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512VBMI2-NEXT: vpaddb %zmm2, %zmm2, %zmm2 {%k1}
; AVX512VBMI2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VBMI2-NEXT: vpunpckhbw {{.*#+}} zmm3 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512VBMI2-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VBMI2-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VBMI2-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512VBMI2-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512VBMI2-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VBMI2-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VBMI2-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512VBMI2-NEXT: vpackuswb %zmm3, %zmm0, %zmm0
; AVX512VBMI2-NEXT: vporq %zmm0, %zmm2, %zmm0
@@ -898,10 +898,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512VLVBMI2-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; AVX512VLVBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLVBMI2-NEXT: vpsllw $4, %zmm0, %zmm2
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm2, %zmm2
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512VLVBMI2-NEXT: vpblendmb %zmm2, %zmm0, %zmm2 {%k1}
; AVX512VLVBMI2-NEXT: vpsllw $2, %zmm2, %zmm3
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VLVBMI2-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; AVX512VLVBMI2-NEXT: vpmovb2m %zmm1, %k1
; AVX512VLVBMI2-NEXT: vmovdqu8 %zmm3, %zmm2 {%k1}
@@ -910,10 +910,10 @@ define <64 x i8> @constant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512VLVBMI2-NEXT: vpaddb %zmm2, %zmm2, %zmm2 {%k1}
; AVX512VLVBMI2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VLVBMI2-NEXT: vpunpckhbw {{.*#+}} zmm3 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
-; AVX512VLVBMI2-NEXT: vpsllvw {{.*}}(%rip), %zmm3, %zmm3
+; AVX512VLVBMI2-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
; AVX512VLVBMI2-NEXT: vpsrlw $8, %zmm3, %zmm3
; AVX512VLVBMI2-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
-; AVX512VLVBMI2-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VLVBMI2-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VLVBMI2-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512VLVBMI2-NEXT: vpackuswb %zmm3, %zmm0, %zmm0
; AVX512VLVBMI2-NEXT: vporq %zmm0, %zmm2, %zmm0
@@ -1014,7 +1014,7 @@ define <64 x i8> @splatconstant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; AVX512F-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512F-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: splatconstant_rotate_v64i8:
@@ -1026,35 +1026,35 @@ define <64 x i8> @splatconstant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_v64i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0
-; AVX512BW-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512BW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512VLBW-LABEL: splatconstant_rotate_v64i8:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512VLBW-NEXT: vpsrlw $4, %zmm0, %zmm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_v64i8:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512VBMI2-NEXT: vpsrlw $4, %zmm0, %zmm0
-; AVX512VBMI2-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512VBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512VBMI2-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_rotate_v64i8:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %zmm0, %zmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
; AVX512VLVBMI2-NEXT: retq
%shl = shl <64 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <64 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
@@ -1070,7 +1070,7 @@ define <8 x i64> @splatconstant_rotate_mask_v8i64(<8 x i64> %a) nounwind {
; AVX512-LABEL: splatconstant_rotate_mask_v8i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vprolq $15, %zmm0, %zmm0
-; AVX512-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%shl = shl <8 x i64> %a, <i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15>
%lshr = lshr <8 x i64> %a, <i64 49, i64 49, i64 49, i64 49, i64 49, i64 49, i64 49, i64 49>
@@ -1084,7 +1084,7 @@ define <16 x i32> @splatconstant_rotate_mask_v16i32(<16 x i32> %a) nounwind {
; AVX512-LABEL: splatconstant_rotate_mask_v16i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vprold $4, %zmm0, %zmm0
-; AVX512-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: retq
%shl = shl <16 x i32> %a, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
%lshr = lshr <16 x i32> %a, <i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28>
@@ -1104,8 +1104,8 @@ define <32 x i16> @splatconstant_rotate_mask_v32i16(<32 x i16> %a) nounwind {
; AVX512F-NEXT: vpsrlw $11, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $11, %ymm2, %ymm2
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm2
-; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512F-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512F-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: splatconstant_rotate_mask_v32i16:
@@ -1117,36 +1117,36 @@ define <32 x i16> @splatconstant_rotate_mask_v32i16(<32 x i16> %a) nounwind {
; AVX512VL-NEXT: vpsrlw $11, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $11, %ymm2, %ymm2
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm2
-; AVX512VL-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512VL-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512VL-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_mask_v32i16:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsllw $5, %zmm0, %zmm1
; AVX512BW-NEXT: vpsrlw $11, %zmm0, %zmm2
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512BW-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512BW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512VLBW-LABEL: splatconstant_rotate_mask_v32i16:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $5, %zmm0, %zmm1
; AVX512VLBW-NEXT: vpsrlw $11, %zmm0, %zmm2
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512VLBW-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512VLBW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_mask_v32i16:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: vpshldw $5, %zmm0, %zmm0, %zmm0
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VBMI2-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_rotate_mask_v32i16:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpshldw $5, %zmm0, %zmm0, %zmm0
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512VLVBMI2-NEXT: retq
%shl = shl <32 x i16> %a, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
%lshr = lshr <32 x i16> %a, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
@@ -1166,8 +1166,8 @@ define <64 x i8> @splatconstant_rotate_mask_v64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm2
-; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512F-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512F-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: splatconstant_rotate_mask_v64i8:
@@ -1179,40 +1179,40 @@ define <64 x i8> @splatconstant_rotate_mask_v64i8(<64 x i8> %a) nounwind {
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm2
-; AVX512VL-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512VL-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512VL-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_mask_v64i8:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm2
-; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512BW-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512BW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512VLBW-LABEL: splatconstant_rotate_mask_v64i8:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512VLBW-NEXT: vpsrlw $4, %zmm0, %zmm2
-; AVX512VLBW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512VLBW-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512VLBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512VLBW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_mask_v64i8:
; AVX512VBMI2: # %bb.0:
; AVX512VBMI2-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512VBMI2-NEXT: vpsrlw $4, %zmm0, %zmm2
-; AVX512VBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512VBMI2-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512VBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512VBMI2-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512VBMI2-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_rotate_mask_v64i8:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %zmm0, %zmm2
-; AVX512VLVBMI2-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $248, {{.*}}(%rip), %zmm2, %zmm0
+; AVX512VLVBMI2-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
; AVX512VLVBMI2-NEXT: retq
%shl = shl <64 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <64 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
diff --git a/llvm/test/CodeGen/X86/vector-sext.ll b/llvm/test/CodeGen/X86/vector-sext.ll
index c2769e7a9cc8f..3ae5f09a146fe 100644
--- a/llvm/test/CodeGen/X86/vector-sext.ll
+++ b/llvm/test/CodeGen/X86/vector-sext.ll
@@ -2332,10 +2332,10 @@ define <8 x i32> @load_sext_8i1_to_8i32(<8 x i1> *%ptr) {
; AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -2553,10 +2553,10 @@ define <16 x i16> @load_sext_16i1_to_16i16(<16 x i1> *%ptr) {
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpeqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
@@ -2626,7 +2626,7 @@ define <32 x i8> @load_sext_32i1_to_32i8(<32 x i1> *%ptr) nounwind readnone {
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[2,2,3,3,4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,1,4,4,5,5]
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9241421688590303745,9241421688590303745]
; AVX1-NEXT: # xmm2 = mem[0,0]
@@ -3623,7 +3623,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; SSE2-NEXT: movd %edi, %xmm0
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; SSE2-NEXT: paddw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,0,0]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
; SSE2-NEXT: psllq $58, %xmm0
@@ -3667,7 +3667,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; SSSE3-NEXT: movd %edi, %xmm0
; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; SSSE3-NEXT: paddw {{.*}}(%rip), %xmm3
+; SSSE3-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,0,0]
; SSSE3-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
; SSSE3-NEXT: psllq $58, %xmm0
@@ -3711,7 +3711,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; SSE41-NEXT: movd %edi, %xmm0
; SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; SSE41-NEXT: paddw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero
; SSE41-NEXT: psllq $58, %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm1
@@ -3750,7 +3750,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; AVX1-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpsllw $10, %xmm0, %xmm0
; AVX1-NEXT: vpsraw $10, %xmm0, %xmm1
; AVX1-NEXT: vpmovsxwq %xmm1, %xmm0
@@ -3768,7 +3768,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
-; AVX2-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsllw $10, %xmm0, %xmm0
; AVX2-NEXT: vpsraw $10, %xmm0, %xmm1
; AVX2-NEXT: vpmovsxwq %xmm1, %ymm0
@@ -3780,7 +3780,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vmovd %edi, %xmm0
; AVX512-NEXT: vpbroadcastw %xmm0, %xmm0
-; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpmovzxwq {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512-NEXT: vpsllq $58, %zmm0, %zmm0
; AVX512-NEXT: vpsraq $58, %zmm0, %zmm0
@@ -3791,7 +3791,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; X86-SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; X86-SSE2-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-SSE2-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,0,0]
; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
; X86-SSE2-NEXT: psllq $58, %xmm0
@@ -3835,7 +3835,7 @@ define <8 x i64> @sext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; X86-SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; X86-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; X86-SSE41-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
+; X86-SSE41-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero
; X86-SSE41-NEXT: psllq $58, %xmm0
; X86-SSE41-NEXT: movdqa %xmm0, %xmm1
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
index 234e1f4512829..b655f3f74f572 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
@@ -672,12 +672,12 @@ define <16 x i8> @shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31(
define <16 x i8> @shuffle_v16i8_00_01_02_zz_04_05_06_zz_08_09_10_zz_12_13_14_zz(<16 x i8> %a) {
; SSE-LABEL: shuffle_v16i8_00_01_02_zz_04_05_06_zz_08_09_10_zz_12_13_14_zz:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: shuffle_v16i8_00_01_02_zz_04_05_06_zz_08_09_10_zz_12_13_14_zz:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 4, i32 5, i32 6, i32 23, i32 8, i32 9, i32 10, i32 27, i32 12, i32 13, i32 14, i32 31>
ret <16 x i8> %shuffle
@@ -769,7 +769,7 @@ define <16 x i8> @shuffle_v16i8_02_20_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu(
; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlq $16, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq
@@ -984,7 +984,7 @@ define <16 x i8> @load_fold_pblendvb_commute(<16 x i8>* %px, <16 x i8> %y) {
define <16 x i8> @trunc_v4i32_shuffle(<16 x i8> %a) {
; SSE2-LABEL: trunc_v4i32_shuffle:
; SSE2: # %bb.0:
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll b/llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
index c81b65a408568..b8bd219a44f82 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
@@ -855,17 +855,17 @@ define <2 x double> @shuffle_v2f64_bitcast_1z(<2 x double> %a) {
define <2 x i64> @shuffle_v2i64_bitcast_z123(<2 x i64> %x) {
; SSE2-LABEL: shuffle_v2i64_bitcast_z123:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE3-LABEL: shuffle_v2i64_bitcast_z123:
; SSE3: # %bb.0:
-; SSE3-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq
;
; SSSE3-LABEL: shuffle_v2i64_bitcast_z123:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: shuffle_v2i64_bitcast_z123:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll b/llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
index 7d5e790ae4728..64ffbda2ccdd1 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
@@ -2758,12 +2758,12 @@ define <8 x i16> @shuffle_v8i16_01u3zzuz(<8 x i16> %a) {
define <8 x i16> @shuffle_v8i16_0z234567(<8 x i16> %a) {
; SSE2-LABEL: shuffle_v8i16_0z234567:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: shuffle_v8i16_0z234567:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: shuffle_v8i16_0z234567:
@@ -2784,12 +2784,12 @@ define <8 x i16> @shuffle_v8i16_0z234567(<8 x i16> %a) {
define <8 x i16> @shuffle_v8i16_0zzzz5z7(<8 x i16> %a) {
; SSE2-LABEL: shuffle_v8i16_0zzzz5z7:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: shuffle_v8i16_0zzzz5z7:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: shuffle_v8i16_0zzzz5z7:
@@ -2810,12 +2810,12 @@ define <8 x i16> @shuffle_v8i16_0zzzz5z7(<8 x i16> %a) {
define <8 x i16> @shuffle_v8i16_0123456z(<8 x i16> %a) {
; SSE2-LABEL: shuffle_v8i16_0123456z:
; SSE2: # %bb.0:
-; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: shuffle_v8i16_0123456z:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: shuffle_v8i16_0123456z:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
index 8e1abdb822a19..2b364713f8df8 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
@@ -160,7 +160,7 @@ define <16 x float> @shuffle_v16f32_03_uu_uu_uu_uu_04_uu_uu_uu_uu_11_uu_uu_uu_uu
define <16 x float> @shuffle_v16f32_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31(<16 x float> %a) {
; ALL-LABEL: shuffle_v16f32_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
; ALL: # %bb.0:
-; ALL-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
+; ALL-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; ALL-NEXT: retq
%tmp1 = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 undef, i32 17, i32 undef, i32 19, i32 undef, i32 5, i32 undef, i32 7, i32 undef, i32 9, i32 undef, i32 11, i32 undef, i32 13, i32 undef, i32 15>
%tmp2 = shufflevector <16 x float> %tmp1, <16 x float> <float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef>, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll b/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
index 1e1224ee5eab1..dbc410c84b846 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
@@ -340,12 +340,12 @@ define <32 x i16> @test_mm512_mask_blend_epi16(<32 x i16> %A, <32 x i16> %W){
;
; KNL64-LABEL: test_mm512_mask_blend_epi16:
; KNL64: # %bb.0: # %entry
-; KNL64-NEXT: vpternlogd $216, {{.*}}(%rip){1to16}, %zmm1, %zmm0
+; KNL64-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
; KNL64-NEXT: retq
;
; KNL32-LABEL: test_mm512_mask_blend_epi16:
; KNL32: # %bb.0: # %entry
-; KNL32-NEXT: vpternlogd $216, {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm1, %zmm0
+; KNL32-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm1, %zmm0
; KNL32-NEXT: retl
entry:
%0 = shufflevector <32 x i16> %A, <32 x i16> %W, <32 x i32> <i32 32, i32 1, i32 34, i32 3, i32 36, i32 5, i32 38, i32 7, i32 40, i32 9, i32 42, i32 11, i32 44, i32 13, i32 46, i32 15, i32 48, i32 17, i32 50, i32 19, i32 52, i32 21, i32 54, i32 23, i32 56, i32 25, i32 58, i32 27, i32 60, i32 29, i32 62, i32 31>
@@ -617,14 +617,14 @@ define <32 x float> @PR47534(<8 x float> %tmp) {
define void @PR43170(<16 x float>* %a0) {
; SKX64-LABEL: PR43170:
; SKX64: # %bb.0: # %entry
-; SKX64-NEXT: vmovaps {{.*}}(%rip), %ymm0
+; SKX64-NEXT: vmovaps src1(%rip), %ymm0
; SKX64-NEXT: vmovaps %zmm0, (%rdi)
; SKX64-NEXT: vzeroupper
; SKX64-NEXT: retq
;
; KNL64-LABEL: PR43170:
; KNL64: # %bb.0: # %entry
-; KNL64-NEXT: vmovaps {{.*}}(%rip), %ymm0
+; KNL64-NEXT: vmovaps src1(%rip), %ymm0
; KNL64-NEXT: vmovaps %zmm0, (%rdi)
; KNL64-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
index 32303f867e4bf..83fb56c674155 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
@@ -77,13 +77,13 @@ define <4 x i64> @combine_permq_pshufb_as_vextracti128(<4 x i64> %a0) {
; X86-LABEL: combine_permq_pshufb_as_vextracti128:
; X86: # %bb.0:
; X86-NEXT: vextracti128 $1, %ymm0, %xmm0
-; X86-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: combine_permq_pshufb_as_vextracti128:
; X64: # %bb.0:
; X64-NEXT: vextracti128 $1, %ymm0, %xmm0
-; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%2 = bitcast <4 x i64> %1 to <32 x i8>
@@ -97,13 +97,13 @@ define <4 x i64> @combine_permq_pshufb_as_vmovdqa(<4 x i64> %a0) {
; X86-LABEL: combine_permq_pshufb_as_vmovdqa:
; X86: # %bb.0:
; X86-NEXT: vmovdqa %xmm0, %xmm0
-; X86-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: combine_permq_pshufb_as_vmovdqa:
; X64: # %bb.0:
; X64-NEXT: vmovdqa %xmm0, %xmm0
-; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
%2 = bitcast <4 x i64> %1 to <32 x i8>
@@ -210,13 +210,13 @@ define <16 x i8> @combine_pshufb_as_vpbroadcastd128(<16 x i8> %a) {
; X86-LABEL: combine_pshufb_as_vpbroadcastd128:
; X86: # %bb.0:
; X86-NEXT: vpbroadcastd %xmm0, %xmm0
-; X86-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: combine_pshufb_as_vpbroadcastd128:
; X64: # %bb.0:
; X64-NEXT: vpbroadcastd %xmm0, %xmm0
-; X64-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>)
%2 = add <16 x i8> %1, <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>
@@ -227,13 +227,13 @@ define <8 x i32> @combine_permd_as_vpbroadcastd256(<4 x i32> %a) {
; X86-LABEL: combine_permd_as_vpbroadcastd256:
; X86: # %bb.0:
; X86-NEXT: vpbroadcastd %xmm0, %ymm0
-; X86-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: combine_permd_as_vpbroadcastd256:
; X64: # %bb.0:
; X64-NEXT: vpbroadcastd %xmm0, %ymm0
-; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %1, <8 x i32> zeroinitializer)
@@ -254,13 +254,13 @@ define <8 x i32> @combine_permd_as_vpbroadcastq256(<4 x i32> %a) {
; X86-LABEL: combine_permd_as_vpbroadcastq256:
; X86: # %bb.0:
; X86-NEXT: vpbroadcastq %xmm0, %ymm0
-; X86-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: combine_permd_as_vpbroadcastq256:
; X64: # %bb.0:
; X64-NEXT: vpbroadcastq %xmm0, %ymm0
-; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %1, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>)
@@ -543,12 +543,12 @@ define <32 x i8> @combine_pshufb_as_unpackhi_zero(<32 x i8> %a0) {
define <32 x i8> @combine_psrlw_pshufb(<16 x i16> %a0) {
; X86-LABEL: combine_psrlw_pshufb:
; X86: # %bb.0:
-; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: combine_psrlw_pshufb:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = lshr <16 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%2 = bitcast <16 x i16> %1 to <32 x i8>
@@ -559,12 +559,12 @@ define <32 x i8> @combine_psrlw_pshufb(<16 x i16> %a0) {
define <32 x i8> @combine_pslld_pshufb(<8 x i32> %a0) {
; X86-LABEL: combine_pslld_pshufb:
; X86: # %bb.0:
-; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: combine_pslld_pshufb:
; X64: # %bb.0:
-; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%1 = shl <8 x i32> %a0, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
%2 = bitcast <8 x i32> %1 to <32 x i8>
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
index 9d61fd2e8ecd5..c9928d198a2c2 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
@@ -901,8 +901,8 @@ define <8 x double> @combine_vpermi2var_8f64_as_permpd(<8 x double> %x0, <8 x do
; X86: # %bb.0:
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0]
-; X86-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
-; X86-NEXT: vinsertf64x4 $1, {{\.LCPI[0-9]+_[0-9]+}}, %zmm2, %zmm2
+; X86-NEXT: vinsertf128 $1, {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
+; X86-NEXT: vinsertf64x4 $1, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm2, %zmm2
; X86-NEXT: vpermi2pd %zmm1, %zmm0, %zmm2
; X86-NEXT: vpermpd {{.*#+}} zmm0 = zmm2[2,3,1,1,6,7,5,5]
; X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
index 7ddd485459239..37f93f6f1d96d 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
@@ -244,7 +244,7 @@ define <16 x i8> @combine_pshufb_psrldq(<16 x i8> %a0) {
define <16 x i8> @combine_and_pshufb(<16 x i8> %a0) {
; SSSE3-LABEL: combine_and_pshufb:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: combine_and_pshufb:
@@ -266,7 +266,7 @@ define <16 x i8> @combine_and_pshufb(<16 x i8> %a0) {
define <16 x i8> @combine_pshufb_and(<16 x i8> %a0) {
; SSSE3-LABEL: combine_pshufb_and:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: combine_pshufb_and:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
index b453517c2885d..0aff325a58960 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
@@ -135,7 +135,7 @@ define <4 x double> @demandedelts_vpermil2pd256_as_shufpd(<4 x double> %a0, <4 x
; X86: # %bb.0:
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0]
-; X86-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
+; X86-NEXT: vinsertf128 $1, {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0
; X86-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3]
; X86-NEXT: retl
@@ -174,12 +174,12 @@ define <16 x i8> @combine_vpperm_zero(<16 x i8> %a0, <16 x i8> %a1) {
define <16 x i8> @combine_vpperm_identity_bitcast(<16 x i8> %a0, <16 x i8> %a1) {
; X86-LABEL: combine_vpperm_identity_bitcast:
; X86: # %bb.0:
-; X86-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: combine_vpperm_identity_bitcast:
; X64: # %bb.0:
-; X64-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
%mask = bitcast <2 x i64> <i64 1084818905618843912, i64 506097522914230528> to <16 x i8>
%res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %mask)
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll b/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll
index 1fe283963a027..0adb06f37f139 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll
@@ -35,7 +35,7 @@ define void @test1() {
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %edi, -8
; X32-NEXT: pxor %mm0, %mm0
-; X32-NEXT: movq LCPI1_0, %mm1 ## mm1 = 0x7070606040400000
+; X32-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}, %mm1 ## mm1 = 0x7070606040400000
; X32-NEXT: xorl %edi, %edi
; X32-NEXT: maskmovq %mm1, %mm0
; X32-NEXT: popl %edi
@@ -44,7 +44,7 @@ define void @test1() {
; X64-LABEL: test1:
; X64: ## %bb.0: ## %entry
; X64-NEXT: pxor %mm0, %mm0
-; X64-NEXT: movq {{.*}}(%rip), %mm1 ## mm1 = 0x7070606040400000
+; X64-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %mm1 ## mm1 = 0x7070606040400000
; X64-NEXT: xorl %edi, %edi
; X64-NEXT: maskmovq %mm1, %mm0
; X64-NEXT: retq
@@ -73,7 +73,7 @@ define void @test2() nounwind {
;
; X64-LABEL: test2:
; X64: ## %bb.0: ## %entry
-; X64-NEXT: movq _tmp_V2i@{{.*}}(%rip), %rax
+; X64-NEXT: movq _tmp_V2i at GOTPCREL(%rip), %rax
; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X64-NEXT: movq %xmm0, (%rax)
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll b/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
index d62462c4e59ac..b8db14c026bf8 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
@@ -364,7 +364,7 @@ define <16 x i8> @shuffle_8_18_uuuuuuuuuuuuuu(<16 x i8> %a, <16 x i8> %b) {
; AMD10H: # %bb.0:
; AMD10H-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; AMD10H-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AMD10H-NEXT: andps {{.*}}(%rip), %xmm0
+; AMD10H-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AMD10H-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[2,1,2,3,4,5,6,7]
; AMD10H-NEXT: packuswb %xmm0, %xmm0
; AMD10H-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
index 0d37bc673a349..04065cd8d6a57 100644
--- a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
@@ -23,7 +23,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -34,7 +34,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
@@ -47,7 +47,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -58,7 +58,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
@@ -226,7 +226,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -237,7 +237,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
@@ -250,7 +250,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -261,7 +261,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm0, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
@@ -429,7 +429,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -440,7 +440,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -458,7 +458,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -469,7 +469,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -672,7 +672,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -683,7 +683,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -701,7 +701,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -712,7 +712,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
@@ -915,7 +915,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -926,7 +926,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
@@ -940,7 +940,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -951,7 +951,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
@@ -1091,7 +1091,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1102,7 +1102,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm0
@@ -1116,7 +1116,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1127,7 +1127,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm0
@@ -1267,7 +1267,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1278,7 +1278,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -1289,7 +1289,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1300,7 +1300,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
@@ -1424,7 +1424,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
@@ -1435,7 +1435,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -1446,7 +1446,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
@@ -1457,7 +1457,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1
-; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
+; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-unsigned-cmp.ll b/llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
index d6849a94ddb91..14b0eef5e70cd 100644
--- a/llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
@@ -481,7 +481,7 @@ define <8 x i16> @PR47448_uge(i16 signext %0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpmaxuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -490,7 +490,7 @@ define <8 x i16> @PR47448_uge(i16 signext %0) {
; AVX2-NEXT: andl $7, %edi
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
-; AVX2-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpmaxuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
%2 = and i16 %0, 7
@@ -508,7 +508,7 @@ define <8 x i16> @PR47448_ugt(i16 signext %0) {
; SSE-NEXT: movd %edi, %xmm0
; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; SSE-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
+; SSE-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: PR47448_ugt:
@@ -517,7 +517,7 @@ define <8 x i16> @PR47448_ugt(i16 signext %0) {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; AVX1-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: PR47448_ugt:
@@ -525,7 +525,7 @@ define <8 x i16> @PR47448_ugt(i16 signext %0) {
; AVX2-NEXT: andl $7, %edi
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
-; AVX2-NEXT: vpcmpgtw {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
%2 = and i16 %0, 7
%3 = insertelement <8 x i16> undef, i16 %2, i32 0
diff --git a/llvm/test/CodeGen/X86/vector-zext.ll b/llvm/test/CodeGen/X86/vector-zext.ll
index 5aeb641e700ef..981be2f0df770 100644
--- a/llvm/test/CodeGen/X86/vector-zext.ll
+++ b/llvm/test/CodeGen/X86/vector-zext.ll
@@ -2341,7 +2341,7 @@ define <4 x i32> @zext_4i17_to_4i32(<4 x i17>* %ptr) {
; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: zext_4i17_to_4i32:
@@ -2362,7 +2362,7 @@ define <4 x i32> @zext_4i17_to_4i32(<4 x i17>* %ptr) {
; SSSE3-NEXT: movd %eax, %xmm2
; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSSE3-NEXT: pand {{.*}}(%rip), %xmm0
+; SSSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: zext_4i17_to_4i32:
@@ -2380,7 +2380,7 @@ define <4 x i32> @zext_4i17_to_4i32(<4 x i17>* %ptr) {
; SSE41-NEXT: shrq $34, %rcx
; SSE41-NEXT: pinsrd $2, %ecx, %xmm0
; SSE41-NEXT: pinsrd $3, %edx, %xmm0
-; SSE41-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: zext_4i17_to_4i32:
@@ -2398,7 +2398,7 @@ define <4 x i32> @zext_4i17_to_4i32(<4 x i17>* %ptr) {
; AVX1-NEXT: shrq $34, %rcx
; AVX1-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; AVX1-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: zext_4i17_to_4i32:
@@ -2449,7 +2449,7 @@ define <8 x i64> @zext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; SSE2-NEXT: movd %edi, %xmm0
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; SSE2-NEXT: paddw {{.*}}(%rip), %xmm3
+; SSE2-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,0,0]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [63,63]
@@ -2470,7 +2470,7 @@ define <8 x i64> @zext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; SSSE3-NEXT: movd %edi, %xmm0
; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; SSSE3-NEXT: paddw {{.*}}(%rip), %xmm3
+; SSSE3-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,0,0]
; SSSE3-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [63,63]
@@ -2491,7 +2491,7 @@ define <8 x i64> @zext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; SSE41-NEXT: movd %edi, %xmm0
; SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
-; SSE41-NEXT: paddw {{.*}}(%rip), %xmm3
+; SSE41-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero
; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [63,63]
; SSE41-NEXT: pand %xmm4, %xmm0
@@ -2511,8 +2511,8 @@ define <8 x i64> @zext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; AVX1-NEXT: vmovd %edi, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; AVX1-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
+; AVX1-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
@@ -2528,8 +2528,8 @@ define <8 x i64> @zext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
-; AVX2-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; AVX2-NEXT: vpmovzxwq {{.*#+}} ymm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
@@ -2539,9 +2539,9 @@ define <8 x i64> @zext_8i6_to_8i64(i32 %x) nounwind uwtable readnone ssp {
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vmovd %edi, %xmm0
; AVX512-NEXT: vpbroadcastw %xmm0, %xmm0
-; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpmovzxwq {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; AVX512-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm0, %zmm0
+; AVX512-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512-NEXT: retq
entry:
%a = trunc i32 %x to i6
@@ -2605,7 +2605,7 @@ define <8 x i32> @splatshuf_zext_v8i32_matching_undefs(<8 x i16> %x) {
; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,7,7]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vmovq.ll b/llvm/test/CodeGen/X86/vmovq.ll
index 3b9a8e2725c9c..a7ad7f3facf19 100644
--- a/llvm/test/CodeGen/X86/vmovq.ll
+++ b/llvm/test/CodeGen/X86/vmovq.ll
@@ -5,14 +5,14 @@
define <2 x i64> @PR25554(<2 x i64> %v0, <2 x i64> %v1) {
; SSE-LABEL: PR25554:
; SSE: # %bb.0:
-; SSE-NEXT: por {{.*}}(%rip), %xmm0
-; SSE-NEXT: paddq {{.*}}(%rip), %xmm0
+; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: PR25554:
; AVX: # %bb.0:
-; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%c1 = or <2 x i64> %v0, <i64 1, i64 0>
diff --git a/llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll b/llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
index 2e348ea17ff22..8ad85406b9d6a 100644
--- a/llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
+++ b/llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
@@ -33,7 +33,7 @@ define void @test(<16 x i32> %a0, <16 x i32> %b0, <16 x i32> %a1, <16 x i32> %b1
; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
; X86-NEXT: kmovw %k1, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
; X86-NEXT: vzeroupper
-; X86-NEXT: calll dummy
+; X86-NEXT: calll dummy at PLT
; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 2-byte Reload
; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k1 # 2-byte Reload
; X86-NEXT: kmovw %k0, %eax
@@ -88,7 +88,7 @@ define void @test(<16 x i32> %a0, <16 x i32> %b0, <16 x i32> %a1, <16 x i32> %b1
; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
; X64-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
; X64-NEXT: vzeroupper
-; X64-NEXT: callq dummy
+; X64-NEXT: callq dummy at PLT
; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 2-byte Reload
; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
; X64-NEXT: kmovw %k0, %eax
diff --git a/llvm/test/CodeGen/X86/vselect-avx.ll b/llvm/test/CodeGen/X86/vselect-avx.ll
index 24849c2b850cd..795a529650674 100644
--- a/llvm/test/CodeGen/X86/vselect-avx.ll
+++ b/llvm/test/CodeGen/X86/vselect-avx.ll
@@ -47,7 +47,7 @@ define void @test2(double** %call1559, i64 %indvars.iv4198, <4 x i1> %tmp1895) {
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: movq (%rdi,%rsi,8), %rax
; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [5.0E-1,5.0E-1,5.0E-1,5.0E-1]
-; AVX1-NEXT: vblendvpd %ymm0, {{.*}}(%rip), %ymm1, %ymm0
+; AVX1-NEXT: vblendvpd %ymm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
; AVX1-NEXT: vmovupd %ymm0, (%rax)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -84,9 +84,9 @@ bb:
define void @test3(<4 x i32> %induction30, <4 x i16>* %tmp16, <4 x i16>* %tmp17, <4 x i16> %tmp3, <4 x i16> %tmp12) {
; AVX1-LABEL: test3:
; AVX1: ## %bb.0:
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm3
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm1
@@ -148,10 +148,10 @@ define <32 x i8> @PR22706(<32 x i1> %x) {
; AVX2-LABEL: PR22706:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
%tmp = select <32 x i1> %x, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <32 x i8> %tmp
diff --git a/llvm/test/CodeGen/X86/vselect-constants.ll b/llvm/test/CodeGen/X86/vselect-constants.ll
index 169aa05513730..e0f0ce6115d88 100644
--- a/llvm/test/CodeGen/X86/vselect-constants.ll
+++ b/llvm/test/CodeGen/X86/vselect-constants.ll
@@ -19,8 +19,8 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
; SSE-NEXT: pslld $31, %xmm0
; SSE-NEXT: psrad $31, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm1
-; SSE-NEXT: pandn {{.*}}(%rip), %xmm1
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -28,7 +28,7 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
; AVX: # %bb.0:
; AVX-NEXT: vpslld $31, %xmm0, %xmm0
; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [42,0,4294967294,4294967295]
-; AVX-NEXT: vblendvps %xmm0, {{.*}}(%rip), %xmm1, %xmm0
+; AVX-NEXT: vblendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX-NEXT: retq
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add
@@ -39,8 +39,8 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm1
-; SSE-NEXT: pandn {{.*}}(%rip), %xmm1
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -48,7 +48,7 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [42,0,4294967294,4294967295]
-; AVX-NEXT: vblendvps %xmm0, {{.*}}(%rip), %xmm1, %xmm0
+; AVX-NEXT: vblendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX-NEXT: retq
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
@@ -58,14 +58,14 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
; SSE-LABEL: sel_Cplus1_or_C_vec:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sel_Cplus1_or_C_vec:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add
@@ -96,14 +96,14 @@ define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
; SSE: # %bb.0:
; SSE-NEXT: pslld $31, %xmm0
; SSE-NEXT: psrad $31, %xmm0
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sel_Cminus1_or_C_vec:
; AVX: # %bb.0:
; AVX-NEXT: vpslld $31, %xmm0, %xmm0
; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
ret <4 x i32> %add
@@ -113,13 +113,13 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: cmp_sel_Cminus1_or_C_vec:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm1, %xmm0
-; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: cmp_sel_Cminus1_or_C_vec:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
@@ -160,14 +160,14 @@ define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
; SSE-LABEL: sel_0_or_minus1_vec:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sel_0_or_minus1_vec:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
@@ -197,12 +197,12 @@ define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
; SSE-LABEL: sel_1_or_0_vec:
; SSE: # %bb.0:
-; SSE-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sel_1_or_0_vec:
; AVX: # %bb.0:
-; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
ret <4 x i32> %add
@@ -228,12 +228,12 @@ define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
; SSE-LABEL: sel_0_or_1_vec:
; SSE: # %bb.0:
-; SSE-NEXT: andnps {{.*}}(%rip), %xmm0
+; SSE-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sel_0_or_1_vec:
; AVX: # %bb.0:
-; AVX-NEXT: vandnps {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vandnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %add
@@ -243,13 +243,13 @@ define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: cmp_sel_0_or_1_vec:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm1, %xmm0
-; SSE-NEXT: pandn {{.*}}(%rip), %xmm0
+; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: cmp_sel_0_or_1_vec:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpandn {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -276,7 +276,7 @@ define <2 x i37> @ossfuzz21167(<2 x i37> %x, <2 x i37> %y) {
; SSE-NEXT: pand %xmm2, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: ossfuzz21167:
diff --git a/llvm/test/CodeGen/X86/vselect-pcmp.ll b/llvm/test/CodeGen/X86/vselect-pcmp.ll
index 146fecfa7843b..75434e45558c5 100644
--- a/llvm/test/CodeGen/X86/vselect-pcmp.ll
+++ b/llvm/test/CodeGen/X86/vselect-pcmp.ll
@@ -495,14 +495,14 @@ define <4 x i64> @blend_splat1_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x
; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512F-NEXT: vptestnmq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpblendmq %zmm1, %zmm2, %zmm0 {%k1}
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: blend_splat1_mask_cond_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VL-NEXT: vpblendmq %ymm1, %ymm2, %ymm0 {%k1}
; AVX512VL-NEXT: retq
;
@@ -535,7 +535,7 @@ define <4 x i32> @blend_splat1_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x
; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512F-NEXT: vptestnmd {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512F-NEXT: vzeroupper
@@ -543,13 +543,13 @@ define <4 x i32> @blend_splat1_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x
;
; AVX512VL-LABEL: blend_splat1_mask_cond_v4i32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmd {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VL-NEXT: vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
; AVX512VL-NEXT: retq
;
; XOP-LABEL: blend_splat1_mask_cond_v4i32:
; XOP: # %bb.0:
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
; XOP-NEXT: vpcomneqd %xmm3, %xmm0, %xmm0
; XOP-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
@@ -583,7 +583,7 @@ define <16 x i16> @blend_splat1_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <
;
; AVX512-LABEL: blend_splat1_mask_cond_v16i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
; AVX512-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
@@ -614,7 +614,7 @@ define <16 x i8> @blend_splat1_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x
;
; AVX512-LABEL: blend_splat1_mask_cond_v16i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
; AVX512-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
@@ -622,7 +622,7 @@ define <16 x i8> @blend_splat1_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x
;
; XOP-LABEL: blend_splat1_mask_cond_v16i8:
; XOP: # %bb.0:
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
; XOP-NEXT: vpcomneqb %xmm3, %xmm0, %xmm0
; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
@@ -653,13 +653,13 @@ define <2 x i64> @blend_splatmax_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2
;
; AVX512VL-LABEL: blend_splatmax_mask_cond_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmq {{.*}}(%rip), %xmm0, %k1
+; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VL-NEXT: vpblendmq %xmm1, %xmm2, %xmm0 {%k1}
; AVX512VL-NEXT: retq
;
; XOP-LABEL: blend_splatmax_mask_cond_v2i64:
; XOP: # %bb.0:
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
; XOP-NEXT: vpcomneqq %xmm3, %xmm0, %xmm0
; XOP-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
@@ -681,14 +681,14 @@ define <8 x i32> @blend_splatmax_mask_cond_v8i32(<8 x i32> %x, <8 x i32> %y, <8
; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512F-NEXT: vptestnmd {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: blend_splatmax_mask_cond_v8i32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmd {{.*}}(%rip){1to8}, %ymm0, %k1
+; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
; AVX512VL-NEXT: vpblendmd %ymm1, %ymm2, %ymm0 {%k1}
; AVX512VL-NEXT: retq
;
@@ -711,7 +711,7 @@ define <8 x i16> @blend_splatmax_mask_cond_v8i16(<8 x i16> %x, <8 x i16> %y, <8
;
; AVX512-LABEL: blend_splatmax_mask_cond_v8i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
; AVX512-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
@@ -719,7 +719,7 @@ define <8 x i16> @blend_splatmax_mask_cond_v8i16(<8 x i16> %x, <8 x i16> %y, <8
;
; XOP-LABEL: blend_splatmax_mask_cond_v8i16:
; XOP: # %bb.0:
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
; XOP-NEXT: vpcomneqw %xmm3, %xmm0, %xmm0
; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
@@ -750,7 +750,7 @@ define <32 x i8> @blend_splatmax_mask_cond_v32i8(<32 x i8> %x, <32 x i8> %y, <32
;
; AVX512-LABEL: blend_splatmax_mask_cond_v32i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
; AVX512-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
@@ -792,14 +792,14 @@ define <4 x i64> @blend_splat_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i
; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512F-NEXT: vptestnmq {{.*}}(%rip){1to8}, %zmm0, %k1
+; AVX512F-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
; AVX512F-NEXT: vpblendmq %zmm1, %zmm2, %zmm0 {%k1}
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: blend_splat_mask_cond_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmq {{.*}}(%rip){1to4}, %ymm0, %k1
+; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
; AVX512VL-NEXT: vpblendmq %ymm1, %ymm2, %ymm0 {%k1}
; AVX512VL-NEXT: retq
;
@@ -832,7 +832,7 @@ define <4 x i32> @blend_splat_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i
; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512F-NEXT: vptestnmd {{.*}}(%rip){1to16}, %zmm0, %k1
+; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512F-NEXT: vzeroupper
@@ -840,13 +840,13 @@ define <4 x i32> @blend_splat_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i
;
; AVX512VL-LABEL: blend_splat_mask_cond_v4i32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmd {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
; AVX512VL-NEXT: vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
; AVX512VL-NEXT: retq
;
; XOP-LABEL: blend_splat_mask_cond_v4i32:
; XOP: # %bb.0:
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
; XOP-NEXT: vpcomneqd %xmm3, %xmm0, %xmm0
; XOP-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
@@ -880,7 +880,7 @@ define <16 x i16> @blend_splat_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <1
;
; AVX512-LABEL: blend_splat_mask_cond_v16i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
; AVX512-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
@@ -911,7 +911,7 @@ define <16 x i8> @blend_splat_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x
;
; AVX512-LABEL: blend_splat_mask_cond_v16i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
; AVX512-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
@@ -919,7 +919,7 @@ define <16 x i8> @blend_splat_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x
;
; XOP-LABEL: blend_splat_mask_cond_v16i8:
; XOP: # %bb.0:
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
; XOP-NEXT: vpcomneqb %xmm3, %xmm0, %xmm0
; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
@@ -933,7 +933,7 @@ define <16 x i8> @blend_splat_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x
define <2 x i64> @blend_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
; AVX1-LABEL: blend_mask_cond_v2i64:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpcmpeqq %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
@@ -941,7 +941,7 @@ define <2 x i64> @blend_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z
;
; AVX2-LABEL: blend_mask_cond_v2i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
; AVX2-NEXT: retq
;
@@ -959,13 +959,13 @@ define <2 x i64> @blend_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z
;
; AVX512VL-LABEL: blend_mask_cond_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmq {{.*}}(%rip), %xmm0, %k1
+; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VL-NEXT: vpblendmq %xmm1, %xmm2, %xmm0 {%k1}
; AVX512VL-NEXT: retq
;
; XOP-LABEL: blend_mask_cond_v2i64:
; XOP: # %bb.0:
-; XOP-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
; XOP-NEXT: retq
%a = and <2 x i64> %x, <i64 1, i64 4>
@@ -977,13 +977,13 @@ define <2 x i64> @blend_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z
define <4 x i32> @blend_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
; AVX1-LABEL: blend_mask_cond_v4i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: blend_mask_cond_v4i32:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX2-NEXT: retq
;
@@ -1001,13 +1001,13 @@ define <4 x i32> @blend_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z
;
; AVX512VL-LABEL: blend_mask_cond_v4i32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmd {{.*}}(%rip), %xmm0, %k1
+; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VL-NEXT: vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
; AVX512VL-NEXT: retq
;
; XOP-LABEL: blend_mask_cond_v4i32:
; XOP: # %bb.0:
-; XOP-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; XOP-NEXT: retq
%a = and <4 x i32> %x, <i32 65536, i32 512, i32 2, i32 1>
@@ -1019,7 +1019,7 @@ define <4 x i32> @blend_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z
define <8 x i16> @blend_mask_cond_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %z) {
; AVX-LABEL: blend_mask_cond_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
@@ -1028,7 +1028,7 @@ define <8 x i16> @blend_mask_cond_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %z
; XOP-LABEL: blend_mask_cond_v8i16:
; XOP: # %bb.0:
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpcomltw %xmm3, %xmm0, %xmm0
; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
; XOP-NEXT: retq
@@ -1041,7 +1041,7 @@ define <8 x i16> @blend_mask_cond_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %z
define <16 x i8> @blend_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %z) {
; AVX-LABEL: blend_mask_cond_v16i8:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
@@ -1049,7 +1049,7 @@ define <16 x i8> @blend_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %z
;
; XOP-LABEL: blend_mask_cond_v16i8:
; XOP: # %bb.0:
-; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
; XOP-NEXT: retq
%a = and <16 x i8> %x, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 128, i8 4, i8 4, i8 4, i8 4, i8 2, i8 2, i8 2, i8 2>
@@ -1061,7 +1061,7 @@ define <16 x i8> @blend_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %z
define <4 x i64> @blend_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %z) {
; AVX1-LABEL: blend_mask_cond_v4i64:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX1-NEXT: vpcmpeqq %xmm4, %xmm3, %xmm3
@@ -1072,7 +1072,7 @@ define <4 x i64> @blend_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %z
;
; AVX2-LABEL: blend_mask_cond_v4i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
; AVX2-NEXT: retq
;
@@ -1089,15 +1089,15 @@ define <4 x i64> @blend_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %z
;
; AVX512VL-LABEL: blend_mask_cond_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmq {{.*}}(%rip), %ymm0, %k1
+; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k1
; AVX512VL-NEXT: vpblendmq %ymm1, %ymm2, %ymm0 {%k1}
; AVX512VL-NEXT: retq
;
; XOP-LABEL: blend_mask_cond_v4i64:
; XOP: # %bb.0:
-; XOP-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm3
+; XOP-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; XOP-NEXT: vextractf128 $1, %ymm0, %xmm0
-; XOP-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
; XOP-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
; XOP-NEXT: retq
@@ -1110,16 +1110,16 @@ define <4 x i64> @blend_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %z
define <8 x i32> @blend_mask_cond_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
; AVX1-LABEL: blend_mask_cond_v8i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm3
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
; AVX1-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: blend_mask_cond_v8i32:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
; AVX2-NEXT: retq
;
@@ -1136,15 +1136,15 @@ define <8 x i32> @blend_mask_cond_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z
;
; AVX512VL-LABEL: blend_mask_cond_v8i32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmd {{.*}}(%rip), %ymm0, %k1
+; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k1
; AVX512VL-NEXT: vpblendmd %ymm1, %ymm2, %ymm0 {%k1}
; AVX512VL-NEXT: retq
;
; XOP-LABEL: blend_mask_cond_v8i32:
; XOP: # %bb.0:
-; XOP-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm3
+; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; XOP-NEXT: vextractf128 $1, %ymm0, %xmm0
-; XOP-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
; XOP-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
; XOP-NEXT: retq
@@ -1157,7 +1157,7 @@ define <8 x i32> @blend_mask_cond_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z
define <16 x i16> @blend_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) {
; AVX1-LABEL: blend_mask_cond_v16i16:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX1-NEXT: vpcmpeqw %xmm4, %xmm3, %xmm3
@@ -1170,7 +1170,7 @@ define <16 x i16> @blend_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i1
;
; AVX2-LABEL: blend_mask_cond_v16i16:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
@@ -1178,7 +1178,7 @@ define <16 x i16> @blend_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i1
;
; AVX512-LABEL: blend_mask_cond_v16i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
; AVX512-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
@@ -1187,10 +1187,10 @@ define <16 x i16> @blend_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i1
; XOP-LABEL: blend_mask_cond_v16i16:
; XOP: # %bb.0:
; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm3, %xmm3
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
; XOP-NEXT: vpcomltw %xmm4, %xmm3, %xmm3
-; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpcomltw %xmm4, %xmm0, %xmm0
; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; XOP-NEXT: vpcmov %ymm0, %ymm1, %ymm2, %ymm0
@@ -1204,7 +1204,7 @@ define <16 x i16> @blend_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i1
define <32 x i8> @blend_mask_cond_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %z) {
; AVX1-LABEL: blend_mask_cond_v32i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX1-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm3
@@ -1217,7 +1217,7 @@ define <32 x i8> @blend_mask_cond_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %z
;
; AVX2-LABEL: blend_mask_cond_v32i8:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
@@ -1225,7 +1225,7 @@ define <32 x i8> @blend_mask_cond_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %z
;
; AVX512-LABEL: blend_mask_cond_v32i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
; AVX512-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
@@ -1234,10 +1234,10 @@ define <32 x i8> @blend_mask_cond_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %z
; XOP-LABEL: blend_mask_cond_v32i8:
; XOP: # %bb.0:
; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
-; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm3, %xmm3
+; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
; XOP-NEXT: vpcomltb %xmm4, %xmm3, %xmm3
-; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpcomltb %xmm4, %xmm0, %xmm0
; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; XOP-NEXT: vpcmov %ymm0, %ymm1, %ymm2, %ymm0
@@ -1265,7 +1265,7 @@ define void @PR46531(i32* %x, i32* %y, i32* %z) {
; AVX512F-NEXT: vmovdqu (%rsi), %xmm0
; AVX512F-NEXT: vmovdqu (%rdx), %xmm1
; AVX512F-NEXT: vpor %xmm0, %xmm1, %xmm2
-; AVX512F-NEXT: vptestnmd {{.*}}(%rip){1to16}, %zmm1, %k1
+; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %k1
; AVX512F-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX512F-NEXT: vmovdqa32 %zmm2, %zmm0 {%k1}
; AVX512F-NEXT: vmovdqu %xmm0, (%rdi)
@@ -1276,7 +1276,7 @@ define void @PR46531(i32* %x, i32* %y, i32* %z) {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqu (%rsi), %xmm0
; AVX512VL-NEXT: vmovdqu (%rdx), %xmm1
-; AVX512VL-NEXT: vptestnmd {{.*}}(%rip){1to4}, %xmm1, %k1
+; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %k1
; AVX512VL-NEXT: vpxor %xmm0, %xmm1, %xmm2
; AVX512VL-NEXT: vpord %xmm0, %xmm1, %xmm2 {%k1}
; AVX512VL-NEXT: vmovdqu %xmm2, (%rdi)
@@ -1287,7 +1287,7 @@ define void @PR46531(i32* %x, i32* %y, i32* %z) {
; XOP-NEXT: vmovdqu (%rsi), %xmm0
; XOP-NEXT: vmovdqu (%rdx), %xmm1
; XOP-NEXT: vpor %xmm0, %xmm1, %xmm2
-; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm3
+; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3
; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
; XOP-NEXT: vpcomneqd %xmm4, %xmm3, %xmm3
; XOP-NEXT: vpxor %xmm0, %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/vselect-zero.ll b/llvm/test/CodeGen/X86/vselect-zero.ll
index 5bf1184c23b12..2b990b2ed33fa 100644
--- a/llvm/test/CodeGen/X86/vselect-zero.ll
+++ b/llvm/test/CodeGen/X86/vselect-zero.ll
@@ -145,7 +145,7 @@ define <2 x double> @vsel_nonzero_constants(<2 x double> %x, <2 x double> %y) {
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movapd %xmm1, %xmm2
; SSE2-NEXT: andnpd %xmm0, %xmm2
-; SSE2-NEXT: andpd {{.*}}(%rip), %xmm1
+; SSE2-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: orpd %xmm2, %xmm1
; SSE2-NEXT: movapd %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -155,7 +155,7 @@ define <2 x double> @vsel_nonzero_constants(<2 x double> %x, <2 x double> %y) {
; SSE42-NEXT: cmplepd %xmm0, %xmm1
; SSE42-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; SSE42-NEXT: movapd %xmm1, %xmm0
-; SSE42-NEXT: blendvpd %xmm0, {{.*}}(%rip), %xmm2
+; SSE42-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE42-NEXT: movapd %xmm2, %xmm0
; SSE42-NEXT: retq
;
@@ -163,7 +163,7 @@ define <2 x double> @vsel_nonzero_constants(<2 x double> %x, <2 x double> %y) {
; AVX: # %bb.0:
; AVX-NEXT: vcmplepd %xmm0, %xmm1, %xmm0
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; AVX-NEXT: vblendvpd %xmm0, {{.*}}(%rip), %xmm1, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX-NEXT: retq
%cond = fcmp oge <2 x double> %x, %y
%r = select <2 x i1> %cond, <2 x double> <double 12.0, double -1.0>, <2 x double> <double 42.0, double 0.0>
diff --git a/llvm/test/CodeGen/X86/vselect.ll b/llvm/test/CodeGen/X86/vselect.ll
index 2354ca1ca5c89..f9469d61a1ada 100644
--- a/llvm/test/CodeGen/X86/vselect.ll
+++ b/llvm/test/CodeGen/X86/vselect.ll
@@ -650,7 +650,7 @@ define i64 @vselect_any_extend_vector_inreg_crash(<8 x i8>* %x) {
; SSE-LABEL: vselect_any_extend_vector_inreg_crash:
; SSE: # %bb.0:
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
+; SSE-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: movq %xmm0, %rax
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: shlq $15, %rax
@@ -659,7 +659,7 @@ define i64 @vselect_any_extend_vector_inreg_crash(<8 x i8>* %x) {
; AVX-LABEL: vselect_any_extend_vector_inreg_crash:
; AVX: # %bb.0:
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vpcmpeqb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: andl $1, %eax
; AVX-NEXT: shlq $15, %rax
diff --git a/llvm/test/CodeGen/X86/vshift-6.ll b/llvm/test/CodeGen/X86/vshift-6.ll
index 3c0081d049f46..4c76f2b4acd54 100644
--- a/llvm/test/CodeGen/X86/vshift-6.ll
+++ b/llvm/test/CodeGen/X86/vshift-6.ll
@@ -42,7 +42,7 @@ define <16 x i8> @do_not_crash(i8*, i32*, i64*, i32, i64, i8) {
; X86-NEXT: pxor %xmm0, %xmm0
; X86-NEXT: pcmpgtb %xmm1, %xmm0
; X86-NEXT: pxor %xmm0, %xmm2
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: por %xmm2, %xmm0
; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: pxor %xmm2, %xmm2
@@ -51,7 +51,7 @@ define <16 x i8> @do_not_crash(i8*, i32*, i64*, i32, i64, i8) {
; X86-NEXT: pandn %xmm0, %xmm4
; X86-NEXT: psllw $2, %xmm0
; X86-NEXT: pand %xmm2, %xmm0
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: por %xmm4, %xmm0
; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: pcmpgtb %xmm1, %xmm3
@@ -77,7 +77,7 @@ define <16 x i8> @do_not_crash(i8*, i32*, i64*, i32, i64, i8) {
; X64-NEXT: pxor %xmm0, %xmm0
; X64-NEXT: pcmpgtb %xmm1, %xmm0
; X64-NEXT: pxor %xmm0, %xmm2
-; X64-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: por %xmm2, %xmm0
; X64-NEXT: paddb %xmm1, %xmm1
; X64-NEXT: pxor %xmm2, %xmm2
@@ -86,7 +86,7 @@ define <16 x i8> @do_not_crash(i8*, i32*, i64*, i32, i64, i8) {
; X64-NEXT: pandn %xmm0, %xmm4
; X64-NEXT: psllw $2, %xmm0
; X64-NEXT: pand %xmm2, %xmm0
-; X64-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: por %xmm4, %xmm0
; X64-NEXT: paddb %xmm1, %xmm1
; X64-NEXT: pcmpgtb %xmm1, %xmm3
diff --git a/llvm/test/CodeGen/X86/vshli-simplify-demanded-bits.ll b/llvm/test/CodeGen/X86/vshli-simplify-demanded-bits.ll
index c4e9ba8b71610..4a3aac4d06b1f 100644
--- a/llvm/test/CodeGen/X86/vshli-simplify-demanded-bits.ll
+++ b/llvm/test/CodeGen/X86/vshli-simplify-demanded-bits.ll
@@ -27,7 +27,7 @@ define <8 x i8> @vshli_target_constant(<8 x i16> %arg, <8 x i32> %arg1) {
; CHECK-NEXT: pslld $15, %xmm4
; CHECK-NEXT: psrad $16, %xmm4
; CHECK-NEXT: packssdw %xmm2, %xmm4
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm4
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; CHECK-NEXT: pmullw %xmm4, %xmm1
diff --git a/llvm/test/CodeGen/X86/widen_cast-5.ll b/llvm/test/CodeGen/X86/widen_cast-5.ll
index c937262d12746..929177039e410 100644
--- a/llvm/test/CodeGen/X86/widen_cast-5.ll
+++ b/llvm/test/CodeGen/X86/widen_cast-5.ll
@@ -9,7 +9,7 @@ define void @convert(<2 x i32>* %dst.addr, i64 %src) nounwind {
; X86: ## %bb.0: ## %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-NEXT: xorps LCPI0_0, %xmm0
+; X86-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movlps %xmm0, (%eax)
; X86-NEXT: retl
;
diff --git a/llvm/test/CodeGen/X86/widen_load-2.ll b/llvm/test/CodeGen/X86/widen_load-2.ll
index a14736bd68374..3ed813acd699b 100644
--- a/llvm/test/CodeGen/X86/widen_load-2.ll
+++ b/llvm/test/CodeGen/X86/widen_load-2.ll
@@ -359,7 +359,7 @@ define void @rot(%i8vec3pack* nocapture sret(%i8vec3pack) %result, %i8vec3pack*
; X86-NEXT: movw $257, (%ecx) # imm = 0x101
; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: psrlw $1, %xmm0
-; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: pextrb $2, %xmm0, 2(%eax)
; X86-NEXT: pextrw $0, %xmm0, (%eax)
; X86-NEXT: retl $4
@@ -373,7 +373,7 @@ define void @rot(%i8vec3pack* nocapture sret(%i8vec3pack) %result, %i8vec3pack*
; X64-NEXT: movw $257, (%rdx) # imm = 0x101
; X64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-NEXT: psrlw $1, %xmm0
-; X64-NEXT: pand {{.*}}(%rip), %xmm0
+; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: pextrb $2, %xmm0, 2(%rdi)
; X64-NEXT: pextrw $0, %xmm0, (%rdi)
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/widen_mul.ll b/llvm/test/CodeGen/X86/widen_mul.ll
index 6c217c30721ac..5fe36da7fd5ff 100644
--- a/llvm/test/CodeGen/X86/widen_mul.ll
+++ b/llvm/test/CodeGen/X86/widen_mul.ll
@@ -13,7 +13,7 @@ define <2 x i8> @mul_v2i8(<2 x i8> %x, <2 x i8> %y) {
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pmullw %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq
;
@@ -42,7 +42,7 @@ define <4 x i8> @mul_v4i8(<4 x i8> %x, <4 x i8> %y) {
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pmullw %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq
;
@@ -71,7 +71,7 @@ define <8 x i8> @mul_v8i8(<8 x i8> %x, <8 x i8> %y) {
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pmullw %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/x86-64-baseptr.ll b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
index c0e84a20faad3..034ddef906423 100644
--- a/llvm/test/CodeGen/X86/x86-64-baseptr.ll
+++ b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
@@ -20,7 +20,7 @@ define void @base() #0 {
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $32, %rsp
; CHECK-NEXT: movq %rsp, %rbx
-; CHECK-NEXT: callq helper
+; CHECK-NEXT: callq helper at PLT
; CHECK-NEXT: movq %rsp, %rcx
; CHECK-NEXT: movl %eax, %eax
; CHECK-NEXT: leaq 31(,%rax,4), %rax
@@ -43,7 +43,7 @@ define void @base() #0 {
; X32ABI-NEXT: andl $-32, %esp
; X32ABI-NEXT: subl $32, %esp
; X32ABI-NEXT: movl %esp, %ebx
-; X32ABI-NEXT: callq helper
+; X32ABI-NEXT: callq helper at PLT
; X32ABI-NEXT: # kill: def $eax killed $eax def $rax
; X32ABI-NEXT: leal 31(,%rax,4), %eax
; X32ABI-NEXT: andl $-32, %eax
diff --git a/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll b/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll
index 187c3963f2fb1..f1bf797d29ad4 100644
--- a/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll
+++ b/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll
@@ -7,14 +7,14 @@
; Clobbered SSE must not be saved when the target doesn't support SSE
define x86_intrcc void @test_isr_sse_clobbers(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i64 %ecode) {
- ; CHECK-LABEL: test_isr_sse_clobbers:
- ; CHECK: # %bb.0:
- ; CHECK-NEXT: pushq %rax
- ; CHECK-NEXT: cld
- ; CHECK-NEXT: #APP
- ; CHECK-NEXT: #NO_APP
- ; CHECK-NEXT: addq $16, %rsp
- ; CHECK-NEXT: iretq
+; CHECK-LABEL: test_isr_sse_clobbers:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: cld
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: addq $16, %rsp
+; CHECK-NEXT: iretq
call void asm sideeffect "", "~{xmm0},~{xmm6}"()
ret void
}
diff --git a/llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll b/llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
index 837b0782004ce..2d9286dd86dc4 100644
--- a/llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
+++ b/llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp --no_x86_scrub_rip
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp
; RUN: llc < %s | FileCheck %s -check-prefixes=CHECK-USER
; RUN: llc -O0 < %s | FileCheck %s -check-prefixes=CHECK0-USER
; RUN: llc -code-model=kernel < %s | FileCheck %s -check-prefixes=CHECK-KERNEL
diff --git a/llvm/test/CodeGen/X86/x86-64-mem.ll b/llvm/test/CodeGen/X86/x86-64-mem.ll
index bd6787e869f7a..f4bbdc7f2df72 100644
--- a/llvm/test/CodeGen/X86/x86-64-mem.ll
+++ b/llvm/test/CodeGen/X86/x86-64-mem.ll
@@ -14,17 +14,17 @@
define void @test1() nounwind {
; DARWIN-LABEL: test1:
; DARWIN: ## %bb.0:
-; DARWIN-NEXT: movq _src@{{.*}}(%rip), %rax
+; DARWIN-NEXT: movq _src at GOTPCREL(%rip), %rax
; DARWIN-NEXT: movl (%rax), %eax
-; DARWIN-NEXT: movq _dst@{{.*}}(%rip), %rcx
+; DARWIN-NEXT: movq _dst at GOTPCREL(%rip), %rcx
; DARWIN-NEXT: movl %eax, (%rcx)
; DARWIN-NEXT: retq
;
; LINUX-LABEL: test1:
; LINUX: # %bb.0:
-; LINUX-NEXT: movq src@{{.*}}(%rip), %rax
+; LINUX-NEXT: movq src at GOTPCREL(%rip), %rax
; LINUX-NEXT: movl (%rax), %eax
-; LINUX-NEXT: movq dst@{{.*}}(%rip), %rcx
+; LINUX-NEXT: movq dst at GOTPCREL(%rip), %rcx
; LINUX-NEXT: movl %eax, (%rcx)
; LINUX-NEXT: retq
%tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @src, i32 0, i32 0) ; <i32> [#uses=1]
@@ -35,15 +35,15 @@ define void @test1() nounwind {
define void @test2() nounwind {
; DARWIN-LABEL: test2:
; DARWIN: ## %bb.0:
-; DARWIN-NEXT: movq _dst@{{.*}}(%rip), %rax
-; DARWIN-NEXT: movq _ptr@{{.*}}(%rip), %rcx
+; DARWIN-NEXT: movq _dst at GOTPCREL(%rip), %rax
+; DARWIN-NEXT: movq _ptr at GOTPCREL(%rip), %rcx
; DARWIN-NEXT: movq %rax, (%rcx)
; DARWIN-NEXT: retq
;
; LINUX-LABEL: test2:
; LINUX: # %bb.0:
-; LINUX-NEXT: movq dst@{{.*}}(%rip), %rax
-; LINUX-NEXT: movq ptr@{{.*}}(%rip), %rcx
+; LINUX-NEXT: movq dst at GOTPCREL(%rip), %rax
+; LINUX-NEXT: movq ptr at GOTPCREL(%rip), %rcx
; LINUX-NEXT: movq %rax, (%rcx)
; LINUX-NEXT: retq
store i32* getelementptr ([0 x i32], [0 x i32]* @dst, i32 0, i32 0), i32** @ptr
@@ -53,13 +53,13 @@ define void @test2() nounwind {
define void @test3() nounwind {
; DARWIN-LABEL: test3:
; DARWIN: ## %bb.0:
-; DARWIN-NEXT: leaq {{.*}}(%rip), %rax
-; DARWIN-NEXT: movq %rax, {{.*}}(%rip)
+; DARWIN-NEXT: leaq _ldst(%rip), %rax
+; DARWIN-NEXT: movq %rax, _lptr(%rip)
; DARWIN-NEXT: retq
;
; LINUX-LABEL: test3:
; LINUX: # %bb.0:
-; LINUX-NEXT: movq $ldst, {{.*}}(%rip)
+; LINUX-NEXT: movq $ldst, lptr(%rip)
; LINUX-NEXT: retq
store i32* getelementptr ([500 x i32], [500 x i32]* @ldst, i32 0, i32 0), i32** @lptr
br label %return
diff --git a/llvm/test/CodeGen/X86/x86-64-pic-4.ll b/llvm/test/CodeGen/X86/x86-64-pic-4.ll
index 57ebd8f9532bf..3900cf7f772a7 100644
--- a/llvm/test/CodeGen/X86/x86-64-pic-4.ll
+++ b/llvm/test/CodeGen/X86/x86-64-pic-4.ll
@@ -6,7 +6,7 @@
define i32 @get_a() {
; CHECK-LABEL: get_a:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq a@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq a at GOTPCREL(%rip), %rax
; CHECK-NEXT: movl (%rax), %eax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/x86-64-pic-5.ll b/llvm/test/CodeGen/X86/x86-64-pic-5.ll
index a24e5a20385d5..f8819d6edff78 100644
--- a/llvm/test/CodeGen/X86/x86-64-pic-5.ll
+++ b/llvm/test/CodeGen/X86/x86-64-pic-5.ll
@@ -6,7 +6,7 @@
define i32 @get_a() {
; CHECK-LABEL: get_a:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl a(%rip), %eax
; CHECK-NEXT: retq
entry:
%tmp1 = load i32, i32* @a, align 4
diff --git a/llvm/test/CodeGen/X86/x86-64-pic-6.ll b/llvm/test/CodeGen/X86/x86-64-pic-6.ll
index 8301dce3e88ab..b23119ed2d898 100644
--- a/llvm/test/CodeGen/X86/x86-64-pic-6.ll
+++ b/llvm/test/CodeGen/X86/x86-64-pic-6.ll
@@ -6,7 +6,7 @@
define i32 @get_a() nounwind {
; CHECK-LABEL: get_a:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: movl a(%rip), %eax
; CHECK-NEXT: retq
entry:
%tmp1 = load i32, i32* @a, align 4
diff --git a/llvm/test/CodeGen/X86/x86-64-pic-7.ll b/llvm/test/CodeGen/X86/x86-64-pic-7.ll
index b884bec7a89e1..3739a6799f20b 100644
--- a/llvm/test/CodeGen/X86/x86-64-pic-7.ll
+++ b/llvm/test/CodeGen/X86/x86-64-pic-7.ll
@@ -4,7 +4,7 @@
define void ()* @g() nounwind {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq f@{{.*}}(%rip), %rax
+; CHECK-NEXT: movq f at GOTPCREL(%rip), %rax
; CHECK-NEXT: retq
entry:
ret void ()* @f
diff --git a/llvm/test/CodeGen/X86/x86-64-pic-8.ll b/llvm/test/CodeGen/X86/x86-64-pic-8.ll
index e1967995d1a94..2856aa6a6e088 100644
--- a/llvm/test/CodeGen/X86/x86-64-pic-8.ll
+++ b/llvm/test/CodeGen/X86/x86-64-pic-8.ll
@@ -4,7 +4,7 @@
define void ()* @g() {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: leaq {{.*}}(%rip), %rax
+; CHECK-NEXT: leaq f(%rip), %rax
; CHECK-NEXT: retq
entry:
ret void ()* @f
diff --git a/llvm/test/CodeGen/X86/x86-64-pic-9.ll b/llvm/test/CodeGen/X86/x86-64-pic-9.ll
index 1f461bf443ac4..2f698141b03f6 100644
--- a/llvm/test/CodeGen/X86/x86-64-pic-9.ll
+++ b/llvm/test/CodeGen/X86/x86-64-pic-9.ll
@@ -4,7 +4,7 @@
define void ()* @g() nounwind {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: leaq {{.*}}(%rip), %rax
+; CHECK-NEXT: leaq f(%rip), %rax
; CHECK-NEXT: retq
entry:
ret void ()* @f
diff --git a/llvm/test/CodeGen/X86/x86-64-psub.ll b/llvm/test/CodeGen/X86/x86-64-psub.ll
index e1ca8680f05a6..9817d798fd4bf 100644
--- a/llvm/test/CodeGen/X86/x86-64-psub.ll
+++ b/llvm/test/CodeGen/X86/x86-64-psub.ll
@@ -14,9 +14,9 @@ define i64 @test_psubb() {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: callq getFirstParam
+; CHECK-NEXT: callq getFirstParam at PLT
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: callq getSecondParam
+; CHECK-NEXT: callq getSecondParam at PLT
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubb %mm1, %mm0
@@ -48,9 +48,9 @@ define i64 @test_psubw() {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: callq getFirstParam
+; CHECK-NEXT: callq getFirstParam at PLT
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: callq getSecondParam
+; CHECK-NEXT: callq getSecondParam at PLT
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubw %mm1, %mm0
@@ -82,9 +82,9 @@ define i64 @test_psubd() {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: callq getFirstParam
+; CHECK-NEXT: callq getFirstParam at PLT
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: callq getSecondParam
+; CHECK-NEXT: callq getSecondParam at PLT
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubd %mm1, %mm0
@@ -116,9 +116,9 @@ define i64 @test_psubsb() {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: callq getFirstParam
+; CHECK-NEXT: callq getFirstParam at PLT
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: callq getSecondParam
+; CHECK-NEXT: callq getSecondParam at PLT
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubsb %mm1, %mm0
@@ -150,9 +150,9 @@ define i64 @test_psubswv() {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: callq getFirstParam
+; CHECK-NEXT: callq getFirstParam at PLT
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: callq getSecondParam
+; CHECK-NEXT: callq getSecondParam at PLT
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubsw %mm1, %mm0
@@ -184,9 +184,9 @@ define i64 @test_psubusbv() {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: callq getFirstParam
+; CHECK-NEXT: callq getFirstParam at PLT
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: callq getSecondParam
+; CHECK-NEXT: callq getSecondParam at PLT
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubusb %mm1, %mm0
@@ -218,9 +218,9 @@ define i64 @test_psubuswv() {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
-; CHECK-NEXT: callq getFirstParam
+; CHECK-NEXT: callq getFirstParam at PLT
; CHECK-NEXT: movq %rax, %rbx
-; CHECK-NEXT: callq getSecondParam
+; CHECK-NEXT: callq getSecondParam at PLT
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubusw %mm1, %mm0
diff --git a/llvm/test/CodeGen/X86/x86-64-ret0.ll b/llvm/test/CodeGen/X86/x86-64-ret0.ll
index 4baf11c532c43..d3f5f74f2789c 100644
--- a/llvm/test/CodeGen/X86/x86-64-ret0.ll
+++ b/llvm/test/CodeGen/X86/x86-64-ret0.ll
@@ -6,7 +6,7 @@ define i32 @f() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl $1, %edi
-; CHECK-NEXT: callq t
+; CHECK-NEXT: callq t at PLT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/x86-64-varargs.ll b/llvm/test/CodeGen/X86/x86-64-varargs.ll
index 82c24ba39b099..9b3a72427de0e 100644
--- a/llvm/test/CodeGen/X86/x86-64-varargs.ll
+++ b/llvm/test/CodeGen/X86/x86-64-varargs.ll
@@ -561,9 +561,9 @@ define i32 @main() nounwind {
; CHECK-X64-NEXT: pushq %rax
; CHECK-X64-NEXT: movl $12, (%rsp)
; CHECK-X64-NEXT: movabsq $_func, %r10
-; CHECK-X64-NEXT: movabsq $LCPI1_0, %rax
+; CHECK-X64-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; CHECK-X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-X64-NEXT: movabsq $LCPI1_1, %rax
+; CHECK-X64-NEXT: movabsq ${{\.?LCPI[0-9]+_[0-9]+}}, %rax
; CHECK-X64-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-X64-NEXT: movabsq $123456677890, %r8 ## imm = 0x1CBE976802
; CHECK-X64-NEXT: movl $1, %edi
diff --git a/llvm/test/CodeGen/X86/x86-interleaved-access.ll b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
index 32598cdcbf088..75a45c459d5fb 100644
--- a/llvm/test/CodeGen/X86/x86-interleaved-access.ll
+++ b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
@@ -521,7 +521,7 @@ define <16 x i1> @interleaved_load_vf16_i8_stride4(<64 x i8>* %ptr) {
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpcmpeqb %xmm0, %xmm5, %xmm0
; AVX1-NEXT: vpxor %xmm0, %xmm2, %xmm0
-; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: interleaved_load_vf16_i8_stride4:
@@ -569,7 +569,7 @@ define <16 x i1> @interleaved_load_vf16_i8_stride4(<64 x i8>* %ptr) {
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]
; AVX2-NEXT: vpcmpeqb %xmm0, %xmm5, %xmm0
; AVX2-NEXT: vpxor %xmm0, %xmm4, %xmm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: interleaved_load_vf16_i8_stride4:
@@ -711,7 +711,7 @@ define <32 x i1> @interleaved_load_vf32_i8_stride4(<128 x i8>* %ptr) {
; AVX1-NEXT: vinsertf128 $1, %xmm9, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm0, %ymm2, %ymm0
-; AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: interleaved_load_vf32_i8_stride4:
@@ -803,7 +803,7 @@ define <32 x i1> @interleaved_load_vf32_i8_stride4(<128 x i8>* %ptr) {
; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm0, %ymm8, %ymm0
-; AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: interleaved_load_vf32_i8_stride4:
diff --git a/llvm/test/CodeGen/X86/x86-interrupt_cc.ll b/llvm/test/CodeGen/X86/x86-interrupt_cc.ll
index 0456695666273..66cee86904da5 100644
--- a/llvm/test/CodeGen/X86/x86-interrupt_cc.ll
+++ b/llvm/test/CodeGen/X86/x86-interrupt_cc.ll
@@ -29,83 +29,83 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK64-KNL-NEXT: .cfi_def_cfa_offset 80
; CHECK64-KNL-NEXT: subq $2096, %rsp ## encoding: [0x48,0x81,0xec,0x30,0x08,0x00,0x00]
; CHECK64-KNL-NEXT: ## imm = 0x830
-; CHECK64-KNL-NEXT: kmovw %k7, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k7, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xbc,0x24,0x2e,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw %k6, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k6, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xb4,0x24,0x2c,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw %k5, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k5, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xac,0x24,0x2a,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw %k4, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k4, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xa4,0x24,0x28,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw %k3, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k3, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x9c,0x24,0x26,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw %k2, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k2, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x94,0x24,0x24,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x8c,0x24,0x22,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
+; CHECK64-KNL-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x84,0x24,0x20,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: vmovups %zmm31, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm31, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x7c,0x24,0x1f]
-; CHECK64-KNL-NEXT: vmovups %zmm30, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm30, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x74,0x24,0x1e]
-; CHECK64-KNL-NEXT: vmovups %zmm29, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm29, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x6c,0x24,0x1d]
-; CHECK64-KNL-NEXT: vmovups %zmm28, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm28, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x64,0x24,0x1c]
-; CHECK64-KNL-NEXT: vmovups %zmm27, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x5c,0x24,0x1b]
-; CHECK64-KNL-NEXT: vmovups %zmm26, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x54,0x24,0x1a]
-; CHECK64-KNL-NEXT: vmovups %zmm25, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x4c,0x24,0x19]
-; CHECK64-KNL-NEXT: vmovups %zmm24, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x44,0x24,0x18]
-; CHECK64-KNL-NEXT: vmovups %zmm23, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x7c,0x24,0x17]
-; CHECK64-KNL-NEXT: vmovups %zmm22, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x74,0x24,0x16]
-; CHECK64-KNL-NEXT: vmovups %zmm21, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x6c,0x24,0x15]
-; CHECK64-KNL-NEXT: vmovups %zmm20, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm20, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x64,0x24,0x14]
-; CHECK64-KNL-NEXT: vmovups %zmm19, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x5c,0x24,0x13]
-; CHECK64-KNL-NEXT: vmovups %zmm18, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x54,0x24,0x12]
-; CHECK64-KNL-NEXT: vmovups %zmm17, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x4c,0x24,0x11]
-; CHECK64-KNL-NEXT: vmovups %zmm16, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x44,0x24,0x10]
-; CHECK64-KNL-NEXT: vmovups %zmm15, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x7c,0x24,0x0f]
-; CHECK64-KNL-NEXT: vmovups %zmm14, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x74,0x24,0x0e]
-; CHECK64-KNL-NEXT: vmovups %zmm13, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x6c,0x24,0x0d]
-; CHECK64-KNL-NEXT: vmovups %zmm12, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x64,0x24,0x0c]
-; CHECK64-KNL-NEXT: vmovups %zmm11, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x5c,0x24,0x0b]
-; CHECK64-KNL-NEXT: vmovups %zmm10, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x54,0x24,0x0a]
-; CHECK64-KNL-NEXT: vmovups %zmm9, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x4c,0x24,0x09]
-; CHECK64-KNL-NEXT: vmovups %zmm8, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x44,0x24,0x08]
-; CHECK64-KNL-NEXT: vmovups %zmm7, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x7c,0x24,0x07]
-; CHECK64-KNL-NEXT: vmovups %zmm6, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x74,0x24,0x06]
-; CHECK64-KNL-NEXT: vmovups %zmm5, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x6c,0x24,0x05]
-; CHECK64-KNL-NEXT: vmovups %zmm4, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x64,0x24,0x04]
-; CHECK64-KNL-NEXT: vmovups %zmm3, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x5c,0x24,0x03]
-; CHECK64-KNL-NEXT: vmovups %zmm2, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x54,0x24,0x02]
-; CHECK64-KNL-NEXT: vmovups %zmm1, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-KNL-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x4c,0x24,0x01]
; CHECK64-KNL-NEXT: vmovups %zmm0, (%rsp) ## 64-byte Spill
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x04,0x24]
@@ -164,83 +164,83 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK64-KNL-NEXT: ## fixup A - offset: 1, value: _bar-4, kind: reloc_branch_4byte_pcrel
; CHECK64-KNL-NEXT: vmovups (%rsp), %zmm0 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x04,0x24]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm1 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x4c,0x24,0x01]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm2 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x54,0x24,0x02]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm3 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x5c,0x24,0x03]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm4 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x64,0x24,0x04]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm5 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x6c,0x24,0x05]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm6 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x74,0x24,0x06]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm7 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x7c,0x24,0x07]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm8 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x44,0x24,0x08]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm9 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x4c,0x24,0x09]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm10 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x54,0x24,0x0a]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm11 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x5c,0x24,0x0b]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm12 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x64,0x24,0x0c]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm13 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x6c,0x24,0x0d]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm14 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x74,0x24,0x0e]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm15 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x7c,0x24,0x0f]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm16 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x44,0x24,0x10]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm17 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x4c,0x24,0x11]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm18 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x54,0x24,0x12]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm19 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x5c,0x24,0x13]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm20 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x64,0x24,0x14]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm21 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm21 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x6c,0x24,0x15]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm22 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x74,0x24,0x16]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm23 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x7c,0x24,0x17]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm24 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x44,0x24,0x18]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm25 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm25 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x4c,0x24,0x19]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm26 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x54,0x24,0x1a]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm27 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x5c,0x24,0x1b]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm28 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x64,0x24,0x1c]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm29 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x6c,0x24,0x1d]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm30 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x74,0x24,0x1e]
-; CHECK64-KNL-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm31 ## 64-byte Reload
+; CHECK64-KNL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 ## 64-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x7c,0x24,0x1f]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x84,0x24,0x20,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x8c,0x24,0x22,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k2 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x94,0x24,0x24,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k3 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k3 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x9c,0x24,0x26,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k4 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k4 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xa4,0x24,0x28,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k5 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k5 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xac,0x24,0x2a,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k6 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k6 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xb4,0x24,0x2c,0x08,0x00,0x00]
-; CHECK64-KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k7 ## 2-byte Reload
+; CHECK64-KNL-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k7 ## 2-byte Reload
; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xbc,0x24,0x2e,0x08,0x00,0x00]
; CHECK64-KNL-NEXT: addq $2096, %rsp ## encoding: [0x48,0x81,0xc4,0x30,0x08,0x00,0x00]
; CHECK64-KNL-NEXT: ## imm = 0x830
@@ -277,83 +277,83 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK64-SKX-NEXT: .cfi_def_cfa_offset 80
; CHECK64-SKX-NEXT: subq $2160, %rsp ## encoding: [0x48,0x81,0xec,0x70,0x08,0x00,0x00]
; CHECK64-SKX-NEXT: ## imm = 0x870
-; CHECK64-SKX-NEXT: kmovq %k7, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k7, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xbc,0x24,0x68,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq %k6, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k6, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xb4,0x24,0x60,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq %k5, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k5, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xac,0x24,0x58,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq %k4, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k4, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xa4,0x24,0x50,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq %k3, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k3, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x9c,0x24,0x48,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq %k2, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k2, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x94,0x24,0x40,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq %k1, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x8c,0x24,0x38,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq %k0, {{[0-9]+}}(%rsp) ## 8-byte Spill
+; CHECK64-SKX-NEXT: kmovq %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x84,0x24,0x30,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: vmovups %zmm31, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm31, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x7c,0x24,0x1f]
-; CHECK64-SKX-NEXT: vmovups %zmm30, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm30, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x74,0x24,0x1e]
-; CHECK64-SKX-NEXT: vmovups %zmm29, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm29, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x6c,0x24,0x1d]
-; CHECK64-SKX-NEXT: vmovups %zmm28, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm28, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x64,0x24,0x1c]
-; CHECK64-SKX-NEXT: vmovups %zmm27, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x5c,0x24,0x1b]
-; CHECK64-SKX-NEXT: vmovups %zmm26, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x54,0x24,0x1a]
-; CHECK64-SKX-NEXT: vmovups %zmm25, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x4c,0x24,0x19]
-; CHECK64-SKX-NEXT: vmovups %zmm24, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x44,0x24,0x18]
-; CHECK64-SKX-NEXT: vmovups %zmm23, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x7c,0x24,0x17]
-; CHECK64-SKX-NEXT: vmovups %zmm22, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x74,0x24,0x16]
-; CHECK64-SKX-NEXT: vmovups %zmm21, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x6c,0x24,0x15]
-; CHECK64-SKX-NEXT: vmovups %zmm20, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm20, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x64,0x24,0x14]
-; CHECK64-SKX-NEXT: vmovups %zmm19, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x5c,0x24,0x13]
-; CHECK64-SKX-NEXT: vmovups %zmm18, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x54,0x24,0x12]
-; CHECK64-SKX-NEXT: vmovups %zmm17, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x4c,0x24,0x11]
-; CHECK64-SKX-NEXT: vmovups %zmm16, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x11,0x44,0x24,0x10]
-; CHECK64-SKX-NEXT: vmovups %zmm15, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x7c,0x24,0x0f]
-; CHECK64-SKX-NEXT: vmovups %zmm14, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x74,0x24,0x0e]
-; CHECK64-SKX-NEXT: vmovups %zmm13, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x6c,0x24,0x0d]
-; CHECK64-SKX-NEXT: vmovups %zmm12, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x64,0x24,0x0c]
-; CHECK64-SKX-NEXT: vmovups %zmm11, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x5c,0x24,0x0b]
-; CHECK64-SKX-NEXT: vmovups %zmm10, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x54,0x24,0x0a]
-; CHECK64-SKX-NEXT: vmovups %zmm9, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x4c,0x24,0x09]
-; CHECK64-SKX-NEXT: vmovups %zmm8, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x11,0x44,0x24,0x08]
-; CHECK64-SKX-NEXT: vmovups %zmm7, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x7c,0x24,0x07]
-; CHECK64-SKX-NEXT: vmovups %zmm6, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x74,0x24,0x06]
-; CHECK64-SKX-NEXT: vmovups %zmm5, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x6c,0x24,0x05]
-; CHECK64-SKX-NEXT: vmovups %zmm4, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x64,0x24,0x04]
-; CHECK64-SKX-NEXT: vmovups %zmm3, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x5c,0x24,0x03]
-; CHECK64-SKX-NEXT: vmovups %zmm2, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x54,0x24,0x02]
-; CHECK64-SKX-NEXT: vmovups %zmm1, {{[0-9]+}}(%rsp) ## 64-byte Spill
+; CHECK64-SKX-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x4c,0x24,0x01]
; CHECK64-SKX-NEXT: vmovups %zmm0, (%rsp) ## 64-byte Spill
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x04,0x24]
@@ -413,83 +413,83 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK64-SKX-NEXT: ## fixup A - offset: 1, value: _bar-4, kind: reloc_branch_4byte_pcrel
; CHECK64-SKX-NEXT: vmovups (%rsp), %zmm0 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x04,0x24]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm1 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x4c,0x24,0x01]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm2 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x54,0x24,0x02]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm3 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x5c,0x24,0x03]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm4 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x64,0x24,0x04]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm5 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x6c,0x24,0x05]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm6 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x74,0x24,0x06]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm7 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x7c,0x24,0x07]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm8 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x44,0x24,0x08]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm9 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x4c,0x24,0x09]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm10 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x54,0x24,0x0a]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm11 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x5c,0x24,0x0b]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm12 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x64,0x24,0x0c]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm13 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x6c,0x24,0x0d]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm14 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x74,0x24,0x0e]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm15 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x71,0x7c,0x48,0x10,0x7c,0x24,0x0f]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm16 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x44,0x24,0x10]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm17 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x4c,0x24,0x11]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm18 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x54,0x24,0x12]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm19 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x5c,0x24,0x13]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm20 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x64,0x24,0x14]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm21 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm21 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x6c,0x24,0x15]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm22 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x74,0x24,0x16]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm23 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0xe1,0x7c,0x48,0x10,0x7c,0x24,0x17]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm24 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x44,0x24,0x18]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm25 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm25 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x4c,0x24,0x19]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm26 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x54,0x24,0x1a]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm27 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x5c,0x24,0x1b]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm28 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x64,0x24,0x1c]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm29 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x6c,0x24,0x1d]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm30 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x74,0x24,0x1e]
-; CHECK64-SKX-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm31 ## 64-byte Reload
+; CHECK64-SKX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 ## 64-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x10,0x7c,0x24,0x1f]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k0 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k0 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x84,0x24,0x30,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k1 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x8c,0x24,0x38,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k2 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k2 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x94,0x24,0x40,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k3 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k3 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x9c,0x24,0x48,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k4 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k4 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xa4,0x24,0x50,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k5 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k5 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xac,0x24,0x58,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k6 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k6 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xb4,0x24,0x60,0x08,0x00,0x00]
-; CHECK64-SKX-NEXT: kmovq {{[0-9]+}}(%rsp), %k7 ## 8-byte Reload
+; CHECK64-SKX-NEXT: kmovq {{[-0-9]+}}(%r{{[sb]}}p), %k7 ## 8-byte Reload
; CHECK64-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xbc,0x24,0x68,0x08,0x00,0x00]
; CHECK64-SKX-NEXT: addq $2160, %rsp ## encoding: [0x48,0x81,0xc4,0x70,0x08,0x00,0x00]
; CHECK64-SKX-NEXT: ## imm = 0x870
@@ -514,35 +514,35 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK32-KNL-NEXT: .cfi_def_cfa_offset 16
; CHECK32-KNL-NEXT: subl $560, %esp ## encoding: [0x81,0xec,0x30,0x02,0x00,0x00]
; CHECK32-KNL-NEXT: ## imm = 0x230
-; CHECK32-KNL-NEXT: kmovw %k7, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k7, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xbc,0x24,0x2e,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw %k6, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k6, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xb4,0x24,0x2c,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw %k5, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k5, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xac,0x24,0x2a,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw %k4, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k4, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xa4,0x24,0x28,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw %k3, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k3, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x9c,0x24,0x26,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw %k2, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k2, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x94,0x24,0x24,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw %k1, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k1, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x8c,0x24,0x22,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw %k0, {{[0-9]+}}(%esp) ## 2-byte Spill
+; CHECK32-KNL-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) ## 2-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x84,0x24,0x20,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: vmovups %zmm7, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-KNL-NEXT: vmovups %zmm7, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x7c,0x24,0x07]
-; CHECK32-KNL-NEXT: vmovups %zmm6, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-KNL-NEXT: vmovups %zmm6, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x74,0x24,0x06]
-; CHECK32-KNL-NEXT: vmovups %zmm5, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-KNL-NEXT: vmovups %zmm5, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x6c,0x24,0x05]
-; CHECK32-KNL-NEXT: vmovups %zmm4, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-KNL-NEXT: vmovups %zmm4, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x64,0x24,0x04]
-; CHECK32-KNL-NEXT: vmovups %zmm3, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-KNL-NEXT: vmovups %zmm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x5c,0x24,0x03]
-; CHECK32-KNL-NEXT: vmovups %zmm2, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-KNL-NEXT: vmovups %zmm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x54,0x24,0x02]
-; CHECK32-KNL-NEXT: vmovups %zmm1, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-KNL-NEXT: vmovups %zmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x4c,0x24,0x01]
; CHECK32-KNL-NEXT: vmovups %zmm0, (%esp) ## 64-byte Spill
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x04,0x24]
@@ -571,35 +571,35 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK32-KNL-NEXT: ## fixup A - offset: 1, value: _bar-4, kind: FK_PCRel_4
; CHECK32-KNL-NEXT: vmovups (%esp), %zmm0 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x04,0x24]
-; CHECK32-KNL-NEXT: vmovups {{[0-9]+}}(%esp), %zmm1 ## 64-byte Reload
+; CHECK32-KNL-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm1 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x4c,0x24,0x01]
-; CHECK32-KNL-NEXT: vmovups {{[0-9]+}}(%esp), %zmm2 ## 64-byte Reload
+; CHECK32-KNL-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm2 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x54,0x24,0x02]
-; CHECK32-KNL-NEXT: vmovups {{[0-9]+}}(%esp), %zmm3 ## 64-byte Reload
+; CHECK32-KNL-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm3 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x5c,0x24,0x03]
-; CHECK32-KNL-NEXT: vmovups {{[0-9]+}}(%esp), %zmm4 ## 64-byte Reload
+; CHECK32-KNL-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm4 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x64,0x24,0x04]
-; CHECK32-KNL-NEXT: vmovups {{[0-9]+}}(%esp), %zmm5 ## 64-byte Reload
+; CHECK32-KNL-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm5 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x6c,0x24,0x05]
-; CHECK32-KNL-NEXT: vmovups {{[0-9]+}}(%esp), %zmm6 ## 64-byte Reload
+; CHECK32-KNL-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm6 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x74,0x24,0x06]
-; CHECK32-KNL-NEXT: vmovups {{[0-9]+}}(%esp), %zmm7 ## 64-byte Reload
+; CHECK32-KNL-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm7 ## 64-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x7c,0x24,0x07]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k0 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x84,0x24,0x20,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k1 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x8c,0x24,0x22,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k2 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k2 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x94,0x24,0x24,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k3 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k3 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0x9c,0x24,0x26,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k4 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k4 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xa4,0x24,0x28,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k5 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k5 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xac,0x24,0x2a,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k6 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k6 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xb4,0x24,0x2c,0x02,0x00,0x00]
-; CHECK32-KNL-NEXT: kmovw {{[0-9]+}}(%esp), %k7 ## 2-byte Reload
+; CHECK32-KNL-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k7 ## 2-byte Reload
; CHECK32-KNL-NEXT: ## encoding: [0xc5,0xf8,0x90,0xbc,0x24,0x2e,0x02,0x00,0x00]
; CHECK32-KNL-NEXT: addl $560, %esp ## encoding: [0x81,0xc4,0x30,0x02,0x00,0x00]
; CHECK32-KNL-NEXT: ## imm = 0x230
@@ -618,35 +618,35 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK32-SKX-NEXT: .cfi_def_cfa_offset 16
; CHECK32-SKX-NEXT: subl $624, %esp ## encoding: [0x81,0xec,0x70,0x02,0x00,0x00]
; CHECK32-SKX-NEXT: ## imm = 0x270
-; CHECK32-SKX-NEXT: kmovq %k7, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k7, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xbc,0x24,0x68,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq %k6, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k6, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xb4,0x24,0x60,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq %k5, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k5, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xac,0x24,0x58,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq %k4, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k4, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0xa4,0x24,0x50,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq %k3, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k3, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x9c,0x24,0x48,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq %k2, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k2, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x94,0x24,0x40,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq %k1, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k1, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x8c,0x24,0x38,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq %k0, {{[0-9]+}}(%esp) ## 8-byte Spill
+; CHECK32-SKX-NEXT: kmovq %k0, {{[-0-9]+}}(%e{{[sb]}}p) ## 8-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x91,0x84,0x24,0x30,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: vmovups %zmm7, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-SKX-NEXT: vmovups %zmm7, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x7c,0x24,0x07]
-; CHECK32-SKX-NEXT: vmovups %zmm6, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-SKX-NEXT: vmovups %zmm6, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x74,0x24,0x06]
-; CHECK32-SKX-NEXT: vmovups %zmm5, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-SKX-NEXT: vmovups %zmm5, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x6c,0x24,0x05]
-; CHECK32-SKX-NEXT: vmovups %zmm4, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-SKX-NEXT: vmovups %zmm4, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x64,0x24,0x04]
-; CHECK32-SKX-NEXT: vmovups %zmm3, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-SKX-NEXT: vmovups %zmm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x5c,0x24,0x03]
-; CHECK32-SKX-NEXT: vmovups %zmm2, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-SKX-NEXT: vmovups %zmm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x54,0x24,0x02]
-; CHECK32-SKX-NEXT: vmovups %zmm1, {{[0-9]+}}(%esp) ## 64-byte Spill
+; CHECK32-SKX-NEXT: vmovups %zmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x4c,0x24,0x01]
; CHECK32-SKX-NEXT: vmovups %zmm0, (%esp) ## 64-byte Spill
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x04,0x24]
@@ -676,35 +676,35 @@ define x86_intrcc void @foo(i8* byval(i8) %frame) {
; CHECK32-SKX-NEXT: ## fixup A - offset: 1, value: _bar-4, kind: FK_PCRel_4
; CHECK32-SKX-NEXT: vmovups (%esp), %zmm0 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x04,0x24]
-; CHECK32-SKX-NEXT: vmovups {{[0-9]+}}(%esp), %zmm1 ## 64-byte Reload
+; CHECK32-SKX-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm1 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x4c,0x24,0x01]
-; CHECK32-SKX-NEXT: vmovups {{[0-9]+}}(%esp), %zmm2 ## 64-byte Reload
+; CHECK32-SKX-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm2 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x54,0x24,0x02]
-; CHECK32-SKX-NEXT: vmovups {{[0-9]+}}(%esp), %zmm3 ## 64-byte Reload
+; CHECK32-SKX-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm3 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x5c,0x24,0x03]
-; CHECK32-SKX-NEXT: vmovups {{[0-9]+}}(%esp), %zmm4 ## 64-byte Reload
+; CHECK32-SKX-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm4 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x64,0x24,0x04]
-; CHECK32-SKX-NEXT: vmovups {{[0-9]+}}(%esp), %zmm5 ## 64-byte Reload
+; CHECK32-SKX-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm5 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x6c,0x24,0x05]
-; CHECK32-SKX-NEXT: vmovups {{[0-9]+}}(%esp), %zmm6 ## 64-byte Reload
+; CHECK32-SKX-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm6 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x74,0x24,0x06]
-; CHECK32-SKX-NEXT: vmovups {{[0-9]+}}(%esp), %zmm7 ## 64-byte Reload
+; CHECK32-SKX-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %zmm7 ## 64-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x7c,0x24,0x07]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k0 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k0 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x84,0x24,0x30,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k1 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k1 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x8c,0x24,0x38,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k2 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k2 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x94,0x24,0x40,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k3 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k3 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0x9c,0x24,0x48,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k4 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k4 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xa4,0x24,0x50,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k5 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k5 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xac,0x24,0x58,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k6 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k6 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xb4,0x24,0x60,0x02,0x00,0x00]
-; CHECK32-SKX-NEXT: kmovq {{[0-9]+}}(%esp), %k7 ## 8-byte Reload
+; CHECK32-SKX-NEXT: kmovq {{[-0-9]+}}(%e{{[sb]}}p), %k7 ## 8-byte Reload
; CHECK32-SKX-NEXT: ## encoding: [0xc4,0xe1,0xf8,0x90,0xbc,0x24,0x68,0x02,0x00,0x00]
; CHECK32-SKX-NEXT: addl $624, %esp ## encoding: [0x81,0xc4,0x70,0x02,0x00,0x00]
; CHECK32-SKX-NEXT: ## imm = 0x270
diff --git a/llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll b/llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
index bfb963bb7540f..8ae190419bedf 100644
--- a/llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
+++ b/llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py for function "bar"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
;; In functions with 'no_caller_saved_registers' attribute, all registers should
@@ -12,13 +12,13 @@ define x86_64_sysvcc i32 @bar(i32 %a0, i32 %a1, float %b0) #0 {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rdx
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: .cfi_offset %rdx, -16
; CHECK-NEXT: .cfi_offset %xmm1, -32
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movl $4, %eax
-; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: popq %rdx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
@@ -27,20 +27,26 @@ define x86_64_sysvcc i32 @bar(i32 %a0, i32 %a1, float %b0) #0 {
}
;; Because "bar" has 'no_caller_saved_registers' attribute, function "foo"
-;; doesn't need to preserve registers except for the arguments passed
+;; doesn't need to preserve registers except for the arguments passed
;; to "bar" (%esi, %edi and %xmm0).
define x86_64_sysvcc float @foo(i32 %a0, i32 %a1, float %b0) {
-; CHECK-LABEL: foo
-; CHECK: movaps %xmm0, %xmm1
-; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: movl %edi, %edx
-; CHECK-NEXT: callq bar
-; CHECK-NEXT: addl %edx, %eax
-; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: xorps %xmm0, %xmm0
-; CHECK-NEXT: cvtsi2ss %eax, %xmm0
-; CHECK-NEXT: addss %xmm0, %xmm1
-; CHECK: retq
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: movl %edi, %edx
+; CHECK-NEXT: callq bar at PLT
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2ss %eax, %xmm0
+; CHECK-NEXT: addss %xmm0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: popq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
%call = call i32 @bar(i32 %a0, i32 %a1, float %b0)
%c0 = add i32 %a0, %call
%c1 = add i32 %c0, %a1
diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
index d91ba93ffb421..2bf3688abe18e 100644
--- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
@@ -1184,10 +1184,10 @@ define i32 @useLEAForPrologue(i32 %d, i32 %a, i8 %c) #3 {
; ENABLE-NEXT: pushq %rbx
; ENABLE-NEXT: subq $16, %rsp
; ENABLE-NEXT: xorl %eax, %eax
-; ENABLE-NEXT: cmpb $0, {{.*}}(%rip)
+; ENABLE-NEXT: cmpb $0, _b(%rip)
; ENABLE-NEXT: movl $48, %ecx
; ENABLE-NEXT: cmovnel %eax, %ecx
-; ENABLE-NEXT: movb %cl, {{.*}}(%rip)
+; ENABLE-NEXT: movb %cl, _c(%rip)
; ENABLE-NEXT: je LBB14_4
; ENABLE-NEXT: ## %bb.1: ## %for.body.lr.ph
; ENABLE-NEXT: ## InlineAsm Start
@@ -1204,7 +1204,7 @@ define i32 @useLEAForPrologue(i32 %d, i32 %a, i8 %c) #3 {
; ENABLE-NEXT: cmpb $45, %dl
; ENABLE-NEXT: jl LBB14_2
; ENABLE-NEXT: ## %bb.3: ## %for.cond.for.end_crit_edge
-; ENABLE-NEXT: movq _a@{{.*}}(%rip), %rax
+; ENABLE-NEXT: movq _a at GOTPCREL(%rip), %rax
; ENABLE-NEXT: movl %esi, (%rax)
; ENABLE-NEXT: LBB14_4: ## %for.end
; ENABLE-NEXT: xorl %edi, %edi
@@ -1219,10 +1219,10 @@ define i32 @useLEAForPrologue(i32 %d, i32 %a, i8 %c) #3 {
; DISABLE-NEXT: pushq %rbx
; DISABLE-NEXT: subq $16, %rsp
; DISABLE-NEXT: xorl %eax, %eax
-; DISABLE-NEXT: cmpb $0, {{.*}}(%rip)
+; DISABLE-NEXT: cmpb $0, _b(%rip)
; DISABLE-NEXT: movl $48, %ecx
; DISABLE-NEXT: cmovnel %eax, %ecx
-; DISABLE-NEXT: movb %cl, {{.*}}(%rip)
+; DISABLE-NEXT: movb %cl, _c(%rip)
; DISABLE-NEXT: je LBB14_4
; DISABLE-NEXT: ## %bb.1: ## %for.body.lr.ph
; DISABLE-NEXT: ## InlineAsm Start
@@ -1239,7 +1239,7 @@ define i32 @useLEAForPrologue(i32 %d, i32 %a, i8 %c) #3 {
; DISABLE-NEXT: cmpb $45, %dl
; DISABLE-NEXT: jl LBB14_2
; DISABLE-NEXT: ## %bb.3: ## %for.cond.for.end_crit_edge
-; DISABLE-NEXT: movq _a@{{.*}}(%rip), %rax
+; DISABLE-NEXT: movq _a at GOTPCREL(%rip), %rax
; DISABLE-NEXT: movl %esi, (%rax)
; DISABLE-NEXT: LBB14_4: ## %for.end
; DISABLE-NEXT: xorl %edi, %edi
@@ -1296,7 +1296,7 @@ define i32 @tlsCall(i1 %bool1, i32 %arg, i32* readonly dereferenceable(4) %sum1)
; ENABLE-NEXT: je LBB15_2
; ENABLE-NEXT: ## %bb.1: ## %master
; ENABLE-NEXT: movl (%rdx), %ecx
-; ENABLE-NEXT: movq _sum1@{{.*}}(%rip), %rdi
+; ENABLE-NEXT: movq _sum1 at TLVP(%rip), %rdi
; ENABLE-NEXT: callq *(%rdi)
; ENABLE-NEXT: movl %ecx, (%rax)
; ENABLE-NEXT: jmp LBB15_3
@@ -1317,7 +1317,7 @@ define i32 @tlsCall(i1 %bool1, i32 %arg, i32* readonly dereferenceable(4) %sum1)
; DISABLE-NEXT: je LBB15_2
; DISABLE-NEXT: ## %bb.1: ## %master
; DISABLE-NEXT: movl (%rdx), %ecx
-; DISABLE-NEXT: movq _sum1@{{.*}}(%rip), %rdi
+; DISABLE-NEXT: movq _sum1 at TLVP(%rip), %rdi
; DISABLE-NEXT: callq *(%rdi)
; DISABLE-NEXT: movl %ecx, (%rax)
; DISABLE-NEXT: jmp LBB15_3
@@ -1377,7 +1377,7 @@ define i32 @irreducibleCFG() #4 {
; ENABLE-NEXT: pushq %rbx
; ENABLE-NEXT: pushq %rax
; ENABLE-NEXT: .cfi_offset %rbx, -24
-; ENABLE-NEXT: movq _irreducibleCFGf@{{.*}}(%rip), %rax
+; ENABLE-NEXT: movq _irreducibleCFGf at GOTPCREL(%rip), %rax
; ENABLE-NEXT: cmpb $0, (%rax)
; ENABLE-NEXT: je LBB16_2
; ENABLE-NEXT: .p2align 4, 0x90
@@ -1385,11 +1385,11 @@ define i32 @irreducibleCFG() #4 {
; ENABLE-NEXT: ## =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: jmp LBB16_1
; ENABLE-NEXT: LBB16_2: ## %split
-; ENABLE-NEXT: movq _irreducibleCFGb@{{.*}}(%rip), %rax
+; ENABLE-NEXT: movq _irreducibleCFGb at GOTPCREL(%rip), %rax
; ENABLE-NEXT: cmpl $0, (%rax)
; ENABLE-NEXT: je LBB16_3
; ENABLE-NEXT: ## %bb.4: ## %for.body4.i
-; ENABLE-NEXT: movq _irreducibleCFGa@{{.*}}(%rip), %rax
+; ENABLE-NEXT: movq _irreducibleCFGa at GOTPCREL(%rip), %rax
; ENABLE-NEXT: movl (%rax), %edi
; ENABLE-NEXT: xorl %ebx, %ebx
; ENABLE-NEXT: xorl %eax, %eax
@@ -1420,7 +1420,7 @@ define i32 @irreducibleCFG() #4 {
; DISABLE-NEXT: pushq %rbx
; DISABLE-NEXT: pushq %rax
; DISABLE-NEXT: .cfi_offset %rbx, -24
-; DISABLE-NEXT: movq _irreducibleCFGf@{{.*}}(%rip), %rax
+; DISABLE-NEXT: movq _irreducibleCFGf at GOTPCREL(%rip), %rax
; DISABLE-NEXT: cmpb $0, (%rax)
; DISABLE-NEXT: je LBB16_2
; DISABLE-NEXT: .p2align 4, 0x90
@@ -1428,11 +1428,11 @@ define i32 @irreducibleCFG() #4 {
; DISABLE-NEXT: ## =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: jmp LBB16_1
; DISABLE-NEXT: LBB16_2: ## %split
-; DISABLE-NEXT: movq _irreducibleCFGb@{{.*}}(%rip), %rax
+; DISABLE-NEXT: movq _irreducibleCFGb at GOTPCREL(%rip), %rax
; DISABLE-NEXT: cmpl $0, (%rax)
; DISABLE-NEXT: je LBB16_3
; DISABLE-NEXT: ## %bb.4: ## %for.body4.i
-; DISABLE-NEXT: movq _irreducibleCFGa@{{.*}}(%rip), %rax
+; DISABLE-NEXT: movq _irreducibleCFGa at GOTPCREL(%rip), %rax
; DISABLE-NEXT: movl (%rax), %edi
; DISABLE-NEXT: xorl %ebx, %ebx
; DISABLE-NEXT: xorl %eax, %eax
@@ -1503,7 +1503,7 @@ define void @infiniteLoopNoSuccessor() #5 {
; ENABLE: ## %bb.0:
; ENABLE-NEXT: pushq %rbp
; ENABLE-NEXT: movq %rsp, %rbp
-; ENABLE-NEXT: movq _x@{{.*}}(%rip), %rax
+; ENABLE-NEXT: movq _x at GOTPCREL(%rip), %rax
; ENABLE-NEXT: cmpl $0, (%rax)
; ENABLE-NEXT: je LBB17_2
; ENABLE-NEXT: ## %bb.1:
@@ -1511,7 +1511,7 @@ define void @infiniteLoopNoSuccessor() #5 {
; ENABLE-NEXT: LBB17_2:
; ENABLE-NEXT: xorl %eax, %eax
; ENABLE-NEXT: callq _somethingElse
-; ENABLE-NEXT: movq _y@{{.*}}(%rip), %rax
+; ENABLE-NEXT: movq _y at GOTPCREL(%rip), %rax
; ENABLE-NEXT: cmpl $0, (%rax)
; ENABLE-NEXT: je LBB17_3
; ENABLE-NEXT: ## %bb.5:
@@ -1530,7 +1530,7 @@ define void @infiniteLoopNoSuccessor() #5 {
; DISABLE: ## %bb.0:
; DISABLE-NEXT: pushq %rbp
; DISABLE-NEXT: movq %rsp, %rbp
-; DISABLE-NEXT: movq _x@{{.*}}(%rip), %rax
+; DISABLE-NEXT: movq _x at GOTPCREL(%rip), %rax
; DISABLE-NEXT: cmpl $0, (%rax)
; DISABLE-NEXT: je LBB17_2
; DISABLE-NEXT: ## %bb.1:
@@ -1538,7 +1538,7 @@ define void @infiniteLoopNoSuccessor() #5 {
; DISABLE-NEXT: LBB17_2:
; DISABLE-NEXT: xorl %eax, %eax
; DISABLE-NEXT: callq _somethingElse
-; DISABLE-NEXT: movq _y@{{.*}}(%rip), %rax
+; DISABLE-NEXT: movq _y at GOTPCREL(%rip), %rax
; DISABLE-NEXT: cmpl $0, (%rax)
; DISABLE-NEXT: je LBB17_3
; DISABLE-NEXT: ## %bb.5:
diff --git a/llvm/test/CodeGen/X86/x86-store-gv-addr.ll b/llvm/test/CodeGen/X86/x86-store-gv-addr.ll
index e8823bd7efbb1..9fdebe293f7ea 100644
--- a/llvm/test/CodeGen/X86/x86-store-gv-addr.ll
+++ b/llvm/test/CodeGen/X86/x86-store-gv-addr.ll
@@ -8,15 +8,15 @@
define void @t() nounwind optsize {
; x86_64-darwin-LABEL: t:
; x86_64-darwin: ## %bb.0:
-; x86_64-darwin-NEXT: movq _v@{{.*}}(%rip), %rax
-; x86_64-darwin-NEXT: movq _v_addr@{{.*}}(%rip), %rcx
+; x86_64-darwin-NEXT: movq _v at GOTPCREL(%rip), %rax
+; x86_64-darwin-NEXT: movq _v_addr at GOTPCREL(%rip), %rcx
; x86_64-darwin-NEXT: movq %rax, (%rcx)
; x86_64-darwin-NEXT: ud2
;
; x86_64-linux-LABEL: t:
; x86_64-linux: # %bb.0:
-; x86_64-linux-NEXT: movq v@{{.*}}(%rip), %rax
-; x86_64-linux-NEXT: movq v_addr@{{.*}}(%rip), %rcx
+; x86_64-linux-NEXT: movq v at GOTPCREL(%rip), %rax
+; x86_64-linux-NEXT: movq v_addr at GOTPCREL(%rip), %rcx
; x86_64-linux-NEXT: movq %rax, (%rcx)
store i32* @v, i32** @v_addr, align 8
unreachable
diff --git a/llvm/test/CodeGen/X86/xchg-nofold.ll b/llvm/test/CodeGen/X86/xchg-nofold.ll
index c6f37090e5899..f2fd3ad702080 100644
--- a/llvm/test/CodeGen/X86/xchg-nofold.ll
+++ b/llvm/test/CodeGen/X86/xchg-nofold.ll
@@ -28,7 +28,7 @@ define zeroext i1 @_Z3fooRSt6atomicIbEb(%"struct.std::atomic"* nocapture derefer
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_2:
-; CHECK-NEXT: callq __asan_report_store1
+; CHECK-NEXT: callq __asan_report_store1 at PLT
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
entry:
diff --git a/llvm/test/CodeGen/X86/xop-mask-comments.ll b/llvm/test/CodeGen/X86/xop-mask-comments.ll
index 418a6479810d0..92577e8ba8cd8 100644
--- a/llvm/test/CodeGen/X86/xop-mask-comments.ll
+++ b/llvm/test/CodeGen/X86/xop-mask-comments.ll
@@ -55,12 +55,12 @@ define <16 x i8> @vpperm_shuffle_binary_zero(<16 x i8> %a0, <16 x i8> %a1) {
define <16 x i8> @vpperm_shuffle_general(<16 x i8> %a0, <16 x i8> %a1) {
; X86-LABEL: vpperm_shuffle_general:
; X86: # %bb.0:
-; X86-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
+; X86-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vpperm_shuffle_general:
; X64: # %bb.0:
-; X64-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
+; X64-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; X64-NEXT: retq
%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 14, i8 29, i8 12, i8 27, i8 10, i8 25, i8 8, i8 23, i8 6, i8 21, i8 4, i8 179, i8 162, i8 177, i8 160>)
ret <16 x i8> %1
diff --git a/llvm/test/CodeGen/X86/zext-fold.ll b/llvm/test/CodeGen/X86/zext-fold.ll
index fcf6959e4bac6..ad1ce14ad8435 100644
--- a/llvm/test/CodeGen/X86/zext-fold.ll
+++ b/llvm/test/CodeGen/X86/zext-fold.ll
@@ -43,7 +43,7 @@ define void @test3(i8 %x) nounwind readnone {
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: andl $-32, %eax
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: calll use
+; CHECK-NEXT: calll use at PLT
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: retl
%A = and i8 %x, -32
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