[PATCH] D103939: [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

The change looks good to me, just have an open question about the test.

@huihuiz Thanks for working on this by the way, this has been on our wish-list for quite a while! :)



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Comment at: llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll:11
+; Check that 2 is extracted as interesting factor for "(16*vscale) / (8*vscale)".
+; LSR-DEBUG: LSR has identified the following interesting factors and types: *2
+
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nit:  I'm not really sure what the convention is here, but I wonder if it's better to just have two RUN lines, where the former checks the full output of the IR itself (more than just the IR-NOT, and instead of checking the debug output of the pass), and one that checks the full output of the asm (or at least more than just the load/store). The reason I'm suggesting checking more of the IR/asm is to check that there are no redundant instructions for other purposes. I'm also not sure if testing debug-output is normally desirable, but if we just check the output, we can remove the `REQUIRES:  asserts` line.


Repository:
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  https://reviews.llvm.org/D103939/new/

https://reviews.llvm.org/D103939