[PATCH] D103602: [regalloc] Don't align stack slots if the stack can't be realigned

[Tomas Matheson via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG773771ba382b: [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned (authored by tmatheson).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103602/new/

https://reviews.llvm.org/D103602

Files:
  llvm/lib/CodeGen/VirtRegMap.cpp
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
  llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
  llvm/test/CodeGen/Thumb2/mve-phireg.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
  llvm/test/CodeGen/Thumb2/mve-vld4.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/X86/AMX/amx-across-func.ll
  llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
  llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
  llvm/test/CodeGen/X86/AMX/amx-spill.ll
  llvm/test/CodeGen/X86/addsub-constant-folding.ll
  llvm/test/CodeGen/X86/avx-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/avx-vzeroupper.ll
  llvm/test/CodeGen/X86/avx512-bugfix-25270.ll
  llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/X86/fma.ll
  llvm/test/CodeGen/X86/half.ll
  llvm/test/CodeGen/X86/rotate-extract-vector.ll
  llvm/test/CodeGen/X86/sext-vsetcc.ll
  llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll
  llvm/test/CodeGen/X86/stack-folding-int-avx512.ll
  llvm/test/CodeGen/X86/vec-libcalls.ll
  llvm/test/CodeGen/X86/vec-strict-128.ll
  llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/X86/vector-half-conversions.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
  llvm/test/CodeGen/X86/vzero-excess.ll

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