[PATCH] D104094: Add missing AArch64 data synchronization barrier (dsb) to __clear_cache

[Stephen Hines via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6455418d3d2a: [compiler-rt] [builtins] [AArch64] Add missing AArch64 data synchronization… (authored by srhines).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104094/new/

https://reviews.llvm.org/D104094

Files:
  compiler-rt/lib/builtins/clear_cache.c


Index: compiler-rt/lib/builtins/clear_cache.c
===================================================================
--- compiler-rt/lib/builtins/clear_cache.c
+++ compiler-rt/lib/builtins/clear_cache.c
@@ -126,6 +126,7 @@
          addr += icache_line_size)
       __asm __volatile("ic ivau, %0" ::"r"(addr));
   }
+  __asm __volatile("dsb ish");
   __asm __volatile("isb sy");
 #elif defined(__powerpc64__)
   const size_t line_size = 32;


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