[llvm] cfbb924 - [SDAG] Fix pow2 assumption when splitting vectors
Carl Ritson via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 10 16:59:01 PDT 2021
Author: Carl Ritson
Date: 2021-06-11T08:58:16+09:00
New Revision: cfbb92441f17d1f5a9d9c3e195646df4117cb0ca
URL: https://github.com/llvm/llvm-project/commit/cfbb92441f17d1f5a9d9c3e195646df4117cb0ca
DIFF: https://github.com/llvm/llvm-project/commit/cfbb92441f17d1f5a9d9c3e195646df4117cb0ca.diff
LOG: [SDAG] Fix pow2 assumption when splitting vectors
When reducing vector builds to shuffles it possible that
the DAG combiner may try to extract invalid subvectors.
This happens as the existing code assumes vectors will be power
of 2 sizes, which is already untrue, but becomes more noticable
with v6 and v7 types.
Specifically the existing code assumes that half PowerOf2Ceil of
a given vector index will fit twice into a given vector.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D103880
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f6f0549b1462c..b470a21b9ec24 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19370,7 +19370,9 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) {
unsigned SplitSize = NearestPow2 / 2;
EVT SplitVT = EVT::getVectorVT(*DAG.getContext(),
InVT.getVectorElementType(), SplitSize);
- if (TLI.isTypeLegal(SplitVT)) {
+ if (TLI.isTypeLegal(SplitVT) &&
+ SplitSize + SplitVT.getVectorNumElements() <=
+ InVT.getVectorNumElements()) {
SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec,
DAG.getVectorIdxConstant(SplitSize, DL));
SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec,
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