[PATCH] D103939: [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:737
+      // Handle special case C1*X*Y /s C2*X*Y.
+      if (const SCEVMulExpr *MulRHS = dyn_cast<SCEVMulExpr>(RHS)) {
+        const SCEVConstant *LC = dyn_cast<SCEVConstant>(Mul->getOperand(0));
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Does the MulRHS also need checks for `IgnoreSignificantBits || isMulSExtable(MulRHS, SE)` ?


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  https://reviews.llvm.org/D103939/new/

https://reviews.llvm.org/D103939