[PATCH] D104006: [PowerPC] Relax register superclasses for paired memops

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: jsji, nemanjai, shchenz, PowerPC.
Herald added subscribers: kbarton, hiraditya, qcolombet.
qiucf requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Relaxing superclass constraint for VSX register classes helps reducing 32-byte spills and copies when register pressure is high.

In test case affected, some of them introduces more copies due to new allocation order. However, this patch should not be the root cause, and we may be able to fix it in other places of register allocation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104006

Files:
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
  llvm/test/CodeGen/PowerPC/constant-pool.ll
  llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/remove-redundant-moves.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vsx.ll

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