[PATCH] D103622: [RISCV] Avoid scalar outgoing arguments overwrite vector frame objects.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll:88
-; CHECK-NEXT:    addi a0, a0, -128
+; CHECK-NEXT:    addi a0, a0, -112
 ; CHECK-NEXT:    vs8r.v v8, (a0)
 ; CHECK-NEXT:    addi a0, zero, 1
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frasercrmck wrote:
> Just so I understand, this is presumably the bug here, right? We're storing a vector register to `a0` which is `s0 - (vlenb<<3) - 128` which is (in a roundabout way) `sp`? And we store the arguments to the same spots `0(sp)` and `8(sp)` on lines 116 and 115?
Yeah, that is the problem. Out going arguments overwrite the vector value here. When users call the function, `lots_args`, second time, the vector value will be loaded from stack under `-O0`. Users will get the wrong value in the second call.


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  https://reviews.llvm.org/D103622/new/

https://reviews.llvm.org/D103622