[PATCH] D103955: [MCA] Use LSU for the in-order pipeline

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic added inline comments.


================
Comment at: llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-noalias.s:97-98
+# CHECK-NEXT: [0,1]     .DeeeE    ..   str	x1, [x10]
+# CHECK-NEXT: [0,2]     .DeeE.    ..   ldr	x2, [x10]
+# CHECK-NEXT: [0,3]     . DE .    ..   nop
+# CHECK-NEXT: [0,4]     .  DeeE   ..   ldr	x2, [x10]
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andreadb wrote:
> This doesn't look correct.
> Any idea why these instructions are executed out of order?
> Edit: I think it might be due to the LSU check you have added (see my other comment).
> 
This is because the store instruction has no writes (Instruction::getDefs returns an empty list), so findLastWriteBackCycle returns 0.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D103955/new/

https://reviews.llvm.org/D103955