[PATCH] D103955: [MCA] Use LSU for the in-order pipeline

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
asavonic added reviewers: andreadb, dmgreen, foad.
Herald added subscribers: gbedwell, hiraditya.
asavonic requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Load/Store unit is used to enforce order of loads and stores if they
alias (controlled by --noalias=false option).

This model is not very accurate though - Cortex-A55 hardware still 
shows quite different results in comparison with MCA.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103955

Files:
  llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
  llvm/lib/MCA/Context.cpp
  llvm/lib/MCA/Stages/InOrderIssueStage.cpp
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-noalias.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D103955.350855.patch
Type: text/x-patch
Size: 16868 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210609/8359f5b0/attachment.bin>