[llvm] f44770c - [ARM] A couple of extra VMOVimm tests, useful for showing BE codegen. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 8 11:39:55 PDT 2021
Author: David Green
Date: 2021-06-08T19:39:45+01:00
New Revision: f44770c32992d51586d11c352f9e825f6aa15fc2
URL: https://github.com/llvm/llvm-project/commit/f44770c32992d51586d11c352f9e825f6aa15fc2
DIFF: https://github.com/llvm/llvm-project/commit/f44770c32992d51586d11c352f9e825f6aa15fc2.diff
LOG: [ARM] A couple of extra VMOVimm tests, useful for showing BE codegen. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
index 74e7aa023d9d..4226dab4adb6 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
@@ -21,6 +21,37 @@ entry:
ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
}
+define arm_aapcs_vfpcc <16 x i8> @mov_int8_1234() {
+; CHECKLE-LABEL: mov_int8_1234:
+; CHECKLE: @ %bb.0: @ %entry
+; CHECKLE-NEXT: adr r0, .LCPI2_0
+; CHECKLE-NEXT: vldrw.u32 q0, [r0]
+; CHECKLE-NEXT: bx lr
+; CHECKLE-NEXT: .p2align 4
+; CHECKLE-NEXT: @ %bb.1:
+; CHECKLE-NEXT: .LCPI2_0:
+; CHECKLE-NEXT: .long 67305985 @ double 2.4380727978175888E-289
+; CHECKLE-NEXT: .long 67305985
+; CHECKLE-NEXT: .long 67305985 @ double 2.4380727978175888E-289
+; CHECKLE-NEXT: .long 67305985
+;
+; CHECKBE-LABEL: mov_int8_1234:
+; CHECKBE: @ %bb.0: @ %entry
+; CHECKBE-NEXT: adr r0, .LCPI2_0
+; CHECKBE-NEXT: vldrb.u8 q1, [r0]
+; CHECKBE-NEXT: vrev64.8 q0, q1
+; CHECKBE-NEXT: bx lr
+; CHECKBE-NEXT: .p2align 4
+; CHECKBE-NEXT: @ %bb.1:
+; CHECKBE-NEXT: .LCPI2_0:
+; CHECKBE-NEXT: .long 16909060 @ double 8.2078802900595913E-304
+; CHECKBE-NEXT: .long 16909060
+; CHECKBE-NEXT: .long 16909060 @ double 8.2078802900595913E-304
+; CHECKBE-NEXT: .long 16909060
+entry:
+ ret <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
+}
+
define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() {
; CHECK-LABEL: mov_int16_1:
; CHECK: @ %bb.0: @ %entry
@@ -60,12 +91,12 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {
; CHECKLE-LABEL: mov_int16_258:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI6_0
+; CHECKLE-NEXT: adr r0, .LCPI7_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI6_0:
+; CHECKLE-NEXT: .LCPI7_0:
; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
; CHECKLE-NEXT: .long 16908546
; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
@@ -73,13 +104,13 @@ define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {
;
; CHECKBE-LABEL: mov_int16_258:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI6_0
+; CHECKBE-NEXT: adr r0, .LCPI7_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI6_0:
+; CHECKBE-NEXT: .LCPI7_0:
; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
; CHECKBE-NEXT: .long 16908546
; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
@@ -127,12 +158,12 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {
; CHECKLE-LABEL: mov_int32_16777217:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI11_0
+; CHECKLE-NEXT: adr r0, .LCPI12_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI11_0:
+; CHECKLE-NEXT: .LCPI12_0:
; CHECKLE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
; CHECKLE-NEXT: .long 16777217
; CHECKLE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
@@ -140,13 +171,13 @@ define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {
;
; CHECKBE-LABEL: mov_int32_16777217:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI11_0
+; CHECKBE-NEXT: adr r0, .LCPI12_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI11_0:
+; CHECKBE-NEXT: .LCPI12_0:
; CHECKBE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
; CHECKBE-NEXT: .long 16777217
; CHECKBE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
@@ -194,12 +225,12 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {
; CHECKLE-LABEL: mov_int32_4278190335:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI16_0
+; CHECKLE-NEXT: adr r0, .LCPI17_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI16_0:
+; CHECKLE-NEXT: .LCPI17_0:
; CHECKLE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
; CHECKLE-NEXT: .long 4278190335
; CHECKLE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
@@ -207,13 +238,13 @@ define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {
;
; CHECKBE-LABEL: mov_int32_4278190335:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI16_0
+; CHECKBE-NEXT: adr r0, .LCPI17_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI16_0:
+; CHECKBE-NEXT: .LCPI17_0:
; CHECKBE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
; CHECKBE-NEXT: .long 4278190335
; CHECKBE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
@@ -231,15 +262,46 @@ entry:
ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
}
+define arm_aapcs_vfpcc <4 x i32> @mov_int32_16908546() {
+; CHECKLE-LABEL: mov_int32_16908546:
+; CHECKLE: @ %bb.0: @ %entry
+; CHECKLE-NEXT: adr r0, .LCPI19_0
+; CHECKLE-NEXT: vldrw.u32 q0, [r0]
+; CHECKLE-NEXT: bx lr
+; CHECKLE-NEXT: .p2align 4
+; CHECKLE-NEXT: @ %bb.1:
+; CHECKLE-NEXT: .LCPI19_0:
+; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
+; CHECKLE-NEXT: .long 16908546
+; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
+; CHECKLE-NEXT: .long 16908546
+;
+; CHECKBE-LABEL: mov_int32_16908546:
+; CHECKBE: @ %bb.0: @ %entry
+; CHECKBE-NEXT: adr r0, .LCPI19_0
+; CHECKBE-NEXT: vldrb.u8 q1, [r0]
+; CHECKBE-NEXT: vrev64.8 q0, q1
+; CHECKBE-NEXT: bx lr
+; CHECKBE-NEXT: .p2align 4
+; CHECKBE-NEXT: @ %bb.1:
+; CHECKBE-NEXT: .LCPI19_0:
+; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
+; CHECKBE-NEXT: .long 16908546
+; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
+; CHECKBE-NEXT: .long 16908546
+entry:
+ ret <4 x i32> <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
+}
+
define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
; CHECKLE-LABEL: mov_int64_1:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI18_0
+; CHECKLE-NEXT: adr r0, .LCPI20_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI18_0:
+; CHECKLE-NEXT: .LCPI20_0:
; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324
; CHECKLE-NEXT: .long 0
; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324
@@ -247,13 +309,13 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
;
; CHECKBE-LABEL: mov_int64_1:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI18_0
+; CHECKBE-NEXT: adr r0, .LCPI20_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI18_0:
+; CHECKBE-NEXT: .LCPI20_0:
; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324
; CHECKBE-NEXT: .long 1
; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324
@@ -292,12 +354,12 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
; CHECKLE-LABEL: mov_int64_f_0:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI22_0
+; CHECKLE-NEXT: adr r0, .LCPI24_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI22_0:
+; CHECKLE-NEXT: .LCPI24_0:
; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321
; CHECKLE-NEXT: .long 0
; CHECKLE-NEXT: .long 0 @ double 0
@@ -305,13 +367,13 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
;
; CHECKBE-LABEL: mov_int64_f_0:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI22_0
+; CHECKBE-NEXT: adr r0, .LCPI24_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI22_0:
+; CHECKBE-NEXT: .LCPI24_0:
; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321
; CHECKBE-NEXT: .long 255
; CHECKBE-NEXT: .long 0 @ double 0
@@ -365,12 +427,12 @@ entry:
define arm_aapcs_vfpcc <4 x float> @mov_float_1() {
; CHECKLE-LABEL: mov_float_1:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI26_0
+; CHECKLE-NEXT: adr r0, .LCPI28_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI26_0:
+; CHECKLE-NEXT: .LCPI28_0:
; CHECKLE-NEXT: .long 1065353216 @ double 0.007812501848093234
; CHECKLE-NEXT: .long 1065353216
; CHECKLE-NEXT: .long 1065353216 @ double 0.007812501848093234
@@ -378,13 +440,13 @@ define arm_aapcs_vfpcc <4 x float> @mov_float_1() {
;
; CHECKBE-LABEL: mov_float_1:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI26_0
+; CHECKBE-NEXT: adr r0, .LCPI28_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI26_0:
+; CHECKBE-NEXT: .LCPI28_0:
; CHECKBE-NEXT: .long 1065353216 @ double 0.007812501848093234
; CHECKBE-NEXT: .long 1065353216
; CHECKBE-NEXT: .long 1065353216 @ double 0.007812501848093234
@@ -396,12 +458,12 @@ entry:
define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {
; CHECKLE-LABEL: mov_float_m3:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI27_0
+; CHECKLE-NEXT: adr r0, .LCPI29_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI27_0:
+; CHECKLE-NEXT: .LCPI29_0:
; CHECKLE-NEXT: .long 3225419776 @ double -32.000022917985916
; CHECKLE-NEXT: .long 3225419776
; CHECKLE-NEXT: .long 3225419776 @ double -32.000022917985916
@@ -409,13 +471,13 @@ define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {
;
; CHECKBE-LABEL: mov_float_m3:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI27_0
+; CHECKBE-NEXT: adr r0, .LCPI29_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI27_0:
+; CHECKBE-NEXT: .LCPI29_0:
; CHECKBE-NEXT: .long 3225419776 @ double -32.000022917985916
; CHECKBE-NEXT: .long 3225419776
; CHECKBE-NEXT: .long 3225419776 @ double -32.000022917985916
@@ -447,12 +509,12 @@ entry:
define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
; CHECKLE-LABEL: mov_double_1:
; CHECKLE: @ %bb.0: @ %entry
-; CHECKLE-NEXT: adr r0, .LCPI30_0
+; CHECKLE-NEXT: adr r0, .LCPI32_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
-; CHECKLE-NEXT: .LCPI30_0:
+; CHECKLE-NEXT: .LCPI32_0:
; CHECKLE-NEXT: .long 0 @ double 1
; CHECKLE-NEXT: .long 1072693248
; CHECKLE-NEXT: .long 0 @ double 1
@@ -460,13 +522,13 @@ define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
;
; CHECKBE-LABEL: mov_double_1:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: adr r0, .LCPI30_0
+; CHECKBE-NEXT: adr r0, .LCPI32_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
-; CHECKBE-NEXT: .LCPI30_0:
+; CHECKBE-NEXT: .LCPI32_0:
; CHECKBE-NEXT: .long 1072693248 @ double 1
; CHECKBE-NEXT: .long 0
; CHECKBE-NEXT: .long 1072693248 @ double 1
More information about the llvm-commits
mailing list