[PATCH] D103736: [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc57bce9cc5fa: [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103736/new/

https://reviews.llvm.org/D103736

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll