[PATCH] D103881: [ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D103881#2805122 <https://reviews.llvm.org/D103881#2805122>, @frasercrmck wrote:

> Awfully brave to add new non-pow2 types; I like it. Unfortunate that we've both filed patches to this same file at the same time (D103884 <https://reviews.llvm.org/D103884>). One of us will have a fun time.

Technically there's precedent with MVT::v3i32 but where does this end? What happens when someone next asks for v8f32 -> v15f32? How tricky would it be for a custom AMDGPU DAG node to encode the vector width instead and it just uses the next pow2 type?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103881/new/

https://reviews.llvm.org/D103881