[llvm] 1465e77 - [VPlan] Print successors of VPRegionBlocks.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 7 09:59:05 PDT 2021
Author: Florian Hahn
Date: 2021-06-07T17:57:21+01:00
New Revision: 1465e7770bcacfb67ca4edc3714cf3a7e8a2a110
URL: https://github.com/llvm/llvm-project/commit/1465e7770bcacfb67ca4edc3714cf3a7e8a2a110
DIFF: https://github.com/llvm/llvm-project/commit/1465e7770bcacfb67ca4edc3714cf3a7e8a2a110.diff
LOG: [VPlan] Print successors of VPRegionBlocks.
The non-DOT printing does not include the successors of VPregionBlocks.
This patch use the same style for printing successors as for
VPBasicBlock.
I think the printing of successors could be a bit improved further, as
at the moment it is hard to ensure a check line matches all successors.
But that can be done as follow-up.
Reviewed By: a.elovikov
Differential Revision: https://reviews.llvm.org/D103515
Added:
Modified:
llvm/lib/Transforms/Vectorize/VPlan.cpp
llvm/lib/Transforms/Vectorize/VPlan.h
llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
llvm/test/Transforms/LoopVectorize/vplan-printing.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 5c7c01e2f0fae..636b70272e446 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -397,6 +397,18 @@ VPBasicBlock *VPBasicBlock::splitAt(iterator SplitAt) {
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+void VPBlockBase::printSuccessors(raw_ostream &O, const Twine &Indent) const {
+ if (getSuccessors().empty()) {
+ O << Indent << "No successors\n";
+ } else {
+ O << Indent << "Successor(s): ";
+ ListSeparator LS;
+ for (auto *Succ : getSuccessors())
+ O << LS << Succ->getName();
+ O << '\n';
+ }
+}
+
void VPBasicBlock::print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const {
O << Indent << getName() << ":\n";
@@ -414,15 +426,7 @@ void VPBasicBlock::print(raw_ostream &O, const Twine &Indent,
O << '\n';
}
- if (getSuccessors().empty()) {
- O << Indent << "No successors\n";
- } else {
- O << Indent << "Successor(s): ";
- ListSeparator LS;
- for (auto *Succ : getSuccessors())
- O << LS << Succ->getName();
- O << '\n';
- }
+ printSuccessors(O, Indent);
if (const VPValue *CBV = getCondBit()) {
O << Indent << "CondBit: ";
@@ -500,6 +504,8 @@ void VPRegionBlock::print(raw_ostream &O, const Twine &Indent,
BlockBase->print(O, NewIndent, SlotTracker);
}
O << Indent << "}\n";
+
+ printSuccessors(O, Indent);
}
#endif
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index 0a308772f3df6..a9fd99ff2a6a9 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -640,6 +640,10 @@ class VPBlockBase {
print(O, "", SlotTracker);
}
+ /// Print the successors of this block to \p O, prefixing all lines with \p
+ /// Indent.
+ void printSuccessors(raw_ostream &O, const Twine &Indent) const;
+
/// Dump this VPBlockBase to dbgs().
LLVM_DUMP_METHOD void dump() const { print(dbgs()); }
#endif
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
index 74562e5c97805..c07b998d78abb 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
@@ -14,46 +14,48 @@ define void @sink_replicate_region_1(i32 %x, i8* %ptr) optsize {
; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next
; CHECK-NEXT: EMIT vp<%3> = icmp ule ir<%iv> vp<%0>
; CHECK-NEXT: Successor(s): loop.0
-
-; CHECK: loop.0:
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.0:
; CHECK-NEXT: Successor(s): pred.load
-
-; CHECK: <xVFxUF> pred.load: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.load: {
; CHECK-NEXT: pred.load.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%3>
; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue
; CHECK-NEXT: CondBit: vp<%3> (loop)
-
-; CHECK: pred.load.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.load.if:
; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V)
; CHECK-NEXT: Successor(s): pred.load.continue
-
-; CHECK: pred.load.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.load.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%6> = ir<%lv>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.1:
+; CHECK-NEXT: Successor(s): loop.1
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.1:
; CHECK-NEXT: WIDEN ir<%conv> = sext vp<%6>
; CHECK-NEXT: Successor(s): pred.srem
-
-; CHECK: <xVFxUF> pred.srem: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.srem: {
; CHECK-NEXT: pred.srem.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%3>
; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue
; CHECK-NEXT: CondBit: vp<%3> (loop)
-
-; CHECK: pred.srem.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.if:
; CHECK-NEXT: REPLICATE ir<%rem> = srem ir<%0>, ir<%x> (S->V)
; CHECK-NEXT: Successor(s): pred.srem.continue
-
-; CHECK: pred.srem.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%9> = ir<%rem>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.1.split:
+; CHECK-NEXT: Successor(s): loop.1.split
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.1.split:
; CHECK-NEXT: WIDEN ir<%add> = add ir<%conv>, vp<%9>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
@@ -85,46 +87,48 @@ define void @sink_replicate_region_2(i32 %x, i8 %y, i32* %ptr) optsize {
; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next
; CHECK-NEXT: EMIT vp<%3> = icmp ule ir<%iv> vp<%0>
; CHECK-NEXT: Successor(s): loop.0
-
-; CHECK: loop.0:
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.0:
; CHECK-NEXT: WIDEN ir<%recur.next> = sext ir<%y>
; CHECK-NEXT: Successor(s): pred.srem
-
-; CHECK: <xVFxUF> pred.srem: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.srem: {
; CHECK-NEXT: pred.srem.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%3>
; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue
; CHECK-NEXT: CondBit: vp<%3> (loop)
-
-; CHECK: pred.srem.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.if:
; CHECK-NEXT: REPLICATE ir<%rem> = srem ir<%recur>, ir<%x>
; CHECK-NEXT: Successor(s): pred.srem.continue
-
-; CHECK: pred.srem.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%6> = ir<%rem>
-; CHECK-NEXT: No successors
+; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.0.split:
+; CHECK-NEXT: Successor(s): loop.0.split
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.0.split:
; CHECK-NEXT: Successor(s): pred.store
-
-; CHECK: <xVFxUF> pred.store: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.store: {
; CHECK-NEXT: pred.store.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%3>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
; CHECK-NEXT: CondBit: vp<%3> (loop)
-
-; CHECK: pred.store.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.store.if:
; CHECK-NEXT: REPLICATE ir<%add> = add vp<%6>, ir<%recur.next>
; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep>
; CHECK-NEXT: Successor(s): pred.store.continue
-
-; CHECK: pred.store.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.store.continue:
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.1:
+; CHECK-NEXT: Successor(s): loop.1
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.1:
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
@@ -156,27 +160,28 @@ define i32 @sink_replicate_region_3_reduction(i32 %x, i8 %y, i32* %ptr) optsize
; CHECK-NEXT: WIDEN-PHI ir<%and.red> = phi ir<1234>, ir<%and.red.next>
; CHECK-NEXT: EMIT vp<%4> = icmp ule ir<%iv> vp<%0>
; CHECK-NEXT: Successor(s): loop.0
-
-; CHECK: loop.0:
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.0:
; CHECK-NEXT: WIDEN ir<%recur.next> = sext ir<%y>
; CHECK-NEXT: Successor(s): pred.srem
-
-; CHECK: <xVFxUF> pred.srem: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.srem: {
; CHECK-NEXT: pred.srem.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%4>
; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue
; CHECK-NEXT: CondBit: vp<%4> (loop)
-
-; CHECK: pred.srem.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.if:
; CHECK-NEXT: REPLICATE ir<%rem> = srem ir<%recur>, ir<%x> (S->V)
; CHECK-NEXT: Successor(s): pred.srem.continue
-
-; CHECK: pred.srem.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%7> = ir<%rem>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.0.split:
+; CHECK-NEXT: Successor(s): loop.0.split
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.0.split:
; CHECK-NEXT: WIDEN ir<%add> = add vp<%7>, ir<%recur.next>
; CHECK-NEXT: WIDEN ir<%and.red.next> = and ir<%and.red>, ir<%add>
; CHECK-NEXT: EMIT vp<%10> = select vp<%4> ir<%and.red.next> ir<%and.red>
@@ -207,70 +212,73 @@ exit:
; containing %conv at the end, because %conv is the last recipe in the block.
define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, i8* %ptr) optsize {
; CHECK-LABEL: sink_replicate_region_4_requires_split_at_end_of_block
-; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
+; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
; CHECK-NEXT: loop:
; CHECK-NEXT: WIDEN-PHI %0 = phi 0, %conv
; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next
; CHECK-NEXT: EMIT vp<%3> = icmp ule ir<%iv> vp<%0>
; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
; CHECK-NEXT: Successor(s): loop.0
-
-; CHECK: loop.0:
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.0:
; CHECK-NEXT: Successor(s): pred.load
-
-; CHECK: <xVFxUF> pred.load: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.load: {
; CHECK-NEXT: pred.load.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%3>
; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue
; CHECK-NEXT: CondBit: vp<%3> (loop)
-
-; CHECK: pred.load.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.load.if:
; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V)
; CHECK-NEXT: Successor(s): pred.load.continue
-
-; CHECK: pred.load.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.load.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%6> = ir<%lv>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.1:
+; CHECK-NEXT: Successor(s): loop.1
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.1:
; CHECK-NEXT: WIDEN ir<%conv> = sext vp<%6>
; CHECK-NEXT: Successor(s): pred.srem
-
-; CHECK: <xVFxUF> pred.srem: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.srem: {
; CHECK-NEXT: pred.srem.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%3>
; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue
; CHECK-NEXT: CondBit: vp<%3> (loop)
-
-; CHECK: pred.srem.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.if:
; CHECK-NEXT: REPLICATE ir<%rem> = srem ir<%0>, ir<%x> (S->V)
; CHECK-NEXT: Successor(s): pred.srem.continue
-
-; CHECK: pred.srem.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.srem.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%9> = ir<%rem>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.1.split:
+; CHECK-NEXT: Successor(s): loop.1.split
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.1.split:
; CHECK-NEXT: Successor(s): pred.load
-
-; CHECK: <xVFxUF> pred.load: {
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.load: {
; CHECK-NEXT: pred.load.entry:
; CHECK-NEXT: BRANCH-ON-MASK vp<%3>
; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue
; CHECK-NEXT: CondBit: vp<%3> (loop)
-
-; CHECK: pred.load.if:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.load.if:
; CHECK-NEXT: REPLICATE ir<%lv.2> = load ir<%gep> (S->V)
; CHECK-NEXT: Successor(s): pred.load.continue
-
-; CHECK: pred.load.continue:
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.load.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%11> = ir<%lv.2>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-
-; CHECK: loop.2:
+; CHECK-NEXT: Successor(s): loop.2
+; CHECK-EMPTY:
+; CHECK-NEXT: loop.2:
; CHECK-NEXT: WIDEN ir<%add.1> = add ir<%conv>, vp<%9>
; CHECK-NEXT: WIDEN ir<%conv.lv.2> = sext vp<%11>
; CHECK-NEXT: WIDEN ir<%add> = add ir<%add.1>, ir<%conv.lv.2>
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
index 7a93d308d27ce..e4ce021b5f3b7 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
@@ -128,6 +128,7 @@ define void @print_replicate_predicated_phi(i64 %n, i64* %x) {
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%3> = ir<%tmp4>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): if.then.0
; CHECK-EMPTY:
; CHECK-NEXT: if.then.0:
; CHECK-NEXT: Successor(s): for.inc
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