[PATCH] D103539: WIP: try to repair RISCV handling of paired relocations

Mon Jun 7 08:37:23 PDT 2021

compnerd added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/fixups-relax-diff.ll:19
   call void asm sideeffect "a:\0Ab:\0A.dword b-a", ""()
   ret i32 0
 }
----------------
jrtc27 wrote:
> jrtc27 wrote:
> > simoncook wrote:
> > > compnerd wrote:
> > > > jrtc27 wrote:
> > > > > There's no longer a RUN line for this... also this test makes no sense in the first place, it's trying to use 64-bit relocations on RV32. That should just be an error.
> > > > I didn't even notice that the relocation types are just flat out wrong.  That seems like a separate issue.
> > > > 
> > > > I wanted to keep the now dead check to do a last round of verification of the changes, at which point it should be removed.
> > > The relocations are 64-bit because of the size of `.dword`, I don't think this is an error?
> > The relocations match the directive, but the directive itself makes no sense on RV32. Can you do `.8byte foo` on i386?...
> And if you did want to support it, I'd argue it should just be a zero-padded 32-bit relocation (i.e. offset by 4 bytes on big-endian).
Well, I don't think that we should change that behaviour in this change.  Furthermore, it will require working with GCC and binutils as it currently _does_ generate a pair of `R_RISCV_ADD64` and `R_RISCV_SUB64` on RV32.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103539/new/

https://reviews.llvm.org/D103539