[PATCH] D103800: [AMDGPU] Add VReg_192 support for MIMG instructions

[Carl Ritson via Phabricator via llvm-commits]

critson created this revision.
critson added reviewers: foad, rampitec, dp.
Herald added subscribers: wenlei, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
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Allow MIMG instructions to be selected with 6 VGPRs for vaddr.
Previously these were rounded up to VReg_256, this saves 2 VGPRs.

As there is no MVT::v6f32 type Selection DAG cannot directly
support selecting VReg_192, instead vaddr is built as v8f32 then
the patched immediately after instruction selection.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103800

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
  llvm/test/CodeGen/AMDGPU/cluster_stores.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
  llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
  llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
  llvm/test/MC/Disassembler/AMDGPU/mimg_gfx10.txt

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