[PATCH] D103743: [RISCV] Optimize bitwise and with constant for the Zbs extension

[Ben Shi via Phabricator via llvm-commits]

benshi001 marked an inline comment as done.
benshi001 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:140
+  // The immediate must have exactly two bits clear.
+  uint64_t I = static_cast<uint64_t>(~N->getSExtValue());
+  return countPopulation(I) == 2;
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craig.topper wrote:
> What if the type is i32 and bit 31 is one of the clear bits. This sign extend won't handle that case.
I have handled the special case you concerned, and two tests are added along, which show improvements of the special case.

It is not needed to pre-commit the tests, since the difference among the pattern

RV32I, RV32IB and RV32IBS shows this improvement.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103743/new/

https://reviews.llvm.org/D103743