[PATCH] D103693: [RISCV] Add support for BUILD_VECTOR, VECTOR_SHUFFLE and INSERT_VECTOR_ELT for RVP

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1733
+    unsigned W = EltTy.getSizeInBits();
+    uint64_t Mask = (EltTy == MVT::i8)
+                        ? 0xff
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Can this be done with getTrailingOnesMask from MathExtras.h


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3543
+    return DAG.getNode(RISCVISD::INSERTB, DL, VecTy, {Vector, Value, Index});
+  else if (EltTy == MVT::i16)
+    return DAG.getNode(RISCVISD::INSERTH, DL, VecTy, {Vector, Value, Index});
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No need for else since the if returned


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:26
 
+def riscv_insertb : SDNode<"RISCVISD::INSERTB", SDT_RISCVVecInsert>;
+def riscv_inserth : SDNode<"RISCVISD::INSERTH", SDT_RISCVVecInsert>;
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Do we really need 3 different RISCVISD opcodes or can we use one and determine the instruction from the element type in the isel pattern?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103693/new/

https://reviews.llvm.org/D103693