[PATCH] D103757: [RISCV] Lower i8/i16 bswap/bitreverse to grevi/greviw with Zbp.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Include known bits support so we know we don't need to zext the
output if the input was already zero extended.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103757

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

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