[PATCH] D103737: [RISCV] Pre-commit

[Jim Lin via Phabricator via llvm-commits]

Jim created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103737

Files:
  llvm/test/CodeGen/RISCV/rvp/bpick.ll


Index: llvm/test/CodeGen/RISCV/rvp/bpick.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvp/bpick.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=RV64
+
+define i32 @bpick32(i32 %a, i32 %b, i32 %mask) nounwind {
+; RV32-LABEL: bpick32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    and a0, a2, a0
+; RV32-NEXT:    not a2, a2
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: bpick32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    and a0, a2, a0
+; RV64-NEXT:    not a2, a2
+; RV64-NEXT:    and a1, a2, a1
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %and1 = and i32 %mask, %a
+  %neg = xor i32 %mask, -1
+  %and2 = and i32 %neg, %b
+  %or = or i32 %and1, %and2
+  ret i32 %or
+}
+
+define i64 @bpick64(i64 %a, i64 %b, i64 %mask) nounwind {
+; RV32-LABEL: bpick64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    and a1, a5, a1
+; RV32-NEXT:    and a0, a4, a0
+; RV32-NEXT:    not a4, a4
+; RV32-NEXT:    not a5, a5
+; RV32-NEXT:    and a3, a5, a3
+; RV32-NEXT:    and a2, a4, a2
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: bpick64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    and a0, a2, a0
+; RV64-NEXT:    not a2, a2
+; RV64-NEXT:    and a1, a2, a1
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %and1 = and i64 %mask, %a
+  %neg = xor i64 %mask, -1
+  %and2 = and i64 %neg, %b
+  %or = or i64 %and1, %and2
+  ret i64 %or
+}


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