[PATCH] D103698: [RISCV] Add support for CLTZ for RVP

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 4 16:21:05 PDT 2021


craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvp/clo.ll:210
 ; RV32-NEXT:    not a0, a0
-; RV32-NEXT:    srli a1, a0, 1
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    srli a1, a0, 2
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    srli a1, a0, 4
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    srli a1, a0, 8
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    srli a1, a0, 16
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    not a0, a0
-; RV32-NEXT:    srli a1, a0, 1
-; RV32-NEXT:    lui a2, 349525
-; RV32-NEXT:    addi a2, a2, 1365
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    sub a0, a0, a1
-; RV32-NEXT:    lui a1, 209715
-; RV32-NEXT:    addi a1, a1, 819
-; RV32-NEXT:    and a2, a0, a1
-; RV32-NEXT:    srli a0, a0, 2
-; RV32-NEXT:    and a0, a0, a1
-; RV32-NEXT:    add a0, a2, a0
-; RV32-NEXT:    srli a1, a0, 4
-; RV32-NEXT:    add a0, a0, a1
-; RV32-NEXT:    lui a1, 61681
-; RV32-NEXT:    addi a1, a1, -241
-; RV32-NEXT:    and a0, a0, a1
-; RV32-NEXT:    lui a1, 4112
-; RV32-NEXT:    addi a1, a1, 257
-; RV32-NEXT:    call __mulsi3 at plt
-; RV32-NEXT:    srli a0, a0, 24
-; RV32-NEXT:    j .LBB2_3
+; RV32-NEXT:    clz32 a0, a0
+; RV32-NEXT:    ret
----------------
Why didn't this use clo32?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103698/new/

https://reviews.llvm.org/D103698



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