[llvm] 12592a4 - Add commutable attribute to opcodes for ARC

[Danila Malyutin via llvm-commits]

Author: Mark Schimmel
Date: 2021-06-04T19:49:19+03:00
New Revision: 12592a439ae53fe35f6b70ee7e2eea60000d3063

URL: https://github.com/llvm/llvm-project/commit/12592a439ae53fe35f6b70ee7e2eea60000d3063
DIFF: https://github.com/llvm/llvm-project/commit/12592a439ae53fe35f6b70ee7e2eea60000d3063.diff

LOG: Add commutable attribute to opcodes for ARC

This patch sets the isCommutable attribute for several opcodes that have
the "reg = OPCODE reg, reg" format.

Differential Revision: https://reviews.llvm.org/D103653

Added: 
    

Modified: 
    llvm/lib/Target/ARC/ARCInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td
index 8fe393dfaf5b6..1dc81dd76a523 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.td
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.td
@@ -118,12 +118,13 @@ def STB_FAR : PseudoInstARC<(outs), (ins GPR32:$dst, MEMrlimm:$addr),
 
 // Generic 3 operand binary instructions (i.e., add r0, r1, r2).
 multiclass ArcBinaryInst<bits<5> major, bits<6> mincode,
-                       string opasm> {
+                       string opasm, bit Commutable> {
   // 3 register variant.
   def _rrr : F32_DOP_RR<major, mincode, 0, (outs GPR32:$A),
                         (ins GPR32:$B, GPR32:$C),
                         !strconcat(opasm, "\t$A, $B, $C"),
-                        []>;
+                        []>
+  { let isCommutable = Commutable; }
   def _f_rrr : F32_DOP_RR<major, mincode, 1, (outs GPR32:$A),
                           (ins GPR32:$B, GPR32:$C),
                           !strconcat(opasm, ".f\t$A, $B, $C"),
@@ -198,10 +199,10 @@ multiclass ArcUnaryInst<bits<5> major, bits<6> subop,
 }
 
 
-multiclass ArcBinaryGEN4Inst<bits<6> mincode, string opasm> :
-  ArcBinaryInst<0b00100, mincode, opasm>;
+multiclass ArcBinaryGEN4Inst<bits<6> mincode, string opasm, bit Commutable = 0> :
+  ArcBinaryInst<0b00100, mincode, opasm, Commutable>;
 multiclass ArcBinaryEXT5Inst<bits<6> mincode, string opasm> :
-  ArcBinaryInst<0b00101, mincode, opasm>;
+  ArcBinaryInst<0b00101, mincode, opasm, 0>;
 
 multiclass ArcUnaryGEN4Inst<bits<6> mincode, string opasm> :
   ArcUnaryInst<0b00100, mincode, opasm>;
@@ -219,24 +220,24 @@ multiclass MultiPat<SDPatternOperator InFrag,
 // ---------------------------------------------------------------------------
 
 // Definitions for 3 operand binary instructions.
-defm ADD : ArcBinaryGEN4Inst<0b000000, "add">;
+defm ADD : ArcBinaryGEN4Inst<0b000000, "add",1>;
 defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">;
 defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">;
 defm SUB2 : ArcBinaryGEN4Inst<0b011000, "sub2">;
 defm SUB3 : ArcBinaryGEN4Inst<0b011001, "sub3">;
-defm OR  : ArcBinaryGEN4Inst<0b000101, "or">;
-defm AND : ArcBinaryGEN4Inst<0b000100, "and">;
-defm XOR : ArcBinaryGEN4Inst<0b000111, "xor">;
-defm MAX : ArcBinaryGEN4Inst<0b001000, "max">;
-defm MIN : ArcBinaryGEN4Inst<0b001001, "min">;
+defm OR  : ArcBinaryGEN4Inst<0b000101, "or",1>;
+defm AND : ArcBinaryGEN4Inst<0b000100, "and",1>;
+defm XOR : ArcBinaryGEN4Inst<0b000111, "xor",1>;
+defm MAX : ArcBinaryGEN4Inst<0b001000, "max",1>;
+defm MIN : ArcBinaryGEN4Inst<0b001001, "min",1>;
 defm ASL : ArcBinaryEXT5Inst<0b000000, "asl">;
 defm LSR : ArcBinaryEXT5Inst<0b000001, "lsr">;
 defm ASR : ArcBinaryEXT5Inst<0b000010, "asr">;
 defm ROR : ArcBinaryEXT5Inst<0b000011, "ror">;
-defm MPY  : ArcBinaryGEN4Inst<0b011010, "mpy">;
-defm MPYM : ArcBinaryGEN4Inst<0b011011, "mpym">;
-defm MPYMU : ArcBinaryGEN4Inst<0b011100, "mpymu">;
-defm SETEQ : ArcBinaryGEN4Inst<0b111000, "seteq">;
+defm MPY  : ArcBinaryGEN4Inst<0b011010, "mpy",1>;
+defm MPYM : ArcBinaryGEN4Inst<0b011011, "mpym",1>;
+defm MPYMU : ArcBinaryGEN4Inst<0b011100, "mpymu",1>;
+defm SETEQ : ArcBinaryGEN4Inst<0b111000, "seteq",1>;
 
 // Patterns for 3 operand binary instructions.
 defm : MultiPat<add, ADD_rrr, ADD_rru6, ADD_rrlimm>;