[llvm] cd093cb - [AMDGPU][MC][NFC] Fixed typos in parser
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 4 05:41:01 PDT 2021
Author: Dmitry Preobrazhensky
Date: 2021-06-04T15:40:42+03:00
New Revision: cd093cbb115a4fda1544a789e3b1355e5b155aea
URL: https://github.com/llvm/llvm-project/commit/cd093cbb115a4fda1544a789e3b1355e5b155aea
DIFF: https://github.com/llvm/llvm-project/commit/cd093cbb115a4fda1544a789e3b1355e5b155aea.diff
LOG: [AMDGPU][MC][NFC] Fixed typos in parser
Differential Revision: https://reviews.llvm.org/D103680
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index bb20f07ef35ac..552071b271510 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4049,8 +4049,8 @@ static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,
unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
auto Reg = Sub ? Sub : Op.getReg();
- const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
- return AGRP32.contains(Reg) ? 1 : 0;
+ const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
+ return AGPR32.contains(Reg) ? 1 : 0;
}
bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
@@ -4089,8 +4089,8 @@ bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
return true;
const MCRegisterInfo *MRI = getMRI();
- const MCRegisterClass &VGRP32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
- const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
+ const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
+ const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
const MCOperand &Op = Inst.getOperand(I);
if (!Op.isReg())
@@ -4100,9 +4100,9 @@ bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
if (!Sub)
continue;
- if (VGRP32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
+ if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
return false;
- if (AGRP32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
+ if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
return false;
}
@@ -4122,12 +4122,12 @@ bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
return true;
const MCRegisterInfo *MRI = getMRI();
- const MCRegisterClass &VGRP32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
+ const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
int Data0Pos =
AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);
assert(Data0Pos != -1);
auto Reg = Inst.getOperand(Data0Pos).getReg();
- auto RegIdx = Reg - (VGRP32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
+ auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
if (RegIdx & 1) {
SMLoc RegLoc = getRegLoc(Reg, Operands);
Error(RegLoc, "vgpr must be even aligned");
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