[PATCH] D102467: [RISCV] Implement codegen patterns for add8, add16, sub8 and sub16

[Jim Lin via Phabricator via llvm-commits]

Jim updated this revision to Diff 349825.
Jim added a comment.

Add support for vector and, or and xor operations and
implement getPreferredVectorAction hook to widen v4i8 and v2i16 to v8i8 and v4i16 for RV64P.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102467/new/

https://reviews.llvm.org/D102467

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/test/CodeGen/RISCV/rvp/vector-alu.ll

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