[PATCH] D103348: [AMDGPU] Add maximum NSA size limit ISA feature

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:1695
+      Register Addr = SrcOp.getReg();
+      int Dwords = (MRI->getType(Addr).getSizeInBits() + 31) / 32;
+      if (Dwords == NumVAddrDwords) {
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`divideCeil(..., 32)`


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Comment at: llvm/lib/Target/AMDGPU/GCNSubtarget.h:139
   bool HasNSAEncoding;
+  int NSAMaxSize;
   bool GFX10_BEncoding;
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Is there a reason this can't be unsigned?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103348/new/

https://reviews.llvm.org/D103348