[PATCH] D103672: [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions

[Carl Ritson via Phabricator via llvm-commits]

critson added a comment.

In D103672#2798535 <https://reviews.llvm.org/D103672#2798535>, @foad wrote:

> My only slight concern is if people have GFX10 disassemblies stored somewhere, they might find they can no longer reassemble them after your change. I don't know how serious that is.

I believe we could allow these by changing the validator.

> Will there be a follow up patch to support v6f32/VReg_192? I think the register classes already exist for that.

v6f32 is not actually defined in LLVM (MVT class), so I am not sure how possible this is.  I realized this as I initially tried to include v6f32 support in this change.


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  https://reviews.llvm.org/D103672/new/

https://reviews.llvm.org/D103672