[PATCH] D103672: [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions

[Carl Ritson via Phabricator via llvm-commits]

critson created this revision.
critson added reviewers: foad, rampitec, dstuttard, arsenm.
Herald added subscribers: wenlei, kerbowa, hiraditya, t-tye, tpr, yaxunl, nhaehnle, jvesely, kzhuravl.
critson requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Avoid having to round up to v8f32/VReg_256 when only 5 VGPRs are
required for a MIMG address operand.

Maintain _V8 instruction variants of pseudo instructions allowing
assembly prior to GFX10 to work as-is.  Currently the validator
can tell for GFX10 what the correct size is, so will disallow
oversize address registers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103672

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
  llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
  llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
  llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
  llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
  llvm/test/MC/Disassembler/AMDGPU/mimg_gfx10.txt

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